KR20170014521A - Method of manufacturing dual transistor having nonvolatile memory characteristics using glass substrate - Google Patents

Method of manufacturing dual transistor having nonvolatile memory characteristics using glass substrate Download PDF

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KR20170014521A
KR20170014521A KR1020150108039A KR20150108039A KR20170014521A KR 20170014521 A KR20170014521 A KR 20170014521A KR 1020150108039 A KR1020150108039 A KR 1020150108039A KR 20150108039 A KR20150108039 A KR 20150108039A KR 20170014521 A KR20170014521 A KR 20170014521A
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thin film
ferroelectric thin
ferroelectric
metal seed
pair
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주승기
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주승기
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    • H01L27/11507—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H01L2924/1435—Random access memory [RAM]
    • H01L2924/1443—Non-volatile random-access memory [NVRAM]

Abstract

The present invention relates to a method for fabricating a dual transistor having a nonvolatile memory characteristic using a glass substrate, wherein crystallization proceeds in a side direction of the ferroelectric thin film in a metal seed formed between the dual transistor element regions to form a monocrystalline ferroelectric thin film A transistor element having two memory characteristics can be manufactured.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a dual transistor having a nonvolatile memory characteristic using a glass substrate,

The present invention relates to a method of manufacturing a dual transistor, and more particularly, to a memory device having a monocrystalline ferroelectric thin film using a metal seed, thereby realizing a high performance memory, and a single monocrystalline ferroelectric thin film The present invention relates to a method of manufacturing a dual transistor having a nonvolatile memory characteristic using a glass substrate which can improve the manufacturing efficiency by manufacturing transistor elements having memory characteristics.

2. Description of the Related Art In general, a flat panel display is composed of a thin film transistor (TFT), a data driver, a gate driver, various cache memories, and a metal wiring connecting the TFT and the memory. The data driver and gate driver are separately fabricated on a single crystal wafer and attached to the glass substrate.

Large flat panel displays are equipped with separately manufactured data drivers or gate drivers, and data lines and gate lines are connected to data drivers or gate drivers.

As the size of a high-resolution large-sized display increases, the number of transistors increases. In addition, the number of gate lines connected to the gates of the transistors and the number of data lines connected to the sources increases.

As a result, there is a need for a technique for manufacturing drivers inside the display panel that regulate gate signals and data signals.

Korean Patent Laid-Open Publication No. 10-2006-0073771 discloses a substrate; An organic semiconductor layer disposed on the substrate; A gate electrode disposed on the organic semiconductor layer and insulated from the organic semiconductor layer; A first intermediate layer and a second intermediate layer disposed to be in contact with the organic semiconductor layer, insulated from the gate electrode, and spaced apart from each other; And a first electrode and a second electrode which are disposed on the organic semiconductor layer and are insulated from the gate electrode and contact the first intermediate layer and the second intermediate layer, respectively, However, by forming the source, the channel, and the drain with the organic semiconductor layer, only transistor elements having no memory function are realized.

Korean Patent Publication No. 10-2006-0073771

It is an object of the present invention to provide a nonvolatile memory device using a glass substrate capable of realizing a high performance memory by implementing a memory device having a monocrystalline ferroelectric thin film using a metal seed The present invention provides a method of manufacturing a dual transistor.

It is another object of the present invention to provide a method of fabricating a transistor device having two memory characteristics as a monocrystalline ferroelectric thin film by progressing crystallization in a lateral direction of a ferroelectric thin film in a metal seed formed between dual transistor device regions, And a method of manufacturing a dual transistor having nonvolatile memory characteristics using a glass substrate capable of improving efficiency.

According to an aspect of the present invention, there is provided a method of fabricating a dual transistor having a nonvolatile memory characteristic using a glass substrate according to an embodiment of the present invention includes sequentially forming a buffer oxide film and a pair of island polysilicon patterns spaced apart from each other ; Forming a ferroelectric buffer layer surrounding the pair of island polysilicon patterns on the buffer oxide layer and depositing a ferroelectric thin film on the ferroelectric buffer layer; Forming a metal seed in the ferroelectric thin film between the pair of island polysilicon patterns; Performing a heat treatment process to crystallize the ferroelectric thin film in a lateral direction around the metal seed to form a monocrystalline ferroelectric thin film; Forming a gate electrode on the monocrystalline ferroelectric thin film surrounding the metal seed; Wherein a laminated structure of the ferroelectric buffer layer, the crystallized ferroelectric thin film, and the gate electrode protrudes in an upper central region of each of the pair of island polysilicon patterns, and an upper portion of each of a pair of island polysilicon patterns on the left and right sides of the central region is exposed, Etching from the gate electrode to the ferroelectric buffer layer by removing the metal seed; And implanting N-type or P-type ions into each of the exposed island polysilicon patterns to form a source region and a drain region, and forming a source electrode and a drain electrode in the source region and the drain region, respectively; And a control unit.

In the method of manufacturing a dual transistor having a nonvolatile memory characteristic using a glass substrate according to an embodiment of the present invention, the step of forming a metal seed in the ferroelectric thin film between the pair of island polysilicon patterns may include: Depositing a metal layer on the entire surface, and patterning the deposited metal layer by a photolithography process to form a metal seed between the pair of island polysilicon patterns.

In the method of manufacturing a dual transistor having a nonvolatile memory characteristic using a glass substrate according to an embodiment of the present invention, the ferroelectric buffer layer may be formed of SiO 2 , Si 3 N 4 , ZrTiO 4 , HfO 2 , Al 2 O 3 .

In the method of manufacturing a dual transistor having a nonvolatile memory characteristic using a glass substrate according to an embodiment of the present invention, the thickness of the ferroelectric buffer layer is 500 nm or less.

In the method of manufacturing a dual transistor having a nonvolatile memory characteristic using a glass substrate according to an embodiment of the present invention, the metal seed may be Ag, Au, Al, Co, Cr, Cd, Cu, Mo, Ni, Pd , Pt, Ru, Rh, Sn, Sb, Ti, and Tr.

In the method of manufacturing a dual transistor having a nonvolatile memory characteristic using a glass substrate according to an embodiment of the present invention, the annealing process is performed in an oxygen atmosphere at a low temperature of 300 to 800 ° C.

According to the present invention, there is an advantage that a transistor element having a memory characteristic can be manufactured on a glass substrate by a low-temperature process, and can be used as a built-in data driver and a gate driver in a display panel.

According to the present invention, crystallization proceeds in the lateral direction of the ferroelectric thin film in the metal seeds formed between the dual transistor element regions, and transistor elements having two memory characteristics can be manufactured by one monocrystalline ferroelectric thin film, There is an advantage that it can be improved.

According to the present invention, metal seeds capable of promoting crystal nucleation can be formed between transistor elements having two memory characteristics, and metal seeds can be removed together in an etching process for defining a structure of a device, The removal process is not required and the number of process steps can be reduced.

According to the present invention, a monocrystalline ferroelectric thin film formed by promoting nucleation of a crystal with a metal seed is applied to a memory device, thereby performing heat treatment for a short time, thereby reducing manufacturing time and manufacturing cost .

According to the present invention, a memory device having a monocrystalline ferroelectric thin film using a metal seed is realized, thereby providing a high-performance memory.

FIGS. 1 to 12 are cross-sectional views illustrating a method of manufacturing a dual transistor having a non-volatile memory characteristic using a glass substrate according to the present invention,
13 is a conceptual plan view for explaining a state in which a ferroelectric thin film is side-crystallized by a metal seed according to the present invention;
FIG. 14 is a conceptual plan view for explaining a state where a ferroelectric thin film for improving a device according to a comparative example of the present invention is side-crystallized;
15 is a graph of a gate voltage-drain current characteristic of an element and a comparative element according to the present invention,
16 is a graph showing retention measurement graphs of Example devices and Comparative example devices according to the present invention,
17 is a fatigue cycle measurement graph of an example device and a comparative device according to the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 to 12 are cross-sectional views illustrating a method of manufacturing a dual transistor having a nonvolatile memory characteristic using a glass substrate according to the present invention.

Referring to FIG. 1, a buffer oxide film 110 is deposited on a glass substrate 100.

The buffer oxide film 110 may be formed of SiO 2 or Si 3 N 4 or may be formed by a method such as plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD) Lt; / RTI >

Next, a polysilicon layer 120 is formed on the buffer oxide film 110 (FIG. 2).

The polysilicon layer 120 is formed by depositing an amorphous silicon layer on the buffer oxide layer 110 and then performing a heat treatment process.

A photolithography process is then performed to pattern the polysilicon layer 120 to form a pair of spaced apart island polysilicon patterns 121 and 122 (FIG. 3).

For example, a photoresist etch mask is formed on the polysilicon layer 120, and the polysilicon layer 120 is patterned by dry etching or wet etching using an etch mask to form a pair of island polysilicon patterns 121 and 122.

The pair of island polysilicon patterns 121 and 122 are active regions.

Then, as shown in FIG. 4, a pair of island polysilicon patterns 121 and 122 are surrounded and a ferroelectric buffer layer 130 is formed on the buffer oxide film 110.

The ferroelectric buffer layer 130 deposits oxides such as SiO 2 , Si 3 N 4 , ZrTiO 4 , HfO 2 , and Al 2 O 3 to a thickness of 500 Å or less.

On the other hand, in the transistor having the nonvolatile memory characteristic, the gate voltage is applied to the ferroelectric buffer layer 130 and the monocrystalline ferroelectric thin film described below.

At this time, if the thickness of the ferroelectric buffer layer 130 is 500 ANGSTROM or more, the gate voltage is applied to the ferroelectric buffer layer 130 a lot, and the ferroelectric buffer layer 130 is applied only to the monocrystalline ferroelectric thin film, Memory characteristics are degraded due to poor performance.

Subsequently, the ferroelectric thin film 140 is deposited on the ferroelectric buffer layer 130 (FIG. 5).

The ferroelectric thin film 140 is preferably a PZT thin film, and the PZT thin film 140 is deposited by RF magnetron sputtering.

Subsequently, a metal seed 150 is formed on the ferroelectric thin film 140 between the pair of island polysilicon patterns 121 and 122 (FIG. 6).

Here, the metal layer is deposited on the entire surface of the ferroelectric thin film 140, and then the deposited metal layer is patterned by a photolithography process to form the metal seed 150 only in the corresponding region (that is, the region between the pair of island polysilicon patterns 121 and 122) do.

One of Ag, Au, Al, Co, Cr, Cd, Cu, Mo, Ni, Pd, Pt, Ru, Rh, Sn, Sb, Ti and Tr is used as the metal seed 150.

That is, the metal seed 150 is formed on the ferroelectric thin film 140 between the neighboring island polysilicon patterns 121 and 122.

In the present invention, when a pair of the island polysilicon patterns 121 and 122 are formed in a matrix form and the metal seeds 150 are arranged in the same pattern as a dot pattern and a subsequent manufacturing process is performed, ) And a plurality of nonvolatile memory characteristics arranged in rows.

Next, as shown in FIGS. 7 and 8, the ferroelectric thin film 140 is crystallized in the lateral direction around the metal seed 150 by performing a heat treatment process in an oxygen atmosphere at 300 to 800.degree.

At this time, the crystallization starts in the ferroelectric thin film 140 contacting the lower part of the metal seed 150 and crystallizes in the lateral direction of the ferroelectric thin film 140. As a result, the upper part of the island polysilicon patterns 121 and 122 is covered with the ferroelectric thin film 140 ).

That is, as shown in FIG. 13, the metal seed 150 acts as a nucleation catalyst at the heat treatment temperature to form the nucleus first in the ferroelectric thin film 140 contacting the bottom of the metal seed 150, The crystallization of the ferroelectric thin film 140 proceeds and then the entire area of the ferroelectric thin film 140 is crystallized by surrounding the polysilicon patterns 121 and 122. The crystallized thin ferroelectric film 140 is a monocrystalline ferroelectric thin film 141). Referring to FIG. 13, a ferroelectric thin film 141 that is monocrystallized in the metal seed 150 is formed first.

In this case, in the present invention, the metal seed 150 acts as a nucleation catalyst, and the annealing process is performed at a temperature of 300 to 800 ° C. for 1 to 4 hours to clean the unrecrystallized ferroelectric thin film 140 .

That is, the method of forming the monocrystalline ferroelectric thin film by the metal seed 150 according to the present invention is shorter than the method of forming the polycrystalline ferroelectric thin film of the comparative example described below for a relatively short time, Thereby reducing the manufacturing cost.

The heat treatment process is performed in an oxygen atmosphere at a low temperature of 300 to 800 ° C. in order to prevent deformation of the glass substrate.

Next, the gate electrode 160 is formed on the crystallized ferroelectric thin film 140 while surrounding the metal seed 150 (FIG. 9).

The gate electrode 160 uses Al, Mo, MoW or the like.

Thereafter, a stacked structure of the ferroelectric buffer layers 131 and 132, the crystallized ferroelectric thin films 141a and 141b and the gate electrodes 160a and 160b is projected in the upper central region of each of the pair of island polysilicon patterns 121 and 122, The gate electrode 160 is etched away from the gate electrode 160 to the ferroelectric buffer layer 130 so that the upper portions of the pair of island polysilicon patterns 121 and 122 are exposed (FIG. 10).

In such an etching process, the metal seed 150 is completely removed.

Then, as shown in FIG. 11, source regions 121a and 122a and drain regions 121b and 122b are formed by implanting N-type or P-type ions into each of the exposed pair of island polysilicon patterns 121 and 122 11)

Finally, after the passivation layer 180 of the silicon oxide film is formed on the entire surface, the passivation layer 180 is selectively removed to expose the source regions 121a and 122a and the drain regions 121b and 122b, Source electrodes 171a and 172a and drain electrodes 171b and 172b are formed in the regions 121a and 122a and the drain regions 121b and 122b (FIG. 12).

Therefore, according to the present invention, the crystallization proceeds in the lateral direction of the ferroelectric thin film in the metal seeds formed between the regions of the dual transistor elements (the first and second elements in FIG. 13), and two memory characteristics It is possible to manufacture a transistor element having an improved manufacturing efficiency.

In addition, the present invention forms a metal seed capable of promoting crystal nucleation between transistor elements having two memory characteristics and removes the metal seeds together in the etching process (the process of FIG. 10) for defining the structure of the device Thereby eliminating the need for a separate metal seed removing step and reducing the number of process steps.

(Example)

A Si 3 N 4 thin film was deposited by plasma enhanced chemical vapor deposition (PECVD) on a glass substrate on which a polysilicon pattern as an active pattern was formed (the polysilicon pattern was formed on a SiO 2 butter oxide film formed on a glass substrate) Deposited by RF reactive magnetron sputtering. At this time, the PZT deposition process was performed using a single ceramic target of PbZrO.sub.0.52Ti.sub.0.48O.sub.3, the initial vacuum was set to 1 × 10 -5 torr or less, and the temperature of the glass substrate during deposition was maintained at 200.degree. The process pressure was 20 mtorr, and the sputtering gas was used by mixing Ar and O 2 at a volume ratio of 1: 9.

Thereafter, a Pt layer, which is a metal seed, was formed in a region 10 micrometers apart from the polysilicon pattern. Pt layer by DC magnetron sputtering method. The initial vacuum was below 1x10 -5 torr, and the glass substrate temperature during the deposition was maintained at room temperature. The process pressure was 45 mtorr.

Then, rapid thermal annealing is performed in an air atmosphere at 600 ° C for 30 seconds at a maximum power, and further heat treatment is performed in a tubular tube furnace at 550 ° C to crystallize the PZT layer in the lateral direction around the Pt layer as a metal seed, PZT layer was formed. At this time, the formed single crystal is subjected to heat treatment until all the polysilicon active layers are covered.

Thereafter, MoW was deposited and a Pt layer was removed to form a gate electrode, and a dopant was implanted into the source and the drain by an ion implantation method. Finally, a passivation layer of a silicon oxide film and source and drain electrodes were formed.

(Comparative Example)

The device of the comparative example was manufactured in the same manner as the method of manufacturing the element of the above-described embodiment except that the polycrystalline ferroelectric thin film was formed only.

That is, in the comparative example, the ferroelectric thin film is heat-treated without forming a Pt layer, which is a metal seed, to form a polycrystalline ferroelectric thin film.

More specifically, as shown in FIG. 14, a plurality of nuclei 145a, 145b, 145c and 145d are formed at random positions of the PZT layer not crystallized by the heat treatment process, and the plurality of nuclei 145a , 145b, 145c, and 145d.

Thereafter, when all the PZT layer regions are crystallized by surrounding the polysilicon patterns 121 and 122, a polycrystalline PZT layer having a large number of grains crystallized in the nuclei 145a, 145b, 145c and 145d is formed.

Here, a polycrystalline PZT layer is formed in each of the first and second device regions.

On the other hand, in the comparative example, since the PT layer, which is a metal seed, acting as a nucleation catalyst is not present as in the embodiment of the present invention, in order to secure nucleation time, Heat treatment is performed.

15 is a graph of the gate voltage-drain current characteristics of the device of Example and the device of Comparative Example according to the present invention.

When a constant voltage is applied to the gate of the device of the above-described embodiment at 10 V for 10 -4 seconds, strong polarization is formed inside the crystallized PZT layer. Then, while the polarization is continuously maintained, when the drain current is measured while a voltage is continuously applied from -3 V to -9 V to the gate and the drain voltage is applied to -0.1 V, a graph of 'A1' appear.

Here, when a reverse voltage is applied to the gate voltage, the polarization direction is reversed.

Therefore, after application of reverse voltage for 10 -4 seconds to -10V to the gate, in applying a voltage sequentially to the gate from -3 V to -9V and applying a drain voltage to -0.1V state measurement of the current in the drain , A hysteresis phenomenon occurs in which the threshold voltage is shifted to the right by a graph of 'A2', thereby realizing a memory device. This difference in the threshold voltage determines the memory performance.

In the device of the comparative example, the drain current was measured in the same manner, and as a result, a graph of 'B' was obtained.

Here, the device (A) of the present invention having the single crystal-nitrided PZT layer had a threshold voltage difference of 3.5 V and the device (B) of the comparative example having the polycrystallized PZT layer had a threshold voltage difference of 1.5 V It can be seen that the monocrystalline PZT layer of the intended element A is formed with a larger polarization than the polycrystallized PZT layer of the element B of the comparative example, and thus the function as a memory element is excellent.

FIG. 16 is a graph showing the retention of a device according to an embodiment of the present invention and a device according to the present invention. The memory performance of the device and the device is measured by applying a constant voltage of 10 V or a reverse voltage of -10 V to the gate.

A gate voltage of a constant voltage of 10 V was applied to the monocrystalline nitride PZT layer of the device of Example and the polycrystalline PZT layer of the comparative device for 10 4 seconds to form a polarization and then a gate voltage of -2 V The drain current was measured, and the device of the embodiment showed a 'C1' graph and the device of the comparative example showed a 'D1' graph.

Here, if the polarization state is maintained well, the drain current should be kept constant with time.

In the 'C1' graph, the drain current of the device of the embodiment was very small even after one month, but the drain current of the device of the comparative example increased for one month.

From the point of view of the voltage-drain current graph, the increase in the drain current is due to the fact that the threshold voltage has shifted to the right again little by little as the polarization is lost.

Then, a gate voltage of -10 V was applied for 10 4 seconds to the monocrystalline nitride PZT layer of the device of the embodiment and the polycrystalline PZT layer of the comparative device to form a polarization, and then a gate voltage of -2 V was applied As a result of measuring the drain current, the device of the embodiment showed a 'C2' graph and the device of the comparative example showed a 'D2' graph.

In the 'C2' graph, the device of the embodiment showed a small change in the drain current even after one month, and in the D2 graph, the drain current decreased in the device of the comparative example after one month.

The reason why the drain current is reduced in this manner is that the threshold voltage is shifted to the left with time as the polarization is lost in view of the voltage-drain current graph.

That is, the device of the comparative example can not maintain the polarization for a long time, and after one month, the maintenance between the two polarizations is reduced by 42%, but the device of the embodiment shows that the polarization is maintained.

Also, with a trend line that assumes 10 years, it can be seen that the device of the comparative example completely loses data while the device of the embodiment exhibits only 22% of current reduction, thereby realizing a high performance memory.

17 is a fatigue cycle measurement graph of an example device and a comparative device according to the present invention.

-10 V and 10 V were defined as one cycle, and the polarization direction was continuously changed to maintain the fatigue at a gate voltage of -2 V, and the drain currents of the device element and the comparative element were measured.

In the graph of FIG. 17, the graph of FIG. 17 shows that the constant voltage 10V is the graph of 'E1' and the reverse voltage -10V is the graph of 'E2' 'Graph.

In this graph, the polycrystalline PZT of the comparative device breaks down to completely lose memory capability when the 10 4 cycle polarization is continuously tilted in the direction, while the single crystal PZT of the device of the embodiment is 10 12 cycle.

This difference indicates that the polycrystalline PZT of the comparative device is depolarized by a plurality of crystal grains and that the single crystal PZT of the device of the embodiment is not well depolarized.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be construed as limited to the embodiments set forth herein. Various changes and modifications may be made by those skilled in the art.

The present invention can realize a high performance memory by implementing a memory element having a monocrystalline ferroelectric thin film using a metal seed, and is applicable to a transistor element having two memory characteristics as one single crystalized ferroelectric thin film.

100: glass substrate 110: buffer oxide film
120: polysilicon 121, 122: island polysilicon pattern
130: ferroelectric buffer layer 140: ferroelectric thin film
150: metal seed

Claims (7)

Sequentially forming a buffer oxide film and a pair of island polysilicon patterns spaced apart from each other on a glass substrate;
Forming a ferroelectric buffer layer surrounding the pair of island polysilicon patterns on the buffer oxide layer and depositing a ferroelectric thin film on the ferroelectric buffer layer;
Forming a metal seed in the ferroelectric thin film between the pair of island polysilicon patterns;
Performing a heat treatment process to crystallize the ferroelectric thin film in a lateral direction around the metal seed to form a monocrystalline ferroelectric thin film;
Forming a gate electrode on the monocrystalline ferroelectric thin film surrounding the metal seed;
Wherein a laminated structure of the ferroelectric buffer layer, the crystallized ferroelectric thin film, and the gate electrode protrudes in an upper central region of each of the pair of island polysilicon patterns, and an upper portion of each of a pair of island polysilicon patterns on the left and right sides of the central region is exposed, Etching from the gate electrode to the ferroelectric buffer layer by removing the metal seed; And
Implanting N-type or P-type ions into each of the exposed island polysilicon patterns to form a source region and a drain region, and forming a source electrode and a drain electrode in the source region and the drain region, respectively; Wherein the method comprises the steps of: forming a gate electrode on a substrate; 2. The method of claim 1, wherein forming the metal seeds in the ferroelectric thin film between the pair of island polysilicon patterns comprises:
Depositing a metal layer on the entire surface of the ferroelectric thin film and patterning the deposited metal layer by a photolithography process to form a metal seed between the pair of island polysilicon patterns. A method of manufacturing a dual transistor. The method of claim 1, wherein the ferroelectric buffer layer is one of SiO 2 , Si 3 N 4 , ZrTiO 4 , HfO 2 , and Al 2 O 3 . . 2. The method of claim 1, wherein the ferroelectric buffer layer has a thickness of 500 nm or less. The method of claim 1, wherein the metal seed is one of Ag, Au, Al, Co, Cr, Cd, Cu, Mo, Ni, Pd, Pt, Ru, Rh, Sn, Sb, A method of manufacturing a dual transistor having a nonvolatile memory characteristic using a glass substrate. The method according to claim 1,
Wherein the annealing process is performed in an oxygen atmosphere at a low temperature of 300 to 800 占 폚. The method according to claim 6,
Wherein the heat treatment step is performed for 1 hour to 4 hours in order to allow the metal seed to serve as a nucleation catalyst and to monocrystallize all the non-crystallized ferroelectric thin films. A method of manufacturing a dual transistor.






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