KR20170006248A - System and method for synchronization and interference rejection in super regenerative receiver - Google Patents

Abstract

A system and method for synchronization in an SRR signal sampled at a chip rate of 1.5 times. The method includes setting the quench rate of SRR as a predefined value. The predefined value is a chip rate of 1.5 times of an incoming signal. The method also includes a step of requesting an expected preamble sequence with an arbitrary set of samples and a step of requesting an expected starting frame delimiter (SFD) sequence for all possible sample sets. The method also includes a step of computing an association metric for each bit of SFD during SFD acquisition for all possible sample sets and a step of calculating a decision metric, based on the association metric when the SFD is detected for one or more sample sets. The method also includes a step of performing pulse synchronization by identifying a best sample set for demodulating an input signal based on the decision metric.

Description

[0001] SYSTEM AND METHOD FOR SYNCHRONIZATION AND INTERFERENCE REJECTION IN SUPER RECOVERY RECEIVERS [0002]

A super regenerative receiver (SRR) is started. Specifically, synchronization related techniques within the SRR are disclosed.

Super Regenerative Receivers (SRRs) are low-power receivers used in wireless sensor networks. In wireless sensor networks (free licensed ISM bands), many nodes coexist in the same frequency band. The coexistence of communication nodes based on SRR is affected by the Adjacent Channel Interference (ACI) and the Alternate Channel Interference (ALCI) rejection capability of the SRR.

In a typical super-heterodyne or direct conversion receiver, pass band signals are down-converted to mixers at intermediate or zero frequency, In the baseband. Placement of the filter in the SRR base receiver is power consuming due to operation at the RF frequency. In addition, the distinction within the output of the SRR depends on whether the input of the SRR is at a resonant frequency or whether it is at some frequency offset from the resonant frequency, preventing the application of the filtering technique at the output of the SRR. none.

이다. 이러한 3 샘플들에서, 샘플 세트로 기대되는(desired), 2개의 칩을 가장 잘 표현하는 2 샘플들이 존재한다. 샘플들의 모든 3가지 가능한 조합으로부터 기대되는 샘플 세트의 확인(identification)은 펄스 동기화에 의해 수행된다.Under sampling of the signal to improve interference rejection capability (e.g., chip rate of less than two times), other approaches may be used for interference rejection of better SRR, but synchronization of the SRR . ≪ / RTI > In addition, sampling of the received signal by using 1.5 times the chip rate (or any fractional sampling) can impose a definite challenge in terms of synchronization. A fractional quench rate of 1.5 times the chip rate provides a fractional number (1.5) sample per chip. That means, for all 2 chips, 3 samples (3 samples) are available at the receiver baseband. A possible number of 2 samples out of 3 possible to represent two chips is 3 or

to be. In these three samples, there are two samples that best represent the two chips desired in the sample set. The identification of the expected sample set from all three possible combinations of samples is performed by pulse synchronization.

Embodiments provide a method and system for synchronization within a super-playback receiver (SRR) when the input to the receiver baseband is sampled at 1.5 times the chip rate, which helps improve the interference rejection capability of the SRR. to provide.

The embodiment provides a mechanism for setting the binary speed to a value that is 1.5 times the chip rate of the incoming signal.

The embodiment provides a mechanism for the determination of metrics based on computing of association metrics, detection of start frame delimiters (SFDs) and association metrics.

The embodiment provides identification and selection of a best sample set (a set of desired samples) based on a decision metric for demodulating an input signal to perform pulse synchronization.

A method for performing pulse synchronization in a super regenerative receiver (SRR), the method comprising: setting a quench rate of the SRR to a predefined value, Wherein the signal comprises 1.5 times the chip rate of the incoming signal; Requesting an expected preamble sequence with an arbitrary set of samples; Requesting an expected Start Frame Delimiter (SFD) with all possible sample sets; Computing an association metric for each bit of the SFD during an SFD acquisition for all of the possible sample sets; Calculating a decision metric based on the association metrics when an SFD is detected for one or more sample sets and determining a best sample set for demodulating the input signal based on the decision metric, ).

The method for synchronization in the super-playback receiver further comprises associating the incoming signal with an expected sequence of any sample set of one of the base preambles at a 1.5-times sampling rate or a ?? .

The method for synchronization in the super-playback receiver may further include obtaining coarse timing synchronization by maximizing the association.

The calculating may be performed after the SFD detection is performed after integer multiples of preamble lengths of all the preamble in the samples.

The computing step may be to associate the samples of the received sequence with the respective SFD spread sequences corresponding to 0 and 1 for all possible sample sets.

Wherein the method for synchronization in the superplug receiver comprises determining a bit received as either 0 or 1 based on the association of each spread bit of the SFD with each sequence corresponding to 0 and 1 As shown in FIG.

The method for synchronization in the super-playback receiver may further comprise associating the detected SFD sequence for all sample sets with an expected SFD sequence and comparing the SFD sequence to a threshold value .

The calculating step may be a step in which the SFD detection is performed when at least one sample set provides an association of the at least one threshold value.

The method for synchronization in the super-playback receiver may further comprise after the SFD is sensed, computing the decision metric for the best sample set.

The decision metric may be computed based on the association metrics and the expected SFD bits.

The best sample set may be obtained by maximizing the decision metric.

A system for performing pulse synchronization in a super-playback receiver includes a processor and a memory coupled to the processor, the memory storing a plurality of modules executed by the processor, Setting a predefined value to a predefined value, said predefined value comprising a chip rate of 1.5 times the incoming signal; Requesting an expected preamble sequence with an arbitrary set of samples; Requesting an expected start frame delimiter (SFD) sequence with all possible sample sets; Computing an association metric for each bit of the SFD during SFD acquisition for all of the possible sample sets; If the SFD is detected for one or more sample sets, calculating a decision metric based on the association metrics and determining the best sample set to demodulate the input signal based on the decision metric .

The modules may be configured to associate the incoming signal with an expected sequence of any sample set of one of the base preambles at a 1.5 times sampling rate or at a rate.

The plurality of modules may be configured to obtain call timing synchronization by maximizing the association.

The calculating of the decision metric may be performed after the preamble length in the samples is multiplied by an integer.

Wherein the computing comprises: Samples of the received sequence may be associated with the respective SFD spread sequence corresponding to 0 and 1 for all possible sample sets.

The computing step may determine a received bit as either 0 or 1 based on the association of each spread bit of the SFD with the respective sequence corresponding to 0 and 1.

The computing may comprise associating the detected SFD sequence with an expected SFD sequence for all sample sets, and comparing the SFD sequence with a threshold value.

The calculating may comprise performing the SFD detection if at least one sample set provides an association of the one or more thresholds.

After the SFD is detected, the decision metric for the best sample set may be computed.

The decision metric may be computed based on the association metric and the expected SFD bits.

The best sample set may be obtained by maximizing the decision metric.

], 칩을 포함하는 베이스 프리앰블을 도시한다.
도 4c는, 일실시예에 따른,

로서 LSFD 비트를 포함하는 스프레드 SFD 구조를 도시한다.
도 4c는 일실시예에 따른,

인 경우,

가 SFD 스프레드 시퀀스이고

는

의 보수(complement) 중 하나인, 칩

으로서 'k번째' 스프레드 비트를 도시한다.
도 5는 일실시예에 따른, 칩 속도의 1.5배에서 샘플링 되는 슈퍼 재생 리시버 신호에서 동기화를 위한 방법의 흐름도이다.
도 6a 및 도 6b는, 슈퍼 재생 리시버에서 동기화를 수행하기 위한 방법(500)의 흐름도이다.
도 7는 일실시예에 따른, AWGN(Additive White Gaussian Noise) 수행을 위한 그래피컬 표현(representation)을 도시한다.
도 8 및 도 9는, 일실시예에 따른, ACI 수행을 위한 그래피컬 표현을 도시한다.
도 10은, 일실시예에 따른, 칩 속도의 1.5배에서 샘플링 되는 슈퍼 리시버 신호 내에서 동기화를 위한 방법 및 시스템을 구현하는 컴퓨팅 환경을 도시한다.Embodiments are described in detail with reference to the drawings, wherein like reference numerals refer to corresponding parts in the several views throughout the specification. The embodiments described herein will be better understood from the following description with reference to the drawings.
Figure 1 shows a block diagram of a Super Playback Receiver (SRR) known in the art.
Figure 2 illustrates details of modules in a system for synchronization in a super-playback receiver, in accordance with one embodiment.
Figures 3A-3C illustrate exemplary sample band combinations produced for an exemplary baseband pulse train, an exemplary phase period, and a number of chips, respectively, in accordance with one embodiment.
4A illustrates a diagram for a synchronization header including a base preamble and a spread SFD, in accordance with one embodiment.
FIG. 4B is a cross-sectional view of an embodiment of a " LBP "

], A base preamble including a chip.
Figure 4c illustrates, in accordance with one embodiment,

Lt; RTI ID = 0.0 > SFF < / RTI >
FIG. 4C is a cross-

Quot;

Is the SFD spread sequence

The

Which is one of the complement of the chip,

K " spread bits as < RTI ID = 0.0 >
5 is a flow diagram of a method for synchronization in a super-playback receiver signal sampled at 1.5 times the chip rate, in accordance with one embodiment.
6A and 6B are flow charts of a method 500 for performing synchronization in a super playback receiver.
FIG. 7 illustrates a graphical representation for performing Additive White Gaussian Noise (AWGN), according to one embodiment.
Figures 8 and 9 illustrate graphical representations for ACI performance, in accordance with one embodiment.
10 illustrates a computing environment implementing a method and system for synchronization within a super-receiver signal sampled at 1.5 times the chip rate, in accordance with one embodiment.

The embodiments and various aspects and their detailed advantages are more fully described with reference to the following non-limiting embodiments, which are illustrated in the details in the accompanying drawings and the following detailed description. In order not to unnecessarily obscure the embodiments, well-known components and processing techniques are omitted in the detailed description. These examples are intended to enable those skilled in the art to readily understand how the embodiments may be practiced and be practicable by those skilled in the art. Accordingly, the illustrations should not be construed as limiting the scope of the embodiments.

The embodiment discloses a system and method for synchronization within an SRR signal sampled at 1.5 times the chip rate. Within the SRR, the phase velocity is a predefined value (1.5 times the chip rate of the incoming signal). Request an expected preamble sequence with an arbitrary set of samples. SFD requests all possible sample sets. For each bit of SFD, the affinity metric is computed during SFD acquisition for all possible sample sets. If an SFD is detected for one or more sample sets, the decision metric is calculated based on the association metric. The best sample set is identified to demodulate the signal to further perform pulse synchronization from one or more sample sets.

에 의해 정의된다.In a super-playback receiver, the sensitivity curve is a damping function, in which s (t) is a function of the in-

Lt; / RTI >

인 경우,

에 의해 정의된다.The SRR's selectivity response is

Quot;

Lt; / RTI >

도

로서 기록될 수 있다. 따라서, 더 좁은(narrower) 선택도 응답은 특정한 펄스 형태 및 보드(baud) 속도를 위해

를 좁게(narrowing) 함으로써 획득될 수 있다.

및

는

의 푸리에 변형 함수 및 수신되는 신호의 펄스 형태

이다.Also,

Degree

Lt; / RTI > Thus, the narrower selectivity response may be used for a particular pulse shape and baud rate

By narrowing it.

And

The

Fourier transform function < RTI ID = 0.0 >

to be.

파라미터는 고정된다(are fixed). 신호를 샘플링 하거나 ??치 속도를 감소시키는 것은, SRR의 더 좁은(narrower) 주파수 응답을 야기하고, SRR의 간섭 거부 능력을 개선하는, 더 좁은

를 야기할 것이다.For a specific baud rate,

The parameters are fixed. Sampling the signal or reducing the phase velocity may result in a narrower frequency response of the SRR and a narrower,

.

The mechanism according to the embodiment uses sampling oversampling 1.5 times over 3 times oversampling. In general, a 1.5 times oversampling may be considered ideal for synchronization in the presence of a pulse shape. The pulse shape may be a Gaussian, a raised cosine, a triangle, or any other pulse shape. Also, a 1.5 times oversampling can be proposed by a system and method according to a methodology for handling synchronization by using spreading properties of a signal.

BRIEF DESCRIPTION OF THE DRAWINGS Referring now to the drawings, and in particular to FIGS. 1 to 10, like reference symbols describe various embodiments, which refer to forms corresponding consistently across the figures.

Figure 1 shows a block diagram of a Super Playback Receiver (SRR) known in the art. Referring to FIG. 1, there is shown a block diagram of a Super Playback Receiver (SRR) 100 known in the art. The SRR broadly includes a low pass filter 102, an envelope detector, an optional network, and an oscillator. Since there is no distinction in the output of the SRR depending on whether the input of the SRR is at a resonant frequency or at some frequency offset from the resonant frequency, smoothening), it is difficult to perform adjacent channel interference rejection.

Figure 2 illustrates details of modules in a system for synchronization in a super-playback receiver, in accordance with one embodiment. Referring to FIG. 2, the system 200 may include at least one processor 202, an input / output (I / O) interface 204 (configurable user interface), and a memory 208. The at least one processor 202 may be based on one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, state machines, logic circuits, and / Lt; RTI ID = 0.0 > signals. ≪ / RTI > Among other capabilities, at least one processor 202 is configured to fetch and execute computer-readable instructions stored in memory 208. The system 200 may be coupled with a Super Playback Receiver (SRR) or may be configured to reside within the SRR 100.

The I / O interface 204 may include various software and hardware interfaces, for example, a web interface, a graphical user interface, or other configurations. The I / O interface 204 may allow the system 200 to interact directly with the user or indirectly through the client device. The I / O interface 204 may also enable the system 200 to communicate with other computing devices, such as a web server and an external data server (not shown). The I / O interface 204 may facilitate multiple communications within a protocol type that includes a wide variety of network and wire networks (e.g., LAN, cable, etc.). The I / O interface 204 may include one or more ports to couple multiple devices to each other or to another server.

The modules include routines, programs, objects, components, data structures or other constructs that perform particular tasks, functions, or implement particular abstract data types. In one implementation, the module may include a rate module 208, an acquisition module 210, a computation module 212, and an identification module 214. The modules may include program or supplemental applications and coded instructions that are functions of the system 200.

In addition, among other configurations, data 216 serves as a repository for storing data generated by processing, receiving, and one or more modules. The data 216 may also include a database 218 and other data 220. Other data 220 may include data generated as a result of execution of one or more modules.

Figures 3A-3C illustrate exemplary sample band combinations produced for an exemplary baseband pulse train, an exemplary phase period, and a number of chips, respectively, in accordance with one embodiment. According to one embodiment, the tooth speed set module 208 sets the tooth speed to a predefined value. The predefined value can be set to 1.5 times the chip rate. Three samples are produced for every two chips. FIG. 3A illustrates an exemplary baseband pulse train, FIG. 3B illustrates exemplary production of a period of time for two chips, and FIG. 3C illustrates exemplary possible sample sets.

After setting the transmit rate to 1.5 by the transmit rate setting module 208, the spreading properties and SFD of the preamble may be used to handle synchronization.

After the setpoint speed is set, the learning module 210 requests an expected preamble sequence with an arbitrary set of samples. The preamble may include a plurality of '1' s and '0' s indicating the presence or absence of a signal, respectively.

4A to 4C are block diagrams showing a base preamble, a spread SFD, and a payload included in a synchronization header.

배에 의해 반복되는 베이스 프리앰블을 포함한다.4A illustrates a synchronization header, a base preamble, a spread SFD, and a payload, according to one embodiment. 4A, in an embodiment, the synchronization header is followed by a spread SFD,

And a bass preamble repeated by a multiplier.

], 칩을 포함하는 베이스 프리앰블을 도시한다. 도 4b를 참조하면, 베이스 프리앰블은

이고,

가 스프레드 코드로서 호출될 경우,

의 시퀀스를 포함할 수 있다. ??치 속도를 1.5로 세팅하는 것은 ??치 속도 세트 모듈(208)에 의해 수행된다. 습득 모듈(210)은 모든 가능한 샘플 세트를 구비한, 기대되는(expected) 시작 프레임 구분자(SFD: start Frame Delimiter) 시퀀스를 더 요청한다. SFD 감지는 모든 프리앰블 길이를 정수 배(integer multiples of preamble length)한 이후 수행된다.FIG. 4B is a cross-sectional view of an embodiment of a " LBP "

], A base preamble including a chip. Referring to FIG. 4B, the base preamble

ego,

Is called as a spread code,

≪ / RTI > Setting the tooth speed to 1.5 is performed by the tooth speed set module 208. The learning module 210 further requests an expected start frame delimiter (SFD) sequence with all possible sample sets. SFD detection is performed after all the preamble lengths are integer multiples of preamble length.

로서 LSFD 비트를 포함하는 스프레드 SFD 구조를 도시한다. 또한, 도 4c는 일실시예에 따른,

인 경우,

가 SFD 스프레드 시퀀스이고

는

의 보수(complement) 중 하나인, 칩

으로서 'k번째' 스프레드 비트를 도시한다. 도 4c를 참조하면, 스프레드 SFD는,

이고 LSF가 SFD 스프레딩을 위해 이용되는 스프레드 시퀀스의 길이인 경우, 좋은 연관관계 속성들 및 SFD 스프레드 시퀀스

에 의해 스프레딩 되는 각각의 비트를 가진 '0' 및 '1'의 임의의 시퀀스(LSFD길이의)로 구성된다.Figure 4c illustrates, in accordance with one embodiment,

Lt; RTI ID = 0.0 > SFF < / RTI > Figure 4c also illustrates a cross-

Quot;

Is the SFD spread sequence

The

Which is one of the complement of the chip,

K " spread bits as < RTI ID = 0.0 > Referring to FIG. 4C,

And the LSF is the length of the spread sequence used for SFD spreading, good association properties and the SFD spread sequence

(Of length LSFD) of '0' and '1' with each bit being spread by a predetermined number of bits.

Learning module 210 may further determine a further setting to correlate the incoming signal with an expected sequence of any sample set of one of the base preambles at a 1.5 times sample rate do. The acquisition module 210 acquires a sampling number (or timing information) that maximizes the association value.

The correlation of the incoming sequence is performed by an expected sequence of any particular set of samples.

, n=0,1,2, ..., 2*LBP-1, 이라 한다.According to one embodiment, the incoming samples comprise a 2-base preamble,

, n = 0, 1, 2, ..., 2 * LBP-1.

The expected sequence is as follows.

인 경우,

Quot;

를 최대화하는

은 "

"으로 지칭되는 콜스(coarse) 동기화를 제공한다.

To maximize

The "

Quot; coarse < / RTI > synchronization.

After the expected preamble sequence is requested, the computation model 212 computes an affinity metric for each bit of the SFD during SFD acquisition for all possible sample sets.

The computation model 212 determines the bits received as either 0 or 1 based on the association of each spread bit of the SFD with each of the sequences corresponding to 0 and 1. The computation model 212 may either correlate or receive samples for the spread bits of each SFD, with each of the expected sample sequences corresponding to '0' and '1' for all sample sets To the respective SFD spread sequences corresponding to 0 and 1 for all possible sample sets. The SFD sequence detected for all sample sets is associated with the expected SFD sequence. The association of the detected SFD and the expected SFD is compared with a threshold.

If at least one sample set provides an association of the one or more threshold values, the SFD detection may be performed.

If the SFD is detected for one or more sample sets, the computation model 212 based on the association metrics computes the decision metric. A sample set with the maximum decision metric is considered the best sample set (the desired sample set).

The decision metric is either computed or computed based on the association metrics and the expected SFD bits based on the association of the detected SFDs with the expected SFD bits, for all possible sample sets.

The confirmation module 214 is configured to identify the desired sample set (the best sample set) to demodulate the input signal. The desired sample is obtained by maximizing the decision metric.

The method of pulse synchronization is described in detail below.

In one embodiment, three types of spread sequences may be generated for the SFD bits:

Zero insertion at the beginning of a pair of all samples in a spread code with a first pair, which is the most significant two bits of the spread code.

- zero insertion between samples of a pair of samples with the first pair, the most significant two bits of the spread code.

- zero insertion at the end of a pair of samples with a first pair, the most significant two bits of the spread code.

For example, the spreading sequence of SFD is as follows:

and

,

and

,

The expected first spread sequence (the first two of the three selected samples) is shown in Table 3.

The expected second spread sequence (two extreme of the three selected samples) is shown in Table 4.

The expected third spread sequence (the last two of the three selected samples) is shown in Table 5.

'i' denotes the selected sample sequence, 'j' denotes '0' or '1', and 'k' denotes the number of bits in the SFD.

..., q = 1, ...,

,

..., q = 1, ...,

,

는 i번째 샘플 세트를 위해 추정되는 SFD의 m번째 비트이다.

Is the m-th bit of the SFD estimated for the i-th sample set.

The detected SFD is associated with the SFD to find the SFD pattern within the frame for every 'i'.

가 임의의 'i'에 대해 임계값을 초과하는 경우, SFD가 감지된다. SFD가 펄스 동기화를 결정하기 위해 감지되는 경우, 프리앰블 내에 포인트(또는 타이밍)에서 연관된 값에 기초하여 새로운 결정 메트릭이 컴퓨팅된다.

SFD < / RTI > is sensed if the threshold is exceeded for any 'i'. When the SFD is detected to determine pulse synchronization, a new decision metric is computed based on the associated value at the point (or timing) in the preamble.

를 최대화하는 'i'는 감지를 위해 최적의 샘플 시퀀스를 제공할 것이고, 'k'는 SFD 비트 수이고, 'i'는 샘플 세트의 인덱스이다.

를 최대화하는 'i'에 종속되는, 3개의 샘플들로부터(out of) 칩을 표시할 수 있고 페이로드(payload)의 감지에 이용될 수 있는(could be), 2개의 샘플이 결정된다.

'I' will provide the best sample sequence for detection, 'k' is the number of SFD bits, and 'i' is the index of the sample set.

The two samples that can be used to sense the payload and can display the chip out of the three samples that depend on the 'i' to maximize the payload are determined.

5 is a flow diagram of a method for synchronization in a super-playback receiver signal sampled at 1.5 times the chip rate, in accordance with one embodiment. Referring to FIG. 5, a method 500 for synchronization within a Super Playback Receiver (SRR) 100 is described. The method 500 may be performed by the system 200.

At step 502, the method 500 provides for setting the value of the SRR to a predefined value. The predefined value includes a value of 1.5 times the chip rate of the incoming signal. The gear speed can be set by the gear speed set module 208.

At step 504, the method 500 provides for the acquisition of the expected preamble sequence with any sample set.

At step 506, the method 500 provides for the acquisition of an expected start frame delimiter (SFD) sequence with all possible sample sets. The learning may be performed by the learning module 210.

At step 508, the method 500 provides a computation of the association metric for each bit of the SFD during SFD acquisition, for a predefined value of the possible sample sets.

At step 510, the method 500 provides a calculation of the decision metric based on the association metric when SFD is detected for one or more sample sets. The computation and computation may be performed by the computation module 212.

At step 512, the method 500 performs pulse synchronization by identifying the best sample set to demodulate the input signal based on the decision metric.

The various actions, acts, blocks, steps, and other arrangements within method 500 may be performed in the order shown, in a different order, or concurrently. Further, in accordance with some embodiments, some actions, acts, blocks, steps, and other configurations may be omitted, added, modified or skipped, and other configurations do not depart from the scope of the description .

6A and 6B are flow charts of a method 500 for performing synchronization in a super playback receiver. 6A and 6B, each step of the method 500 is described in detail.

Referring to FIG. 6A, in step 602, m is set to one, and reference_sample_sequence, Time-out, and SRR output samples are used as inputs.

의 컬렉션으로서 수신되는 신호 벡터를 획득한다.In step 604, the SRR output samples starting from the m < th > sample

Lt; RTI ID = 0.0 > a < / RTI >

어레이의 m번째 구성요소를 획득하기 위해 수행된다.In step 606, the association of the received signal vector, with the reference sample sequence,

Is performed to obtain the mth component of the array.

인지 여부를 판단한다(610).In step 608, m is incremented by one.

(610).

As a result of the determination, if m = time out, or if the correlation crosses the threshold, 'Timing' is obtained (611).

As a result of the determination, if m ≠ time out and the association does not intersect the threshold, step 604 is performed.

Referring to FIG. 6B, in step 612, q is set to one.

In step 614, the expected sequence described below is obtained.

of length

with elements denoted by

of length

with elements denoted by

At step 616, the association metric is computed as described below. 'i' denotes the selected sample sequence, 'j' denotes '0' or '1', and 'k' denotes the number of bits in the SFD.

,

,

,

,

At step 618, for every 'i' the SFD bit is estimated to be the kth component of the SFD. Estimates are as follows.

=

=

In step 620, the decision metric is calculated as follows.

(i는 H(i)를 최대화하는 i)

(i maximizes H (i)

In step 622, it is determined whether an SFD has been detected.

. 인지 여부를 판단한다(626). 판단 결과,

인 경우, 종료한다. 판단 결과,

가 아닌 경우, q를 1 증가시킨다(628). q를 1 증가시킨 후, 다시 단계(614)를 수행한다.As a result of the determination, if a SFD is detected, a desired sample ('i') for demodulating is selected (624). As a result of the determination, if the SFD is not detected,

. (626). As a result,

, The process ends. As a result,

, Then q is incremented by one (628). q is incremented by one, and then step 614 is performed again.

The various actions, acts, blocks, steps, and other arrangements within the method 500 may be performed in the indicated order, different orders, or concurrently. Also, in accordance with some embodiments, some actions, actives, blocks, steps, and other configurations may be omitted, added, modified or skipped, and other configurations do not depart from the scope of the description.

FIG. 7 is a block diagram of an additive white Gaussian noise (AWGN) system for three times oversampling and 1.5 times oversampling (as a ?? speed rate setting proposed by method 500 via system 200) ) ≪ / RTI > performance.

FIG. 8 is a graphical representation of ACI performance at a 5 MHz offset, for 1.5 times oversampling (as a separate detector velocity suggested by method 500 via system 200) and for 3 times oversampling, according to one embodiment. Graphical representation is shown.

9 is a block diagram of an embodiment of a system 100 for performing 1.5 times oversampling (as per phase value suggested by method 500 via system 200) and at 10 MHz offset for 3x oversampling, 0.0 > ACI < / RTI >

10 illustrates a computing environment for implementing a method and system for synchronization and interference rejection in a Super Playback Receiver (SRR), in accordance with one embodiment. 10, a computing environment 1002 includes a control unit 1004, an arithmetic logic unit (ALU) 1006, a memory 1010, a storage unit 1012, a plurality of networking devices 1016, And at least one processing unit 1004 on which a plurality of input output (I / O) devices 1014 are mounted. The processing unit 1008 is responsible for processing the instructions of the algorithm. The processing unit 1008 receives a command from the control unit to perform processing of the instruction. In addition, any logic and arithmetic operations associated with the execution of the instructions are computed using the ALU 1006.

The overall computing environment 1002 may include a plurality of homogeneous and / or heterogeneous cores, a plurality of different types of CPUs, special media, and other accelerators. The processing unit 908 is responsible for processing the instructions of the algorithm. Further, the plurality of processing units 908 may be located on a single chip or a chip over a plurality.

The algorithms, including the instructions and the code requested for implementation, are stored in the instruction and memory unit 1010 or on one or both sides of the storage 1012. Upon execution, the instructions may be fetched from the corresponding memory 1010 and / or storage 1012, and executed by the processing unit 1008.

In the case of any hardware that implements the various network devices 1016 or external I / O devices 1014, it may be coupled to a computing environment to support implementation through a networking unit and an I / O device unit.

In an embodiment, it may be implemented through at least one software program running on at least one hardware device, and may perform network management functions to control the components. The components shown in FIG. 2 include blocks that can be at least one of a hardware device or a combination of hardware devices and software modules.

The description of specific embodiments is provided to enable any person skilled in the art to make or use the present invention by applying the present knowledge to a variety of applications, such as particular embodiments, ), It is to be understood that such adaptations and modifications should be understood within the scope and meaning of equivalents of the disclosed embodiments. It is to be understood that the phraseology or employed terms are for the purpose of description and that the invention is not limited thereto. Therefore, it is to be understood that those skilled in the art will recognize that the embodiments may be practiced with modification within the spirit and scope of the embodiments described in the specification, although the preferred embodiments are described in the terminology.

Claims (22)

A method for performing pulse synchronization in a super regenerative receiver (SRR), the method comprising:
Setting a quench rate of the SRR to a predefined value, the predefined value comprising 1.5 times the chip rate of the incoming signal;
Requesting an expected preamble sequence with an arbitrary set of samples;
Requesting an expected Start Frame Delimiter (SFD) with all possible sample sets;
Computing an association metric for each bit of the SFD during an SFD acquisition for all of the possible sample sets;
If the SFD is detected for one or more sample sets, calculating a decision metric based on the association metrics; and
Identifying the best sample set to demodulate the input signal based on the decision metric,
/ RTI >
Methods for synchronization.
The method according to claim 1,
Associating an incoming signal with an expected sequence of any sample set of one of the base preambles at a 1.5-times sample rate or a ??
≪ / RTI >
Methods for synchronization.
3. The method of claim 2,
Obtaining coarse timing synchronization by maximizing the association;
≪ / RTI >
Methods for synchronization.
The method according to claim 1,
Wherein the calculating step comprises:
Wherein the SFD detection is performed after integer preamble lengths of all the preamble lengths in the samples.
Methods for synchronization.
The method according to claim 1,
Wherein the computing comprises:
Associating the samples of the received sequence with the respective SFD spread sequences corresponding to 0 and 1 for all possible sample sets
≪ / RTI >
Methods for synchronization.
6. The method of claim 5,
Determining a bit received as either 0 or 1 based on the association of each spread bit of the SFD with each of the sequences corresponding to 0 and 1
≪ / RTI >
Methods for synchronization.
5. The method of claim 4,
Associating the detected SFD sequence with an expected SFD sequence for all sample sets and
Comparing the SFD sequence with a threshold value
≪ / RTI >
Methods for synchronization.
The method according to claim 1,
Wherein the calculating step comprises:
Wherein at least one sample set provides an association of the one or more threshold values,
Methods for synchronization.
The method according to claim 1,
Wherein the decision metric comprises:
After the SFD is detected,
Methods for synchronization.
10. The method of claim 9,
Wherein the decision metric comprises:
Computing based on the association metrics and the expected SFD bits,
Methods for synchronization.
10. The method of claim 9,
The best sample set includes:
Wherein the decision metric is obtained by maximizing the decision metric,
Methods for synchronization.
A system for performing pulse synchronization in a super-playback receiver,
Processor and
A memory coupled to the processor, the memory storing a plurality of modules executed by the processor,
Said plurality of modules comprising:
Setting a trigger rate of the SRR to a predefined value, the predefined value comprising a chip rate of 1.5 times the incoming signal;
Requesting an expected preamble sequence with an arbitrary set of samples;
Requesting an expected start frame delimiter (SFD) sequence with all possible sample sets;
Computing an association metric for each bit of the SFD during SFD acquisition for all of the possible sample sets;
If the SFD is detected for one or more sample sets, calculating a decision metric based on the association metrics; and
Identifying the best sample set for demodulating the input signal based on the decision metric
Lt; RTI ID = 0.0 >
system.
13. The method of claim 12,
The modules,
The incoming signal is set to associate an incoming signal with an expected sequence of any sample set of one of the base preambles at a 1.5-times sampling rate or at a < RTI ID = 0.0 >
system.
14. The method of claim 13,
Wherein the plurality of modules comprises:
And to acquire call timing synchronization by maximizing the association,
system.
13. The method of claim 12,
Wherein the step of calculating the decision metric comprises:
Wherein the SFD detection is performed after an integer multiple of the preamble length in the samples,
system.
13. The method of claim 12,
Wherein the computing comprises:
Associating samples of a received sequence with the respective SFD spread sequences corresponding to 0 and 1 for all possible sample sets,
system.
17. The method of claim 16,
Determining a bit to be received as either 0 or 1 based on the association of each spread bit of the SFD with the respective sequence corresponding to 0 and 1,
system.
17. The method of claim 16,
The above-
Associating the detected SFD sequence with the expected SFD sequence for all sample sets,
Comparing the SFD sequence with a threshold value,
system.
13. The method of claim 12,
Wherein the calculating step comprises:
Wherein at least one sample set provides an association of the one or more threshold values,
system.
13. The method of claim 12,
Wherein the decision metric comprises:
If the SFD is sensed and computed,
system.
21. The method of claim 20,
Wherein the decision metric comprises:
Computing based on the association metric and the expected SFD bits,
system.
21. The method of claim 20,
The best sample set includes:
Wherein the decision metric is obtained by maximizing the decision metric,
system.

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