KR102434593B1 - System and method for synchronization and interference rejection in super regenerative receiver - Google Patents

Abstract

A system and method for synchronization in an SRR signal sampled at 1.5 times the chip rate. The method includes setting the trigger rate of the SRR to a predefined value. The predefined value includes a chip rate of 1.5 times the incoming signal. The method also includes requesting an expected preamble sequence, with any sample set, and requesting an expected starting frame delimiter (SFD) sequence for all possible sample sets. The method also includes computing an association metric for each bit of the SFD during SFD acquisition for all possible sample sets and determining based on the association metric if an SFD is sensed for one or more sample sets. calculating a metric. The method also includes performing pulse synchronization by identifying a best sample set to demodulate the input signal based on the decision metric.

Description

System and method for synchronization and interference rejection in super regenerative receiver

Super Regenerative Receivers (SRRs) are disclosed. Specifically, a technique related to synchronization in SRR is disclosed.

Super Regenerative Receivers (SRRs) are low-power receivers used in wireless sensor networks. In a wireless sensor network (free license ISM band), many nodes coexist in the same frequency band. The coexistence of communication nodes based on SRR is affected by low Adjacent Channel Interference (ACI) and Alternate Channel Interference (ALCI) rejection capability of SRR.

In a typical super-heterodyne or direct conversion receiver, the pass band signal is down-converted to an intermediate frequency or zero frequency by mixers, improving interference rejection capability. to be filtered within the baseband. The positioning of the filter in the SRR base receiver is power consuming because of its operation at the RF frequency. Also, there is a distinction in the output of the SRR depending on whether the input of the SRR is at a resonant frequency or at some frequency offset from the resonant frequency, which prevents the application of filtering techniques at the output of the SRR. none.

이다. 이러한 3 샘플들에서, 샘플 세트로 기대되는(desired), 2개의 칩을 가장 잘 표현하는 2 샘플들이 존재한다. 샘플들의 모든 3가지 가능한 조합으로부터 기대되는 샘플 세트의 확인(identification)은 펄스 동기화에 의해 수행된다.Under the sampling of the signal to improve the interference rejection capability (eg less than twice the chip speed), other approaches can be used for better interference rejection of the SRR, but the synchronization of the SRR under the sampling of the signal may interfere with Also, sampling the signal received by using 1.5 times the chip rate (or any fractional sampling) can pose a definite challenge in terms of synchronization. A fractional quench rate of 1.5 times the chip rate provides a fractional number (1.5) samples for each chip. That means, for all 2 chips, 3 samples are available at the receiver baseband. A possible number of 2 samples out of 3 samples, capable of representing 2 chips, is 3 or

to be. In these 3 samples, there are 2 samples that best represent 2 chips, desired as a sample set. Identification of the expected sample set from all three possible combinations of samples is performed by pulse synchronization.

An embodiment provides a method and system for synchronization within a super regenerative receiver (SRR) when the input to the receiver baseband is sampled at 1.5 times the chip rate, helping to improve the interference rejection capability of the SRR. to provide.

An embodiment provides a mechanism for setting the trigger rate to a value of 1.5 times the chip rate of the incoming signal.

An embodiment provides a mechanism for computing an affinity metric, detecting a Start Frame Delimiter (SFD), and determining a metric based on an affinity metric.

An embodiment provides identification and selection of a best sample set (desired sample set) based on a decision metric for demodulating an input signal to perform pulse synchronization.

A method for performing pulse synchronization in a super regenerative receiver (SRR) comprises the steps of setting a quench rate of the SRR to a predefined value - the predefined value is includes 1.5 times the chip rate of the coming signal -; requesting an expected preamble sequence with an arbitrary set of samples; requesting an expected Start Frame Delimiter (SFD) with all possible sample sets; during SFD acquisition for all possible sample sets, computing an association metric for each bit of the SFD; If SFD is sensed for one or more sample sets, calculating a decision metric based on the correlation metrics and identifying a best sample set for demodulating an input signal based on the decision metric. ), including the step of

The method for synchronization in the super playback receiver may further comprise associating an incoming signal with an expected sequence of an arbitrary set of samples of one of a base preamble at a 1.5x sampling rate or an unset rate. can

The method for synchronization in the super playback receiver may further include obtaining coarse timing synchronization by maximizing the association.

The calculating may be a step in which the SFD detection is performed after all preamble lengths in the samples are multiplied by integer multiples of preamble length.

The computing may be associating the samples of the received sequence with the respective SFD spread sequence corresponding to 0 and 1 for all possible sample sets.

The method for synchronization in the super playback receiver comprises: determining a bit to be received as either a 0 or a 1 based on the association of each spread bit of the SFD with the respective sequence corresponding to 0 and 1. may further include.

The method for synchronization in the super reproduction receiver may further comprise associating the sensed SFD sequence with an expected SFD sequence for all sample sets and comparing the SFD sequence to a threshold. .

The calculating may be a step in which the SFD sensing is performed when at least one sample set provides a correlation between the one or more threshold values.

The method for synchronization in the super reproduction receiver may further include, after the SFD is sensed, computing the decision metric for the best sample set.

The decision metric may be computed based on the association metrics and expected SFD bits.

The best sample set may be obtained by maximizing the decision metric.

A system for performing pulse synchronization in a super regenerative receiver, comprising: a processor and a memory coupled to the processor, the memory storing a plurality of modules executed by the processor, the plurality of modules comprising the SRR setting the launch rate of n to a predefined value, said predefined value comprising a chip rate of 1.5 times the incoming signal; requesting an expected preamble sequence with an arbitrary set of samples; requesting an expected start frame delimiter (SFD) sequence with all possible sample sets; computing an association metric for each bit of the SFD during SFD acquisition for all possible sample sets; If SFD is sensed for one or more sample sets, calculating a decision metric based on the correlation metrics and identifying a best sample set for demodulating an input signal based on the decision metric. includes

The modules may be configured to associate an incoming signal with an expected sequence of any set of samples, either a base preamble at a 1.5x sampling rate or an unset rate.

The plurality of modules may be configured to obtain collision timing synchronization by maximizing the association.

In the calculating of the decision metric, the SFD sensing may be performed after multiplying the length of the preamble in the samples by an integer.

The computing step may associate the samples of the received sequence with the respective SFD spread sequence corresponding to 0 and 1 for all possible sample sets.

The computing may determine a bit to be received as either a 0 or a 1 based on the association of each spread bit of the SFD with the respective sequence corresponding to 0 and 1.

The computing may be performed by associating the sensed SFD sequence with an expected SFD sequence for all sample sets, and comparing the SFD sequence with a threshold value.

In the calculating, when at least one sample set provides a correlation between the one or more threshold values, the SFD sensing may be performed.

After the SFD is sensed, the decision metric for the best sample set may be computed.

The decision metric may be computed based on the association metric and expected SFD bits.

The best sample set may be obtained by maximizing the decision metric.

], 칩을 포함하는 베이스 프리앰블을 도시한다.
도 4c는, 일실시예에 따른,

로서 LSFD 비트를 포함하는 스프레드 SFD 구조를 도시한다.
도 4c는 일실시예에 따른,

인 경우,

가 SFD 스프레드 시퀀스이고

는

의 보수(complement) 중 하나인, 칩

으로서 'k번째' 스프레드 비트를 도시한다.
도 5는 일실시예에 따른, 칩 속도의 1.5배에서 샘플링 되는 슈퍼 재생 리시버 신호에서 동기화를 위한 방법의 흐름도이다.
도 6a 및 도 6b는, 슈퍼 재생 리시버에서 동기화를 수행하기 위한 방법(500)의 흐름도이다.
도 7는 일실시예에 따른, AWGN(Additive White Gaussian Noise) 수행을 위한 그래피컬 표현(representation)을 도시한다.
도 8 및 도 9는, 일실시예에 따른, ACI 수행을 위한 그래피컬 표현을 도시한다.
도 10은, 일실시예에 따른, 칩 속도의 1.5배에서 샘플링 되는 슈퍼 리시버 신호 내에서 동기화를 위한 방법 및 시스템을 구현하는 컴퓨팅 환경을 도시한다.Embodiments are described in detail with reference to the drawings, and throughout the specification the same reference numerals refer to corresponding parts in the various drawings. Embodiments described herein will be better understood from the following description with reference to the drawings.
1 shows a block diagram of a super regenerative receiver (SRR) known in the art.
Figure 2 shows details of a module in a system for synchronization in a super playback receiver, according to one embodiment;
3A-3C show exemplary baseband pulse trains, exemplary quench periods, and exemplary sample combinations produced for each number of chips, according to one embodiment.
4A shows a diagram for a synchronization header including a base preamble and a spread SFD, according to one embodiment.
Figure 4b, according to an embodiment, 'LBP' length [

], shows the base preamble including the chip.
Figure 4c, according to one embodiment,

A spread SFD structure including LSFD bits is shown.
Figure 4c is according to one embodiment,

If ,

is the SFD spread sequence and

Is

One of the complements of

as 'kth' spread bit.
5 is a flow diagram of a method for synchronization in a super playback receiver signal sampled at 1.5 times the chip rate, according to one embodiment.
6A and 6B are flow diagrams of a method 500 for performing synchronization at a super playback receiver.
7 illustrates a graphical representation for performing Additive White Gaussian Noise (AWGN), according to an embodiment.
8 and 9 show graphical representations for performing ACI, according to an embodiment.
10 illustrates a computing environment implementing a method and system for synchronization within a super receiver signal sampled at 1.5 times the chip rate, according to one embodiment.

Embodiments and various forms and detailed advantages thereof are more fully described with reference to non-limiting embodiments of the invention, which are shown within the details within the accompanying drawings and the following detailed description. In order not to unnecessarily obscure the embodiments, well-known components and processing techniques are omitted from the detailed description. These examples are merely provided to enable those skilled in the art to readily understand and practice how the embodiments may be practiced. Accordingly, the examples should not be construed as limiting the scope of the embodiments.

An embodiment discloses a system and method for synchronization in an SRR signal sampled at 1.5 times the chip rate. Within SRR, the trigger rate is a predefined value (1.5 times the chip rate of the incoming signal). Request an expected preamble sequence with an arbitrary set of samples. SFD further requests all possible sample sets. For each bit of SFD, an association metric is computed during SFD acquisition for all possible sample sets. When an SFD is detected for one or more sample sets, a decision metric is calculated based on the association metric. A best sample set is identified to demodulate the signal to further perform pulse synchronization from one or more sample sets.

에 의해 정의된다.In a super regenerative receiver, the sensitivity curve is a function of damping, where s(t) is a function of the unset signal in turn.

is defined by

인 경우,

에 의해 정의된다.The selectivity response of SRR is

If ,

is defined by

도

로서 기록될 수 있다. 따라서, 더 좁은(narrower) 선택도 응답은 특정한 펄스 형태 및 보드(baud) 속도를 위해

를 좁게(narrowing) 함으로써 획득될 수 있다.

및

는

의 푸리에 변형 함수 및 수신되는 신호의 펄스 형태

이다.In addition,

do

can be recorded as Thus, a narrower selectivity response is required for a particular pulse shape and baud rate.

It can be obtained by narrowing

and

Is

Fourier transform function of and the pulse shape of the received signal

to be.

파라미터는 고정된다(are fixed). 신호를 샘플링 하거나 ??치 속도를 감소시키는 것은, SRR의 더 좁은(narrower) 주파수 응답을 야기하고, SRR의 간섭 거부 능력을 개선하는, 더 좁은

를 야기할 것이다.For a specific baud rate,

Parameters are fixed. Sampling the signal or reducing the set-up rate results in a narrower frequency response of the SRR and narrower frequency response, which improves the ability of the SRR to reject interference.

will cause

A mechanism according to an embodiment uses sampling 1.5 times oversampling rather than 3 times oversampling. In general, 1.5x oversampling can be considered ideal for synchronization in the presence of pulse shapes. The pulse shape can be a Gaussian, raised cosine, triangle, or any other pulse shape. In addition, 1.5x oversampling may be proposed by the system and method according to the methodology for handling synchronization by using the spreading properties of the signal.

Referring to the drawings, particularly FIGS. 1-10 , like reference numerals describe various embodiments, in which like reference numerals consistently refer to corresponding forms throughout.

1 shows a block diagram of a super regenerative receiver (SRR) known in the art. 1, there is shown a block diagram of a super regenerative receiver (SRR) 100 known in the art. The SRR broadly includes a low pass filter 102 , an envelope detector, an optional network and an oscillator. Since there is no distinction in the output of the SRR depending on whether the input of the SRR is at the resonant frequency or at some frequency offset from the resonant frequency, this low-pass filter It is useful only for smoothening), and it is difficult to perform adjacent channel interference rejection.

Figure 2 shows details of a module in a system for synchronization in a super playback receiver, according to one embodiment; Referring to FIG. 2 , the system 200 may include at least one processor 202 , an input/output (I/O) interface 204 (a configurable user interface), and a memory 208 . The at least one processor 202 may be based on one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, state machines, logic circuits, and/or operating instructions. It can be implemented with any devices that produce signals. Among other capabilities, the at least one processor 202 is configured to fetch and execute computer readable instructions stored in the memory 208 . The system 200 may be coupled to a super regenerative receiver (SRR) or configured to exist within the SRR (100).

The I/O interface 204 may include a variety of software and hardware interfaces, such as a web interface, a graphical user interface, or other configurations. The I/O interface 204 may allow the system 200 to interact directly with a user or indirectly through a client device. I/O interface 204 may also enable system 200 to communicate with other computing devices, such as web servers and external data servers (not shown). The I/O interface 204 may facilitate a plurality of communications within a protocol type including a wide variety of networks and wire networks (eg, LAN, cable, etc.). I/O interface 204 may include one or more ports for connecting multiple devices to each or another server.

The modules include routines, programs, objects, components, data structures, or other constructs that perform particular tasks, functions, or implement particular abstract data types. In one implementation method, the modules may include a launch speed module 208 , an acquisition module 210 , a computation module 212 , and a validation module 214 . The modules may include programs or supplemental applications and coded instructions that are functions of the system 200 .

Also, among other configurations, data 216 serves as a repository for processing, receiving, and storing data generated by one or more modules. Data 216 may also include database 218 and other data 220 . Other data 220 may include data generated as a result of execution of one or more modules.

3A-3C show exemplary baseband pulse trains, exemplary quench periods, and exemplary sample combinations produced for each number of chips, according to one embodiment. According to one embodiment, the set-up speed set module 208 sets the set-up speed to a predefined value. The predefined value can be set to 1.5 times the chip speed. Three samples are produced for every two chips. Fig. 3a shows an exemplary baseband pulse train, Fig. 3b shows an exemplary production of a quench period for two chips, and Fig. 3c shows exemplary possible sample sets.

After setting the set-up rate to 1.5 by the set-up speed set module 208, the spreading properties and SFD of the preamble can be used to handle the synchronization.

After the training rate is set, the acquisition module 210 requests the expected preamble sequence with an arbitrary set of samples. The preamble may include a plurality of '1' and '0' indicating the presence and absence of a signal, respectively.

4A to 4C are block diagrams illustrating a base preamble and a spread SFD included in a synchronization header, and a payload.

배에 의해 반복되는 베이스 프리앰블을 포함한다.4A illustrates a synchronization header, a base preamble, a spread SFD, and a payload, according to one embodiment. Referring to FIG. 4A , in an embodiment, the synchronization header is followed by the spread SFD.

Contains the base preamble repeated by the double.

], 칩을 포함하는 베이스 프리앰블을 도시한다. 도 4b를 참조하면, 베이스 프리앰블은

이고,

가 스프레드 코드로서 호출될 경우,

의 시퀀스를 포함할 수 있다. ??치 속도를 1.5로 세팅하는 것은 ??치 속도 세트 모듈(208)에 의해 수행된다. 습득 모듈(210)은 모든 가능한 샘플 세트를 구비한, 기대되는(expected) 시작 프레임 구분자(SFD: start Frame Delimiter) 시퀀스를 더 요청한다. SFD 감지는 모든 프리앰블 길이를 정수 배(integer multiples of preamble length)한 이후 수행된다.Figure 4b, according to an embodiment, 'LBP' length [

], shows the base preamble including the chip. 4B, the base preamble is

ego,

is called as spread code,

may contain a sequence of Setting the set-up speed to 1.5 is performed by the set-up speed set module 208 . The acquisition module 210 further requests an expected start frame delimiter (SFD) sequence with all possible sample sets. SFD detection is performed after all preamble lengths are multiplied by integer multiples of preamble length.

로서 LSFD 비트를 포함하는 스프레드 SFD 구조를 도시한다. 또한, 도 4c는 일실시예에 따른,

인 경우,

가 SFD 스프레드 시퀀스이고

는

의 보수(complement) 중 하나인, 칩

으로서 'k번째' 스프레드 비트를 도시한다. 도 4c를 참조하면, 스프레드 SFD는,

이고 LSF가 SFD 스프레딩을 위해 이용되는 스프레드 시퀀스의 길이인 경우, 좋은 연관관계 속성들 및 SFD 스프레드 시퀀스

에 의해 스프레딩 되는 각각의 비트를 가진 '0' 및 '1'의 임의의 시퀀스(LSFD길이의)로 구성된다.Figure 4c, according to one embodiment,

A spread SFD structure including LSFD bits is shown. In addition, Figure 4c according to an embodiment,

If ,

is the SFD spread sequence and

Is

One of the complements of

as 'k'th spread bit. Referring to Figure 4c, the spread SFD is,

and LSF is the length of the spread sequence used for SFD spreading, good association properties and SFD spread sequence

Consists of a random sequence (of LSFD length) of '0' and '1' with each bit spread by .

The acquisition module 210 further configures the incoming signal to correlate with an expected sequence of any set of samples in one of the base preambles at a 1.5x sampling rate (or accretion rate). do. The acquisition module 210 acquires a sampling number (or timing information) that maximizes the correlation value.

Correlation of the incoming sequence is performed by the expected sequence of any particular set of samples.

, n=0,1,2, ..., 2*LBP-1, 이라 한다.According to one embodiment, the incoming samples include a 2 base preamble,

Let , n=0,1,2, ..., 2*LBP-1,

The expected sequence is said to be

인 경우,

If ,

를 최대화하는

은 "

"으로 지칭되는 콜스(coarse) 동기화를 제공한다.

to maximize

silver "

provides a coarse synchronization referred to as ".

After the expected preamble sequence is requested, the computation model 212 computes an association metric for each bit of the SFD during SFD acquisition for all possible sample sets.

The computation model 212 determines which bit is received as either a 0 or a 1 based on the association of each spread bit of the SFD with the respective sequence corresponding to 0 and 1. Computational model 212 correlates or receives samples for the spread bit of each SFD, with each expected sequence of samples corresponding to '0' and '1' for all sample sets. Associates the samples of the given sequence with the respective SFD spread sequence corresponding to 0 and 1 for all possible sample sets. The detected SFD sequence for all sample sets is associated with the expected SFD sequence. The association of the sensed SFD and the expected SFD is compared to a threshold.

When at least one sample set provides the correlation of the one or more threshold values, it may be said that the SFD sensing is performed.

When an SFD is sensed for one or more sets of samples, a computational model 212 based on the association metrics computes a decision metric. The sample set with the maximum decision metric is considered the best sample set (desired sample set).

A decision metric is computed based on the association of the sensed SFD with the expected SFD bits, or based on the association metrics and the expected SFD bits, for all possible sample sets.

The validation module 214 is configured to identify a desired sample set (best sample set) for demodulating the input signal. Desired samples are obtained by maximizing the decision metric.

The method of pulse synchronization is described in detail below.

In one embodiment, three types of spread sequences may be generated for SFD bits:

- a zero insertion at the beginning of a pair of all samples in the spread code with the first pair, which is the most significant 2 bits of the spread code.

- Insertion of zeros between a pair of samples with a first pair, which is the most significant 2 bits of the spread code.

- Insertion of zeros at the end of the pair of samples with the first pair, which is the most significant 2 bits of the spread code.

For example, let's say the spread sequence of SFD is:

and

,

and

,

The expected first spread sequences (the first two of the three selected samples) are shown in Table 3.

The expected second spread sequence (extreme two of the three selected samples) is shown in Table 4.

The expected third spread sequence (last two of the three selected samples) is shown in Table 5.

'i' is the selected sample sequence, 'j' indicates '0' or '1', and 'k' is the number of bits in the SFD.

..., q = 1, ...,

,

..., q = 1, ...,

,

는 i번째 샘플 세트를 위해 추정되는 SFD의 m번째 비트이다.

is the m-th bit of the SFD estimated for the i-th sample set.

The detected SFD is associated with the SFD to find the SFD pattern within the frame for every 'i'.

가 임의의 'i'에 대해 임계값을 초과하는 경우, SFD가 감지된다. SFD가 펄스 동기화를 결정하기 위해 감지되는 경우, 프리앰블 내에 포인트(또는 타이밍)에서 연관된 값에 기초하여 새로운 결정 메트릭이 컴퓨팅된다.

SFD is sensed if n exceeds the threshold for any 'i'. When SFD is sensed to determine pulse synchronization, a new decision metric is computed based on the associated value at a point (or timing) in the preamble.

를 최대화하는 'i'는 감지를 위해 최적의 샘플 시퀀스를 제공할 것이고, 'k'는 SFD 비트 수이고, 'i'는 샘플 세트의 인덱스이다.

를 최대화하는 'i'에 종속되는, 3개의 샘플들로부터(out of) 칩을 표시할 수 있고 페이로드(payload)의 감지에 이용될 수 있는(could be), 2개의 샘플이 결정된다.

'i' that maximizes 'i' will provide the optimal sample sequence for detection, 'k' is the number of SFD bits, and 'i' is the index of the sample set.

Two samples are determined, which could represent the chip out of and be used for detection of the payload, subject to 'i' that maximizes .

5 is a flow diagram of a method for synchronization in a super playback receiver signal sampled at 1.5 times the chip rate, according to one embodiment. Referring to FIG. 5 , a method 500 for synchronization within a super regenerative receiver (SRR) 100 is described. Method 500 may be performed by system 200 .

At step 502, the method 500 provides for setting the trigger rate of the SRR to a predefined value. The predefined value includes 1.5 times the chip rate of the incoming signal. The set-up speed may be set by the set-up speed set module 208 .

At step 504, the method 500 provides for acquisition of an expected preamble sequence with an arbitrary set of samples.

At step 506, the method 500 provides for acquisition of an expected starting frame delimiter (SFD) sequence with all possible sample sets. The acquisition may be performed by the acquisition module 210 .

At step 508, the method 500 provides a computation of an association metric for each bit of the SFD during SFD acquisition, for predefined values of possible sample sets.

At step 510, the method 500 provides calculation of a decision metric based on the correlation metric when SFDs have been detected for one or more sets of samples. The computation and calculation may be performed by the computation module 212 .

At step 512, the method 500 performs pulse synchronization by identifying the best sample set to demodulate the input signal based on the decision metric.

The various actions, acts, blocks, steps, and other components within method 500 may be performed in the order indicated, in a different order, or concurrently. Further, according to some embodiments, some actions, acts, blocks, steps and other components may be omitted, added, modified, or skipped, and other components do not depart from the scope of the description in the specification. .

6A and 6B are flow diagrams of a method 500 for performing synchronization at a super playback receiver. 6A and 6B , each step of the method 500 is described in detail.

Referring to FIG. 6A , in step 602 , m is set to 1, and the reference_sample_sequence, Time-out and SRR output samples are used as inputs.

의 컬렉션으로서 수신되는 신호 벡터를 획득한다.In step 604, the SRR output sample starting from the mth sample is

Obtain the received signal vector as a collection of .

어레이의 m번째 구성요소를 획득하기 위해 수행된다.In step 606, the correlation of the received signal vector with the reference sample sequence is:

is performed to obtain the mth element of the array.

인지 여부를 판단한다(610).In step 608, m is incremented by one.

It is determined whether it is recognized (610).

As a result of the determination, when m = time out or the correlation crosses the threshold, 'Timing' is acquired (611).

As a result of the determination, if m ≠ time out and the correlation does not cross the threshold, step 604 is performed.

Referring to FIG. 6B , in step 612 , q is set to 1.

In step 614, the expected sequence, described below, is obtained.

of length

with elements denoted by

of length

with elements denoted by

At step 616, the association metric is computed as described below. 'i' is the selected sample sequence, 'j' indicates '0' or '1', and 'k' is the number of bits in the SFD.

,

,

,

,

In step 618, the SFD bit is assumed to be the kth component of the SFD, for every 'i'. The estimate is as follows.

=

=

In step 620, the decision metric is calculated as follows.

(i는 H(i)를 최대화하는 i)

(i is the i that maximizes H(i))

In step 622, it is determined whether an SFD has been detected.

. 인지 여부를 판단한다(626). 판단 결과,

인 경우, 종료한다. 판단 결과,

가 아닌 경우, q를 1 증가시킨다(628). q를 1 증가시킨 후, 다시 단계(614)를 수행한다.As a result of the determination, when the SFD is detected, a desired sample ('i') for demodulation is selected ( 624 ). As a result of the judgment, if the SFD is not detected,

. It is determined whether it is recognized (626). As a result of judgment,

If yes, exit. As a result of judgment,

If not, q is increased by 1 (628). After increasing q by 1, step 614 is performed again.

The various actions, acts, blocks, steps, and other components within method 500 may be performed in the order indicated, in a different order, or concurrently. Further, according to some embodiments, some actions, acts, blocks, steps, and other components may be omitted, added, modified, or skipped, and other components do not depart from the scope of the description in the specification.

7 shows additive white Gaussian noise (AWGN) for 1.5x oversampling (as an unset rate setting suggested by method 500 via system 200) and 3x oversampling, according to one embodiment. ) shows a graphical representation of the performance.

8 is a diagram of ACI performance at a 5 MHz offset for 1.5x oversampling (as an individual quench rate suggested by method 500 over system 200) and 3x oversampling, according to one embodiment. A graphical representation is shown.

9 is a diagram at 10 MHz offset for 1.5x oversampling (as per set rate suggested by method 500 over system 200) and 3x oversampling, according to one embodiment. A graphical representation of the ACI performance is shown.

10 illustrates a computing environment implementing a method and system for synchronization and interference rejection in a super replay receiver (SRR), according to one embodiment. Referring to FIG. 10 , the computing environment 1002 includes a control unit 1004 , an arithmetic logic unit (ALU) 1006 , a memory 1010 , a storage unit 1012 , and a plurality of networking devices 1016 . and at least one processing unit 1004 mounted with a plurality of input/output (I/O) devices 1014 . The processing unit 1008 is responsible for processing the instructions of the algorithm. The processing unit 1008 receives commands from the control unit to perform instruction processing. Also, any logical and arithmetic operations associated with the execution of the instructions are computed using the ALU 1006 .

The overall computing environment 1002 may comprise a plurality of homogeneous and/or heterogeneous cores, a plurality of different kinds of CPUs, specialized media and other accelerators. The processing unit 908 is responsible for processing the instructions of the algorithm. Also, the plurality of processing units 908 may be located on a single chip or on more than one chip.

The algorithm, including instructions and codes requested for implementation, is stored in one or both of the instructions and memory unit 1010 or storage 1012 . Upon execution, the instructions may be fetched from the corresponding memory 1010 and/or storage 1012 and executed by the processing unit 1008 .

Any hardware implementing various network devices 1016 or external I/O devices 1014 may be coupled to the computing environment to support implementation via networking units and I/O device units.

In an embodiment, it may be implemented through at least one software program executed on at least one hardware device, and may perform network management functions to control components. The components shown in FIG. 2 include a block which may be at least one of a hardware device or a combination of hardware devices and a software module.

The description of specific embodiments describes the general nature of embodiments in which others are possible, by applying current knowledge, easily transforming and/or adapting for various applications such as specific embodiments without departing from the generic concept. ), it is meant that such adaptations and variations are to be understood within the scope and meaning of equivalents of the disclosed embodiments. It is to be understood that the usage or employed term is for the purpose of description and the invention is not limited thereto. Therefore, although the embodiment has been described in terms of the preferred embodiment, those skilled in the art will recognize that the embodiment can be practiced with modifications within the spirit or scope of the embodiment described in the specification.

Claims (22)

In a method for performing pulse synchronization in a super regenerative receiver (SRR),
setting a quench rate of the SRR to a predefined value, the predefined value comprising 1.5 times the chip rate of the incoming signal;
requesting an expected preamble sequence with an arbitrary set of samples;
requesting an expected Start Frame Delimiter (SFD) sequence with all possible sample sets;
computing an association metric for each bit of the SFD during acquisition of an SFD for all possible sample sets;
if SFD is sensed for one or more sample sets, calculating a decision metric based on the correlation metrics; and
identifying a best sample set to demodulate an input signal based on the decision metric;
containing,
How to synchronize.
According to claim 1,
associating the incoming signal with an expected sequence of an arbitrary set of samples of one of the base preambles at either the 1.5x sampling rate or the unset rate.
further comprising,
How to synchronize.
3. The method of claim 2,
obtaining coarse timing synchronization by maximizing the association
further comprising,
How to synchronize.
According to claim 1,
The calculating step is
The detection of the SFD is performed after integer multiples of preamble length in all samples.
How to synchronize.
According to claim 1,
The computing step is
associating the samples of the received sequence with the respective SFD spread sequence corresponding to 0 and 1 for all possible sample sets;
further comprising,
How to synchronize.
6. The method of claim 5,
determining the bit to be received as either 0 or 1 based on the association of each spread bit of the SFD with the respective sequence corresponding to 0 and 1;
further comprising,
How to synchronize.
5. The method of claim 4,
associating the sensed SFD sequence with an expected SFD sequence for all sample sets; and
comparing the SFD sequence to a threshold
further comprising,
How to synchronize.
According to claim 1,
The calculating step is
If at least one sample set provides an association of the one or more threshold values, the detection of the SFD is performed,
How to synchronize.
According to claim 1,
The decision metric is
After the SFD is detected, it is computed,
How to synchronize.
10. The method of claim 9,
The decision metric is
computed based on the association metrics and expected SFD bits;
How to synchronize.
10. The method of claim 9,
The best sample set is
obtained by maximizing the decision metric,
How to synchronize.
A system for performing pulse synchronization in a super regenerative receiver (SRR), comprising:
processor and
a memory coupled to the processor, the memory storing a plurality of modules executed by the processor;
The plurality of modules include:
setting a trigger rate of the super regenerative receiver (SRR) to a predefined value, the predefined value including a chip rate of 1.5 times the incoming signal;
requesting an expected preamble sequence with an arbitrary set of samples;
requesting an expected start frame delimiter (SFD) sequence with all possible sample sets;
computing an association metric for each bit of the SFD during SFD acquisition for all possible sample sets;
if SFD is sensed for one or more sample sets, calculating a decision metric based on the correlation metrics; and
identifying a best set of samples to demodulate an input signal based on the decision metric;
set to include
system.
13. The method of claim 12,
The modules are
configured to associate the incoming signal with an expected sequence of any set of samples of one of the base preambles at either a 1.5x sampling rate or an unset rate;
system.
14. The method of claim 13,
The plurality of modules are
configured to obtain call timing synchronization by maximizing the association,
system.
13. The method of claim 12,
Calculating the decision metric comprises:
The detection of the SFD is performed after multiplying the length of the preamble in the samples by an integer.
system.
13. The method of claim 12,
The computing step is
associating the samples of the received sequence with the respective SFD spread sequence corresponding to 0 and 1 for all possible sample sets;
system.
17. The method of claim 16,
determining which bit is received as either a 0 or 1 based on the association of each spread bit of the SFD with the respective sequence corresponding to 0 and 1.
system.
17. The method of claim 16,
The association is
associating the sensed SFD sequence with an expected SFD sequence for all sample sets,
comparing the SFD sequence to a threshold,
system.
13. The method of claim 12,
The calculating step is
If at least one sample set provides an association of the one or more threshold values, the detection of the SFD is performed,
system.
13. The method of claim 12,
The decision metric is
After the SFD is detected, it is computed,
system.
21. The method of claim 20,
The decision metric is
computed based on the association metric and expected SFD bits;
system.
21. The method of claim 20,
The best sample set is
obtained by maximizing the decision metric,
system.

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