KR20170002092A - Digital controllable digital variable gain amplifier - Google Patents

Digital controllable digital variable gain amplifier Download PDF

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KR20170002092A
KR20170002092A KR1020150092052A KR20150092052A KR20170002092A KR 20170002092 A KR20170002092 A KR 20170002092A KR 1020150092052 A KR1020150092052 A KR 1020150092052A KR 20150092052 A KR20150092052 A KR 20150092052A KR 20170002092 A KR20170002092 A KR 20170002092A
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South Korea
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digital control
control signal
parallel
transistor
main transistor
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KR1020150092052A
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Korean (ko)
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정진철
염인복
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한국전자통신연구원
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Priority to KR1020150092052A priority Critical patent/KR20170002092A/en
Publication of KR20170002092A publication Critical patent/KR20170002092A/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers without distortion of the input signal
    • H03G3/20—Automatic control
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers without distortion of the input signal
    • H03G3/20—Automatic control
    • H03G3/30—Automatic control in amplifiers having semiconductor devices

Abstract

Disclosed is a digital variable gain amplifier, a bias circuit, and a bias circuit digital control device for amplifying an RF signal. The digital variable gain amplifier includes an amplifier for amplifying the signal based on the gate voltage and drain current, a bias circuit for supplying the gate voltage and drain current to the amplifier based on the parallel digital control signal, and a serial digital control signal to a parallel digital control signal And transmits the resultant signal to a bias circuit. The bias circuit includes a plurality of switching transistors, a drain and a power source connected to each bit constituting a parallel digital control signal at a gate, and a main transistor having a source connected to the switching transistor in parallel. The digital control device of the bias circuit is connected in parallel with a load resistor connected to the source of the main transistor, and receives the parallel digital control signal to adjust the resistance of the source of the main transistor.

Figure P1020150092052

Description

[0001] DIGITAL CONTROLLABLE DIGITAL VARIABLE GAIN AMPLIFIER [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency amplifier and, more particularly, to a variable gain amplifier capable of digital control.

High-frequency amplifiers above 10 GHz mostly use the circuitry of the gallium-arsenic (GaAs) process because of their superior RF (Radio Frequency) characteristics. In an RF system in which such an amplifier is used, the gain of the signal needs to be controlled in system operation. Two methods are used to control the gain of the signal. One of them is a method of controlling the gain using a digital attenuator. This method has an advantage that control is easy because the attenuation value is set by the digital control signal. However, since the attenuator attenuates the signal due to its characteristics, it has the drawback of deteriorating the noise figure characteristic and the output power of the RF system. Another method of controlling the gain of a signal is an amplifier that can vary the gain by control. Such an amplifier is referred to as a variable gain amplifier (VGA). In general, since an analog control system is used, a complex control system that converts a digital control signal into an analog control signal is required in an actual system.

The present invention proposes a digital variable gain amplifier, a bias circuit and a bias circuit digital control device which are easy to control and can easily implement a control circuit.

A bias circuit for supplying a gate voltage and a drain current to the amplifier based on the parallel digital control signal and a bias circuit for changing the serial digital control signal into a parallel digital control signal, And a serial-to-parallel converter circuit for transmitting the digital signal to a circuit.

The present invention provides a bias circuit including a plurality of switching transistors each having a bit connected to a gate of the parallel digital control signal, a drain connected to the power supply, and a main transistor having a source connected to the switching transistor in parallel.

The bias circuit of the variable gain amplifier is connected in parallel with a load resistor connected to the source of the main transistor and receives a parallel digital control signal to control the resistance of the source of the main transistor.

According to an embodiment of the present invention, there is provided an amplifier for amplifying a signal based on a gate voltage and a drain current, a bias circuit for supplying the gate voltage and the drain current to the amplifier based on a parallel digital control signal, And a serial-to-parallel conversion circuit for converting the parallel digital control signal into the parallel digital control signal and transmitting the parallel digital control signal to the bias circuit.

According to an embodiment of the present invention, the bias circuit includes a plurality of switching transistors, each of which has a gate connected to a plurality of switching transistors and a plurality of drains connected to each bit constituting the parallel digital control signal, A digital variable gain amplifier comprising a transistor is provided.

According to an embodiment of the present invention, the switching transistor and the main transistor are provided with a digital variable gain amplifier which is a high-electron-mobility transistor (HEMT).

According to an embodiment of the present invention, the plurality of switching transistors are each connected in series with different resistors to adjust a resistance of the main transistor source according to a parallel digital control signal.

According to an embodiment of the present invention, the main transistor operates in an enhancement mode (E-mode) and the switching transistor is a digital variable gain amplifier (D-mode) operating in a depletion mode Is provided.

According to an embodiment of the present invention, the serial digital control signal is a digital variable gain amplifier, which is a transistor-transistor logic (TTL) signal.

According to an embodiment of the present invention, the digital variable gain amplifier is provided with a digital variable gain amplifier implemented with a gallium-arsenic single chip high-frequency integrated circuit (GaAs MMIC, GaAs Monolithic Microwave Integrated Circuit).

According to an embodiment of the present invention, a plurality of switching transistors, each of which has a gate connected to each bit constituting a parallel digital control signal, a drain connected to a power source, and a source including a main transistor, Circuit is provided.

According to an embodiment of the present invention, a bias circuit is provided in which the switching transistor and the main transistor are high electron mobility transistors (HEMTs).

According to an embodiment of the present invention, the plurality of switching transistors are each connected in series with a different resistor, and a bias circuit is provided for adjusting the resistance of the main transistor source according to a parallel digital control signal.

According to an embodiment of the present invention, the main transistor is operated in an enhancement mode (E-mode), and the switching transistor is provided in a bias circuit operating in a depletion mode (D-mode).

According to one embodiment of the present invention, the bias circuit is provided with a bias circuit embodied in a gallium-arsenide single chip high-frequency integrated circuit (GaAs MMIC).

According to an embodiment of the present invention, there is provided a bias circuit of a variable gain amplifier, the bias circuit comprising: a first switch connected in parallel with a load resistor connected to a source of the main transistor, A digital control device is provided.

According to an embodiment of the present invention, the digital control device includes a plurality of switching transistors each bit of which constitutes the parallel digital control signal, and the plurality of switching transistors are connected in parallel to the source of the main transistor And each of the transistors is connected in series with a different resistor to control the resistance of the main transistor source according to the parallel digital control signal.

According to an embodiment of the present invention, a digital control device is provided in which the switching transistor and the main transistor are high electron mobility transistors (HEMTs).

According to an embodiment of the present invention, the main transistor operates in an enhancement mode (E-mode), and the switching transistor operates in a depletion mode (D-mode).

According to one embodiment of the present invention, the digital control apparatus is provided with a digital control apparatus implemented with a gallium-arsenic single chip high-frequency integrated circuit (GaAs MMIC).

According to an embodiment of the present invention, there is provided a digital variable gain amplifier, a bias circuit, and a bias circuit digital control device which are easy to control and can easily implement a control circuit.

According to an embodiment of the present invention, there is provided a semiconductor device comprising: an amplifier for amplifying a signal based on a gate voltage and a drain current; a bias circuit for supplying a gate voltage and a drain current to the amplifier based on a parallel digital control signal; And a serial-to-parallel converter circuit for converting the control signal into a control signal and transmitting the control signal to a bias circuit.

According to an embodiment of the present invention, a bias circuit including a main transistor having a plurality of switching transistors, a drain and a power source connected to respective bits constituting a parallel digital control signal at a gate thereof, Is provided.

According to an embodiment of the present invention, there is provided a bias circuit of a variable gain amplifier, comprising: a digital circuit connected in parallel with a load resistor connected to a source of a main transistor, A control device is provided.

1 is a diagram illustrating a structure of a digital variable gain amplifier according to an embodiment of the present invention.
2 is a diagram illustrating the structure of a bias circuit according to an embodiment of the present invention.
3 is a diagram illustrating a digital control apparatus of a bias circuit according to an embodiment of the present invention.
4 is a graph illustrating frequency-dependent characteristics of a digital variable gain amplifier according to an exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a structure of a digital variable gain amplifier according to an embodiment of the present invention. The digital variable gain amplifier 101 may include an amplifier 102, a bias circuit 103, and a serial to parallel conversion circuit 104. The amplifier 102 amplifies the input signal according to the set gain and outputs the amplified signal. The gain of the amplifier 102 may be adjusted by the gate voltage 107 of the amplifier and / or the drain current 108 of the amplifier. According to one embodiment of the present invention, the input signal of the amplifier 102 may be an RF input signal 105 and the output signal may be an RF output signal 106.

According to one embodiment of the present invention, the amplifier 102 may amplify the RF signal. According to one embodiment of the present invention, the amplifier 102 may be implemented with a broadband amplifier of 6 GHz to 18 GHz. According to one embodiment of the present invention, the amplifier 102 is implemented as a GaAs HEMT (GaAs High-Electron-Mobility Transistor) operated in an enhancement mode (E-mode) . As an example without limiting the invention, the amplifier 102 may be a GaAs MESFET, a GaAs HBT, or a GaAs Heterojunction Bipolar Transistor (GaAs MESFET) , A silicon-germanium heterojunction bipolar transistor (SiGe HBT), or a silicon germanium heterojunction bipolar transistor (SiGe HBT).

According to one embodiment of the present invention, a bias circuit 103 is provided that is capable of controlling the gain of the amplifier 102. The bias circuit 103 receives the bias voltage 109 and can output the gate voltage 110 and / or the drain current 111. [ According to some embodiments, the bias voltage 109 may be included in the interior of the bias circuit 103 in the form of a battery or the like. According to an embodiment of the present invention, the bias voltage 109 may be applied directly to the drain current 111, and thus the voltage of the drain current 111 may be set equal to the bias voltage 109. [ According to one embodiment of the present invention, the bias circuit 103 may adjust the gate voltage 110 and / or the drain current 111 based on the parallel digital control signal 113.

In accordance with one embodiment of the present invention, a serial-to-parallel conversion circuit 104 for delivering a parallel digital control signal to the bias circuit 103 is provided. The serial / parallel conversion circuit 104 receives the serial digital control signal 112 and outputs the serial digital control signal 112 as a parallel digital control signal 113. In accordance with one embodiment of the present invention, the serial digital control signal 112 may be in the form of a transistor-transistor logic (TTL) signal. The TTL signal is a signal in which a + 5V signal and a 0V signal correspond to a logic value 1 and a logic value 0, respectively. A logic value 1 and a logical value 0 may correspond to a 0V signal and a + 5V signal, respectively.

According to one embodiment of the present invention, the voltage of the input signal and the voltage of the output signal of the serial-parallel conversion circuit 104 may not be the same. As an example without limiting the present invention, when a TTL signal having a serial digital control signal 112 of + 5V / 0V is input, the output digital control signal 113 is a signal capable of controlling a GaAs HEMT of 0V / Can be output. In this case, the 0V / -2.4V signal can turn the GaAs HEMT ON and OFF, respectively.

According to an embodiment of the present invention, the digital variable gain amplifier 101 may be implemented as a gallium arsenide single chip high-frequency integrated circuit (GaAs MMIC, GaAs Monolithic Microwave Integrated Circuit). According to one embodiment of the present invention, a combination of all or a part of the amplifier 102, the bias circuit 103, and the serial-parallel conversion circuit 104 may be implemented by a GaAs MMIC. It is apparent to those of ordinary skill in the art that when a part or a combination thereof is implemented in a GaAs MMIC, they can be combined to implement a digital variable gain amplifier 101.

2 is a diagram illustrating the structure of a bias circuit according to an embodiment of the present invention. The digital variable gain amplifier may include a bias circuit 201 that adjusts the gate voltage and / or the drain current of the amplifier. The bias circuit 201 may include a gate voltage output port 203 for regulating the gate voltage of the amplifier and a drain current output port 204 for regulating the drain current of the amplifier and may include a bias voltage 202 and a parallel digital control And a signal input port 217.

2, the bias circuit 201 includes a plurality of switching transistors 209, 210, 211, and 212 whose gates are connected to each bit constituting a parallel digital control signal, and a drain and a bias voltage 202 is connected, a switching transistor and a load resistance R 2 (207) to the source may include a main transistor 205 connected in parallel. According to one embodiment, the drain current output port 204 may be coupled directly to the bias voltage 202 to output a voltage equal to the bias voltage. According to one embodiment, one bias voltage 202 can output the voltage of the drain current output port 204 and the voltage of the gate voltage output port 203.

2, a plurality of switching transistors 209, 210, 211 and 212 are connected in series with different resistors 213, 214, 215 and 216, respectively, Can be adjusted based on the parallel digital control signal. More specifically, a plurality of port modules 208 connected in parallel to the source of the main transistor 205 are provided, each port module 208 being connected to a respective bit constituting a parallel digital control signal. The port module 208 may include a switching transistor 209 and a resistor 213 connected in series with the switching transistor 209.

An embodiment in which the gate voltage output port 203 and the drain current output port 204 of the bias circuit 201 are adjusted in accordance with the parallel digital control signal will be described with reference to FIG. Assume that the LSB (Least Significant Bit) of the 4-bit parallel digital control signal is input to VC a of the parallel digital control signal input port 217 and is input as VC b , VC c , and VC d in order from the next LSB. In this case, the MSB (Most Significant Bit) will be input as VC d . The resistance of the load resistor R 2 207 and the resistance of the resistor R a 213 connected to the source of the switching transistor 209 corresponding to the LSB are the same and the resistance connected to the source of the switching transistor 210 corresponding to the next LSB The resistance of R b 214 is 1/2 of load resistance R 2 207 and the resistance of resistor R c 215 connected to the source of switching transistor 211 corresponding to the next LSB is equal to the load resistance R 2 207 and the resistance of the resistor R d 216 connected to the source of the switching transistor 212 corresponding to the MSB is 1/4 of the load resistance R 2 207. [

When all of the 4-bit parallel digital control signals are ON 1111, not only the load resistor R 2 207 but also R a 213 to R d 216 are connected in parallel to the source of the main transistor 205. Thus, the source resistance of the main transistor 205 is minimized, so that the gate voltage of the main transistor 205 is minimized. This minimizes the drain current of the main transistor 205. Therefore, a minimum voltage flows to the gate voltage output port 203, and a minimum current flows to the drain current output port 204. [ This minimizes the gain of the connected amplifier.

Conversely, when all the parallel digital control signals are OFF (0000), only the load resistor R 2 207 is connected to the source of the main transistor 205, so that the source resistance of the main transistor 205 becomes the maximum. Therefore, the maximum voltage is applied to the gate voltage output port 203 of the main transistor 205, the maximum current flows to the drain current output port 204, and the gain of the connected amplifier is maximized. According to the present embodiment, the bias circuit 201 can provide 16 outputs according to a 4-bit parallel digital control signal, and a 16-state variable gain amplifier can be implemented using the 16 outputs.

Although only an embodiment for a 4 bit parallel digital control signal is described, embodiments for other types of parallel digital control signals are possible. More specifically, the number of port modules 208 may be increased to implement a bias circuit capable of receiving not only 4 bits but also other types of parallel digital control signals such as 8 bits and 16 bits. When an 8-bit parallel digital control signal is input, the bias circuit 201 can provide 256 outputs, and therefore, a 256-state variable gain amplifier can be implemented using the 8-bit parallel digital control signal.

According to an embodiment of the present invention, the transistors 205, 209, 210, 211, and 212 constituting the bias circuit 201 may be implemented as GaAs HEMTs. As a further example that does not limit the invention, these transistors may be implemented with either GaAs MESFETs, GaAs HBTs, or SiGe HBTs. In addition, the bias circuit 201 may be implemented as a GaAs MMIC. The switching transistors 209, 210, 211 and 212 of the bias circuit 201 may operate in a D-mode, and the main transistor 205 may operate in an enhancement mode E- mode.

3 is a diagram illustrating a digital control apparatus of a bias circuit according to an embodiment of the present invention. 3, the bias circuit 302 may include a main transistor 304 and a load resistor 305 coupled to the source of the main transistor 304. [ The bias circuit 302 may receive the bias voltage 303. According to another embodiment not shown, the bias voltage 303 may be implemented in the form of a battery or the like inside the bias circuit 302. The bias circuit 302 may include a gate voltage output port 325 and / or a drain current output port 324 and may include a gate voltage output port 325 and a drain current output port 325, according to one embodiment of the present invention. 324 may be coupled to the amplifier to determine the gain of the amplifier.

Referring to FIG. 3, there is provided a digital control device 301 connected to the bias circuit 302 to adjust the resistance of the source of the main transistor 304. The digital control device 301 is connected to the source of the main transistor 304 in parallel with the load resistor 305 and can receive the parallel digital control signal 323 to adjust the resistance of the source of the main transistor 304 . According to one embodiment of the present invention, the voltage of the gate voltage output port 325 of the bias circuit 302 and / or the current of the drain current output port 324 can be adjusted by adjusting the resistance of the source.

The digital control device 301 may include a plurality of switching transistors 307, 308, 309, 310, 311, 312, 313 and 314 to which each bit constituting the parallel digital control signal 323 is connected. The plurality of switching transistors 307, 308, 309, 310, 311, 312, 313 and 314 are connected in parallel to the source of the main transistor 304 and are respectively connected to different resistors 315, 316, 317, , 320, 321, 322) to adjust the resistance of the source of the main transistor 304 according to the parallel digital control signal 323.

Referring to FIG. 3, the digital control device 301 may include a plurality of port modules 306 connected to respective bits constituting the parallel digital control signal 323. Each of the port modules 306 includes resistors 315, 316, 317, 318, 319, 320, 321, 322 connected in series with the switching transistors 307, 308, 309, 310, 311, 312, 313, ).

According to one embodiment of the present invention, each bit constituting the parallel digital control signal 323 regulates the switching transistor of the corresponding port module. When the switching transistor is ON, a resistor connected in series to the switching transistor is connected to the source of the main transistor 304. [ In this case, since each port module is connected in parallel to the source of the main transistor 304, the resistance of the source of the main transistor 304 is reduced. Accordingly, the voltage of the gate voltage output port 325 is reduced, and the current of the drain current output port 324 is also reduced.

According to one embodiment of the present invention, the gate voltage output port 325 and the drain current output port 324 may each be connected to the gates and drains of the amplifiers. As the drain current decreases, the gain of the amplifier is reduced, so that the gain of the amplifier connected to the bias circuit 302 is reduced as the number of ON switching transistors increases.

Referring to FIG. 3, there is provided an embodiment of a digital control device 301 receiving an 8-bit parallel digital control signal 323. The port module 306 is connected to each bit constituting the parallel digital control signal 323. Since the parallel digital control signal 323 is an 8-bit signal, the digital control unit 301 includes a total of eight port modules 306. The LSB of the 8-bit digital control signal becomes high in importance as VC and a, b VC, VC c, d VC VC order Let h is assumed to be corresponding to the MSB. In this case, the outputs of the bias circuit 302 can be variously changed by setting the resistors 315, 316, 317, 318, 319, 320, 321, and 322 connected in series with the switching transistors of the port modules to be different from each other.

A resistor R a 315 coupled to the switching transistor 307 of the port module 306 corresponding to the LSB is coupled to a load resistor 305 connected to the main transistor 304 of the bias circuit 302 ). ≪ / RTI > And then to resistance R b (316) connected to the switching transistor of the port module corresponding to the LSB may have a resistance value corresponding to 1/2 of the R a (315). The resistance R c 317 corresponding to the next LSB may have a resistance value corresponding to 1/3 of R a 315. This also applies to R d 318 to R h 322 so that the MSB R h 322 may have a resistance value corresponding to 1/8 of R a 315. In this embodiment, the state signal has the greatest effect on the resistance of the source of the transistor 304 is VC h is the MSB.

In the above-described embodiment, when all the parallel digital control signals 323 are 0 (OFF), all the switching transistors of the port module do not operate. That is, no resistor is connected to the source of the main transistor 304 in addition to the load resistor 305, and the resistance of the source of the main transistor 304 becomes the maximum. This maximizes the voltage of the gate voltage output port 325 and the drain current output port 324. Since the drain current is at its maximum, the gain of the amplifier connected to the bias circuit 302 is maximized. Conversely, when the parallel digital control signal 323 is all 1 (ON), all the switching transistors of the port module operate. That is, the load resistor 305 and the R a 315 to R h 322 are connected to the source of the main transistor 304, so that the resistance of the source of the main transistor 304 is minimized. This minimizes the voltage of the gate voltage output port 325 and the drain current output port 324. Since the drain current is minimal, the gain of the amplifier connected to the bias circuit 302 is minimized.

According to one embodiment of the present invention, at least one of each of the switching transistors 307, 308, 309, 310, 311, 312, 313, 314 included in the main transistor 304 and the port module is implemented as a GaAs HEMT . By way of example and not by way of limitation, the transistors may be implemented as either GaAs MESFETs, GaAs HBTs, or SiGe HBTs. According to one embodiment of the present invention, the main transistor 304 may operate in an enhancement mode (E-mode) and the switching transistors 307, 308, 309, 310, 311, 312, 313, Mode (D-mode). In addition, the digital control device 301 may be implemented as a GaAs MMIC.

According to an embodiment of the present invention, a digital control device 301 implemented with a GaAs HEMT may be provided. In this case, the ON / OFF voltages of the GaAs HEMT are 0V / -2.4V, respectively, so that the ON / OFF voltages of the parallel digital control signals can be provided as 0V / -2.4V, respectively.

According to one embodiment of the present invention, the gate voltage and the drain current output by the bias circuit 302 may be applied at one bias voltage 303. [

4 is a graph illustrating frequency-dependent characteristics of a digital variable gain amplifier according to an exemplary embodiment of the present invention. More specifically, it is a graph 301 showing frequency-dependent characteristics of a digital variable gain amplifier that performs amplification based on a 4-bit serial digital control signal. An RF signal in the range of 6 GHz to 18 GHz was amplified by adjusting the parallel digital control signal. The x axis is the frequency of the RF signal and the y axis is the magnitude of the output signal.

When ON is set to 1 and OFF is set to 0, when the 4-bit digital control signal is 0000 (402), the drain current flowing through the amplifier is maximized, and the gain of the amplifier is maximized. When the LSB is ON only (0001) (403), the drain current flowing to the amplifier is reduced, and the gain of the amplifier is reduced compared to the case where all the digital control signals are OFF (402). In the case of 404 (405), the case of 1000 (406) is shown in order. MSB has the greatest effect on the gain of the amplifier.

Referring to FIG. 4, it can be seen that RF signals can be amplified between 14 dB and 17 dB at 6 GHz, and RF signals can be amplified between 14 and 16 dB at 18 GHz. It is one of the effects according to the embodiment of the present invention that the characteristics such as the reflection loss, the noise figure, and the output power are hardly changed in addition to the gain. It is one of the effects according to the embodiment of the present invention that the gain change due to the temperature of the amplifier and the process error of the GaAs process can be compensated.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. This is possible.

Therefore, the scope of the present invention should not be construed as being limited to the embodiments described, but should be determined by equivalents to the appended claims, as well as the appended claims.

101: Digital Variable Gain Amplifier
102: amplifier
103: Bias circuit
104: serial / parallel conversion circuit
105: RF input signal
106: RF output signal
107: Amplifier gate voltage
108: Drain current of the amplifier
109: bias voltage
110: gate voltage
111: drain current
112: serial digital control signal
113: parallel digital control signal

Claims (17)

An amplifier for amplifying the signal based on the gate voltage and the drain current;
A bias circuit for supplying the gate voltage and the drain current to the amplifier based on a parallel digital control signal; And
A serial-to-parallel conversion circuit for converting the serial digital control signal into the parallel digital control signal and transmitting the serial digital control signal to the bias circuit
/ RTI > The method according to claim 1,
The bias circuit includes:
A plurality of switching transistors whose gates are connected to each bit constituting the parallel digital control signal;
A main transistor having a drain and a power source connected to each other and having a source connected to the switching transistor in parallel;
/ RTI > 3. The method of claim 2,
Wherein the switching transistor and the main transistor are high-electron-mobility transistors (HEMTs). 3. The method of claim 2,
Wherein the plurality of switching transistors comprise:
Each of which is connected in series with a different resistor to adjust the resistance of the main transistor source according to a parallel digital control signal. 3. The method of claim 2,
The main transistor operates in an enhancement mode (E-mode)
Wherein the switching transistor operates in a D-mode (Depletion mode). The method according to claim 1,
Wherein the serial digital control signal comprises:
A digital variable gain amplifier that is a transistor-transistor logic (TTL) signal. The method according to claim 1,
The digital variable gain amplifier is implemented as a gallium-arsenide single chip high-frequency integrated circuit (GaAs MMIC, GaAs Monolithic Microwave Integrated Circuit). A plurality of switching transistors whose gates are connected to each other to constitute a parallel digital control signal at a gate;
A main transistor having a drain and a power source connected to each other and having a source connected to the switching transistor in parallel;
≪ / RTI > 9. The method of claim 8,
Wherein the switching transistor and the main transistor are high electron mobility transistors (HEMTs). 9. The method of claim 8,
Wherein the plurality of switching transistors comprise:
Each of which is connected in series with a different resistor to regulate the resistance of the main transistor source according to a parallel digital control signal. 9. The method of claim 8,
The main transistor operates in an enhancement mode (E-mode)
Wherein the switching transistor operates in a depletion mode (D-mode). 9. The method of claim 8,
The bias circuit is implemented as a gallium-arsenide single chip high frequency integrated circuit (GaAs MMIC). In a bias circuit of a variable gain amplifier,
Connected in parallel with a load resistor connected to the source of the main transistor,
A digital control device receiving a parallel digital control signal and adjusting a resistance of a source of the main transistor. 14. The method of claim 13,
The digital control apparatus includes:
Wherein the parallel digital control signal includes a plurality of switching transistors each bit of which is connected,
Wherein the plurality of switching transistors comprise:
Connected in parallel to a source of the main transistor,
Each of which is connected in series with a different resistor to adjust the resistance of the main transistor source according to the parallel digital control signal. 15. The method of claim 14,
Wherein the switching transistor and the main transistor are high electron mobility transistors (HEMTs). 15. The method of claim 14,
The main transistor operates in an enhancement mode (E-mode)
Wherein the switching transistor operates in a depletion mode (D-mode). 14. The method of claim 13,
The digital control device is implemented as a gallium-arsenide single chip high frequency integrated circuit (GaAs MMIC).
KR1020150092052A 2015-06-29 2015-06-29 Digital controllable digital variable gain amplifier KR20170002092A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112799020A (en) * 2020-12-16 2021-05-14 北京无线电测量研究所 Multi-voltage power supply modulation chip
US11736112B2 (en) 2021-05-28 2023-08-22 Samsung Electronics Co., Ltd. Digitally controlled oscillator insensitive to changes in process, voltage, temperature and digital phase locked loop including same
KR20240047895A (en) 2022-10-05 2024-04-12 서울대학교산학협력단 Multi-level signal processing apparatus and variable gain amplifer gain control method using the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112799020A (en) * 2020-12-16 2021-05-14 北京无线电测量研究所 Multi-voltage power supply modulation chip
CN112799020B (en) * 2020-12-16 2023-11-28 北京无线电测量研究所 Multi-voltage power supply modulation chip
US11736112B2 (en) 2021-05-28 2023-08-22 Samsung Electronics Co., Ltd. Digitally controlled oscillator insensitive to changes in process, voltage, temperature and digital phase locked loop including same
KR20240047895A (en) 2022-10-05 2024-04-12 서울대학교산학협력단 Multi-level signal processing apparatus and variable gain amplifer gain control method using the same

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