KR20160150244A - PCB for POP structure, method of manufacturing the same and device package using the PCB - Google Patents

Abstract

According to one embodiment of the present invention, a method to manufacture a printed circuit board (PCB) for a package on package (POP) structure, providing a carrier substrate including an insulation layer and a base copper layer installed at least one surface of the insulation layer. A copper pattern layer for a stud and a copper pattern layer to manufacture a cavity are formed on the base copper layer by plating. A first interlayer insulation layer burying between the copper pattern layer to manufacture the cavity and the copper pattern layer for the stud is formed on the base copper layer. While the insulation layer and the base copper layer on the carrier substrate are separated from each other to expose the base copper layer, an intermediate structure stacking the copper pattern layer to manufacture the cavity and the copper pattern layer for the stud is formed in an upper part of the base copper layer. Plating using the exposed base copper layer as a seed layer is performed, so a first circuit pattern layer is formed on a lower surface of the copper pattern layer to manufacture the cavity and the copper pattern layer for the stud. Since the copper pattern layer to manufacture the cavity is selectively removed, a die mounting cavity to expose the first circuit pattern layer is formed.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a printed circuit board for POP structure, a manufacturing method thereof, and a device package using the same,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board (PCB) and an element package using the same, and more particularly, to a printed circuit board for POP structure, a method of manufacturing the same, and an element package using the same.

With the miniaturization of electronic devices, electronic components are becoming more sophisticated and smaller. Due to the advancement of digital networks, portable information terminal devices such as mobile phones and portable computers are becoming more sophisticated and sophisticated, and various functions are being combined and integrated into one device.

As electronic devices are miniaturized and highly functionalized, the number of component elements to be mounted on a printed circuit board is greatly increased. On the other hand, the area of the substrate is not reduced. Rather, it is demanded to reduce the thickness of the existing printed circuit board and the thickness of the component element in accordance with the trend of downsizing described above.

In recent years, as a method for manufacturing a printed circuit board to satisfy the above-described requirements, an embedded printed circuit board technology in which a device chip is embedded in a printed circuit board has appeared. Embedded printed circuit board technology can be advantageous in reducing the thickness of the entire component by embedding the component chip in a printed circuit board. As an example of a manufacturing technique of such an embedded printed circuit board, there is a technique disclosed in Korean Patent Publication No. 2012-0070075.

In addition, POP (Package On Package) technology has been popular recently. Functionally close elements can be operated in the same structure by sequentially stacking a plurality of different packages and electrically connecting the plurality of packages through wiring.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a printed circuit board for POP structure that reduces the thickness of a printed circuit board by mounting a device chip in a cavity formed in a printed circuit board and a method of manufacturing the same.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a printed circuit board for POP structure and a method of manufacturing the same, which are provided with a connecting structure for connecting an upper package and a lower package when implementing a POP structure.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a printed circuit board for POP structure having a fine pad pattern electrically connected to the device chip in a cavity in which the device chip is mounted, and a method of manufacturing the same.

An object of the present invention is to provide an element package using the above-described POP structure printed circuit board.

A manufacturing method of a POP structure printed circuit board according to one aspect is disclosed. A manufacturing method of the printed circuit board according to the present invention provides a carrier substrate having an insulating layer and a base copper layer disposed on at least one side of the insulating layer. A copper pattern layer for studs and a copper pattern layer for cavity fabrication are formed on the base copper layer by a plating method. A first interlayer insulating layer is formed on the base copper layer to fill the space between the copper pattern layer for cavity formation and the copper pattern layer for the stud. Forming an intermediate structure in which the copper pattern layer for cavity fabrication and the copper pattern layer for stud are stacked on the base copper layer by separating the insulating layer and the base copper layer of the carrier substrate from each other, do. A first circuit pattern layer is formed on the lower surfaces of the cavity-forming copper pattern layer and the stud-forming copper pattern layer by performing a plating method using the exposed base copper layer as a seed layer. The copper pattern layer for manufacturing a cavity is selectively removed to form a die cavity for exposing the first circuit pattern layer.

A manufacturing method of a POP structure printed circuit board according to another aspect is disclosed. A manufacturing method of the printed circuit board according to the present invention provides a carrier substrate having an insulating layer and a base copper layer disposed on at least one side of the insulating layer. And a conductive etch stop layer is formed on the base copper layer. A copper pattern layer for cavity formation and a copper pattern layer for a stud are formed on the conductive etch stop layer by a plating method. A first interlayer insulating layer is formed on the conductive etch stop layer so as to fill the space between the cavity forming copper pattern layer and the stud copper pattern layer and expose the upper surfaces of the cavity forming copper pattern layer and the stud copper pattern layer . Forming an intermediate structure in which the copper pattern layer for cavity fabrication and the copper pattern layer for stud are stacked on the base copper layer by separating the insulating layer and the base copper layer of the carrier substrate from each other, do. A first circuit pattern layer is formed on the lower surfaces of the cavity-forming copper pattern layer and the stud-forming copper pattern layer by performing a plating method using the exposed base copper layer as a seed layer. A solder resist pattern layer is selectively formed on the first interlayer insulating layer to selectively expose the top surfaces of the cavity-forming copper pattern layer and the stud-forming copper pattern layer. And a cavity open mask pattern layer is selectively formed on the solder resist layer so as to selectively expose the upper surface of the cavity-forming copper pattern layer. And the first circuit pattern layer is exposed by etching the copper pattern layer for cavity formation using the cavity-opening mask pattern layer as an etching mask.

A POP structure printed circuit board according to another aspect is disclosed. The printed circuit board comprising: a lower insulation layer having a die connection pad and a stud connection pad; And an upper insulating layer disposed on the lower insulating layer and having a copper pattern layer for a stud electrically connected to the stud connection pad and having a die mounting cavity for selectively exposing the die connection pad do. At this time, a connection structure with an external package is mounted on the copper pattern layer for stud.

A device package according to another aspect is disclosed. The device package has an upper package and a lower package connected by a solder structure. The lower package comprising: a lower insulating layer having a die connection pad and a stud connection pad; An upper insulating layer disposed on the lower insulating layer and having a copper pattern layer for a stud electrically connected to the stud connection pad and having a die mounting cavity for selectively exposing the die connection pad; And a device chip connected to the die connection pad inside the die mounting cavity. And the solder structure with the upper package is mounted on the copper pattern layer for studs.

According to one embodiment, when implementing a POP structure, a printed circuit board having a copper stud pattern layer as a connection structure connecting the upper package and the lower package can be provided.

In addition, a cavity having a depth corresponding to the height of the copper stud can be formed in the interlayer insulating layer located at least a part of the printed circuit board, and the device chip can be mounted in the cavity. This has the advantage that a separate mold layer for protecting the device chip can be omitted.

According to the manufacturing method of the embodiment, there is an advantage that the micro pad and the circuit pattern electrically connected to the device chip mounted in the cavity can be built in the printed circuit board.

By applying the above-described structure, it is possible to provide a thin POP structure printed circuit board and an element package using the same, while improving structural stability.

1 to 15 are sectional views schematically showing a method of manufacturing a printed circuit board for POP structure according to an embodiment of the present invention.
16 is a cross-sectional view schematically showing an element package according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the techniques disclosed in the present invention are not limited to the embodiments described herein but may be embodied in other forms. It should be understood, however, that the embodiments disclosed herein are provided so that this disclosure will be thorough and complete, and will fully convey the concept of this disclosure to those skilled in the art. In the drawings, the width, thickness, and the like of the components are enlarged in order to clearly illustrate the components of each device. It is to be understood that when an element is described as being located on another element, it is meant that the element is directly on top of the other element or that additional elements can be interposed between the elements .

Like numbers refer to like elements throughout the several views. It is to be understood that the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise, and the terms "comprise" Or combinations thereof, and does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Further, in carrying out the method or the manufacturing method, the respective steps of the method may take place differently from the stated order unless clearly specified in the context. That is, each process may occur in the same order as described, may be performed substantially concurrently, or may be performed in the opposite order.

As used herein, the term " top surface " or " bottom " of a substrate or device chip is a relative concept observed at an observer's viewpoint. Therefore, one of the two surfaces except the side of the substrate or the element chip may be referred to as an 'upper surface' or 'lower surface', and the other surface may be referred to as 'lower surface' or 'upper surface' correspondingly. Likewise, in the present specification, the concept of 'upper', 'upper' or 'lower' and 'lower' can be used as a relative concept as well.

Generally, a POP (Package On Package) connects the lower package and the upper package to each other using various connection structures. For example, a first solder ball may be mounted on a printed circuit board of a lower package, a second solder ball may be mounted on a printed circuit board of an upper package, and solder bonding may be performed between the first solder ball and the second solder ball, The package and the upper package can be electrically connected. The POP product according to an embodiment of the present invention described below forms a cavity in a printed circuit board of a lower package to mount a die (i.e., a device chip) and a copper stud having a height corresponding to the depth of the cavity And is formed on the printed circuit board, thereby functioning as a connection structure joining the upper package. As a result, it is possible to provide a thin POP structure printed circuit board with improved structural reliability of the connection structure.

1 to 15 are sectional views schematically showing a method of manufacturing a printed circuit board for POP structure according to an embodiment of the present invention. Referring to FIG. 1, a carrier substrate 100 is prepared. The carrier substrate 100 has an insulating layer 110 and a base copper layer 115 disposed on at least one side of the insulating layer 110. [ The insulating layer 110 may comprise, by way of example, an epoxy or prepreg. Although the base copper layer 115 is laminated on both surfaces of the insulating layer 110, the base copper layer 115 may be laminated only on the upper surface of the insulating layer 110.

Referring to FIG. 2, a conductive etch stop layer 120 is formed on the base copper layer 115. As one example, the conductive etch stop layer 120 may be formed by a plating method. As an example, the conductive etch stop layer 120 may comprise a nickel layer. The conductive etch stop layer 120 may have an etch selectivity to the copper material.

In some other embodiments, the conductive etch stop layer 120 may not be formed and may be omitted.

Referring to FIG. 3, a copper pattern layer 130 is formed on the conductive etch stop layer 120 by a plating method. As a method of forming the copper pattern layer 130, for example, a chemical plating method, an electroplating method, or a combination thereof can be applied. As an example of the method of forming the copper pattern layer 130, a known tenting method, a semi- additive process (SAP), a modified semi-additive process (MSAP), or the like can be applied. In one embodiment, the copper pattern layer 130 may include a copper pattern layer 131 for cavity fabrication and a copper pattern layer 132 for studs.

In some other embodiments, when the conductive etch stop layer 120 is omitted, the copper pattern layer 130 may be formed on the base copper layer 115 with the base copper layer 115 as the plating seed layer .

Referring to FIG. 4, a first interlayer insulating layer 140 is formed on the conductive etch stop layer 120 to fill the space between the copper pattern layer 131 for forming cavities and the copper pattern layer 132 for studs.

In one embodiment, the step of forming the first interlayer insulating layer 140 may proceed as follows. First, an epoxy molding compound (EMC) is provided on the conductive etch stop layer 120 to form an insulating film for burying the copper pattern layer 131 for forming cavities and the copper pattern layer 132 for studs. Next, the insulating layer is ground to expose the upper surfaces of the copper pattern layer 131 for forming cavities and the copper pattern layer 132 for studs. Thus, the upper surface of the first interlayer insulating layer 140 can be located on the same plane as the upper surface of the cavity-forming copper pattern layer 131 and the stud-forming copper pattern layer 132.

Referring to FIG. 5, the insulating layer 110 and the base copper layer 115 of the carrier substrate 100 are separated from each other to expose the base copper layer 115. At this time, an intermediate structure in which a copper pattern layer 131 for forming cavities and a copper pattern layer 132 for studs are laminated on the base copper layer 115 can be formed.

6, a plating method using the exposed base copper layer 115 as a seed layer is performed to form a first circuit pattern layer 131 on the lower surface of the cavity forming copper pattern layer 131 and the stud copper pattern layer 132, (150). Specifically, the first circuit pattern layer 150 includes a die connection pad 151 formed on the lower surface of the cavity-forming copper pattern layer 131, and a stud connection (not shown) formed on the lower surface of the copper- A pad 152 may be included.

The process of forming the first circuit pattern layer 150 may, for example, proceed as follows. A resist pattern layer having a predetermined contact or trench pattern is formed on the exposed base copper layer 115. Subsequently, a plating pattern is formed to form a copper pattern layer 155 on the base copper layer 115 to fill the contact or trench pattern. Subsequently, the resist pattern layer is removed, and the base copper layer 115 and the conductive etch stop layer 120 outside the copper pattern layer 155 are additionally etched using the copper pattern layer 155. Thereby, the neighboring copper pattern layers 155 can be electrically insulated from each other.

The first circuit pattern layer 150 may include a conductive etch stop layer pattern 120a, a base copper layer pattern 115a, and a copper pattern layer 155. The die connection pad 151 and the stud connection pad 152 may have a stacked structure of the conductive etch stop layer pattern 120a, the base copper layer pattern 115a, and the copper pattern layer 155. [

Referring to FIG. 7, a second interlayer insulating layer 160 covering the first circuit pattern layer 150 is formed on the lower surface of the copper pattern layer 131 for cavity formation and the copper pattern layer 132 for studs. According to one embodiment, in the step of forming the second interlayer insulating layer 160, an intermediate substrate of an epoxy or prepreg material is prepared, and the intermediate substrate is patterned into a copper pattern layer 131 for forming cavities and a copper pattern layer To the lower surface of the base plate 132.

Referring to FIG. 8, a via hole 165 is formed through the second interlayer insulating layer 160 to expose at least a portion of the first circuit pattern layer 150. As an example, the via hole 165 may expose the stud connection pad 152.

Referring to FIG. 9, a via 170 filling the via hole 165 is formed by performing a plating method, and a second circuit pattern layer 175 is formed on the second interlayer insulating layer 160.

The via 170 may be electrically connected to at least a portion of the first circuit pattern layer 150, e.g., the stud connection pad 152 and the copper pattern layer 132 for studs. The second circuit pattern layer 175 may be electrically connected to the via 170.

Referring to FIG. 10, a third interlayer insulating layer 180 covering the second circuit pattern layer 175 is formed on the lower surface of the second interlayer insulating layer 160. According to one embodiment, in the step of forming the third interlayer insulating layer 180, an intermediate substrate of an epoxy or prepreg material is prepared, and the intermediate substrate is bonded to the lower surface of the second interlayer insulating layer 160 Process.

Referring to FIG. 11, a via hole is formed through the third interlayer insulating layer 180 to be electrically connected to at least a part of the second circuit pattern layer 175. Subsequently, a via 190 filling the via hole is formed by performing a plating method, and a third circuit pattern layer 195 is formed on the third interlayer insulating layer 180.

The process of forming the via 190 and the third circuit pattern layer 195 may be the same as that described with reference to Figs. 8 and 9.

12, a solder resist pattern (not shown) having a contact hole 215 for selectively exposing the upper surface of the copper pattern layer 131 for forming cavities and the copper pattern layer 132 for studs on the first interlayer insulating layer 140, Layer 210 is formed. In addition, the solder resist pattern layer 210 may be formed to cover the third circuit pattern layer 195 on the third interlayer insulating layer 180.

Referring to FIG. 13, a cavity opening mask pattern layer 220 having contact holes 225 selectively exposing an upper surface of a cavity-forming copper pattern layer 131 is formed on a solder resist pattern layer 210. The cavity-opening mask patter layer 220 may be a resist pattern layer, for example. In addition, the cavity-opening mask pattern layer 220 may be formed on the solder resist pattern layer 210 so as to cover the third circuit pattern layer 195.

14, a cavity 145 for exposing at least a portion of the first circuit pattern layer 150 by etching the cavity pattern-forming copper pattern layer 131 using the cavity-opening mask pattern layer 220 as an etching mask, . As a specific example, the die-bonding pad 151 and the second insulating layer 160 may be exposed by etching the copper pattern layer 131 for manufacturing a cavity.

The etching process may be performed by a wet etching method using an etchant for copper. The etching process can be performed until the copper etching is stopped on the conductive etch stop layer pattern 120a of the die connection pad 151. [ On the other hand, the conductive etch stop layer pattern 120a can protect the underlying base copper layer pattern 115a and the copper pattern layer 155 from the etchant.

In some other embodiments, when the conductive etch stop layer 120 is not used, etching of the copper pattern layer 131 for cavity fabrication can be performed by controlling the etching process conditions such as the etching time.

Referring to FIG. 15, the cavity-opening mask pattern layer 220 is removed to expose the solder resist pattern layer 210. Through the above-described process, the POP structure printed circuit board according to the embodiment of the present invention can be manufactured.

On the other hand, referring to Fig. 15, a POP structure printed circuit board will be described. The POP structure printed circuit board may include a lower insulating layer 160 having a die connection pad 151 and a stud connection pad 152. In addition, the POP structure printed circuit board may include an upper insulating layer 140 disposed on the lower insulating layer 160. The upper insulating layer 140 includes a copper pattern layer 132 for a stud which is electrically connected to the stud connection pad 152 and has a cavity for die mounting that selectively exposes the die connection pad 151 145).

At this time, the die connection pad 151 is buried in the upper insulating layer 140, and only the surface can be exposed to the outside. As described above, the die connection pad 151 is made of a built-in circuit pattern, so that the printed circuit board can be made thin.

The POP structure printed circuit board may include a solder resist pattern layer 210 selectively exposing the copper pattern layer 132 for stud and the cavity 145 for die mounting on the upper insulating layer 140. On the copper pattern layer 132 for studs exposed by the solder resist pattern layer 210, a connection structure for connection with an external package can be mounted.

The POP structure printed circuit board includes at least one via 170 and 190 and a circuit pattern layer 175 and 195 disposed under the lower insulating layer 160 and connected to the stud connection pad 152 can do. At this time, the solder resist pattern layer 210 can selectively expose the surfaces of the circuit pattern layers 175 and 195. The circuit pattern layers 175 and 195 exposed by the solder resist pattern layer 210 can function as a pad layer for external connection.

Meanwhile, in the POP structure printed circuit board, an etch protection layer 120 having an etching selection ratio with copper may be disposed on the die connection pad and the stud connection pads 151 and 152. As an example, the etch protection layer 120 may be a nickel layer.

16 is a cross-sectional view schematically showing an element package according to an embodiment of the present invention. As shown, device package 1600 may be a POP product.

16, the device package 1600 may have a structure in which a top package 1600A and a bottom package 1600B are connected by a solder structure 1640. [

The lower package 1600B includes a lower insulating layer 160 having a die connection pad 151 and a stud connection pad 152 and an upper insulating layer 140 disposed on the lower insulating layer 160 can do. The upper insulating layer 140 includes a copper pattern layer 132 for a stud which is electrically connected to the stud connection pad 152 and includes a die mounting cavity 151 for selectively exposing the die connection pad 151, (Not shown). The device chip 10 connected to the die connection pad 151 can be mounted inside the die mounting cavity 145. As shown in the figure, the element chip 10 can be connected to the die connection pad 151 through the bump structure 1010. [

On the other hand, the solder structure 1640 is mounted on the copper pattern layer 132 for studs with a structure such as a solder ball and then connected to a connection pad (not shown) formed on the lower surface of the printed circuit board 1610 of the upper package 1600A ) And a junction by heating.

As shown in the figure, the upper package 1600A includes, as an example, an element chip 20 mounted on a printed circuit board 1610 by a wire 1620 in a state that the element chip 20 is mounted on a printed circuit board 1610 1610) and an electrical signal exchange mechanism. The device chip 20 may be surrounded by a molding layer 1630. Although the upper package in Fig. 16 shows a structure in which the element chip 20 is wire-bonded and molded with the printed circuit board 1610, it is not limited thereto. Various other modifications are possible as long as they have a structure that is connected to the lower package 1600B by the solder structure 1640. [

In this embodiment, the protective layer for molding the device chip 10 to be mounted in the die mounting cavity 145 of the lower package 1600B may be omitted. At this time, the depth of the die mounting cavity 145 may correspond to the height of the copper pattern layer 132 for stud. That is, the depth of the die mounting cavity 145 may be substantially the same as the height of the copper pattern layer 132 for stud. In this way, the device chip 10 can be structurally stabilized without a protective layer.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. It can be understood that

10 20: element chip, 100: carrier substrate,
110: insulating layer, 115: base copper layer, 115a: base copper layer pattern,
120: etch stop layer, 120a: etch stop layer pattern,
130: copper pattern layer,
131: Copper pattern layer for cavity fabrication, 132: Copper pattern layer for stud,
140: first interlayer insulating layer, 150: first circuit pattern layer,
151: die connection pad, 152: stud connection pad, 155: copper pattern layer,
160: second interlayer insulating layer, 165: via hole, 170: via,
175: second circuit pattern layer, 180: third interlayer insulating layer,
190: via, 195: third circuit pattern layer,
210: a resist pattern layer, 215: a contact hole,
220: cavity-opening mask pattern layer, 225: contact hole,
1010: bump structure,
1600: POP products,
1600A: upper package, 1600B: lower package,
1610: printed circuit board, 1620: wire,
1630: molding layer, 1640: solder structure.

Claims (19)

(a) providing a carrier substrate having an insulating layer and a base copper layer disposed on at least one side of the insulating layer;
(b) forming a copper pattern layer for a stud and a copper pattern layer for manufacturing a cavity on the base copper layer by a plating method;
(c) forming a first interlayer insulating layer on the base copper layer to fill the space between the copper pattern layer for cavity formation and the copper pattern layer for the stud;
(d) separating the insulating layer and the base copper layer of the carrier substrate from each other to expose the base copper layer, wherein the copper pattern layer for cavity formation and the copper pattern layer for stud are stacked on the base copper layer, Forming a structure;
(e) performing a plating method using the exposed base copper layer as a seed layer to form a first circuit pattern layer on a lower surface of the cavity-forming copper pattern layer and the stud-forming copper pattern layer; And
(f) forming the cavity for die-mounting to expose the first circuit pattern layer by selectively removing the copper pattern layer for cavity formation
A method of manufacturing a printed circuit board for POP structure.
The method according to claim 1,
(c)
(c1) providing an epoxy molding compound (EMC) on the base copper layer to form an insulating film that buries the copper pattern layer for cavity fabrication and the copper pattern layer for the stud; And
(c2) grinding the insulating layer to expose the top surfaces of the cavity-forming copper pattern layer and the stud-forming copper pattern layer
A method of manufacturing a printed circuit board for POP structure.
The method according to claim 1,
(e)
A die connection pad is formed on the lower surface of the copper pattern layer for manufacturing a cavity,
And forming a stud connection pad on the lower surface of the copper pattern layer for studs
A method of manufacturing a printed circuit board for POP structure.
The method of claim 3,
(f)
The removal process of the copper pattern layer for manufacturing cavities proceeds to expose the die connection pad
A method of manufacturing a printed circuit board for POP structure.
The method according to claim 1,
After step (e)
Forming a second interlayer insulating layer covering the first circuit pattern layer on the lower surface of the copper pattern layer for cavity formation and the copper pattern layer for the stud;
Forming a via through the second interlayer dielectric layer and electrically connected to at least a portion of the first circuit pattern layer; And
Forming a second circuit pattern layer electrically connected to the vias and disposed on the second interlayer dielectric layer
A method of manufacturing a printed circuit board for POP structure.
The method according to claim 1,
(f)
(f1) forming a solder resist pattern layer selectively exposing an upper surface of the cavity-forming copper pattern layer and the stud-forming copper pattern layer on the first interlayer insulating layer;
(f2) forming a cavity-opening mask pattern layer selectively exposing an upper surface of the cavity-forming copper pattern layer on the solder resist pattern layer; And
(f3) etching the cavity-forming copper pattern layer using the cavity-opening mask pattern layer as an etching mask to expose the first circuit pattern layer;
(f4) removing the cavity-opening mask pattern layer to expose the solder resist pattern layer
A method of manufacturing a printed circuit board for POP structure.
The method according to claim 1,
After step (a)
Further comprising forming a conductive etch stop layer on the base copper layer,
The conductive etch stop layer
In the step (f), the first circuit pattern layer
A method of manufacturing a printed circuit board for POP structure.
8. The method of claim 7,
The conductive etch stop layer is a nickel layer
A method of manufacturing a printed circuit board for POP structure.
(a) providing a carrier substrate having an insulating layer and a base copper layer disposed on at least one side of the insulating layer;
(b) forming a conductive etch stop layer on the base copper layer;
(c) forming a copper pattern layer for cavity formation and a copper pattern layer for a stud on the conductive etch stop layer by a plating method;
(d) a first interlayer insulating layer for burring between the cavity forming copper pattern layer and the stud copper pattern layer on the conductive etch stop layer, the first interlayer insulating layer exposing an upper surface of the cavity forming copper pattern layer and the copper pattern layer for the stud, ;
(e) separating the insulating layer and the base copper layer of the carrier substrate from each other to expose the base copper layer, wherein the copper pattern layer for cavity formation and the copper pattern layer for stud are stacked on the base copper layer, Forming a structure;
(f) performing a plating method using the exposed base copper layer as a seed layer to form a first circuit pattern layer on the lower surfaces of the cavity-forming copper pattern layer and the stud-forming copper pattern layer;
(g) forming a solder resist pattern layer selectively exposing an upper surface of the copper pattern layer for cavity formation and the copper pattern layer for stud on the first interlayer insulating layer;
(h) forming a cavity-opening mask pattern layer on the solder resist layer to selectively expose an upper surface of the cavity-forming copper pattern layer; And
(i) etching the cavity-forming copper pattern layer using the cavity-opening mask pattern layer as an etching mask to expose the first circuit pattern layer
A method of manufacturing a printed circuit board for POP structure.
10. The method of claim 9,
(j) removing the cavity-opening mask pattern layer to expose the solder resist pattern layer
A method of manufacturing a printed circuit board for POP structure.
10. The method of claim 9,
The conductive etch stop layer
(i), the second circuit pattern layer
A method of manufacturing a printed circuit board for POP structure.
10. The method of claim 9,
After step (f)
Forming a second interlayer insulating layer covering the first circuit pattern layer on the lower surface of the copper pattern layer for cavity formation and the copper pattern layer for the stud;
Forming a via through the second interlayer dielectric layer and electrically connected to at least a portion of the first circuit pattern layer; And
Forming a second circuit pattern layer electrically connected to the vias and disposed on the second interlayer dielectric layer
A method of manufacturing a printed circuit board for POP structure.
A lower insulating layer having a die connecting pad and a stud connecting pad;
And an upper insulating layer disposed on the lower insulating layer and having a copper pattern layer for a stud electrically connected to the stud connection pad and having a die mounting cavity for selectively exposing the die connection pad, ,
And a connection structure with an external package is mounted on the copper pattern layer for studs
POP structure printed circuit board.
14. The method of claim 13,
And a solder resist pattern layer for selectively exposing the stud copper pattern layer and the die mounting cavity on the upper insulating layer
POP structure printed circuit board.
14. The method of claim 13,
And at least one via and circuit pattern layer disposed below the lower insulating layer and connected to the stud connection pad
POP structure printed circuit board.
14. The method of claim 13,
Wherein the die connection pad and the stud connection pad comprise an etch protection layer having an etch selectivity to copper
POP structure printed circuit board.
17. The method of claim 16,
The etch protection layer is a nickel layer
POP structure printed circuit board.
An upper package and a lower package connected by a solder structure,
The lower package
A lower insulating layer having a die connecting pad and a stud connecting pad;
An upper insulating layer disposed on the lower insulating layer and having a copper pattern layer for a stud electrically connected to the stud connection pad and having a die mounting cavity for selectively exposing the die connection pad; And
And a device chip connected to the die connection pad inside the die mounting cavity,
And the solder structure with the upper package is mounted on the copper pattern layer for studs
Device package.
19. The method of claim 18,
And the depth of the die mounting cavity corresponds to the height of the copper pattern layer for stud
Device package.

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