KR20160147629A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

The present technology includes a semiconductor device and a manufacturing method thereof. The semiconductor device comprises: a first wiring group including a plurality of wirings stacked by being mutually separated in a step shape; and a second wiring group including the wirings stacked by mutually separated in the step, and mutually separated from the first wiring group. By forming stacked wirings, a size of the semiconductor device can be reduced.

Description

TECHNICAL FIELD The present invention relates to a semiconductor device and a method of manufacturing the same,

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a three-dimensional semiconductor device including stacked wirings and a method of manufacturing the same.

The semiconductor device includes a memory cell array in which data is stored, a peripheral circuit configured to perform program, read, and erase operations of the memory cell array, and a control circuit that controls peripheral circuits in response to the command. The memory cell array includes a plurality of memory blocks, each of the memory blocks including a plurality of cell strings.

In the three-dimensional semiconductor device, since the cell strings are arranged in the vertical direction from the substrate, the source select lines, the word lines, and the drain select lines are vertically stacked from the substrate. In particular, as the number of memory cells and the number of word lines connected to the memory cells increase as the data storage capacity increases, the number of lines for connecting the peripheral circuits and the respective lines also increases.

As the number of wirings increases, the area occupied by the wirings in the three-dimensional semiconductor device also increases, so there is a limitation in reducing the size of the semiconductor device.

Embodiments of the present invention provide a semiconductor device and a method of manufacturing the same that can reduce the size of a semiconductor device by forming stacked wirings.

A semiconductor device according to an embodiment of the present invention includes: a first wiring group including a plurality of wirings stacked in a step-like manner; And a plurality of wiring lines spaced apart from each other in the form of a step, and includes a first wiring group and a second wiring group spaced apart from each other.

A semiconductor device according to an embodiment of the present invention includes: a memory block in which data is stored; Local lines connected to the memory block; A peripheral circuit disposed at a lower end of the memory block; And a plurality of interconnections connecting the peripheral circuit and the local lines to each other and stacked in a stepped manner.

A method of fabricating a semiconductor device according to an embodiment of the present invention includes: stacking insulating films and conductive films alternately; Performing a first etching process such that the conductive films and the insulating films are left in a stepped shape such that a part of the top surfaces of the conductive films are exposed to each layer; And performing a second etching process such that the conductive films and the insulating films having a stepped shape are spaced apart from each other in a horizontal direction.

The present technology can reduce the size of the semiconductor device because the area occupied by the wirings can be reduced by forming a plurality of wirings in a stacked structure.

1 is a view for explaining a semiconductor device according to an embodiment of the present invention.
2 is a perspective view illustrating a three-dimensional memory block according to an embodiment of the present invention.
3 is a perspective view illustrating a memory block having a three-dimensional structure according to another embodiment.
4 is a schematic diagram for explaining the arrangement of the memory cell array and the peripheral circuit of FIG.
5 is a perspective view illustrating a structure of stacked wirings according to an embodiment of the present invention.
6A to 6C are perspective views illustrating a method of manufacturing stacked wirings according to an embodiment of the present invention.
7 is a perspective view for explaining an embodiment in which stacked wirings are applied to a three-dimensional semiconductor device.
8 is a circuit diagram for explaining an embodiment in which stacked wirings are applied to a three-dimensional semiconductor device.
9 is a view for explaining the structure of stacked wirings according to another embodiment of the present invention.
10 is a block diagram illustrating a solid state drive including a semiconductor device according to an embodiment of the present invention.
11 is a block diagram illustrating a memory system including a semiconductor device according to an embodiment of the present invention.
12 is a diagram for explaining a schematic configuration of a computing system including a semiconductor device according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. It should be understood, however, that the invention is not limited to the disclosed embodiments, but may be embodied in many different forms and should not be construed as limiting the scope of the invention to those skilled in the art It is provided to let you know completely.

1 is a view for explaining a semiconductor device according to an embodiment of the present invention.

1, a semiconductor device 1000 includes a memory cell array 110 in which data is stored, a peripheral circuit 120 configured to perform a program operation, a read operation, or an erase operation of the memory cell array 110, And a control circuit (130) configured to control the control circuit (120).

The memory cell array 110 includes a plurality of memory blocks configured identically to each other. Each of the memory blocks may include a plurality of cell strings in a three-dimensional structure. The plurality of strings includes a plurality of memory cells in which data is stored, and may be a three-dimensional structure vertically arranged from the substrate. The memory cells may be composed of single level cells (SLC) capable of storing 1-bit data, multi-level cells (MLC) capable of storing 2-bit or more data, triple- a triple level cell (TLC) or a quadruple level cell (QLC). For example, the multi-level cells MLC are cells in which two bits of data are stored in one memory cell, the triple-level cells TLC are cells in which three bits of data are stored in one memory cell, The level cells QLC are cells in which four bits of data are stored in one memory cell.

The peripheral circuit 120 includes a voltage generating circuit 21, a row decoder 22, a page buffer 23, a column decoder 24 and an input / output circuit 25.

The voltage generating circuit 21 generates operating voltages having various levels in response to the operation signal OP_CMD and applies the generated operating voltages to the global lines GL. For example, the voltage generating circuit 21 can generate a program voltage, a read voltage, and an erase voltage. In addition, the voltage generating circuit 21 can generate various voltages necessary for various operations.

The row decoder 22 selects one of the memory blocks included in the memory cell array 110 in response to the row address RADD and applies the operating voltages to the local lines LL connected to the selected memory block . For example, local lines LL may include source select lines, word lines, and drain select lines.

The page buffer 23 is connected to memory blocks via bit lines BL. The page buffer 23 exchanges data with the selected memory block in response to the page buffer control signals PBSIGNALS during the program, read and erase operations, and temporarily stores the received data.

The column decoder 24 transfers data between the page buffer 23 and the input / output circuit 25 in response to the column address CADD.

The input / output circuit 25 transfers the command (CMD) and the address ADD received from the outside to the control circuit 130, transfers the data (DATA) received from the outside to the column decoder 24, 24 to the outside.

The control circuit 130 controls the peripheral circuit 120 in response to the command CMD and the address ADD. For example, the control circuit 130 may control the peripheral circuit 120 to perform a program operation, a read operation, or an erase operation in response to the command CMD.

2 is a perspective view illustrating a three-dimensional memory block according to an embodiment of the present invention.

Referring to FIG. 2, the memory block of the three-dimensional structure may include cell strings arranged vertically from the substrate and having an I-shape.

The cell strings may be arranged vertically between the bit lines BL and the common source line CSL. This structure is also called BiCS (Bit Cost Scalable). For example, when the common source line CSL is horizontally formed on the top of the substrate, the cell strings having the BiCS structure can be formed in a direction perpendicular to the top of the common source line CSL. More specifically, the cell strings may be arranged in a matrix form in the X and Y directions and include source select transistors formed along the vertical channel films CH arranged vertically above the common source line CSL, Memory cells and drain select transistors. The source select transistors are connected to the source select lines (SSL), the memory cells are connected to the word lines (WL), and the drain select transistors are connected to the drain select lines (DSL). The source select lines SSL, the word lines WL and the drain select lines DSL are sequentially stacked on top of the common source line CSL and extend along the X direction and extend in the Y direction Are spaced apart from each other. The X direction and the Y direction are horizontal with respect to the substrate and perpendicular to each other. The vertical channel films CH are formed inside the vertical holes VH vertically penetrating the source select lines SSL, the word lines WL and the drain select lines DSL, May be projected to the top of the lines (DSL). The bit lines BL may be formed on the vertical channel films CH protruding above the drain select lines DSL. The bit lines BL may be formed in a direction orthogonal to the word lines WL. For example, the bit lines BL extend along the Y direction and are spaced apart from each other in the X direction. A contact plug CT may be further formed between the vertical channel films CH and the bit lines BL.

3 is a perspective view illustrating a memory block having a three-dimensional structure according to another embodiment.

Referring to FIG. 3, cell strings according to another embodiment may be formed in a U-shape.

The cell strings include first substrings arranged vertically between the bit lines BL and the pipeline PL and second substrings arranged vertically between the common source line CSL and the pipeline PL. And a pipeline (PL) connecting the first substrings and the second substrings to each other. This structure is also called P-BiCS (Pipe-shaped Bit Cost Scalable). For example, when the pipeline PL is horizontally formed on the top of the substrate, the cell strings having the P-BiCS structure are formed in the vertical direction on the top of the pipeline PL, and the bit lines BL, A second substring formed between the common source lines CSL and PL and formed in a direction perpendicular to the top of the pipeline PL; . More specifically, the first substrings include word lines WL and drain select lines DSL, which are spaced apart from each other, and word lines WL and drain select lines DSL vertically And may include first vertical channel films (D_CH) passing therethrough. The second substrings are formed by stacking word lines WL and source select lines SSL spaced apart from each other and a second vertical channel passing vertically through word lines WL and source select lines SSL, (S_CH). ≪ / RTI > The word lines WL, the source select lines SSL and the drain select lines DSL may be arranged to extend in the X direction and be spaced apart from each other in the Y direction. The first vertical channel films D_CH and the second vertical channel films S_CH are vertically penetrating through the word lines WL, the source select lines SSL and the drain select lines DSL VH). ≪ / RTI > The first vertical channel films D_CH and the second vertical channel films S_CH are connected to each other by the pipe channel films P_CH in the pipeline PL. The bit lines BL may be arranged in contact with the upper portions of the first vertical channel films D_CH protruding above the drain select lines DSL, extending in the Y direction and spaced apart from each other in the X direction.

4 is a schematic diagram for explaining the arrangement of the memory cell array and the peripheral circuit of FIG.

Referring to FIG. 4, in order to reduce the size of the semiconductor device, a part of the peripheral circuit 120 may be formed under the memory cell array 110. For example, among the peripheral circuits 120, a row decoder (22 in FIG. 1) and a page buffer (23 in FIG. 1) may be formed below the memory cell array 110.

The memory cell array 110 includes a plurality of memory blocks MB1 to MBk (k is a positive integer). Local lines LL are connected to each of the memory blocks MB1 to MBk and bit lines BL are commonly connected to the memory blocks MB1 to MBk. In the case of a three-dimensional semiconductor device, since a plurality of word lines are stacked, a large number of local lines LL are connected to the memory blocks MB1 to MBk.

The total number of the source select lines, the word lines and the drain select lines connected to one memory block is denoted by A, the number of memory blocks MB1 to MBk is denoted by k, , The total number N of the local lines LL is equal to Equation (1). For example, assuming that the number of source select lines connected to one memory block is 3, the number of word lines is 32, the number of drain select lines is 3, and the number of memory blocks is 10, 'A' The total number N of the local lines LL can be 38 × 10 = 380 according to Equation (1) since 3 + 32 + 3 = 38 and k is 10. As such, the semiconductor device includes a large number of wirings in addition to the local lines LL. As the area occupied by the wirings increases, the size of the semiconductor device also increases, so that the area occupied by the wirings can be reduced by forming the wirings in a laminated structure as follows.

5 is a perspective view illustrating a structure of stacked wirings according to an embodiment of the present invention.

Referring to FIG. 5, stacked wirings 120M, which are directly contacted with local lines (LL in FIG. 4) among the peripheral circuits 120, include a plurality of wirings M11 to M76. The stacked wirings 120M are stacked in the vertical direction, that is, the Z direction from the substrate, extend in the X direction, and can be arranged apart from each other in the Y direction.

The structure of the stacked wirings 120M will be described in detail as follows.

The wirings M11 to M16, M21 to M26, M31 to M36, M41 to M46, M51 to M56, M61 to M66 and M71 to M76 formed on the same layer among the stacked wirings 120M are spaced apart from each other in the Y direction And extend in the X direction, respectively. A structure in which wiring lines are stacked in seven layers will be described as an example. It is assumed that the lowermost layer among the layers on which the stacked wirings 120M are formed is referred to as a first layer and the uppermost layer is referred to as a seventh layer. The first wirings M11 to M16 are formed in the first layer, the second wirings M21 to M26 are formed in the second layer, the third wirings M31 to M36 are formed in the third layer The fourth wiring lines M41 to M46 are formed on the fourth layer, the fifth wiring lines M51 to M56 are formed on the fifth layer and the sixth wiring lines M61 to M66 are formed on the sixth layer And seventh wirings M71 to M76 may be formed in the seventh layer. The region where the wirings are separated from each other along the Y direction can be referred to as a slit region (SLR). The first to seventh interlayer insulating films IL1 to ILn are formed from the lower end of the first wirings M11 to M16 to the lower ends of the seventh wirings M71 to M76 for electrical interception between the wirings M11 to M76, And an insulating film (not shown) may also be formed in the slit region SLR. That is, insulating films are formed between the wirings arranged horizontally to each other and between the wirings stacked in a stepwise manner so that the wirings can be electrically separated from each other. The lengths (X direction) of the first interconnection lines M11 to M16 and the first interlayer insulating films IL1 are equal to each other and the length of the second interconnection lines M21 to M26 and the second interlayer insulating films IL2 And the lengths (X direction) of the third interconnection lines M31 to M36 and the third interlayer insulating films IL3 are equal to each other, and the fourth interconnection lines M41 to M46 and the fourth interlayer insulating film The lengths (X direction) of the insulating films IL4 are equal to each other and the lengths (X direction) of the fifth interconnection lines M51 through M56 and the fifth interlayer insulating films IL5 are equal to each other. The lengths (X direction) of the seventh interlayer insulating films IL1 to M66 and the sixth interlayer insulating films IL6 are equal to each other, and the lengths (X direction) of the seventh interconnection lines M71 to M76 and the seventh interlayer insulating films IL7 are Can be formed in the same manner. Alternatively, the lengths of the wirings M1n to M7n of the respective layers and the interlayer insulating films IL1 to IL7 may be formed differently depending on the semiconductor device. The length difference of the wirings formed in each layer can be determined in consideration of the width and length in which the local lines LL contact.

The first interconnection lines M11 to M16 are formed on the first interlayer insulating films IL1 and the second interlayer insulating films IL2 are formed on the upper surface of the first interconnection lines M11 to M16 And is formed on the first wirings M11 to M16. The second interconnection lines M21 to M26 are formed on the second interlayer insulating films IL2 and the third interlayer insulating films IL3 are formed on the upper surface of the second interconnection lines M21 to M26 And is formed on the second wirings M21 to M26. The third interconnection lines M31 to M36 are formed on the third interlayer insulating films IL3 and the fourth interlayer insulating films IL4 are formed on the upper surface of the third interconnection lines M31 to M36 And is formed on the third wirings M31 to M36. The fourth interconnection lines M41 to M46 are formed on the fourth interlayer insulating films IL4 and the fifth interlayer insulating films IL5 are formed on the upper surface of the fourth interconnection lines M41 to M46 And is formed on the fourth wirings M41 to M46. The fifth interconnection lines M51 to M56 are formed on the fifth interlayer insulating films IL5 and the sixth interlayer insulating films IL6 are formed on the upper surface of the fifth interconnection lines M51 to M56 And is formed on the fifth wirings M51 to M56. The sixth interconnection lines M61 to M66 are formed on the sixth interlayer insulating films IL6 and the seventh interlayer insulating films IL7 are formed so that a part of the upper surface of the end portions of the sixth interconnection lines M61 to M66 is exposed And is formed on the sixth wirings M61 to M66. The seventh interconnection lines M71 to M76 are formed on the seventh interlayer insulating films IL7. Local lines may be formed on top of exposed wirings for each layer. More specifically, the contact plugs included in the local lines can be formed on top of exposed wirings for each layer.

As such, by stacking the stacked wirings 120M in the Z direction and the Y direction, the number of wirings can be formed by multiplying the number of wirings stacked in the Y direction and the number of wirings separated in the Y direction.

A method of forming the above-described stacked wirings 120M will be described in detail as follows.

6A to 6C are perspective views illustrating a method of manufacturing stacked wirings according to an embodiment of the present invention.

6A, a first interlayer insulating film IL1, a first conductive film M1, a second interlayer insulating film IL2, a second conductive film M2, and a third interlayer insulating film (not shown) are formed on a substrate IL3, a fourth conductive film M4, a fifth interlayer insulating film IL5, a sixth conductive film M6, a seventh interlayer insulating film IL7 and a seventh conductive film M7 are sequentially formed. In this embodiment, seven interlayer insulating films and conductive films are stacked, respectively, but the number of interlayer insulating films and conductive films may be different depending on semiconductor devices. The first to seventh interlayer insulating films IL1 to IL7 may be formed of an oxide film and the first to seventh conductive films M1 to M7 may be formed of a metal film. For example, the first to seventh conductive films M1 to M7 may be formed of a tungsten film. There are various methods of forming the first to seventh conductive films M1 to M7 from a tungsten film. For example, after a nitride film and a tungsten film are formed between the first to seventh interlayer insulating films IL1 to IL7, a heat treatment process may be performed to perform a replacement process of mixing the tungsten films into the nitride films have. Alternatively, after the sacrificial films are formed between the first to the seventh interlayer insulating films IL1 to IL7, the sacrificial films can be removed in a subsequent process, and the tungsten films can be filled in the regions where the sacrificial films are removed. In addition, the first to seventh interlayer insulating films IL1 to IL7 and the first to seventh conductive films M1 to M7 can be formed by various methods. Hereinafter, a case where the first to seventh conductive films M1 to M7 are formed of a tungsten film will be described as an example. However, since the tungsten film corresponds to the embodiment for understanding the explanation, various kinds of conductive films other than the tungsten film may be used.

Referring to FIG. 6B, a step structure in which the first to seventh interlayer insulating films IL1 to IL7 and the first to seventh conductive films M1 to M7 are paired, 61 - 62). The first etching process may be performed by a slimming process. In the slimming process, the seventh to the first conductive films M7 to M1 and the seventh conductive films M7 to M1 are formed so as to form a stepped structure in which a part of the upper end surface of the conductive films from the seventh conductive film M7 to the first conductive film M1 is sequentially exposed. 7 to the first interlayer insulating films IL7 to IL1. For example, part of the seventh conductive film M7 and the seventh interlayer insulating film IL7 is removed so that a part of the upper surface of the seventh conductive film M7 remains. The etching process for removing the seventh conductive film M7 and the seventh interlayer insulating film IL7 is performed until the sixth conductive film M6 is exposed. When the sixth conductive film M6 is exposed, a part of the sixth conductive film M6 and the sixth interlayer insulating film IL6 are removed so that a part of the upper surface of the sixth conductive film M6 is left. In this manner, the first etching process is performed until a part of the top surface of the first conductive film M 1 is exposed to form a stepped structure.

Referring to FIG. 6C, a second etching process is performed to separate the first to seventh conductive films M1 to M7 having a step structure along the slit regions SLR. The second etching process may be performed using etch mask patterns (not shown) including a plurality of openings. For example, the openings may extend in the X direction and be arranged horizontally to each other along the Y direction. The seventh to the first interlayer insulating films IL7 to IL1 remaining on the bottoms of the seventh to the first conductive films M7 to M1 and the seventh to the first conductive films M7 to M1 exposed along the openings, The first to seventh conductive films M1 to M7 formed on the same layer are separated by a plurality of wirings. For example, if the first layer having the first conductive layer M 1 is formed, the first conductive layer M 1 is divided into six conductive layers by the five slit regions SLR, Wirings M11 to M16 are formed. The width and the interval of the seventh to the first conductive films M7 to M1 may be variously adjusted according to the width and the interval of the slit regions SLR. In order to electrically disconnect between the wirings, an insulating film may be filled in the slit regions SLR. Since the first to seventh conductive films M1 to M7 formed on the first to seventh layers are separated into six conductive films to form a plurality of wirings M11 to M76, The stacked wirings 120M for connecting the different local lines LL can be formed.

7 is a perspective view for explaining an embodiment in which stacked wirings are applied to a three-dimensional semiconductor device.

Referring to FIG. 7, the three-dimensional semiconductor device includes a plurality of local lines LL connecting a memory block and a peripheral circuit to each other. Local lines LL may include a plurality of source select lines SSL, word lines WL, drain select lines DSL and contact plugs. For example, the source select lines (SSL), the word lines (WL), and the drain select lines (DSL) included in the memory block may be sequentially stacked on top of the substrate and the contact plugs Select lines (SSL), word lines (WL), and drain select lines (DSL) and stacked wirings (120M) may be formed to connect with each other.

As the data storage capacity of the semiconductor device increases, the number of memory cells increases, so that the number of word lines WL connected to the memory cells also increases. As the number of word lines WL increases, the number of local lines LL including the word lines WL also increases.

Accordingly, the wiring 120M for connecting the local lines LL to the peripheral circuit 120 (FIG. 4), such as the slimming structure of the word lines WL included in the three-dimensional semiconductor device, And the number of wirings 120M to which different voltages can be applied can be increased within a limited area by separating the wirings stacked in the stepwise structure through the slit regions again with a plurality of wirings. For example, the local lines LL connected to one memory block can be grouped and the local lines LL corresponding to the respective groups can be connected to the wiring groups 71 and 72 divided into the slit regions, respectively .

8 is a circuit diagram for explaining an embodiment in which stacked wirings are applied to a three-dimensional semiconductor device.

Referring to FIG. 8, the memory blocks MBLK and FBLK of the three-dimensional semiconductor device may include main blocks MBLK and flag blocks FBLK. Main data used by a user is stored in the main blocks MBLK, and data necessary for operation of the semiconductor device is stored in the flag blocks FBLK. The memory blocks MBLK and FBLK may include source select transistors SST, memory cells F0 to Fn, and drain select transistors DST connected vertically from the substrate. The source select transistors SST may be connected to the common source line SL and the drain select transistors DST may be connected to the bit lines BL0 to BLj. The gates of the source select transistors SST can be connected to the source select lines SSL and the gates of the memory cells F0 to Fn can be connected to the word lines WL0 to WLn and the drain select transistors DST may be connected to the drain select lines DSL. The source select lines SSL, the word lines WL0 to WLn and the drain select lines DSL may be included in the local lines LL. The local lines LL may be connected to the peripheral circuits via the wirings 120M of the peripheral circuits. For example, the local lines LL may be connected to the path switch circuit SW included in the low-level decoder among the peripheral circuits. The pass switch circuit SW may be a circuit for transferring an operating voltage to local lines LL of a memory block selected from among a plurality of memory blocks. The pass switch circuit SW may include a plurality of pass transistors TR_P connected between the global lines GL and the local lines LL. Although not shown in the figure, the global lines GL may be connected to a voltage generating circuit (21 in Fig. 1).

9 is a view for explaining the structure of stacked wirings according to another embodiment of the present invention.

9, the drawing in the X-Y direction is a layout view of the layered wirings 120M, and the drawing shown in the lower part of the layout diagram is a perspective view in the X, Y, and Z directions.

The number of the stacked wirings 120M is determined by the number of layers of the stairs 90 and the number of the slit regions SLR and the layout for connecting the stacked wirings 120M and the peripheral circuits to each other is determined by the number of slit regions SLR). ≪ / RTI > Therefore, by modifying the layout of the slit regions SLR, the stacked wirings 120M can be formed in various structures that can connect a plurality of local lines LL and peripheral circuits within a limited area with each other. Further, since the thickness and the width of the wirings formed on each layer can be adjusted, the resistance of the wirings can be controlled to be different for each layer, and the wirings can be formed taking the electrical characteristics into consideration. Although not shown in FIG. 9, interlayer insulating films are formed between the stacked wirings 120M, so that the stacked wirings 120M of different layers can be electrically separated from each other.

As described above, since a plurality of wirings can be formed in a limited area without increasing the area occupied by the wirings, the size of the semiconductor device can be reduced.

10 is a block diagram illustrating a solid state drive including a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 10, a drive device 2000 includes a host 2100 and an SSD 2200. The SSD 2200 includes an SSD controller 2210, a buffer memory 2220, and a semiconductor device 1000.

The SSD control unit 2210 provides a physical connection between the host 2100 and the SSD 2200. That is, the SSD control unit 2210 provides interfacing with the SSD 2200 in response to the bus format of the host 2100. In particular, the SSD control unit 2210 decodes the command provided from the host 2100. The SSD control unit 2210 accesses the semiconductor device 1000 according to the decoded result. (PCI) express, ATA, PATA (Parallel ATA), SATA (Serial ATA), SAS (Serial Attached SCSI), and the like are used as the bus format of the host 2100. [ And the like.

In the buffer memory 2220, program data provided from the host 2100 or data read from the semiconductor device 1000 is temporarily stored. When data existing in the semiconductor device 1000 is cached at the time of a read request of the host 2100, the buffer memory 2220 supports a cache function of directly providing the cached data to the host 2100. In general, the data transfer rate by the bus format (e.g., SATA or SAS) of the host 2100 is faster than the transfer rate of the memory channel of the SSD 2200. That is, when the interface speed of the host 2100 is higher than the transmission speed of the memory channel of the SSD 2200, performance degradation caused by the speed difference can be minimized by providing the buffer memory 2220 of a large capacity. The buffer memory 2220 may be provided to a synchronous DRAM (DRAM) in order to provide sufficient buffering in the SSD 2200 used as a large capacity auxiliary storage device.

The semiconductor device 1000 is provided as a storage medium of the SSD 2200. For example, the semiconductor device 1000 may be provided as a nonvolatile memory device having a large capacity storage capability as described above with reference to FIG. 1, and may be provided as a NAND-type flash memory among nonvolatile memories .

11 is a block diagram illustrating a memory system including a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 11, a memory system 3000 according to the present invention may include a memory controller 3100 and a semiconductor device 1000.

Since the semiconductor device 1000 can be configured substantially the same as that of FIG. 1, a detailed description of the semiconductor device 1000 will be omitted.

The memory control unit 3100 may be configured to control the semiconductor device 1000. [ The SRAM 3110 can be used as a working memory of the CPU 3120. [ The host interface 3130 (Host I / F) may have a data exchange protocol of a host connected to the memory system 3000. An error correction circuit 3140 (ECC) provided in the memory control unit 3100 can detect and correct an error included in the data read from the semiconductor device 1000. A semiconductor interface (I / F) 3150 may interface with the semiconductor device 1000. The CPU 3120 can perform a control operation for exchanging data of the memory control unit 3100. [ 11, the memory system 3000 may further be provided with a ROM (not shown) or the like for storing code data for interfacing with a host (Host).

The memory system 3000 in accordance with the present invention may be implemented as a computer system, such as a computer, a UMPC (Ultra Mobile PC), a workstation, a netbook, a PDA, a portable computer, a web tablet, a wireless phone A mobile phone, a smart phone, a digital camera, a digital audio recorder, a digital audio player, a digital picture recorder, A digital video player, a digital video player, a device capable of transmitting and receiving information in a wireless environment, and a device applied to one of various devices constituting a home network .

12 is a diagram for explaining a schematic configuration of a computing system including a semiconductor device according to an embodiment of the present invention.

12, a computing system 4000 according to the present invention includes a semiconductor device 1000 electrically connected to a bus 4300, a memory controller 4100, a modem 4200, a microprocessor 4400, and a user interface 4500). If the computing system 4000 according to the present invention is a mobile device, a battery 4600 for supplying the operating voltage of the computing system 4000 may additionally be provided. Although not shown in the figure, the computing system 4000 according to the present invention may further include an application chip set, a camera image processor (CIS), a mobile DRAM, and the like.

Since the semiconductor device 1000 can be configured substantially the same as that of FIG. 1, a detailed description of the semiconductor device 1000 will be omitted.

The memory controller 4100 and the semiconductor device 1000 may constitute a solid state drive / disk (SSD).

The semiconductor device and the memory controller according to the present invention can be mounted using various types of packages. For example, the semiconductor device and the memory control unit according to the present invention can be used in various applications such as package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PLCC) PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP) ), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP) and Wafer-Level Processed Stack Package And can be implemented using the same packages.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention.

1000: semiconductor device 110: memory cell array
120: peripheral circuit 130: control circuit
21: voltage generation circuit 22:
23: page buffer 24: column decoder
25: I / O circuit 120M: stacked wirings
SLR: Slit area

Claims (20)

A first wiring group including a plurality of wirings stacked and spaced apart in a stepwise manner; And
And a second wiring group spaced apart from the first wiring group, wherein the second wiring group includes a plurality of wirings separated from each other in a stepped shape.
A memory block in which data is stored;
Local lines connected to the memory block;
A peripheral circuit disposed at a lower end of the memory block; And
And a plurality of interconnections interconnecting the peripheral circuit and the local lines and stacked in a stepped manner.
The memory device according to claim 2,
A semiconductor device comprising a plurality of cell strings in a three-dimensional structure.
3. The method of claim 2,
Wherein the local lines comprise source select lines, word lines and drain select lines.
The semiconductor device according to claim 2,
Wherein the semiconductor device is stacked in a stepped shape having a shorter length from the lower part to the upper part and is spaced apart from each other in the horizontal direction.
The semiconductor device according to claim 2,
First wirings arranged horizontally to each other in the first layer;
And second wirings arranged horizontally to each other in a second layer above the first layer and shorter than the first wirings.
7. The semiconductor device according to claim 6,
And a plurality of wirings arranged horizontally to each other in the upper layers of the second layer and having a shorter length toward the upper layer.
8. The method of claim 7,
Wherein the insulating films are formed between the wirings arranged horizontally to each other and between the wirings stacked in the stepwise form so that the wirings are electrically isolated from each other.
3. The method of claim 2,
And each of the wirings exposes a part of the upper surface of the end.
10. The method of claim 9,
Wherein the local lines are connected to an upper portion of the exposed wiring.
The semiconductor device according to claim 1,
Various widths, various heights, and various gaps,
And is formed to have various widths, various heights, or various intervals.
Alternately laminating the insulating films and the conductive films;
Performing a first etching process such that the conductive films and the insulating films are left in a stepped shape such that a part of the top surfaces of the conductive films are exposed to each layer;
And performing a second etching process so that the conductive films having the step shape and the insulating films are spaced apart from each other in the horizontal direction.
13. The method of claim 12,
Wherein the insulating films include oxide films.
13. The method of claim 12,
Wherein the conductive films are formed of a doped polysilicon film or a metal film.
15. The method of claim 14,
Wherein the metal film comprises a tungsten film.
13. The method of claim 12,
Wherein the first etching process is performed by a slimming process.
17. The method of claim 16, wherein the slimming step comprises:
Wherein the conductive films and the insulating films are sequentially etched so as to form a stepped structure in which a part of an upper end surface of the conductive films is sequentially exposed.
13. The method of claim 12,
Wherein the second etching process is performed such that a part of the conductive films and the insulating films are removed in a vertical direction.
19. The method of claim 18,
Wherein the second etching process is performed using etching mask patterns in which openings are formed in a region where the conductive films and a part of the insulating films are to be removed.
20. The method of claim 19,
And the layout of the wirings is determined according to the shape of the openings.

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