KR20160147369A - Receiver for ocean bottom seismology - Google Patents

Abstract

Provided is a receiver for ocean floor seismic wave exploration. According to a preferred embodiment of the present invention, the receiver for ocean floor seismic wave exploration uses ADS1251 as an A/D converter, does not use an additional clock generator IC for providing a system clock (CLK) to the A/D converter, and has a microprocessor, which provides a system CLK to the A/D converter during only a period requiring A/D conversion. Therefore, the receiver for ocean floor seismic wave exploration can simplify configuration thereof, reduce power consumption, and control the speed of A/D conversion as desired. In particular, according to a preferred embodiment of the present invention, the receiver for ocean floor seismic wave exploration can synchronize multiple A/D converters in a simple manner by simultaneously inputting the system CLK, output by the microprocessor, into the AD/ converts.

Description

Receiver for ocean bottom seismology [

The present invention relates to a receiver for seabed seismic wave navigation.

Receivers for Ocean Bottom Seismology (OBS) should be installed on the seafloor and operate with battery only, so they should be recovered after a few days to several weeks. OBS uses one hydrophone and one or more geophones, so a multi-channel data collector is required. Also, since the dynamic range of the acoustic signal received by the OBS is very wide, a high-resolution A / D converter 20 of 24-bit or more is required.

The ADS1251 is a 24-bit high-resolution analog-to-digital converter (AD) 20, which is the most widely used IC for OBS. Since the ADS1251 is a single-channel A / D converter 20, the ADS1251 should be used for the number of channels to perform two or more synchronized multi-channel A / D conversions.

The ADS1251 is a single-channel 24-bit A / D converter (20) designed for high resolution signal measurements and is widely used in precision scales, heart rate meters, and hydrophone receivers.

FIG. 1A is a schematic diagram of an ADS1251, and FIG. 1B is a diagram illustrating an example of a conventional undersea seismic wave detection receiver using ADS1251.

1A and 1B, the analog signal measured by the sensor unit 10 is input to the + Vin and -Vin pins as differential inputs, and the range of the input voltage is allowed between + Vref and -Vref. The maximum voltage of Vref is + 5V. In this case, the input voltage range is 5V. The interface between the ADS 1251 and the microprocessor 30 is connected by three digital pins, and the names of the pins are CLK, SCLK and DOUT / DRDY.

The ADS1251 outputs data controlled by SCLK and converted to DOUT / DRDY pins. CLK is a system clock generated by a clock generator and always supplied, and SCLK is a digital clock that the user must control in A / D conversion. The system clock generator IC (40) recommended by the ADS1251 manufacturer is the ICD2053 variable clock generator.

2 is a diagram showing the DOUT / DRDY pulse timing output from the ADS 1251 to the microprocessor 30. [

The pulse waveform shown in FIG. 2 is the DOUT / DRDY pulse timing according to the SCLK clock of the ADS1251, and the DOUT / DRDY pulse is composed of two modes. DRDY mode is a mode that indicates whether A / D conversion data is prepared in the output register inside the ADS1251. DOUT mode outputs 24 bits from MSB (least significant bit) to LSB (least significant bit).

In DRDY mode, A / D conversion is performed while 24 clocks of CLK are supplied first (t4), DOUT / DRDY outputs a high pulse, and then DOUT / DRDY outputs a low pulse. After DOUT / DRDY outputs a high pulse again for six CLKs (t3), the DRDY mode ends and the mode changes to DOUT mode.

In the DOUT mode, DOUT mode is a mode for outputting 24 bits of data, one bit per SCLK clock, irrespective of CLK. The output order of the data bits is from MSB. In DOUT mode, the output of data is not related to CLK, but a total of 348 CLK clocks must be supplied to terminate DOUT mode. When the DOUT mode ends, the DRDY mode is resumed and a new A / D conversion is performed. In FIG. 2, it can be seen that tDRDY is composed of a total of 384 CLKs with a time length corresponding to one A / D conversion. Even if SCLK is not used during tDRDY and it is kept low, one A / D conversion is performed. The 24 SCLKs are the clocks that must be input to read the converted 24-bit data.

Here, the A / D conversion function of the ADS1251, which is the A / D converter 20 used in the prior art, can be summarized as follows.

- A / D conversion is performed every 384 CLK clock periods (tDRDY).

- To read the converted AD value, 24 SCLK clocks must be supplied.

- The start of the SCLK clock supply should be timed by sensing the moment when the DOUT / DRDY pulse changes from high to low to high again.

At least two A / D conversion channels are required for OBS receivers and synchronization between channels is essential in A / D conversion. That is, there should be no difference in conversion time between channels. The multi-channel A / D converter 20 composed of one IC sequentially performs A / D conversion on a channel-by-channel basis, so that there is a difference in conversion time and there is a synchronized multichannel A / D converter 20, This is large and expensive and is rarely used in OBS receivers. For the OBS receiver, it is common to configure a synchronized multi-channel A / D converter 20 using a single channel, the ADS1251.

3 is a timing diagram illustrating a synchronization mode in which ADS1251 can be synchronized when a plurality of ADS1251 is used as a synchronization mode provided basically by ADS1251. For synchronization of multiple ADS1251s, SCLK should be held high during four tDRDYs (corresponding to 4 tDRDY in Fig. 3). Once switched to the synchronous mode, the synchronized A / D conversion can continue with the DOUT / DRDY pulse timing as shown in FIG. 2 until the power is turned off. After each tDRDY, each ADS1251 synchronized conversion data is generated and read individually, and it must be read within the DOUT mode period (348 CLK). After this period, the new A / D conversion will resume and the previous data will be erased.

As described above, a method of performing multi-channel A / D conversion using a plurality of ADS1251 has been provided by Texas Instrument Co., Ltd. with a PCB board for evaluation of ADS1251 and a recommended circuit diagram. Conventional OBS receivers mainly adopt this method.

The ADS1251 is an A / D converter 20 having a structure in which a separate system clock (CLK) is continuously supplied. Since A / D conversion is performed once every 384 CLKs, the A / D conversion speed is also determined by the system clock. The same system clock should be supplied to each transducer 20 even when the ADS1251 should be used for the number of channels for two or more multichannel A / D conversions.

The ADS1251's own multi-channel synchronization mode is also available. However, the basic synchronization mode must be continuously detecting the DOUT / DRDY pulse timing even if the setting is complicated and the A / D conversion data is unnecessary. In other words, the basic A / D conversion function is suitable only for the application that suits a certain A / D conversion speed.

In recent high resolution A / D conversion, it is common to use the average of the measured values several times in order to reduce the error, and the fixed A / D conversion speed is not efficient. This is because a conversion rate much faster than the sample interval is required for multiple measurements. Also, it is desirable to reduce power consumption by disabling A / D conversion during periods when data are not needed. Therefore, using the ADS1251's own multi-channel synchronization mode is very inefficient.

A problem to be solved by the present invention is to provide an undersea seismic wave receiver using an ADS1251 as an A / D converter, which is most commonly used for an undersea seismic wave receiver, without using a separate clock generator IC as a system clock (CLK) It is possible to simplify the configuration of the receiver by providing the system clock in the microprocessor only during the period in which the / D conversion is required, to reduce the power consumption, to adjust the A / D conversion rate arbitrarily, .

According to a preferred embodiment of the present invention, there is provided a receiver for seabed acoustic-wave navigation, comprising: a plurality of sensor units for measuring seafloor seismic waves; A plurality of A / D converters receiving sensor values from the plurality of sensor units, respectively, and synchronizing with each other according to a clock signal input from the microprocessor, and converting an analog measurement signal input from a sensor unit connected thereto into a digital signal; And a microprocessor for generating and outputting a system clock signal as a common clock signal to the plurality of A / D converters, and receiving a digital signal from the plurality of A / D converters.

Also, the microprocessor may generate a clock signal only when a sensor value measured by the sensor unit is required, and output the generated clock signal to the plurality of A / D converters.

The A / D converter includes a first mode (DRDY mode) for converting an analog signal input from the sensor unit into a digital signal, and a second mode (DOUT mode) for outputting the converted digital signal to the microprocessor Lt; / RTI >

In the first mode, the A / D converter converts an analog signal input from the sensor unit into a digital signal while receiving 24 clock signals from the microprocessor, and in the second mode, every four clocks And output the digital signal to the microprocessor by one bit for each signal.

A submarine seismic wave seeker according to a preferred embodiment of the present invention includes a separate clock generator IC for providing a system clock (CLK) to an A / D converter in an undersea seismic wave receiver using the ADS1251 as an A / D converter By providing the system clock from the microprocessor to the A / D converter only during the period when the A / D conversion is not required, the receiver configuration can be simplified, power consumption can be reduced, and the A / It is possible to arbitrarily adjust it. Particularly, a submarine seismic wave seeker according to a preferred embodiment of the present invention includes a plurality of A / D converters, .

FIG. 1A is a schematic diagram of an ADS1251, and FIG. 1B is a diagram illustrating an example of a conventional undersea seismic wave detection receiver using ADS1251.
2 is a diagram showing the DOUT / DRDY pulse timing output from the ADS1251 to the microprocessor.
3 is a timing diagram illustrating a synchronization mode in which ADS1251 can be synchronized when a plurality of ADS1251 is used as a synchronization mode provided basically by ADS1251.
FIG. 4A is a block diagram illustrating a configuration of a seabed seismic wave detection receiver according to a preferred embodiment of the present invention, and FIG. 4B is a diagram illustrating a circuit configuration of a receiver according to a preferred embodiment of the present invention.
5 is a timing chart for explaining a processing flow of a signal performed in the receiver shown in Figs. 4A and 4B.

FIG. 4A is a block diagram illustrating a configuration of a seabed seismic wave detection receiver according to a preferred embodiment of the present invention, FIG. 4B is a diagram illustrating a circuit configuration of a receiver according to a preferred embodiment of the present invention, 4A and 4B; Fig.

Hereinafter, a submarine seismic wave sensing receiver according to a preferred embodiment of the present invention will be described with reference to FIGS.

4A and 4B, another submarine seismic wave detection receiver according to a preferred embodiment of the present invention includes a plurality of sensor units 210-1 to 210-N, a plurality of A / D converters 220-1 to 220- 220-N, and a microprocessor 230.

First, a plurality of sensor units 210-1 to 210-N measure seafloor seismic waves and output analog measurement signals to a plurality of A / D converters 220-1 to 220-N to which they are connected.

When a CLK signal is input from the microprocessor 230, the plurality of A / D converters 220-1 to 220-N receive sensor values, which are analog signals, from the sensor unit 210 connected thereto, 230, and converts the analog measurement signal input from the sensor unit 210 to a digital signal and outputs the digital signal to the microprocessor 230. [

The microprocessor 230 generates a system clock signal when a signal measured by the plurality of sensor units 210-1 to 210-N is requested and outputs a system clock signal as a common clock signal to the plurality of A / D converters 220-1 to 220- N, and receives and processes digital signals from a plurality of A / D converters 220-1 to 220-N.

4A and 4B, configurations and power sources that are not related to the operation of the A / D converter 220 and the microprocessor 230 are omitted from illustration. Although FIG. 4B shows an example in which the PIC32MX795 is used as the microprocessor 230, those skilled in the art will recognize that other types of microprocessors may be used.

In the example shown in Figure 4B, the two A / D converters ADS1251, 220 CLK clocks are connected to the same microprocessor pin (here RG7) and the SCLK clock is also connected to the same microprocessor pin RG6, The two A / D converters (ADS1251) 220 are simply synchronized.

Data of two 24-bit channels, Ch0 and Ch1, according to the A / D conversion are received at the RB0 and RB1 pins of the microprocessor 230, respectively. When the channel is added, the CLK clock of the added A / D converter is connected to the same RG7 pin, and the SCLK clock is connected to the same RG6 pin. The Ch2 data is connected to the RB2 pin and the Ch3 data is output to the RB3 pin As shown in FIG.

5 is a timing chart for explaining a processing flow of a signal performed in the receiver shown in Figs. 4A and 4B. In FIG. 5, the CLK clock is generated at a single output pin of the microprocessor 230 in a software manner. In FIG. 5, the number of CLK clocks required for one A / D conversion is shown. In the period t4, 24 CLK clocks are supplied to perform 24-bit A / D conversion. And the DOUT / DRDY pulse changes from low to high to complete the DRDY mode.

A total of 348 CLK clocks are required in DOUT mode. Each SCLK clock generates four CLKs (two at SCLK low and two at high), providing a total of 96 CLKs while the SCLK clock is 24 outputs. Then, the remaining 252 CLKs are supplied to terminate the DOUT mode. Here, whenever the SCLK clock is input from the microprocessor 230 one by one, the A / D converter 220 outputs the digitally converted signal to the microprocessor 230 by 1 bit from the MSB to the LSB.

After that, CLK returns to the low state until the next A / D conversion. Since the prior art has a separate clock generator IC as shown in FIG. 2, the clock CLK is generated at a constant frequency without interruption, and the A / D conversion is forcibly performed whenever CLK is input 384 times. Therefore, since the present invention generates a CLK signal (clock signal) only when a measurement signal is required by the microprocessor 230 and no CLK is generated at other times, power consumption can be greatly reduced compared to the prior art Effect appears.

In this example, it is possible to supply 348 CLKs at a time without supplying CLK during the 24 SCLK clock periods used for the A / D conversion once, but there are reasons for supplying four CLKs every SCLK clock. The number of CLKs to be supplied for each SCLK clock may be appropriately distributed according to the processing speed of the microprocessor 230 to be used. In the embodiment of the present invention, the microprocessor 230 uses a 32-bit PIC32MX795 manufactured by Microchip, At a processing speed of 40 MHz, the maximum clock speed that can be output to the microprocessor pins is 20 MHz. This rate is very fast, requiring a reasonable amount of time delay per SCLK clock, so that instead of this delay, CLK is properly placed.

As for the synchronization between channels, in order to synchronize the A / D conversion data at a specific point of the CLK clock, the synchronized tDRDY can be generated after the SCLK is kept high during four times of tDRDY as shown in FIG. 3 On the other hand, in the method according to the present invention, synchronization is automatically performed without keeping the SCLK clock high. This is because the A / D conversion timing is accurate since the start and the number of the CLK clocks are clearly defined by software. Since there is no CLK clock in a period in which there is no A / D conversion, no timing error occurs.

On the other hand, one software CLK clock is created with two lines of commands listed in Table 1 below. The following command sets the RG7 pin of PORTG corresponding to CLK to high (1) or low (0). The programming language is C.

// Command to create one CLK clock Two lines
PORTGSET = 0x0080; // RG7 high (corresponds to CLK = 1)
PORTGCLR = 0x0080; // RG7 low (corresponds to CLK = 0)

It is an easy and quick way to separate 24-bit data by A / D conversion by channel by bit operation after reading PORTB port rather than by reading each channel separately. 5 shows an example of a bit operation program for extracting 24-bit data during the DOUT mode period in FIG. It can be seen in the program example below that the SCLK clock has been supplied with two CLK clocks before and after the transition from low to high.

////////////////////////////////////////////////////// ///////////////////
ch0_data = 0; // Initialize 32bit integer variable for ch0
ch1_data = 0; // initialization of 32bit integer variable for ch1
i = 0; // Initialize the SCLK count counter
do {
// Supply two CLK clocks
PORTGSET = 0x0080; // Port command corresponding to CLK = 1
PORTGCLR = 0x0080; // Port instruction corresponding to CLK = 0
PORTGSET = 0x0080; // Port command corresponding to CLK = 1
PORTGCLR = 0x0080; // Port instruction corresponding to CLK = 0
// Set SCLK clock high and read PORTB
PORTGSET = 0x0040; // Port instruction corresponding to SCLK = 1
j = mPORTBRead (); // Read PORTB and store it in variable j


// Supply two CLK clocks
PORTGSET = 0x0080; // Port command corresponding to CLK = 1
PORTGCLR = 0x0080; // Port instruction corresponding to CLK = 0
PORTGSET = 0x0080; // Port command corresponding to CLK = 1
PORTGCLR = 0x0080; // Port instruction corresponding to CLK = 0
// Change the SCLK clock to low
PORTGCLR = 0x0040; // Port instruction corresponding to SCLK = 0
// Split bits of Ch0 and Ch1
ch0_data + = j &
ch1_data + = j &
// shift the bit left for the next bit
ch0_data << = 1;
ch1_data << = 1;
i ++;
} while (i <24); // If the SCLK clock is 24, end the loop
// Up to now, 24 * 4 = 96 CLK clocks have been supplied
// Supply the remaining 252 clocks to supply a total of 348 CLKs
do {
PORTGSET = 0x0080; // Port command corresponding to CLK = 1
PORTGCLR = 0x0080; // Port instruction corresponding to CLK = 0
i ++;
} while (i &lt;348);
// Abnormal DOUT mode ended

// Because ch0 data is PORTB's 0th pin input, no correction is needed
// The data of ch1 is the input of pin 1 of PORTB, so it needs to be corrected by one bit.
ch1_data >> = 1;
// 24-bit ch0 data is stored in ch0_data and ch1 data is stored in ch1_data
////////////////////////////////////////////////////// ///////////////////

The present invention has been described with reference to the preferred embodiments. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the present invention is defined by the appended claims rather than by the foregoing description, and all differences within the scope of equivalents thereof should be construed as being included in the present invention.

210:
220: A / D converter
230: Microprocessor

Claims (3)

A plurality of sensor units for measuring seafloor elastic waves;
A plurality of A / D converters receiving sensor values from the plurality of sensor units, respectively, and synchronizing with each other according to a clock signal input from the microprocessor, and converting an analog measurement signal input from a sensor unit connected thereto into a digital signal; And
And a microprocessor for generating a system clock signal and outputting the system clock signal as a common clock signal to the plurality of A / D converters, and receiving a digital signal from the plurality of A / D converters. The method according to claim 1,
Wherein the microprocessor generates a clock signal only when a sensor value measured by the sensor unit is required and outputs the generated clock signal to the plurality of A / D converters. 3. The apparatus of claim 2, wherein the A / D converter
A first mode (DRDY mode) for converting an analog signal input from the sensor unit into a digital signal, and a second mode (DOUT mode) for outputting the converted digital signal to the microprocessor Tom use receiver.

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