KR20160141189A - Display device - Google Patents

Abstract

An embodiment of the present invention relates to a display device which can determine an alignment error of a color filter using an alignment confirm key by forming, on a display region, the alignment confirm key (or referred to as an overlay key) capable of determining the alignment error of the color filter. The display device according to an embodiment of the present invention comprises a lower substrate, an upper substrate, and a liquid crystal layer interposed between the lower substrate and the upper substrate. In the lower substrate, a display region and a non-display region around the display region are provided. The display region includes pixels including gate lines, data lines, transistors connected to the gate and data lines and pixel electrodes connected to the transistors. In the display region of the lower substrate, a first alignment confirm key is provided.

Description

Display device {DISPLAY DEVICE}

An embodiment of the present invention relates to a display device.

2. Description of the Related Art Recently, various flat display devices capable of reducing weight and volume, which are disadvantages of cathode ray tubes (CRTs), have been developed. Examples of such flat panel display devices include a liquid crystal display, a field emission display, and an organic light emitting display.

In recent years, a large-sized flat panel display device having a size of 100 inches or more has been developed according to the development of technology, and a demand for a large-sized flat panel display device of 100 inches or more is increasing. In order to manufacture a large-screen flat panel display device having a size of 100 inches or more, a 2200 x 2500 mm mother substrate (mother substrate, also referred to as a mother substrate) must be used as a whole.

The largest inch large screen flat panel display that can be manufactured using a 2200x2500 mm motherboard is known as 128 inches. The 128-inch large screen flat panel display can be manufactured by attaching a thin film transistor mother substrate having a thin film transistor array formed thereon and a color filter mother substrate having a color filter array formed thereon.

1 is an exemplary view showing a color filter mask and a color filter mother board for forming a color filter array in the case of a large-screen display apparatus. 1, since the size of the color filter array CA is large in the case of the large screen display device, the color filter mother substrate MS is divided into the plurality of areas A1 to A20, Is moved to each of the plurality of regions A1 to A20 to form a color filter. The color filter mask CM includes a masking area MA, a patterned opening area OA, and a second alignment key AK2 as shown in Fig.

In the case of the large-screen display device, the dummy area DA exists only on the edge of the color filter mother substrate MS because the color filter array CA is formed over the color filter mother substrate MS. The dummy area DA is the area outside the scribing line SL in the color filter mother substrate MS. The thin film transistor mother substrate and the color filter mother substrate are bonded together and cut along the scribing line (SL). Therefore, the dummy area DA is an area to be discarded after the scribing process.

The color filter may be formed in the color filter array CA by aligning the color filter mask CM on the color filter mother substrate MS and then performing a photolithography process. Specifically, the color filter mother substrate MS and the color filter mask CM sandwich each of the first alignment keys AK1 formed on the color filter mother substrate MS with a second alignment Keys AK2, respectively. The opening area of the color filter array CA can be reduced when the first alignment keys AK1 are formed in the color filter array CA so that they are formed outside the color filter array CA. FIG. 1 shows only a part of the first alignment keys AK1 for convenience of explanation.

In order to properly align the color filter mother substrate MS and the color filter mask CM, it is preferable to arrange them using the first alignment keys and the second alignment keys in the diagonal direction. For example, when a color filter is formed in the sixth area A6 of the color filter array CA as shown in Fig. 1, the first and second alignment keys AK1 and AK2, which are located diagonally of the first and second alignment keys AK1 and AK2, The color filter mother substrate MS and the color filter mask CM can be aligned using the alignment keys AK1_D and the second alignment keys AK2_D. Even when the color filters are formed in the first, sixth, seventh, fourteenth and fifteenth regions A6, A7, A14, and A15, the first and second alignment areas AK1 and AK2, The color filter mother substrate MS and the color filter mask CM can be aligned using the keys and the second alignment keys.

However, in the case of the large-screen display device, since the dummy area DA exists only on the edge of the color filter mother substrate MS, it can not be aligned using the first and second alignment keys in the diagonal direction, There may arise a case where only the first alignment keys and the second alignment keys are used to align. For example, when the color filters are formed in the eleventh area A11 of the color filter array CA as shown in FIG. 1, the color filters in the vertical direction (y-axis direction) among the first and second alignment keys AK1 and AK2, The color filter mother substrate MS and the color filter mask CM can be aligned using the first alignment keys AK1_V and the second alignment keys AK2_V. When forming color filters in the first to fifth, eighth to tenth, twelfth, thirteenth, and sixteenth to twentieth regions A1 to A5, A8 to A10, A12, A13, A16 to A20 The color filter mother substrate MS and the color filter MA are formed using only the first alignment keys and the second alignment keys located in the vertical direction (y-axis direction) among the first and second alignment keys AK1 and AK2, The mask CM can be aligned.

As a result, in the case of the large-screen display device, the color filter mother substrate MS and the color filter mask CM are aligned (aligned) using the first alignment keys in the diagonal direction and the second alignment keys in accordance with the area of the color filter array CA. Or aligned using first and second alignment keys in the vertical direction (y-axis direction). Therefore, there is a need for a separate alignment check key (also referred to as an overlay key) to determine whether an alignment error of the color filters has occurred and thus formed the color filter properly.

An embodiment of the present invention provides a display device capable of determining an alignment error of a color filter using an alignment confirmation key by forming an alignment confirmation key in a display area capable of determining an alignment error of the color filter.

A display device according to an embodiment of the present invention includes a lower substrate, an upper substrate, and a liquid crystal layer interposed between the lower substrate and the upper substrate. Wherein the lower substrate includes a display region including pixels including gate lines, data lines, transistors connected to the gate lines and data lines, and pixel electrodes connected to the transistors, Is provided. A first alignment confirmation key is provided in a display area of the lower substrate.

An embodiment of the present invention forms a first alignment confirmation key including a color filter key in a display area. As a result, the embodiment of the present invention can confirm whether the color filters are properly formed in the display area by using the first alignment confirmation key in the large-screen display device.

Also, embodiments of the present invention form first and second alignment confirmation keys in the non-aperture region of the pixel. As a result, in the embodiment of the present invention, since there is no loss of the aperture area due to the first and second alignment confirmation keys, even if the first and second alignment confirmation keys are formed in the display area, Do not.

In addition, the embodiment of the present invention places a plurality of gate lines and a plurality of common lines between pixel electrodes. In this case, since the first and second alignment confirmation keys can be formed in the region where the plurality of gate lines and the plurality of common lines are formed, the embodiment of the present invention is effective in the case of arranging one gate line between the pixel electrodes The width of the opening region can be widened.

Furthermore, by forming the first alignment confirmation keys in the non-display area, the difference in friction force felt by the rubbing cloth between the area where the exposure hole is formed in the display area and the area where the exposure hole is not formed can be reduced. Therefore, in the embodiment of the present invention, it is possible to reduce the occurrence of orientation difference in the region where the exposure hole is formed in the display region and the region where the exposure hole is not formed, and as a result, the problem that a predetermined line is visually recognized along the rubbing direction is prevented can do.

1 is an exemplary view showing a color filter mask and a color filter mother board for forming a color filter array in case of a large-screen display apparatus.
2 is a plan view showing a display device according to an embodiment of the present invention;
FIGS. 3A and 3B are plan views showing the thin film transistor substrate and the black column spacer substrate in detail, when the color filter is formed on the thin film transistor substrate. FIG.
4 is an exemplary view showing a display region of a lower substrate according to an embodiment of the present invention;
5 is a plan view showing a first embodiment of a pixel in which first and second alignment confirmation keys are not provided;
6 is a cross-sectional view of I-I 'and II-II' of FIG. 5;
7 is a plan view showing a first embodiment of a pixel provided with a first alignment confirmation key;
8 is a sectional view of III-III 'and IV-IV' of FIG. 7;
9 is a plan view showing a first embodiment of a pixel provided with a second alignment confirmation key;
10 is a sectional view of V-V 'and VI-VI' of FIG. 9;
11 is an exemplary view showing a display region of a lower substrate according to another embodiment of the present invention.
12A and 12B are plan views showing the thin film transistor substrate and the color filter substrate in detail when the color filter is formed on the color filter substrate.
13 is a plan view showing a second embodiment of a pixel in which first and second alignment confirmation keys are not provided;
14 is a sectional view of VII-VII 'and VIII-VIII' of FIG. 13;
15 is a plan view showing a second embodiment of a pixel provided with a first alignment confirmation key;
16 is a sectional view of IX-IX 'and X-X' of Fig. 15;
17 is a plan view showing a second embodiment of a pixel provided with a second alignment confirmation key;
18 is a cross-sectional view of i-i 'and ii-ii' in Fig. 17;
19A and 19B are another plan views showing the thin film transistor substrate and the black column spacer substrate in detail when the color filter is formed on the thin film transistor substrate.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

Where the terms "comprises," "having," "consisting of," and the like are used in this specification, other portions may be added as long as "only" is not used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if the temporal relationship is described by 'after', 'after', 'after', 'before', etc., May not be continuous unless they are not used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

The terms "X-axis direction "," Y-axis direction ", and "Z-axis direction" should not be construed solely by the geometric relationship in which the relationship between them is vertical, It may mean having directionality.

It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the second item and the second item among the first item, May refer to any combination of items that may be presented from more than one.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other, partially or wholly, technically various interlocking and driving, and that the embodiments may be practiced independently of each other, It is possible.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a plan view showing a display device according to an embodiment of the present invention. Although the display device according to the exemplary embodiment of the present invention is a liquid crystal display (LCD), the organic light emitting display device, the field emission display device, or the electrophoretic display device Device (Electrophoresis display).

2, a display device according to an exemplary embodiment of the present invention includes a display panel 10, a gate driver 20, a source driver IC (integrated circuit) 30, a flexible film 40, a circuit board 50, and a timing controller 60.

The display panel 10 includes a lower substrate 11, an upper substrate 12, and a liquid crystal layer interposed between the lower substrate 11 and the upper substrate 12. The lower substrate 11 may be a thin film transistor array substrate provided with thin film transistors. The upper substrate 12 may be a color filter array substrate provided with a black matrix and color filters. Alternatively, the color filters may be formed on the lower substrate 11 in a COT (colorfilter on tft array) method. In FIGS. 3A and 3B, FIGS. 5 to 11, 19A and 19B, color filters are formed on the lower substrate 11 by the COT method. 12A and 12B, 13 to 18, 20A and 20B, the upper substrate 12 is a color filter array substrate.

In the display area DA of the display panel 10, pixels arranged in the intersecting regions of the gate lines, the data lines, the gate lines and the data lines are formed. The display area DA can display an image due to the pixels.

Each of the pixels of the display area DA may include a thin film transistor, a pixel electrode, and a storage capacitor. The thin film transistor supplies the data voltage of the data line to the pixel electrode in response to the gate signal of the gate line. Thus, each of the pixels drives the liquid crystal layer of the liquid crystal layer by the electric field generated by the potential difference between the data voltage supplied to the pixel electrode and the common voltage supplied to the common electrode, thereby adjusting the amount of light transmitted from the backlight unit . The common electrode receives a common voltage from the common line. The storage capacitor is provided between the pixel electrode and the common electrode to maintain a constant voltage difference between the pixel electrode and the common electrode. A detailed description of the pixels will be given later by referring to Figs. 5 to 11 and Fig. 13 to Fig.

The gate driver 20 supplies gate signals to the gate lines according to a gate control signal input from the timing controller 60. 2, the gate driver 20 is formed on the outside of one side of the display area DA of the display panel 10 in a gate driver in panel (GIP) manner, but the present invention is not limited thereto. That is, the gate driver 20 may be formed on the outside of both sides of the display area DA of the display panel 10 by a GIP method, or may be formed of a driving chip, mounted on a flexible film, As shown in Fig.

The source drive IC 30 receives the digital video data and the source control signal from the timing control unit 60. The source driver IC 30 converts the digital video data into analog data voltages according to the source control signal and supplies the analog data voltages to the data lines. When the source drive IC 30 is fabricated from a drive chip, it can be mounted on the flexible film 40 in a COF (chip on film) or COP (chip on plastic) manner.

The size of the lower substrate 11 is larger than that of the upper substrate 12, thereby exposing a part of the upper surface of the lower substrate 11. Pads, such as data pads, are provided on a part of the exposed upper surface of the lower substrate 11. Wires connecting the pads to the source drive IC 30 and wirings connecting the pads and the wirings of the circuit board 50 may be formed in the flexible film 40. The flexible film 40 is attached on the pads using an anisotropic conducting film, whereby the pads and the wirings of the flexible film 40 can be connected.

The circuit board 50 may be attached to the flexible films 40. [ The circuit board 50 may be implemented with a plurality of circuits implemented with driving chips. For example, the timing control section 60 may be mounted on the circuit board 50. The circuit board 50 may be a printed circuit board or a flexible printed circuit board.

The timing control unit 60 receives digital video data and a timing signal from an external system board (not shown). The timing control unit 60 generates a gate control signal for controlling the operation timing of the gate driving unit 20 and a source control signal for controlling the source drive ICs 30 based on the timing signal. The timing controller 60 supplies a gate control signal to the gate driver and a source control signal to the source driver ICs 30.

When the display device is implemented as a liquid crystal display device, the display device further includes a backlight unit. The backlight unit may be disposed under the display panel 10 to illuminate the display panel 10 with light. The backlight unit may be implemented as a direct type or an edge type.

3A and 3B are plan views showing the thin film transistor substrate and the black column spacer substrate in detail when the color filter is formed on the lower substrate.

3A and 3B illustrate that the lower substrate is a thin film transistor substrate in which color filters are formed and the upper substrate is a black column spacer substrate. 3A and 3B show only the display area DA, the non-display area NDA, the first alignment confirmation keys ACK1, and the second alignment confirmation keys ACK2 for convenience of explanation.

Referring to FIGS. 3A and 3B, the lower substrate 11 includes a display area DA and a non-display area NDA. The display area DA is an area where pixels are formed to display an image, and the non-display area NDA is an area that does not display an image in the peripheral area of the display area DA.

First alignment confirmation keys (ACK1) are formed in the display area (DA) of the lower substrate (11). The first sorting confirmation keys ACK1 are keys for judging whether or not the color filter is properly aligned. The first sort acknowledgment keys (ACK1) are referred to in the art as overlay keys.

Specifically, the position of the color filter key CFK formed on the first alignment confirmation key ACK1 is checked to determine whether the color filter is properly aligned. The first alignment confirmation key ACK1 includes an exposure hole EH formed by a common line or a gate line and a color filter key CFK formed in the exposure hole EH as shown in Figs. The exposure hole EH may be surrounded by a common line or a gate line as shown in Fig. The color filter key (CKF) is formed of the same material as the color filter.

The alignment of the color filters can be determined depending on where the color filter key CFK is formed in the exposure hole EH. For example, the color filter key CFK may be designed to be formed at the center of the exposure hole EH, and the color filter key CFK may be formed from the center of the exposure hole EH using an optical microscope- It is possible to judge whether or not the color filter is properly aligned.

In addition, second alignment confirmation keys ACK2 are formed in the display area DA of the upper substrate 12. The second alignment confirmation keys ACK2 are keys for determining whether the black column spacers are properly aligned. The second sort acknowledgment keys ACK2 are referred to in the industry as TP keys.

Specifically, the distance between the second alignment confirmation keys ACK2 is measured to determine whether the black column spacers are properly aligned. The second alignment confirmation key (ACK2) is formed for the purpose of determining whether the black column spacers are properly aligned and formed of the same material as the black column spacer. In Figs. 4 and 11, the second alignment confirmation key ACK2 is formed in the "+" shape, but the present invention is not limited thereto.

On the other hand, as described in the background of the invention, it is important to check the alignment error of the color filter in the large screen display device. The embodiment of the present invention forms the first alignment confirmation key ACK1 including the color filter key CFK in the display area DA of the lower substrate 11. [ As a result, the embodiment of the present invention can confirm whether the color filters are properly formed in the display area DA by using the first alignment confirmation key ACK1 in the large-screen display device.

4 is an exemplary view showing a display region of a lower substrate according to an embodiment of the present invention. 4, gate lines GLn and GLn + 1, data lines DLm to DLm + 2, and common lines CLn and CLn + 1 are provided in a display area DA according to an embodiment of the present invention. And the pixels P each including the thin film transistor T and the pixel electrode PE are formed.

Each of the pixels P includes an opening region OA and a non-opening region NOA. A pixel electrode PE is formed in the opening region OA and a thin film transistor T is formed in the non-opening region NOA.

The gate lines GLn and GLn + 1 and the data lines DLm to DLm + 2 are formed to intersect with each other. The gate lines GLn and GLn + 1 and the common lines CLn and CLn + 1 are formed in parallel with each other. That is, the gate lines GLn and GLn + 1 and the common lines CLn and CLn + 1 are formed in the horizontal direction (x axis direction) and the data lines DLm to DLm + 2 are formed in the vertical direction y Axis direction).

The thin film transistor T includes a gate electrode which is a part of the gate line, a semiconductor layer, a source electrode extending from the data line, and a drain electrode connected to the pixel electrode PE. The thin film transistor T is turned on when a gate signal is supplied to the gate line. In this case, the data voltage of the data line may be supplied to the pixel electrode PE via the source electrode, the semiconductor layer, and the drain electrode.

Each of the pixel electrodes PE is connected to the drain electrode of the thin film transistor T connected to the gate line GLn disposed below the pixel electrode. Therefore, the pixel electrode PE, the nth common line CLn, the nth gate line GLn, the pixel electrode PE, the (n + 1) th common line CLn + 1, And the (n + 1) th gate line GLn + 1 are arranged in this order.

It is preferable that the first and second alignment confirmation keys ACK1 and ACK2 are formed in the non-aperture area NOA in order to minimize the loss of the aperture area OA of the display area DA. 4, the first alignment confirmation key ACK1 may be formed in a region where the gate line GLn and the common line CLn are disposed in the non-opening region NOA, and the second alignment confirmation key ACK1 ACK2 may be formed in a region where the gate line GLn + 1 is disposed.

In this case, the first alignment confirmation key ACK1 may include an exposure hole EH surrounded by the common line CLn and a color filter key CFK formed in the exposure hole EH as shown in FIG. A second alignment confirmation key ACK2 may be formed on the gate line as shown in FIG.

Since the common line CLn and the gate line GLn are opaque and occupy most of the non-aperture area NOA, the exposure hole EH of the first alignment confirmation key ACK1 is the common line CLn or It is preferable to expose the gate line GLn by patterning. Therefore, the exposure hole EH of the first alignment confirmation key ACK1 is surrounded by the common line CLn or the gate line GLn.

As described above, the first and second alignment confirmation keys ACK1 and ACK2 are formed in the non-aperture area NOA of the pixel P to minimize the loss of the aperture area OA of the display area DA . Hereinafter, a pixel in which the first and second alignment confirmation keys (ACK1 and ACK2) are not formed, the pixel in which the first alignment confirmation key (ACK1) is formed according to the first embodiment of the present invention, The pixel on which the second alignment confirmation key ACK2 is formed will be described in detail.

5 is a plan view showing a first embodiment of a pixel in which first and second alignment confirmation keys are not provided. 6 is a cross-sectional view taken along line I-I 'and II-II' in FIG.

5 and 6, the pixel in which the first and second alignment confirmation keys are not provided will be described in detail.

5 and 6 illustrate that the pixel P is implemented as a horizontal electric field system in an in-plane switching (IPS) mode. However, the present invention is not limited to this, and a horizontal electric field in an FFS (frndge field switching) Or a vertical electric field system such as a twisted nematic (TN) mode or a vertical alignment (VA) mode. In the case of the vertical electric field type, the common electrode CE may be formed on the upper substrate 12.

First, referring to FIG. 5, a pixel P according to the first embodiment of the present invention includes an opening area OA and a non-opening area NOA. The pixel electrode PE and the common electrode CE are formed in the opening region OA. A thin film transistor T, a storage capacitor Cst, a gate line GL, a common line CL, and a black column spacer BCS are formed in the non-aperture region NOA.

One color filter is formed in the aperture area OA and a plurality of color filters are formed in the non-aperture area OA. One color filter may be any one of a red color filter, a green color filter, and a blue color filter. Although embodiments of the present invention include red, green, and blue color filters, the present invention is not limited thereto. A plurality of color filters are formed so as to cover the non-aperture area (OA). The red color filter RC and the blue color filter BC can act like a black matrix because the external light can be blocked most of the time when the red color filter RC and the blue color filter BC are laminated. On the other hand, it is preferable that a plurality of color filters include a red color filter (RC) and a blue color filter (BC) as shown in FIG. 6, but it is not limited thereto.

The gate line GL and the data line DL are formed so as to intersect with each other. The common line CL may be formed in parallel with the gate line GL between the gate line GL and the opening region OA.

The thin film transistor T may be formed adjacent to the intersection of the gate line GL and the data line DL. The thin film transistor T includes a gate electrode GE which is a part of the gate line GL, a semiconductor layer SM, a source electrode SE extending from the data line DL and a drain electrode DE. And the drain electrode DE is connected to the pixel electrode PE through the first contact hole CNT1. Therefore, when a gate signal is applied to the gate line GL, the data voltage of the data line DL can be supplied to the pixel electrode PE.

The drain electrode DE may be formed on the common line CL so that the common line CL overlapping the drain electrode DE and the drain electrode DE serves as the storage capacitor Cst.

The common line CL is connected to the common electrode CE through the second contact hole CNT2. The pixel electrode PE and the common electrode CE may be formed in a slit shape in the opening region OA. A slit slc of the common electrode CE may be formed between the slits slp of the pixel electrode PE. The pixel electrode PE and the common electrode CE may be formed of the same metal material on the same plane. A horizontal electric field may be formed between the slits slp of the pixel electrode PE and the slits slc of the common electrode CE.

The slit slp of the pixel electrode PE formed adjacent to the data line DL may be affected by the voltage change of the data line DL. The electric field barrier layer EB extending from the common line CL is formed between the data line DL and the pixel electrode PE in order to reduce the influence of the slit slp of the pixel electrode PE by the voltage change of the data line DL. May be formed between the slits (slp) of the substrate (PE).

A black column spacer (BCS) may be formed in the non-aperture region NOA to maintain the cell gap of the liquid crystal layer LC. In FIG. 5, a black column spacer (BCS) is formed on the gate line GL of the non-opening region NOA. However, the present invention is not limited thereto. The black column spacer BCS serves not only to serve as a column spacer (BCS) but also to cover the first alignment confirmation key ACK1, so that the black column spacer BCS is preferably formed of a material capable of blocking light. A detailed description thereof will be given later with reference to FIGS. 7 and 8. FIG.

Hereinafter, the cross section of the non-aperture region OA of the pixel P will be described in detail with reference to FIG.

On the lower substrate 11, a gate metal layer including a gate line GL, a gate electrode GE, and a common line CL is formed. The gate metal layer may be formed of any one of molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), and chromium (Cr) or an alloy thereof.

A gate insulating film (GI) is formed on the gate metal layer. A gate insulating film (GI) may be formed of a composite film of a silicon oxide (SiO ₂₎ or silicon nitride (SiNx) is formed as a single film or a silicon oxide (SiO ₂₎ and silicon nitride (SiNx) of.

A semiconductor layer SM is formed on the gate insulating film GI. The semiconductor layer SM is formed so as to overlap with the gate electrode GI. A source / drain metal layer including a source electrode SE connected to one side of the semiconductor layer SM and a drain electrode DE connected to the other side is formed on the semiconductor layer SM. The source / drain metal layer may be formed of molybdenum (Mo) and molybdenum alloy.

A protective film PAS is formed on the semiconductor layer SM, the source electrode SE, and the drain electrode DE. When a color filter is formed on the lower substrate 11, a color filter may be formed on the protective film PAS. One color filter is formed in the opening area OA, whereas a plurality of color filters are formed in the non-opening area NOA. For example, as shown in Fig. 6, a red color filter RC may be formed on the protective film PAS and a blue color filter BC may be formed on the red color filter RC in the non-aperture region NOA . A photo acryl (PAC) may be formed on the plurality of color filters (RC, BC).

A pixel electrode PE and a common electrode CE may be formed on the photoacetal (PAC). A first contact hole CNT1 may be formed to expose the drain electrode DE through the passivation film PAS, the plurality of color filters RC and BC and the photoacryl PAC. The pixel electrode PE may be connected to the drain electrode DE through the first contact hole CNT1. A second contact hole CNT2 may be formed to expose the common line CL through the gate insulating film GI, the protective film PAS, the plurality of color filters RC and BC and the photoacryl PAC have. The common electrode CE may be connected to the common line CL through the second contact hole CNT2.

A polyimide film (PI), which is an alignment film, is formed on the photoacid (PAC), the pixel electrode (PE), and the common electrode (CE).

On the upper substrate 12, a black column spacer (BCS) is formed. A black column spacer (BCS) may be formed in the non-opening region NOA. A polyimide film (PI), which is an alignment film, is formed on the upper substrate 12 and the black column spacer (BCS). A liquid crystal layer LC is interposed between the polyimide film PI of the lower substrate 11 and the polyimide film PI of the upper substrate 12. [

7 is a plan view showing a first embodiment of a pixel provided with a first alignment confirmation key. 8 is a cross-sectional view of III-III 'and IV-IV' of FIG.

7 and 8, the pixel P provided with the first alignment confirmation key ACK1 will be described in detail.

7 and 8 illustrate that the pixel P is implemented as a horizontal electric field system in an in-plane switching (IPS) mode for the sake of convenience of explanation. However, the present invention is not limited to this, Or a vertical electric field system such as a twisted nematic (TN) mode or a vertical alignment (VA) mode. In the case of the vertical electric field type, the common electrode CE may be formed on the upper substrate 12.

First, referring to FIG. 7, a pixel P according to the first embodiment of the present invention includes an opening region OA and a non-opening region NOA. The pixel electrode PE and the common electrode CE are formed in the opening region OA. The thin film transistor T, the storage capacitor Cst, the gate line GL, the common line CL, the black column spacer BCS and the first alignment confirmation key ACK1 are formed in the non-aperture region NOA .

The thin film transistor T, the storage capacitor Cst, the pixel electrode PE, the common electrode CE and the electric field barrier layer EB are substantially the same as those described with reference to FIG. 5, It is omitted.

One color filter is formed in the aperture area OA and a plurality of color filters are formed in the non-aperture area OA. One color filter may be any one of a red color filter, a green color filter, and a blue color filter. A plurality of color filters are formed so as to cover the non-aperture area (OA). A plurality of color filters may include a red color filter (RC) and a blue color filter (BC) as shown in FIG. 8, since the majority of the external light can be blocked when the red color filter RC and the blue color filter BC are laminated But is not limited thereto.

The gate line GL and the data line DL are formed so as to intersect with each other. The common line CL may be formed in parallel with the gate line GL between the gate line GL and the opening region OA.

The first alignment confirmation key ACK1 is formed in the non-aperture area NOA. The first alignment confirmation key ACK1 includes an exposure hole EH surrounded by an opaque material such as a plurality of color filters RC and BC and a common line CL and a color formed in the exposure hole EH, Filter key CFK. In FIGS. 7 and 8, the exposure hole EH is a hole surrounded by the plurality of color filters RC and BC and the common line CL, but is not limited thereto. That is, the exposure hole EH may be a hole surrounded by the plurality of color filters RC and BC and the gate line GL.

In order to check the alignment error of the color filter using the first alignment confirmation key ACK1, the first alignment confirmation key ACK1 is formed to have a size of 130 mu m x 130 mu m or more and smaller than the non-aperture area NOA Size. This is because it is difficult to confirm whether the color filter is properly aligned when the first alignment confirmation key ACK1 is smaller than 130 mu m x 130 mu m and when the size is larger than the non-aperture area NOA, a loss occurs in the aperture area OA .

The exposure hole EH can transmit light so that the black column spacer BCS can be formed on the first alignment confirmation key ACK1 to cover the exposure hole EH of the first alignment confirmation key ACK1 have. Since the black column spacer BCS has to cover the first alignment confirmation key ACK1, it is preferable that the black column spacer BCS is formed to have a larger area than the first alignment confirmation key ACK1.

Hereinafter, the cross section of the non-aperture region OA of the pixel P will be described in detail with reference to FIG. 8 is substantially the same as the sectional view taken along line I-I 'of FIG. 6, so that a detailed description thereof will be omitted and a sectional view of FIG.

On the lower substrate 11, a gate metal layer including a gate line GL, a gate electrode GE, and a common line CL is formed. The gate metal layer may be formed of any one of molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), and chromium (Cr) or an alloy thereof.

A gate insulating film (GI) is formed on the gate metal layer. A gate insulating film (GI) may be formed of a composite film of a silicon oxide (SiO ₂₎ or silicon nitride (SiNx) is formed as a single film or a silicon oxide (SiO ₂₎ and silicon nitride (SiNx) of.

A protective film PAS is formed on the gate insulating film GI. When a color filter is formed on the lower substrate 11, a color filter may be formed on the protective film PAS. One color filter is formed in the opening area OA, whereas a plurality of color filters are formed in the non-opening area NOA. For example, as shown in Fig. 8, a red color filter RC may be formed on the protective film PAS and a blue color filter BC may be formed on the red color filter RC in the non-aperture region NOA .

The color filter key CFK is formed on the protective film PAS of the exposure hole EH in which the common line CL and the plurality of color filters are not formed in the non-aperture area NOA. The exposure hole EH is surrounded by a common line CL and a plurality of color filters. The exposure hole EH may be designed to be surrounded by the gate line GL and the plurality of color filters.

The color filter key CFK is formed in the same color as the color filter formed in the opening area OA. It is possible to determine the misalignment of each of the red color filter, the green color filter and the blue color filter by forming the color filter key CFK in the same color as the color filter formed in the aperture area OA.

A photo acryl (PAC) may be formed on the plurality of color filters (RC, BC) and the color filter key (CFK). A pixel electrode PE and a common electrode CE may be formed on the photoacetal (PAC). A polyimide film (PI), which is an alignment film, is formed on the photoacid generator (PAC).

On the upper substrate 12, a black column spacer (BCS) is formed. The exposure hole EH can transmit light so that the black column spacer BCS can be formed on the first alignment confirmation key ACK1 to cover the exposure hole EH of the first alignment confirmation key ACK1 have. Since the black column spacer BCS has to cover the first alignment confirmation key ACK1, it is preferable that the black column spacer BCS is formed to have a larger area than the first alignment confirmation key ACK1.

A polyimide film (PI), which is an alignment film, is formed on the upper substrate 12 and the black column spacer (BCS). A liquid crystal layer LC is interposed between the polyimide film PI of the lower substrate 11 and the polyimide film PI of the upper substrate 12. [

As described above, the first embodiment of the present invention forms the first alignment confirmation key (ACK1) in the non-aperture region NOA of the pixel P. As a result, in the first embodiment of the present invention, since there is no loss of the aperture area OA due to the first alignment confirmation key ACK1, even when the first alignment confirmation key ACK1 is formed in the display area DA, (OA) loss.

9 is a plan view showing a first embodiment of a pixel provided with a second alignment confirmation key. 10 is a cross-sectional view of V-V 'and VI-VI' of FIG.

9 and 10, the pixel P provided with the second alignment confirmation key ACK2 will be described in detail.

Although FIGS. 9 and 10 illustrate that the pixel P is implemented as a horizontal electric field system in an IPS (in-plane switching) mode for the convenience of description, the present invention is not limited thereto. Or a vertical electric field system such as a twisted nematic (TN) mode or a vertical alignment (VA) mode. In the case of the vertical electric field type, the common electrode CE may be formed on the upper substrate 12.

First, referring to FIG. 9, a pixel P according to the first embodiment of the present invention includes an opening area OA and a non-opening area NOA. The pixel electrode PE and the common electrode CE are formed in the opening region OA. The non-aperture region NOA is formed with a thin film transistor T, a storage capacitor Cst, a gate line GL, a common line CL, and a second alignment confirmation key ACK2.

5 and 6, the pixel electrode PE, the common electrode CE, the thin film transistor T, the storage capacitor Cst, the gate line GL and the common line CL shown in FIGS. Are substantially the same as those described above, so a detailed description thereof will be omitted.

A second alignment confirmation key ACK2 is formed in place of the black column spacer BCS in the pixel P provided with the second alignment confirmation key ACK2. The second alignment confirmation key ACK2 is formed in the non-aperture area NOA. And the second alignment confirmation key ACK2 is formed in the "+" shape. However, the present invention is not limited thereto.

The second alignment confirmation key ACK2 is formed of the same material as the black column spacer BCS since it is for determining whether the black column spacers BCS are properly aligned. The second alignment confirmation key ACK2 serves to serve as a TP key, so that it need not be formed to have the same thickness as the black column spacer BCS. For example, the thickness of the second alignment confirmation key ACK2 may be made thinner or equal to the thickness of the black column spacer BCS.

As described above, the first embodiment of the present invention forms the second alignment confirmation key ACK2 in the non-aperture area NOA of the pixel P. As a result, in the second embodiment of the present invention, since there is no loss of the aperture area OA due to the second alignment confirmation key ACK2, even though the second alignment confirmation key ACK2 is formed in the display area DA, (OA) loss.

11 is an exemplary view showing a display region of a lower substrate according to another embodiment of the present invention. 11, gate lines GLn to GLn + 3, data lines DLm to DLm + 2, and common lines CLn to CLn (not shown) are formed in a display area DA according to another exemplary embodiment of the present invention. +3), and pixels P each including a thin film transistor T and a pixel electrode PE are formed.

Each of the pixels P includes an aperture region OA and a non-aperture region NOA. The pixel electrode PE is formed in the opening region OA and the gate lines GLn to GLn + 3, the data lines DLm to DLm + 2, and the common lines CLn- CLn + 3, and a thin film transistor T are formed.

The gate lines GLn to GLn + 3 and the data lines DLm to DLm + 2 are formed so as to intersect with each other. The gate lines GLn to GLn + 3 and the common lines CLn to CLn + 3 are formed in parallel with each other. That is, the gate lines GLn to GLn + 3 and the common lines CLn to CLn + 3 are formed in the horizontal direction (x axis direction) and the data lines DLm to DLm + 2 are formed in the vertical direction y Axis direction).

The thin film transistor T includes a gate electrode that is a part of a gate line, a semiconductor layer, a source electrode extending from the data line, and a drain electrode connected to the pixel electrode PE. The thin film transistor T is turned on when a gate signal is supplied to the gate line. In this case, the data voltage of the data line may be supplied to the pixel electrode PE via the source electrode, the semiconductor layer, and the drain electrode.

The n-th gate line Gn is disposed adjacent to the (n + 1) -th gate line Gn + 1 and the n-th and (n + 1) -th gate lines Gn and Gn + 1 adjacent to each other are arranged in opposite directions Are connected to the pixel electrodes PE. Thus, the pixel P including the thin film transistor T connected to the nth gate line Gn and the thin film transistor T connected to the (n + 1) th gate line Gn + 1 P share a non-aperture area (NOA).

Further, the pixel electrode PE of the pixel connected to the odd gate line is connected to the drain electrode of the thin film transistor T connected to the gate line arranged below the pixel electrode PE. The pixel electrode PE of the pixel connected to the outermost gate line is connected to the drain electrode of the thin film transistor T connected to the gate line disposed thereon. For example, when the n-th gate line GLn is the odd gate line, the pixel electrode PE of the pixel connected to the n-th gate line GLn is connected to the n-th gate line GLn disposed thereunder To the drain electrode of the thin film transistor (T). In this case, since the (n + 1) -th gate line GLn + 1 is the outermost gate line, the pixel electrode PE of the pixel connected to the (n + 1) -th gate line GLn + To the drain electrode of the thin film transistor T connected to the gate electrode GLn. Therefore, the pixel electrode PE, the nth common line CLn, the nth gate line GLn, the (n + 1) -th gate line GLn + 1, the (n + 1) (CLn + 1), and the pixel electrode PE may be arranged in this order.

It is preferable that the first and second alignment confirmation keys ACK1 and ACK2 are formed in the non-aperture area NOA in order to minimize the loss of the aperture area OA of the display area DA. For this purpose, the first and second alignment confirmation keys ACK1 and ACK2 may be formed in a region where adjacent gate lines GLn and GLn + 1 are disposed, as shown in FIG.

In this case, the first alignment confirmation key (ACK1) is formed in the exposure hole EH formed by the nth and (n + 1) th gate lines and the color filter key CFK formed in the exposure hole EH . The second alignment confirmation key ACK2 may be formed on the nth and (n + 1) th gate lines GLn and GLn + 1 as shown in FIG.

Meanwhile, in order to confirm the alignment error of the color filters, it is preferable that each of the first and second alignment confirmation keys ACK1 and ACK2 is formed to have a size of 130 mu m x 130 mu m or more. It is difficult to confirm whether the color filter is properly aligned when each of the first and second alignment confirmation keys ACK1 and ACK2 is smaller than 130 mu m x 130 mu m and when the size is larger than the non-aperture area NOA, OA).

When one gate line is arranged between the pixel electrodes PE as shown in FIG. 4, the first and second alignment confirmation keys (ACK1 and ACK2) must be designed within the width of the gate line and the common line. For this purpose, the widths of the gate lines and the common lines may be designed to have a first width W1 as shown in FIG. Accordingly, when one gate line is arranged between the pixel electrodes PE as shown in FIG. 4, the width of the opening region OA can be designed as the second width W2.

In contrast, when a plurality of gate lines are arranged between the pixel electrodes PE as shown in FIG. 11, the first and second alignment confirmation keys ACK1 and ACK2 are formed within the widths of the plurality of gate lines and the plurality of common lines, Should be designed. To this end, the widths of the plurality of gate lines and the plurality of common lines may be designed to have a third width (W3) as shown in FIG. The third width W3 may be greater than or equal to the first width W1 and less than twice the first width W1. 11, when the plurality of gate lines are arranged between the pixel electrodes PE, the width of the opening area OA can be designed as a fourth width W4 that is wider than the second width W2 have.

As a result, when a plurality of gate lines are arranged between the pixel electrodes PE as shown in FIG. 11, the number of the gate electrodes of the pixel electrodes PE is smaller than that of the gate electrodes You can expand the width.

The pixels and the first and second alignment confirmation keys ACK1 and ACK2 shown in FIG. 11 are formed of a hole that is formed such that the exposure hole EH of the first alignment confirmation key ACK1 is exposed by a plurality of gate lines And the second alignment confirmation key ACK2 are formed on the plurality of gate lines, as shown in Figs. 5 to 10. Therefore, detailed description of the pixel and the first and second alignment confirmation keys (ACK1, ACK2) shown in FIG. 11 will be omitted.

12A and 12B are plan views showing the thin film transistor substrate and the color filter substrate in detail when the color filter is formed on the color filter substrate.

12A and 12B illustrate that the lower substrate is a thin film transistor substrate on which thin film transistors are formed and the upper substrate is a color filter substrate on which black column spacers and color filters are formed. 12A and 12B show only the display area DA, the non-display area NDA, the first alignment confirmation keys ACK1, and the second alignment confirmation keys ACK2 for convenience of explanation.

12A and 12B, the lower substrate 11 includes a display area DA and a non-display area NDA. The display area DA is an area where pixels are formed to display an image, and the non-display area NDA is an area that does not display an image in the peripheral area of the display area DA.

The first and second alignment confirmation keys ACK1 and ACK2 are formed on the upper substrate 12 without forming the first and second alignment confirmation keys ACK1 and ACK2 on the lower substrate 11. [ First alignment confirmation keys ACK1 are formed in the display area DA of the upper substrate 12. [ The first sorting confirmation keys ACK1 are keys for judging whether or not the color filter is properly aligned. The first sort acknowledgment keys (ACK1) are referred to in the art as overlay keys.

Specifically, the position of the color filter key CFK formed on the first alignment confirmation key ACK1 is checked to determine whether the color filter is properly aligned. The first alignment confirmation key ACK1 includes an exposure hole EH formed by a black matrix and a color filter key CFK formed in an exposure hole EH as shown in FIG. 12B. The exposure hole EH may be surrounded by a black matrix BM as shown in Fig. The color filter key (CKF) is formed of the same material as the color filter.

The alignment of the color filters can be determined depending on where the color filter key CFK is formed in the exposure hole EH. For example, the color filter key CFK may be designed to be formed at the center of the exposure hole EH, and the color filter key CFK may be formed from the center of the exposure hole EH using an optical microscope- It is possible to judge whether or not the color filter is properly aligned. A detailed description of the first sorting confirmation key (ACK1) will be given later with reference to FIG. 15 and FIG.

In addition, the second alignment confirmation keys ACK2 are keys for determining whether the black column spacers are properly aligned. The second sort acknowledgment keys ACK2 are referred to in the industry as TP keys. Specifically, the distance between the second alignment confirmation keys ACK2 is measured to determine whether the black column spacers are properly aligned. The second alignment confirmation key (ACK2) is formed for the purpose of determining whether the black column spacers are properly aligned and formed of the same material as the black column spacer. A detailed description of the second sorting confirmation key (ACK2) will be given later with reference to FIGS. 17 and 18. FIG.

On the other hand, as described in the background of the invention, it is important to check the alignment error of the color filter in the large screen display device. The embodiment of the present invention forms a first alignment confirmation key ACK1 including the color filter key CFK in the display area DA of the upper substrate 12. [ As a result, the embodiment of the present invention can confirm whether the color filters are properly formed in the display area DA by using the first alignment confirmation key ACK1 in the large-screen display device.

5 to 10, a pixel in which the first and second alignment confirmation keys ACK1 and ACK2 are not formed, a pixel in which the first alignment confirmation key ACK1 is formed, The pixel on which the second alignment confirmation key ACK2 is formed will be described in detail.

13 is a plan view showing a second embodiment of a pixel in which first and second alignment confirmation keys are not provided. 14 is a cross-sectional view of VII-VII 'and VIII-VIII' of FIG.

13 and 14 illustrate that the pixel P is implemented as a horizontal electric field system in an in-plane switching (IPS) mode for the sake of convenience of explanation. However, the present invention is not limited to this and the horizontal electric field FFS (frndge field switching) Or a vertical electric field system such as a twisted nematic (TN) mode or a vertical alignment (VA) mode. In the case of the vertical electric field type, the common electrode CE may be formed on the upper substrate 12.

First, referring to FIG. 13, a pixel P according to the second embodiment of the present invention includes an opening area OA and a non-opening area NOA. The pixel electrode PE and the common electrode CE are formed in the opening region OA. A thin film transistor T, a storage capacitor Cst, a gate line GL, a common line CL, and a black column spacer BCS are formed in the non-aperture region NOA.

A color filter is formed in the opening area OA and a black matrice is formed in the non-opening area OA. The color filter may be any one of a red color filter, a green color filter, and a blue color filter.

The gate line GL and the data line DL are formed so as to intersect with each other. The common line CL may be formed in parallel with the gate line GL between the gate line GL and the opening region OA.

The thin film transistor T, the storage capacitor Cst, the pixel electrode PE, the common electrode CE, the electric field barrier layer EB and the black column spacer BCS are substantially the same as those described with reference to Fig. 5 . Therefore, the detailed description of the thin film transistor T, the storage capacitor Cst, the pixel electrode PE, the common electrode CE, the electric field barrier layer EB, and the black column spacer BCS will be omitted.

Hereinafter, the cross section of the non-aperture region OA of the pixel P will be described in detail with reference to FIG.

On the lower substrate 11, a gate metal layer including a gate line GL, a gate electrode GE, and a common line CL is formed. The gate metal layer may be formed of any one of molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), and chromium (Cr) or an alloy thereof.

A gate insulating film (GI) is formed on the gate metal layer. A gate insulating film (GI) may be formed of a composite film of a silicon oxide (SiO ₂₎ or silicon nitride (SiNx) is formed as a single film or a silicon oxide (SiO ₂₎ and silicon nitride (SiNx) of.

A semiconductor layer SM is formed on the gate insulating film GI. The semiconductor layer SM is formed so as to overlap with the gate electrode GI. A source / drain metal layer including a source electrode SE connected to one side of the semiconductor layer SM and a drain electrode DE connected to the other side is formed on the semiconductor layer SM. The source / drain metal layer may be formed of molybdenum (Mo) and molybdenum alloy.

A protective film PAS is formed on the semiconductor layer SM, the source electrode SE, and the drain electrode DE. A photo acryl (PAC) may be formed on the protective film PAS.

A pixel electrode PE and a common electrode CE may be formed on the photoacetal (PAC). A first contact hole CNT1 may be formed to expose the drain electrode DE through the passivation film PAS and the photoacid PAC. The pixel electrode PE may be connected to the drain electrode DE through the first contact hole CNT1. A second contact hole CNT2 may be formed through the gate insulating film GI, the passivation film PAS and the photoacryl PAC to expose the common line CL. The common electrode CE may be connected to the common line CL through the second contact hole CNT2.

A polyimide film (PI), which is an alignment film, is formed on the photoacid (PAC), the pixel electrode (PE), and the common electrode (CE).

On the upper substrate 12, a black matrix BM is formed. The black matrix BM is formed only in the non-aperture region NOA to cover the non-aperture region NOA of the pixel P. [

Color filters CF are formed on the black matrix BM. The color filters CF are formed differently depending on the color that the pixel P wants to display. For example, a red color filter is formed in a pixel P displaying red, a green color filter is formed in a pixel P displaying green, and a blue color filter is formed in a pixel P displaying blue . The color filters CF may be formed both in the aperture area OA and the non-aperture area NOA of the pixel P or only in the aperture area OA of the pixel P as shown in Fig. 14 .

An overcoat layer (OC) for planarization is formed on the color filters (CF). A black column spacer (BCS) is formed on the overcoat layer OC. A black column spacer (BCS) may be formed in the non-opening region NOA. A polyimide film (PI) as an alignment film is formed on the black column spacer (BCS). A liquid crystal layer LC is interposed between the polyimide film PI of the lower substrate 11 and the polyimide film PI of the upper substrate 12. [

15 is a plan view showing a second embodiment of a pixel provided with a first alignment confirmation key. 16 is a sectional view of IX-IX 'and X-X' of Fig. 15.

15 and 16, the pixel P provided with the first alignment confirmation key ACK1 will be described in detail.

15 and 16 illustrate that the pixel P is implemented as a horizontal electric field system in an in-plane switching (IPS) mode for the sake of convenience of explanation. However, the present invention is not limited to this, and a horizontal electric field FFS (frndge field switching) Or a vertical electric field system such as a twisted nematic (TN) mode or a vertical alignment (VA) mode. In the case of the vertical electric field type, the common electrode CE may be formed on the upper substrate 12.

First, referring to FIG. 15, a pixel P according to the second embodiment of the present invention includes an opening area OA and a non-opening area NOA. The pixel electrode PE and the common electrode CE are formed in the opening region OA. The thin film transistor T, the storage capacitor Cst, the gate line GL, the common line CL, the black column spacer BCS and the first alignment confirmation key ACK1 are formed in the non-aperture region NOA .

A color filter is formed in the opening area OA and a black matrice is formed in the non-opening area OA. The color filter may be any one of a red color filter, a green color filter, and a blue color filter.

The gate line GL and the data line DL are formed so as to intersect with each other. The common line CL may be formed in parallel with the gate line GL between the gate line GL and the opening region OA.

The thin film transistor T, the storage capacitor Cst, the pixel electrode PE, the common electrode CE and the electric field barrier layer EB are substantially the same as those described with reference to Fig. Therefore, the detailed description of the thin film transistor T, the storage capacitor Cst, the pixel electrode PE, the common electrode CE, and the electric field barrier layer EB will be omitted.

The first alignment confirmation key ACK1 is formed in the non-aperture area NOA. The first alignment confirmation key ACK1 includes an exposure hole EH surrounded by the black matrix and exposed transparently and a color filter key CFK formed in the exposure hole EH. In order to check the alignment error of the color filter using the first alignment confirmation key ACK1, the first alignment confirmation key ACK1 is formed to have a size of 130 mu m x 130 mu m or more and smaller than the non-aperture area NOA Size. This is because it is difficult to confirm whether the color filter is properly aligned when the first alignment confirmation key ACK1 is smaller than 130 mu m x 130 mu m and when the size is larger than the non-aperture area NOA, a loss occurs in the aperture area OA .

The color filter key CFK is formed in the same color as the color filter formed in the opening area OA. It is possible to determine the misalignment of each of the red color filter, the green color filter and the blue color filter by forming the color filter key CFK in the same color as the color filter formed in the aperture area OA.

The exposure hole EH can transmit light so that the black column spacer BCS can be formed on the first alignment confirmation key ACK1 to cover the exposure hole EH of the first alignment confirmation key ACK1 have. Since the black column spacer BCS has to cover the first alignment confirmation key ACK1, it is preferable that the black column spacer BCS is formed to have a larger area than the first alignment confirmation key ACK1.

Hereinafter, the cross section of the non-aperture region OA of the pixel P will be described in detail with reference to FIG. Sectional view taken along line IX-IX 'of FIG. 16 is substantially the same as the sectional view taken along the line VII-VII' of FIG. 14, so that a detailed description thereof will be omitted and a sectional view taken along the line X-X 'will be mainly described.

On the lower substrate 11, a gate metal layer including a gate line GL, a gate electrode GE, and a common line CL is formed. The gate metal layer may be formed of any one of molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), and chromium (Cr) or an alloy thereof.

A gate insulating film (GI) is formed on the gate metal layer. A gate insulating film (GI) may be formed of a composite film of a silicon oxide (SiO ₂₎ or silicon nitride (SiNx) is formed as a single film or a silicon oxide (SiO ₂₎ and silicon nitride (SiNx) of.

A protective film PAS is formed on the gate insulating film GI. A photo acryl (PAC) may be formed on the protective film PAS. A pixel electrode PE and a common electrode CE may be formed on the photoacetal (PAC). A polyimide film (PI), which is an alignment film, is formed on the photoacid generator (PAC).

On the upper substrate 12, a black matrix BM is formed. The black matrix BM is formed only in the non-aperture region NOA to cover the non-aperture region NOA of the pixel P. [ The exposure hole EH in which the black matrix BM is not formed is formed in the non-aperture area NOA. The exposure hole EH is surrounded by a black matrix BM. A color filter key CFK is formed on the upper substrate 12 of the exposure hole EH.

Color filters CF are formed on the black matrix BM. The color filters CF are not formed in the exposure hole EH. The color filters CF are formed differently depending on the color that the pixel P wants to display. For example, a red color filter is formed in a pixel P displaying red, a green color filter is formed in a pixel P displaying green, and a blue color filter is formed in a pixel P displaying blue . The color filters CF may be formed both in the aperture area OA and the non-aperture area NOA of the pixel P or only in the aperture area OA of the pixel P as shown in Fig. 16 .

An overcoat layer (OC) for planarization is formed on the color filters (CF) and the exposure hole (EH). A black column spacer (BCS) is formed on the overcoat layer OC. The exposure hole EH can transmit light so that the black column spacer BCS can be formed on the first alignment confirmation key ACK1 to cover the exposure hole EH of the first alignment confirmation key ACK1 have. Since the black column spacer BCS has to cover the first alignment confirmation key ACK1, it is preferable that the black column spacer BCS is formed to have a larger area than the first alignment confirmation key ACK1.

A polyimide film (PI) as an alignment film is formed on the black column spacer (BCS). A liquid crystal layer LC is interposed between the polyimide film PI of the lower substrate 11 and the polyimide film PI of the upper substrate 12. [

As described above, the second embodiment of the present invention forms the first alignment confirmation key (ACK1) in the non-aperture area NOA of the pixel P. As a result, in the second embodiment of the present invention, since there is no loss of the aperture area OA due to the first alignment confirmation key ACK1, even when the first alignment confirmation key ACK1 is formed in the display area DA, (OA) loss.

17 is a plan view showing a second embodiment of a pixel provided with a second alignment confirmation key. 18 is a cross-sectional view of i-i 'and ii-ii' in Fig.

17 and 18, the pixel P provided with the second alignment confirmation key ACK2 will be described in detail.

17 and 18 illustrate that the pixel P is implemented as a horizontal electric field system in an in-plane switching (IPS) mode for the sake of convenience of explanation. However, the present invention is not limited thereto, and the horizontal electric field FFS (frndge field switching) Or a vertical electric field system such as a twisted nematic (TN) mode or a vertical alignment (VA) mode. In the case of the vertical electric field type, the common electrode CE may be formed on the upper substrate 12.

First, referring to FIG. 17, a pixel P according to the second embodiment of the present invention includes an opening area OA and a non-opening area NOA. The pixel electrode PE and the common electrode CE are formed in the opening region OA. The non-aperture region NOA is formed with a thin film transistor T, a storage capacitor Cst, a gate line GL, a common line CL, and a second alignment confirmation key ACK2.

The pixel electrode PE, the common electrode CE, the thin film transistor T, the storage capacitor Cst, the gate line GL and the common line CL shown in Figs. 17 and 18 are shown in Figs. 13 and 14 Are substantially the same as those described above, so a detailed description thereof will be omitted.

A second alignment confirmation key ACK2 is formed in place of the black column spacer BCS in the pixel P provided with the second alignment confirmation key ACK2. The second alignment confirmation key ACK2 is formed in the non-aperture area NOA. And the second alignment confirmation key ACK2 is formed in the "+" shape. However, the present invention is not limited thereto.

The second alignment confirmation key ACK2 is formed of the same material as the black column spacer BCS since it is for determining whether the black column spacers BCS are properly aligned. The second alignment confirmation key ACK2 serves to serve as a TP key, so that it need not be formed to have the same thickness as the black column spacer BCS. For example, the thickness of the second alignment confirmation key (ACK2) may be formed to be thinner or equal to the thickness of the black column spacer (BCS).

As described above, the second embodiment of the present invention forms the second alignment confirmation key (ACK2) in the non-aperture region NOA of the pixel P. [ As a result, in the second embodiment of the present invention, since there is no loss of the aperture area OA due to the second alignment confirmation key ACK2, even though the second alignment confirmation key ACK2 is formed in the display area DA, (OA) loss.

19A and 19B are another plan views showing the thin film transistor substrate and the black column spacer substrate in detail when the color filter is formed on the thin film transistor substrate.

19A and 19B illustrate that the lower substrate is a thin film transistor substrate on which color filters are formed and the upper substrate is a black column spacer substrate. 19A and 19B show only the display area DA, the non-display area NDA, the first alignment confirmation keys ACK1, and the second alignment confirmation keys ACK2 for convenience of explanation.

19A and 19B, the lower substrate 11 includes a display area DA and a non-display area NDA. The display area DA is an area where pixels are formed to display an image, and the non-display area NDA is an area that does not display an image in the peripheral area of the display area DA.

The first alignment confirmation keys ACK1 formed in the display area DA of the lower substrate 11 are substantially the same as those described with reference to FIG. The second alignment confirmation keys ACK2 formed in the display area DA of the upper substrate 12 are substantially the same as those described with reference to FIG. 3B.

3A, when the first alignment confirmation keys ACK1 are formed in only a part of the pixels of the display area DA of the lower substrate 11, There is a difference between the height between the lower substrate 12 and the polyimide film PI and the height between the lower substrate 12 and the polyimide film PI in the region where the exposure hole EH is not formed. In this case, when the rubbing process is performed for orientation after the polyimide film PI is formed, the frictional force felt by the rubbing cloth is different between the region where the exposure hole EH is formed and the region where the exposure hole EH is not formed do. As a result, a difference in orientation occurs between the region where the exposure hole EH is formed and the region where the exposure hole EH is not formed, and as a result, a predetermined line may be visually recognized along the rubbing direction.

In order to solve the above problem, the embodiment of the present invention forms first alignment confirmation keys (ACK1) in the non-display area (NDA) of the lower substrate (11). In particular, the first alignment confirmation keys ACK1 may be formed for each gate line and / or common line in the non-display area NDA. The first alignment confirmation keys ACK1 formed in the non-display area NDA are intended to prevent certain lines that are viewed along the rubbing direction, rather than to determine alignment errors of the color filters.

When the rubbing direction proceeds in the x-axis direction, the first alignment confirmation keys ACK1 may be formed in the non-display area NDA on the left and right outside of the display area DA in the x-axis direction as shown in Fig. 19A have. Further, when the rubbing direction proceeds in the y-axis direction, the first alignment confirmation keys ACK1 may be formed in the non-display area NDA on the left and right outside of the display area DA in the y-axis direction.

In this way, when the first alignment confirmation keys ACK1 are formed in the non-display area NDA, in the display area DA between the area where the exposure hole EH is formed and the area where the exposure hole EH is not formed The difference in friction force felt by the rubbing can be reduced. Therefore, in the embodiment of the present invention, it is possible to reduce the occurrence of orientation difference in the region where the exposure hole EH is formed in the display region DA and the region where the exposure hole EH is not formed, and as a result, It is possible to prevent a problem that a predetermined line is visible.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Lower substrate
12: upper substrate 20: gate driver
30: Source drive IC 40: Flexible film
50: circuit board 60: timing controller
DA: display area NDA: non-display area
ACK1: first sorting confirmation key ACK2: second sorting confirmation key
EH: Exposure hole CFK: Color filter key
T: transistor GE: gate electrode
SE: source electrode DE: drain electrode
PE: pixel electrode CNT1: first contact hole
CNT2: second contact hole GL: gate line
DL: Data line CL: Common line
BCS: Black column spacer Cst: Storage capacitor

Claims (15)

A display region including pixels including gate lines, data lines, and transistors connected to the gate lines and data lines and pixel electrodes connected to the transistors, and a non-display region A lower substrate provided with a lower electrode;
An upper substrate disposed on the lower substrate; And
And a liquid crystal layer interposed between the lower substrate and the upper substrate,
And a first alignment confirmation key is provided in a display region of the lower substrate. The method according to claim 1,
Each of the pixels includes an aperture region in which the pixel electrode is provided and a non-aperture region in which the transistor is provided,
Wherein the first alignment confirmation key is provided in the non-aperture area of one of the pixels. 3. The method of claim 2,
Wherein the lower substrate is provided with one color filter in the opening region and the plurality of color filters are provided in the non-opening region. The method of claim 3,
Wherein the plurality of color filters include a red color filter and a blue color filter. The method of claim 3,
Wherein the first sorting confirmation key comprises:
An exposure hole surrounded by the plurality of color filters; And
And a color filter key provided in the exposure hole. 6. The method of claim 5,
Wherein the lower substrate is provided with a common line arranged in parallel with the gate lines,
Wherein the exposure hole is surrounded by the common line or the gate line. 3. The method of claim 2,
Wherein the upper substrate is provided with a color filter in an opening region, and a black matrix is provided in the non-opening region. 8. The method of claim 7,
Wherein the first sorting confirmation key comprises:
An exposure hole surrounded by the black matrix; And
And a color filter key provided in the exposure hole. 9. The method according to claim 5 or 8,
Wherein the color filter key is the same index as a color filter provided in the opening area. 8. The method according to claim 3 or 7,
And a black column spacer provided on the upper substrate to cover the first alignment confirmation key. 11. The method of claim 10,
And a second alignment confirmation key is provided in the non-aperture area of another pixel among the pixels. 12. The method of claim 11,
And the second alignment confirmation key is the same material as the black column spacer. 13. The method of claim 12,
And the thickness of the second alignment confirmation key is thinner than or equal to the thickness of the black column spacer. 3. The method of claim 2,
A plurality of gate lines and a plurality of common lines are provided between adjacent pixel electrodes,
Wherein the first alignment confirmation key is formed in an area where the plurality of gate lines are arranged. The method according to claim 1,
Wherein the lower substrate is provided with a plurality of first alignment confirmation keys in a non-display area provided in a periphery of a display area where the pixels are provided.

Images