KR20160133877A - Lamp apparatus and driving circuit for the lamp apparatus - Google Patents

Abstract

The present invention relates to a lighting apparatus capable of being used as a lamp for lighting. The lighting apparatus includes: a converter which supplies output voltage to loads for lighting, and supplies the output voltage to the loads by driving a switching element using a driving signal; and a driving circuit which generates the control voltage of which the level corresponds to variation in load quantity at a time when the load quantity is changed, and supplies the driving signal having an on time controlled to correspond to the control voltage at a time when the load quantity is changed. The present invention stably maintains output voltage supplied to the loads.

Description

FIELD OF THE INVENTION [0001] The present invention relates to a lighting apparatus,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lighting apparatus, and more particularly, to a lighting apparatus that can be used as an illumination lamp such as a rear combination lamp of a vehicle and a driving circuit of the lighting apparatus.

BACKGROUND ART [0002] Generally, a vehicle has a lighting device for various purposes indoors or outdoors. As an example of the lighting device, a rear combination lamp installed at both sides of the vehicle can be exemplified.

The rear combination lamp includes a direction indicator lamp, a braking lamp, a tail lamp, and a back lamp, and is used as a means for informing a driver of another vehicle located behind the vehicle of the running state or running state of the vehicle.

BACKGROUND ART [0002] Lighting apparatuses using a light-emitting diode (LED) are being developed in recent years, and rear combination lamps using LEDs as lighting apparatuses for automobiles are being developed. As the LED is used as a light source, the rear combination lamps are changed into various designs, and the number of LEDs employed in rear combination lamps is gradually increasing with design changes.

The lighting apparatus such as the rear combination lamp needs to be operated stably, the power can be saved, and the lighting apparatus needs to be developed so as to be realized with a small number of parts.

An illumination device using LEDs may be configured to provide an output voltage to a plurality of LED channels. If the number of emitting LED channels changes, a load change in the illuminator may occur, and the output voltage of the illuminator provided in the LED channels may become temporarily unstable at the time the load change occurs.

In response to the change of the output voltage, the illumination device can compensate for the change of the output voltage according to the load change by the compensation of the output voltage using the feedback voltage and the linear regulation using the sensing signal, and stabilize the output voltage.

However, a general lighting device takes much time to compensate and stabilize the output voltage in response to the above-mentioned load change. If stabilization of the output voltage takes a long time, a change in the output voltage may affect the luminance.

Therefore, a lighting apparatus using an LED needs to be improved so that the output voltage can be stabilized even when the load is changed.

In addition, the lighting apparatus uses a converter including a switching element to perform power conversion and provides an output voltage that is generated as a result of power conversion. The converter of the lighting apparatus may be constituted by a buck converter as an example.

Converters consume a lot of power at the switching point for power conversion, which can lead to EMI (Electro Magnetic Interference). The EMI generated by the converter described above may affect the operation of the lighting device and thus must be reduced. Therefore, it is necessary to develop a driving technique of a converter in which EMI can be reduced.

Also, if the duty of the drive signal driving the converter to provide the output voltage is 50% or more, an unstable Sub-Harmonic Oscillation may occur in the converter of the lighting device. The unstable sub harmonic oscillation described above may act as an unstable element of the operation of the lighting apparatus.

The unstable sub harmonic oscillation of the converter can be controlled by the slope (SLOP) compensation of the drive signal driving the converter. The slope compensation of the driving signal means to control the slope of the rising edge and the falling edge of the driving signal, and the slope compensation is implemented by the slope compensation voltage charged with the fixed value of the current.

The buck converter can have a large variable range of the switching frequency, for example, a variable range from 100 KHz to 1 MHz. The switching frequency of the buck converter may be determined by a driving signal provided in a driving circuit. If the variable range of the switching frequency is large, the value of the inductance of the buck converter should also be set to a variable switching frequency. However, if the value of the inductance of the buck converter is varied, the value of the slope compensation voltage for controlling the sub harmonic oscillation must be changed.

In general, the value of the slope compensation voltage is provided based on the fixed current as described above. Therefore, the driving circuit needs to externally receive a voltage or current for changing the slope compensation voltage in accordance with the variable switching frequency, and a connection terminal for receiving an external current or voltage is additionally required in the driving circuit . Further, in order to generate a voltage or a current for changing the slope compensation voltage, there is a problem that a configuration of an additional circuit including many parts is required.

In addition, the LED channels of the lighting device are configured to emit light at different times for power concentration and thus EMI resolution, as described above. And, the LED current of each LED channel must be ensured to be kept above a predetermined amount for normal light emission.

To ensure that the LED current of each LED channel is maintained above a certain amount, the lighting device detects the lowest voltage among the feedback voltages of each LED channel as the detected voltage, compares the detected voltage with the reference voltage of the fixed level, The output voltage can be controlled according to the comparison result. A technique for controlling the output voltage of the lighting apparatus as described above is disclosed in Korean Patent No. 10-0941509.

The bias voltage of the LED channels may be varied depending on the characteristic deviation. For example, when the bias voltages of the LED channels are all different, the lowest feedback voltage of the LED channels may be changed each time the LED channels are emitted.

Therefore, the output voltage generated by the converter can be varied in level from time to time. When the output voltage changes unstably in this manner, audible noise corresponding to the change in the output change in the converter may occur.

Further, when a large number of LED channels are configured in a lighting device, it is difficult to take charge of all the LED channels with one driving circuit. Therefore, in order to control the emission of a large number of LED channels, a plurality of driving circuits need to be configured. In this case, the driving circuits can be implemented as a multi-chip.

When the driving circuits are implemented in a multi-chip, there is a need to reduce the number of components and manufacturing cost by sharing components such as a converter.

As described above, a proposal of a lighting device capable of sharing components such as a converter in order to solve the need to reduce the number of components and the manufacturing cost when driving circuits are formed by multi-chips corresponding to a large number of LED channels Is required.

In addition, the converter switched by the drive signal must have minimum on-time and minimum off-time. The minimum on-time means the smallest time that the converter's switch can turn on, and the minimum off-time means the smallest time that the converter's switch can turn off. In general, the minimum on-time for turning on the converter and the minimum off-time for turning off the converter are fixed.

However, when the switching frequency of the converter is changed, securing an effective duty of the driving signal for controlling the dimming may be difficult due to the fixed minimum ON time. More specifically, the higher the switching frequency of the converter, the more the fixed minimum on-time occupies an increasing proportion of the turn-on duration of the converter. As a result, it becomes increasingly difficult to sufficiently secure the duty of the driving signal for use in dimming.

Further, when the switching frequency of the converter is changed, securing an effective duty of the driving signal for controlling the dimming may be difficult due to the fixed minimum off-time. More specifically, the higher the switching frequency of the converter, the smaller the off-time occupies an increasingly large portion within one period of the driving signal. As a result, it becomes increasingly difficult to sufficiently secure the duty of the driving signal for use in dimming.

Therefore, there is a need for a method of ensuring effective duty of the drive signal for controlling the dimming of the LED lamp regardless of the change in the switching frequency of the converter.

An object of the present invention is to stably maintain an output voltage provided to loads in response to a change in the load of lighting loads such as LEDs for stable operation of the lighting apparatus.

The present invention quickly compensates the ON time of a driving signal for generating an output voltage at a time of a load change of lighting loads included in an illumination apparatus to a preset value, and stably maintains an output voltage in a short period of time in response to a load change For other purposes.

Another object of the present invention is to reduce the EMI generated in the power conversion process for generating the output voltage to be provided to the lighting loads of the lighting apparatus.

The present invention diffuses the switching point of the converter by controlling the driving signal provided for the power conversion of the converter to have the dispersion frequency applied with the dispersion spectrum and solves the problem that the power consumption is concentrated at the switching point of the converter, And the like.

Another object of the present invention is to control the sub harmonic oscillation that can occur according to the duty state of the output voltage by providing the slope compensation voltage corresponding to the variable switching frequency for the power conversion of the converter in the lighting apparatus .

The present invention relates to a switching regulator which, when a switching frequency for power conversion of a converter in a lighting apparatus is variable, changes the switching frequency of the switching signal in response to a change in current or voltage corresponding to a switching frequency change of an oscillation circuit, And a slope compensation voltage corresponding to the variable of the slope compensation voltage.

The present invention can be applied to a lighting apparatus in which the structure for actively responding to a switching frequency variable for power conversion of a converter is constructed so as to be easily implemented by an interlocking structure inside a driving circuit composed of chips, It is another purpose.

The present invention increases the reference voltage when the feedback voltage of the lowest level among the feedback voltages corresponding to the bias voltages of the LED channels is lower than a preset level, To stabilize the < / RTI >

The present invention generates a reference voltage by charging / discharging according to a feedback voltage of a minimum level among the feedback voltages corresponding to the bias voltages of the LED channels, regulates the output voltage using the charged / discharged reference voltage, Thereby stabilizing the output voltage.

Another object of the present invention is to control the unstable output voltage by the bias voltage difference of each LED channel, thereby eliminating the audible noise that can be generated in the converter due to the unstable output voltage.

Another object of the present invention is to reduce the number of components and manufacturing cost by sharing components such as a converter when a plurality of drive circuits are configured corresponding to a large number of LED channels.

Another object of the present invention is to drive LED channels using a single converter when a plurality of driving circuits are configured corresponding to a large number of LED channels.

In the case where a plurality of driving circuits are configured corresponding to a large number of LED channels, the present invention shares the lowest feedback voltage for the LED channels corresponding to the respective driving circuits, and the lowest feedback voltage And to control the output voltage provided to the LED channels using the lowest feedback voltage for all the LED channels.

Another object of the present invention is to secure an effective duty of a driving signal for controlling the dimming of the LED lamp even if the switching frequency of the converter changes.

Another object of the present invention is to secure an effective duty of a driving signal for dimming control irrespective of a change of a switching frequency of a converter by changing a minimum ON time corresponding to a switching frequency change of the converter.

Another object of the present invention is to secure effective duty of the driving signal for dimming control regardless of the change of the switching frequency of the converter by changing the minimum off time in accordance with the switching frequency change of the converter.

A lighting device for providing an output voltage to the lighting loads of the present invention includes: a converter for providing the output voltage to the loads by driving a switching element using a driving signal; And a drive circuit for generating a control voltage at a level corresponding to a load change of the loads at a time of a load change and providing the drive signal having an on time adjusted to correspond to the control voltage at the time of the load change, ; And

The driving circuit of the lighting apparatus for providing the driving signal to the converter for providing the output voltage to the lighting loads by driving the switching element using the driving signal according to the present invention is characterized in that, A control voltage providing circuit for providing a corresponding control voltage; And a drive signal providing circuit for providing the drive signal compensated for the load change of the loads at the time of the load change by controlling the ON time of the drive signal in response to the control voltage .

The present invention has the effect of providing an output voltage to the lighting loads using the LED, and quickly performing compensation corresponding to the load change of the loads, thereby stably maintaining the output voltage.

According to the present invention, an output voltage is provided to lighting loads by power conversion using a driving signal, and the on-time of the driving signal is quickly compensated to a predetermined value corresponding to a load change of the loads, And can be stably maintained.

According to the present invention, it is possible to perform power conversion for providing an output voltage using a drive signal having a dispersed frequency, and the switching time of the converter for power conversion is dispersed by the dispersed frequency of the drive signal, The concentration can be mitigated and the EMI can be reduced.

According to the present invention, it is possible to control the sub harmonic oscillation that may occur depending on the state of the voltage output from the converter of the lighting apparatus, and even when the switching frequency for power conversion of the converter is varied, So that the sub harmonic oscillation can be effectively controlled.

According to the present invention, since the structure of the driving circuit for actively responding to the switching frequency variable for power conversion of the converter of the lighting apparatus can be easily implemented by the internal interlocking structure, the number of components and the manufacturing cost can be reduced .

According to the present invention, by changing the reference voltage in accordance with the change in the minimum level feedback voltage, the output voltage generated in the converter can be stabilized by using the changed reference voltage, and the audible noise due to the unstable output voltage can be eliminated .

According to the present invention, the reference voltage is generated by charging / discharging according to the change of the feedback voltage of the minimum level, and the output voltage is regulated by using the reference voltage generated by charge / discharge to stabilize the output voltage generated in the converter And it is possible to eliminate the audible noise due to the unstable output voltage.

According to the present invention, a plurality of driving circuits can be configured corresponding to a large number of LED channels of the driving circuits, and parts such as a converter can be shared, thereby reducing the number of parts and manufacturing cost.

According to the present invention, it is possible to drive LED channels using a single converter corresponding to a large number of LED channels, thereby reducing the number of parts and manufacturing cost.

According to the present invention, the lowest feedback voltage for the LED channels corresponding to each driving circuit is shared, the lowest feedback voltage for all the LED channels is detected, and the lowest feedback voltage for all the LED channels To control the output voltage provided to the LED channels.

According to the present invention, even when the switching frequency of the converter changes, the corrected minimum ON time or the corrected minimum OFF time can be applied, so that an effective duty for controlling dimming of the LED lamp can be secured.

According to the present invention, since the minimum ON time is corrected corresponding to the change of the switching frequency of the converter, the converter can be switched while securing an effective duty even if the switching frequency of the converter is changed.

According to the present invention, since the minimum off-time is corrected in accordance with the change of the switching frequency of the converter, the converter can be switched while securing an effective duty even if the switching frequency of the converter is changed.

1 is a view for explaining embodiments of a lighting apparatus of the present invention;
Fig. 2 is a detailed circuit diagram corresponding to Fig. 1 for explaining a first embodiment of the present invention; Fig.
3 is a waveform diagram for explaining the operation of a general lighting apparatus;
Fig. 4 is a waveform diagram for explaining the operation of the first embodiment of Fig. 2; Fig.
Fig. 5 is a waveform diagram illustrating that the center frequency Fc of the drive signal varies; Fig.
6 is a waveform diagram illustrating a bandwidth of a frequency modulated waveform of a driving signal;
7 is a circuit diagram for explaining a second embodiment of the present invention;
8 is a timing diagram illustrating that the PWM signal is adjusted according to the embodiment of FIG.
9 is a waveform diagram illustrating a frequency dithered drive signal;
10 is a circuit diagram for explaining a third embodiment of the present invention;
11 is a graph illustrating a slope compensation voltage according to the third embodiment.
12 is a circuit diagram for explaining a fourth embodiment of the present invention;
13 is a circuit diagram illustrating the reference voltage generating circuit of FIG. 12;
Fig. 14 is a waveform diagram for voltages of the reference voltage generating circuit of Fig. 13; Fig.
15 is a block diagram for explaining a fifth embodiment of the present invention;
16 is a circuit diagram illustrating linear regulators and a detection voltage generating circuit of the master driving circuit and the slave driving circuit of Fig. 15;
17 is a circuit diagram for explaining a sixth embodiment of the present invention.
FIG. 18 is a waveform diagram for explaining the operation of the embodiment of FIG. 17; FIG.
19 is a graph illustrating the minimum ON time versus frequency variation according to the embodiment of FIG.
20 is a circuit diagram for explaining a seventh embodiment of the present invention;
Fig. 21 is a waveform diagram for explaining the operation of the embodiment of Fig. 20; Fig.
22 is a graph illustrating the minimum off-time versus frequency variation according to the embodiment of Fig.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. It is to be understood that the terminology used herein is for the purpose of description and should not be interpreted as limiting the scope of the present invention.

The embodiments described in the present specification and the configurations shown in the drawings are preferred embodiments of the present invention and are not intended to represent all of the technical ideas of the present invention and thus various equivalents and modifications Can be.

1 is a view for explaining embodiments of the present invention. Referring to Fig. 1, the lighting apparatus includes a converter 10 and a driving circuit 20. Fig. The illumination device may include a vehicle control unit 30, a path unit 40, and an LED lamp 50. [ In the above configuration, the driving circuit 20 may be implemented as a one chip.

The LED lamp 50 may be configured for a vehicle, and as a specific example, a rear combination lamp installed on both sides of the vehicle may be applied. The LED lamp 50 is an example of a light source used as a load, and a light source using various optical elements can be used as a load.

The LED lamp 50 includes a plurality of LED channels CH1 to CH8, wherein each of the LED channels CH1 to CH8 includes one or more LEDs, and the plurality of LED channels CH1 to CH8 may be configured in parallel have.

1 illustrates that one driving circuit 20 drives a plurality of LED channels CH1 to CH8 included in the LED lamp 50. In FIG. The LED lamp 50 may be classified into a type in which LED channels are formed only in the vehicle body depending on the vehicle type and a type in which LED channels are dispersed in a door of a vehicle body and a trunk in case of a rear combination lamp. The LED lamp 50 of FIG. 1 may be defined to include LED channels that are not limited to a particular type but may be configured in various types. The current of each LED channel (CH1 to CH8) is indicated by "ICH1 to ICH8".

The vehicle control unit 30 may include a microcontroller unit (MCU) 32. The MCU 32 may include a main MCU for providing various control signals required for driving the vehicle or some functions necessary for driving the vehicle It can be understood as an auxiliary MCU that cooperates with the main MCU to provide auxiliary control signals.

1 controls the battery voltage VB to be transmitted to the converter 10 in response to the direction instruction signal T / S of the MCU 32, and controls the battery 10, So that the voltage VB is transferred to the converter 10 and the drive circuit 20. [ At this time, the battery voltage VB transmitted to the driving circuit 20 in response to the rapid braking signal ESS can be defined as a dim signal DIM. The direction indicating signal T / S and the sudden braking signal ESS illustrate control signals provided by the MCU 32. [ However, the present invention is not limited thereto and can be configured to provide a voltage corresponding to various control signals for driving the LED lamp 50 to at least one of the converter 10 and the drive circuit 20 according to the maker's needs .

The path portion 40 may be formed between the vehicle control portion 30 and the converter 10 and the drive circuit 20. [ The path unit 40 includes paths D1 and D2 through which the battery voltage VB is transferred to the converter 10 and a path D3 through which the dim signal DIM is transferred to the driving circuit 20. When the direction indicating signal T / S is activated, the battery voltage VB is transmitted to the converter 10 via the path D1. When the sudden braking signal ESS is activated, the battery voltage VB is transferred to the converter 10 via the path D2. The battery voltage VB is transmitted as the dim signal DIM through the path D3 and the activated dim signal DIM is input to the driving circuit 20. [ For example, the path D3 may include a circuit for outputting a dim signal (DIM) having a logic level corresponding to the battery voltage VB. The battery voltage VB transmitted from the path unit 40 to the converter 10 may be defined as an input voltage.

The converter 10 generates the output voltage VOUT and the internal voltage VDIN using the input voltage VIN and supplies the output voltage VOUT to the LED lamp 50, (20). As an example, the converter 10 may be a variety of power conversion circuits such as a buck converter or a flyback converter.

The driving circuit 20 is configured to perform sensing and control for the converter 10 and the LED lamp 50. [

The driving circuit 20 can receive the internal voltage VDIN and the sensing signal SEN from the converter 10 and can provide the driving signal GATE to the converter 10. [ Here, the internal voltage VDIN is a voltage for the operation of the controller 20, and the sensing signal SEN determines the level of the input voltage VIN or the operation state of the converter 10 or the output voltage VOUT state And the drive signal GATE is a signal for use in a switching operation for power conversion of the converter 10 and may be provided as a pulse width modulation (PWM) signal .

The driving circuit 20 also includes feedback resistors R1 to R8 for linear regulation of the feedback voltages FB1 to FB8 of the LED channels CH1 to CH8 and LED channels CH1 to CH8 of the LED lamp 50, The blanking voltage BIN applied to the blanking resistor RBIN for controlling the dimming of the entire LED channels CH1 to CH8 of the LED lamp 50 and the regulation voltages RCH1 to RCH8 applied to the RLs R8, .

Herein, the empty resistor RBIN can be defined as a load current control resistor acting on all of the LED channels CH1 to CH8 as loads, and the empty voltage BIN applied to the blank resistor RBIN can be defined as a load change And can be defined as a load current control voltage.

More specifically, each of the LED channels CH1 to CH8 may be configured to emit light at different points of time in order to distribute a load. At the time when each of the LED channels CH1 to CH8 emits light, an empty voltage of the blank resistor RBIN BIN) can be changed. The change times of the bin voltage BIN may be determined as the change time of the load.

For example, a blank voltage (BIN) in a state in which one LED channel is lighted is higher than a state in which all LED channels are lighted, and an empty voltage (BIN) in a state in which two LED channels are lighted BIN) is high. The time point at which the bin voltage BIN changes may be determined as the time point of the load change as described above.

As a result, the drive circuit 20 can determine the load change time point using the bin voltage BIN and generate the control voltage V _N corresponding to the load amount after the load change time point. The control voltage V _N may be generated corresponding to a preset value, and a detailed description will be given later with reference to the control voltage providing circuit 230.

1, the converter 10 uses the drive signal GATE to provide the output voltage VOUT to the load-side LED channels CH1 to CH8.

Hereinafter, the detailed configuration of the converter 10 and the drive circuit 20 constituted by the embodiment of the present invention will be described with reference to Fig.

The converter 10 includes a switching element Qb and the input voltage VIN is transmitted to the switching element Qb through the resistor Rb and the voltage across the resistor Rb is sensed by the amplifier 110. [ And outputted as a sensing signal SEN. The switching element Qb may be an NMOS transistor, and a FET may be used. The inductor Lb and the capacitor Cb are connected in series to the switching element Qb and the diode Db is connected in parallel between the switching element Qb and the inductor L, The current flows in the reverse direction to the current flow provided from the switching element Qb.

The converter 10 performs power conversion by periodically turning on and off the switching element Qb and the turn-on and turn-off of the switching element Qb can be determined by the driving signal GATE.

When the switching element Qb is turned on, a current loop including a switching element Qb, an inductor Lb, and a capacitor Cb is formed. Current flows into the inductor Lb to accumulate energy, And flows through the capacitor Cb. At this time, the LED channels CH1 to CH8, which are loads, are connected in parallel with the capacitor Cb and supplied with an increasing current as the capacitor Cb.

When the switching element Qb is turned off, a current loop including a diode Db, an inductor Lb and a capacitor Cb is formed. An inductor current, which is energy stored in the inductor Lb, (Cb). At this time, the inductor current gradually decreases, and the LED channels CH1 to CH8 connected in parallel with the capacitor Cb are also supplied with a gradually decreasing current.

In the converter 10, the voltage accumulated in the capacitor Cb is the output voltage VOUT, which is the same as the voltage applied to the LED channels LED1 to LED8.

On the other hand, the drive circuit 20 LED channels (CH1 ~ CH8) load changes to provide the control voltage (V _N) corresponding to the changed load for each time point, and by using the control voltage (V _N) control voltage (V _NC And provides the converter 10 with the drive signal GATE compensated for the load change by having an on time corresponding to the regulated voltage V _NC . Further, the driving circuit 20 for generating a detection voltage (V _D) corresponding to the minimum voltage of the LED channels of the feedback voltage (CH1 ~ CH8) (FB1 ~ FB8), and the detection voltage (V _D) Thereby generating the compensation voltage Vc. Then, the driving circuit 20 is combined with the compensation voltage (Vc) to a control voltage (V _N) may generate a control voltage (V _N).

The feedback voltages FB1 to FB8 are voltages applied to the linear regulators 201 to 208 as described above. The driving circuit 20 includes the linear regulators 201 to 208 and outputs feedback to monitor whether or not the output voltage VOUT maintains above a minimum voltage for normally maintaining the illumination of the LED channels CH1 to CH8 And the received feedback voltages FB1 to FB8 are provided to the detection voltage generating circuit 220 inside the driving circuit 20. [

The linear regulators 201 to 208 are respectively constituted between the regulation resistors R1 to R8 and the LED channels CH1 to CH8. The linear regulator 201 includes a comparator 211 and an NMOS transistor M1. The comparator 211 compares the regulation voltage RCH1 applied to the regulation resistor R1 with a preset reference voltage VREF1 and the NMOS transistor M1 compares the voltage of the LED channel LED1) and the regulation resistor R1. The linear regulators 202 to 208 also include the comparators 212 to 218 and the NMOS transistors M2 to M8, respectively, like the linear regulator 201.

The linear regulators 201 to 208 control the current flowing through the LED channels CH1 to CH8 corresponding to the result of comparing the regulation voltages RCH1 to RCH8 and the reference voltage VREF1, . The amount of current of the LED channels CH1 to CH8 can be limited by the reference voltage VREF1 by the linear regulation operation.

1 or 2, the LEDs CH1 to CH8, the linear regulators 201 to 208, the comparators 211 to 218, the NMOS transistors M1 to M8, the regulation resistors R1 to R8, Some of the regulation voltages RVH1 to RCH8 and the feedback voltages FB1 to FB8 are omitted for the sake of brevity.

The drive circuit 20 further includes not only the above-described linear regulators 201 to 208 but also a detection voltage generation circuit 220, a control voltage supply circuit 230, a load change detection circuit 232 and a drive signal supply circuit .

The detection voltage generation circuit 220 detects the feedback voltage having the minimum value among the feedback voltages FB1 to FB8 and provides the feedback voltage having the minimum value as the detection voltage V _D.

The load change detecting circuit 232 detects the load change time point using the empty voltage BIN. The load change detection circuit 232 not only detects the load change time point but also provides the control voltage supply circuit 230 with a digital value N corresponding to the load amount after the change of the empty voltage BIN, can do.

The empty voltage BIN can be changed at the time when the number of the emitting LED channels CH1 to CH8 is changed, that is, when the load is changed. For example, the load change detection circuit 232 can output binary code " 0000 " when all of the LED channels CH1 to CH8 are extinguished, and when the number of LED channels CH1 to CH8 to emit light increases (N) represented by the binary code can be output in increments of one bit. When the number of the LED channels CH1 to CH8 to emit light decreases, the digital value N is decreased by 1 bit and output can do.

That is, the LED channels to emit light if an increase in the number of (CH1 ~ CH8), a digital value (N) is a (0000), _2, (0001), _2, (0010), _2, (0011), _2, (0100) _2, ( 0101) ₂ , (0110) ₂ , (0111) ₂ , and (1000) ₂ . On the other hand, the LED channels to emit light (CH1 ~ CH8) if the reduction in the number of a digital value (N) is 1000 _2, (0111), _2, (0110), _2, (0101), _2, (0100) _2, (0011) ₂ , (0010) ₂ , (0001) ₂ , and (0000) ₂ .

For example, when all of the LED channels CH1 to CH8 are turned off and one of the LED channels CH1 to CH8 changes to a light emitting state, the load change detection circuit 232 senses a load change time point by a change in the bin voltage BIN . A digital value N corresponding to a state in which all the LED channels CH1 to CH8 are turned off is (0000) ₂ corresponding to a state in which one of the LED channels CH1 to CH8 emits light, (0001) ₂ , the load change detection circuit 232 changes the digital value N from (0000) ₂ to (0001) ₂ and outputs it.

The control voltage providing circuit 230 outputs a control voltage V _N corresponding to the digital value N and outputs a control voltage V _N of an increased level when the digital value N increases, And outputs a control voltage V _N of a reduced level when the value N decreases. For example, when the digital value N is (0001) ₂ than when the digital value N is (0000) ₂ , the control voltage providing circuit 230 outputs a high level control voltage V _N. As described above, the control voltage V _N may be determined by the digital value N input to the control voltage providing circuit 230, and the control voltage providing circuit 230 may supply the control voltage V N corresponding to the digital value N And a digital-analog converter for outputting a voltage V _N.

On the other hand, the drive signal providing circuit generates the compensation voltage Vc corresponding to the detection voltage V _D , generates the adjustment voltage V _NC by adding the control voltage V _N and the compensation voltage Vc, And is configured to generate the driving signal GATE by using the comparison result of the voltage V _NC and the comparison voltage Vs as a reset signal. Here, the comparison voltage Vs is a sum of the sensing signal SEN provided by the converter 10 and the slope compensation voltage provided by the slope compensating unit 240, and the driving signal GATE is a sum of the comparison signal Vs Assuming that it has a fixed value, the on time is determined corresponding to the regulated voltage V _NC .

To this end, the driving signal providing circuit may include a comparator 222, a summer 234, a slope compensator 240, a summer 242, a comparator 244 and an SR latch 250. Here, the SR latch 250 is configured as a pulse generator for generating a gate signal, and may be configured as an SR flip-flop.

The comparator 222 compares the detection voltage V _D0 output from the detection voltage generation circuit 220 with a reference voltage VREF2 having a preset level and outputs the compensation voltage Vc. At this time, the compensation voltage Vc may be stabilized by a capacitor Cd connected to the output terminal of the comparator 222. [ And, in an embodiment of the present invention, the comparator 222 is configured such that the detection voltage V _D0 is applied to the negative terminal (-) and the reference voltage VREF2 is applied to the positive terminal (+).

The adder 234 generates a regulated voltage V _NC by adding the control voltage V _N provided from the control voltage providing circuit 230 and the compensated voltage Vc outputted from the comparator 222, V _NC ) to the negative terminal (-) of the comparator 244.

The embodiment of the present invention may include a slope compensating unit 240. The slope compensating unit 240 may compensate the slope if there is a need to adjust the rising edge of the driving signal GATE. And outputs a slope compensation voltage to be used.

The summer 242 sums the slope compensation voltage of the slope compensator 240 and the sensing signal SEN output from the converter 10 and outputs the sum as a comparison voltage Vs.

The comparator 244 outputs the comparison result of the comparison voltage Vs and the adjustment voltage V _NC . In an embodiment of the present invention, the comparator 244 is configured such that the comparison voltage Vs is applied to the positive terminal (+) and the regulated voltage V _NC is applied to the negative terminal (-). The driving signal GATE can have a waveform reflecting the slope compensation voltage of the slope compensating unit 240 and the sensing signal SEN of the converter 10 by the configuration of the comparator 244 and the summer 242 , And the on-time can be determined by the regulated voltage (V _NC ).

The SR latch 250 receives the PWM signal including the periodic pulse at the set terminal S and receives the output of the comparator 244 at the reset terminal R. The SR latch 250 outputs the driving signal GATE through the output terminal Q and the driving signal GATE is applied to the gate of the switching element Qb. The PWM signal may be provided in an oscillation circuit such as an oscillator (not shown), and the oscillation circuit may be configured inside or outside the drive circuit 20. The output of the comparator 244 functions as a reset signal for determining the ON time of the driving signal GATE. That is, the SR latch 250 is reset by the output of the comparator 244 to determine the on-time at which the drive signal GATE is output to the output stage Q, And outputs the PWM signal as the driving signal GATE.

The relationship between the output current IL and the output voltage VOUT and the compensation voltage Vc can be described as shown in FIG. 3 when the control voltage providing circuit 230 according to the embodiment of the present invention is not configured. In Fig. 3, Real Vc shows the change in the compensation voltage Vc, and Ideal Vc shows the ideal compensation voltage Vc corresponding to the change in the load change.

That is, when the number of LED channels emitting light from the LED lamp 50 increases, the output voltage VOUT temporarily decreases due to an increase in load. When the output voltage VOUT is lowered, the feedback voltages FB1 to FB8 are also lowered, and the detection voltage V _D output from the detection voltage generation circuit 220 is also lowered.

The comparator 222 outputs a compensation voltage Vc having an increased level in proportion to the difference between the reference voltage VREF2 and the detection voltage V _D and outputs the compensation voltage Vc from the SR latch 250 to the output The on-time of the driving signal GATE becomes faster. When the on-time of the drive signal GATE increases, the level of the output voltage VOUT output from the converter 10 rises.

As the output voltage VOUT is compensated, the amount of decrease of the feedback voltages FB1 to FB8 and the detection voltage V _D decreases and the compensation voltage Vc gradually increases. After a certain period of time, it may return to normal level.

Conversely, when the number of LED channels emitting light in the LED lamp 50 decreases, the output voltage VOUT temporarily increases due to the decrease in load. The temporary increase of the output voltage VOUT due to the above-described reduction in the load is gradually compensated because the compensation voltage Vc gradually decreases due to the rise of the feedback voltages FB1 to FB8 and the detection voltage V _D , VOUT) may be returned to a normal level.

However, since the compensation of the output voltage VOUT by the compensation voltage Vc proceeds slowly in response to the change in the load, the output voltage VOUT is hard to be stably maintained.

In addition, when the output voltage VOUT is significantly lowered, it may be difficult to ensure the minimum voltage at which the LED channels CH1 to CH8 can stably emit light, so that it may be difficult to maintain a stable lighting state.

The embodiment of the present invention can stably maintain the output voltage VOUT even when a load change occurs due to the operation of the control voltage providing circuit 230. [ The output current IL according to the embodiment of the present invention described above. The correlation between the regulated voltage V _NC , the compensated voltage Vc, and the output voltage VOUT can be described as shown in FIG.

That is, when the number of LED channels that emit light from the LED lamp 50 increases, the load detection circuit 232 provides the control voltage supply circuit 230 with a digital value N corresponding to the load amount increased at the time of the load change , And the control voltage providing circuit 230 provides the control voltage V _N having the raised level corresponding to the increased load amount from the load change time point. The regulated voltage V _Nc also increases from the load change time point by the change of the control voltage V _N and the SR latch 250 outputs the output voltage V OUT from the load change time by the regulated voltage V _Nc And outputs a drive signal GATE having a changed on-time that can be stably maintained.

Further, when the number of LED channels emitting light from the LED lamp 50 decreases, the load detection circuit 232 provides the control voltage supply circuit 230 with a digital value N corresponding to the load amount that is reduced at the time of the load change And the control voltage providing circuit 230 provides the control voltage V _N having the lowered level corresponding to the reduced load amount from the load change time point. The regulated voltage V _Nc also falls from the load change time point by the change of the control voltage V _N and the SR latch 250 outputs the output voltage V OUT from the load change time by the regulated voltage V _Nc And outputs a drive signal GATE having a changed on-time so as to be stably maintained.

The output voltage VOUT can be stably maintained because the compensation of the output voltage VOUT according to the embodiment of the present invention can be performed rapidly in response to the change in the load amount. On the other hand, the output voltage VOUT is stably maintained, so that the feedback voltages FB1 to FB8 are also stabilized. As a result, the compensation voltage Vc also has a waveform maintaining a constant level without change.

Therefore, the embodiment of the present invention can quickly perform the compensation corresponding to the load change of the loads, stably maintain the output voltage VOUT, and maintain a good lighting state.

In the embodiment of the present invention described above, the driving signal GATE is generated using a PWM signal including a periodic pulse. When the driving signal GATE includes a pulse of a fixed frequency by a PWM signal of a constant frequency, the converter 10 of the lighting apparatus can consume a large amount of power at the switching time by the driving signal GATE, .

In order to reduce the EMI, the present invention discloses an embodiment in which the frequency of the PWM signal used for generation of the drive signal GATE can be changed over time by a spread spectrum method. According to the embodiment of the present invention, the driving signal GATE may have pulses of a dispersed frequency. The converter 10 can perform the power conversion by the dispersed switching point by the pulse of the dispersed frequency of the driving signal GATE and the power consumption can be dispersed by the dispersion of the switching time point and the EMI can be reduced have.

The frequency of the PWM signal can be distributed using Carson's rule. Fig. 5 shows that the center frequency fc varies with time within a constant variable frequency ([Delta] f) range according to Carson's law. Fig. 6 illustrates the bandwidth of a frequency-modulated waveform according to Carson's law, wherein the modulation frequency of the variable frequency [Delta] f is denoted by "fm ".

The dispersion spectrum can be implemented as "center frequency fc ± variable frequency Δf" or "center frequency fc-variable frequency Δf". Embodiments of the present invention can be implemented using "center frequency fc +/- variable frequency f.

The variable frequency (Δf) can be non-dithered, 5%, 10%, 20% and 30%, for example, by using optional information. Non-dithering means maintaining the original frequency, and option information is set to change the resistance value of the dithering resistor Rf described later.

The modulation frequency fm of the variable frequency f is a frequency variable by changing the frequency reference voltage FREF and the frequency reference voltage FREF is variable by 5 msec, 10 msec, 40 msec, for example, can do. The digital control means that the step control unit 304, which will be described later, is controlled by the dithering control signal DMOD.

By applying the above-described spread spectrum, the frequency of the pulse included in the driving signal FATE can be changed with time. An embodiment for this can be illustrated as shown in FIG.

Referring to FIG. 7, an embodiment of the present invention may include a dithering control unit 300, filters 310 and 320, and an oscillator 330.

The dithering controller 300 exemplarily has a configuration for varying the frequency reference voltage FREF by 64 steps and includes a dithering resistor Rf and a dithering control signal DMOD whose resistance value is changed by option information, And a step control unit 304 for changing the frequency reference voltage. The dithering control unit 300 further includes a comparator 302, a PMOS transistor Qp, and a resistor string.

First, the resistance string includes resistors Rd1 to Rd64 connected in series corresponding to 64 steps and a dithering resistor Rf connected in series to the resistors Rd1 to RD64. It is preferable that the dithering resistor Rf is constituted by a variable resistor which is grounded at the end of the resistor string and can be changed in resistance value corresponding to the option information. The resistors (Rd1 to Rd64) are divided into a lower resistance group (Rd1 to Rd32) of 32 steps and an upper resistance group (Rd33 to Rd64) of 32 steps.

The comparator 302 outputs a voltage corresponding to the comparison result of the voltages Vf1 and Vf2 and the PMOS transistor Qp is driven by the voltage outputted from the comparator 302 and the driving voltage VDD is applied to the resistor string. . Here, the voltage Vf1 input to the negative terminal (-) of the comparator 302 may be supplied with a voltage of a fixed level. The voltage Vf2 input to the positive terminal (+) of the comparator 302 can use the voltage applied to the node between the lower resistance group Rd1 to Rd32 and the upper resistance group Rd33 to Rd64.

The step control unit 304 includes switches connected in parallel to nodes between the resistors Rd1 to Rd64 of the resistor string. The switches of the step control unit 304 are configured in the same number as the resistors Rd1 to Rd64. Switches are individually controlled by a dithering control signal DMOD having a digital value, and the dithering control signal DMOD has a bit number that can be allocated to each switch by one bit.

In the step control unit 304, one end of the switches is connected to the nodes between the resistors Rd1 to Rd64 of the resistor string as described above, and the other ends of the switches are commonly connected to output the frequency reference voltage FREF And forms the output terminal of the dithering control unit 300.

The dithering controller 300 may be configured as a digital-to-analog converter that provides a frequency reference voltage (FREF) represented by an analog value corresponding to a dithering control signal (DMOD) having a digital value.

The step control unit 304 sequentially turns on the switches connected to the lower resistance groups Rd1 to Rd32 so that the frequency reference voltage FREF rises stepwise from a low level to a high level. Thereafter, the step control unit 304 sequentially turns on the switches connected to the upper resistance group Rd33 to Rd64, so that the frequency reference voltage FREF falls stepwise from a high level to a low level. Under the control of the step control unit 304, the frequency reference voltage FREF has a triangular waveform in which a rising period of 32 steps and a falling period of 32 steps are formed.

The period of the frequency reference voltage (FREF) can be controlled by adjusting the switching period of 64 steps of the step control unit 304. [ That is, if the cycle in which the dithering control signal DMOD is provided is variable, the period of the frequency reference voltage FREF may be varied correspondingly. In an embodiment of the present invention, the frequency of the frequency reference voltage FREF May be configured to change the period.

Further, the period of the frequency reference voltage (FREF) can be controlled by adjusting the voltage variation width for each step. The stepwise voltage variation width may be adjusted corresponding to the option information provided to the dithering resistor Rf.

The sum of the height variations of the respective steps due to the change in the resistance value of the dithering resistor Rf is represented by the change in height of the triangular waveform of the frequency reference voltage FREF. Therefore, the height of the triangular waveform of the frequency reference voltage FREF can be controlled by the resistance value of the dithering resistor Rf which varies depending on the option information.

More specifically, when the height of the triangular waveform of the frequency reference voltage VREF increases, the time required for the frequency reference voltage FREF to rise from the lowest level to the highest level and the time to fall from the highest level to the lowest level are further required. That is, the period of the frequency reference voltage FREF can be long. Conversely, when the height of the triangular waveform of the frequency reference voltage VREF is lowered, the time for the frequency reference voltage FREF to rise from the lowest level to the highest level and the time to fall from the highest level to the lowest level are reduced. That is, the period of the frequency reference voltage FREF can be shortened.

The step control unit 304 configured by the embodiment of the present invention can change the shape of the frequency reference voltage VREF.

The frequency reference voltage FREF of the triangular waveform outputted from the dithering control unit 300 is applied to the filter 310 and the frequency reference voltage VREF is applied to the filter 310 by the action of the filter 310 in which the resistor and the capacitor are connected in parallel. FREF) is relaxed.

The frequency reference voltage FREF is applied to the filter 320 via the filter 310 and the filter 320 applies the oscillation signal VOSC shaped in a triangular waveform to the oscillator 330.

The oscillator 330 may compare the oscillation signal VOSC of the triangular waveform with an internal reference voltage (not shown) to output a PWM signal having a periodic pulse waveform.

The embodiment of FIG. 7 described above can be applied to the driving circuit 20, and the frequency of the PWM signal can be changed along with the change of the shape of the oscillation signal Vosc. When the oscillation signal Vosc changes every cycle, the oscillator 330 provides a PWM signal having a frequency dispersed every cycle. As a result, the driving circuit 20 can provide the driving signal GATE having the frequency-dispersed pulses by the frequency dithering to the converter 10. [ Therefore, the converter 10 can perform switching for power conversion at a time when it is dispersed by the frequency dithering drive signal Gate, and consequently concentration of power consumption can be alleviated and EMI can be reduced.

Referring to FIG. 8, DIM_EN is a dimming control enable signal of the lighting apparatus, JIT_EN is a frequency dithering enable signal, and MAX and MIN are control signals for controlling the timing when the triangular waveform oscillation signal Vosc has a maximum value or a minimum value Lt; / RTI >

The lighting apparatus performs an initializing operation in which the oscillation signal Vosc is maintained at a constant level after power-on, and then outputs the oscillation signal Vosc having a triangular waveform when the dimming control enable signal DIM_EN is enabled Lt; / RTI >

Before the frequency dithering enable signal JIT_EN is enabled, the oscillation signal Vosc is output so as to have a triangular waveform of a uniform shape. That is, the period T of the oscillation signal Vosc at this time is uniform.

After the frequency dithering enable signal JIT_EN is enabled, the frequency reference voltage FREF changes according to the change of the option information applied to the dithering resistor Rf or the frequency reference At least one of the magnitude and the period of the triangular waveform of the oscillation signal Vosc may be changed every cycle by the period change of the voltage FREF.

The driving circuit 20 configured as an embodiment of the present invention can store a plurality of values corresponding to the option information or the dithering control signal DMOD in a storage and can output the frequency of the frequency reference voltage FREF in a regular or irregular manner Information and a dithering control signal DMOD.

 The dithering control unit 300 of the driving circuit 20 controls the dithering of the driving signal GATE for a predetermined period of time before the enable of the driving signal GATE and the first period, And a second period during which the enable period ends and the enable period ends.

The driving circuit 20 may perform frequency dithering on the driving signal GATE by periodically changing the option information or the dithering control signal DMOD to the dithering control unit 300. [ In addition, the driving circuit 20 performs frequency dithering on the driving signal GATE by changing the option information or the dithering control signal DMOD in a repeated pattern in units of a plurality of periods to the dithering control unit 300 . In addition, the driving circuit 20 can perform frequency demodulation by changing the frequency reference voltage VREF in a pattern that gradually changes the frequency.

The peak value of the drive signal GATE can be reduced by frequency dithering and the frequency can be dispersed by the frequency divider for the drive signal GATE described above as shown in FIG. Therefore, the converter 10 can disperse the switching time for power conversion so as to mitigate concentration of power consumption, and EMI can be reduced.

The driving circuit 20 of the present invention may be implemented by including a slope compensation unit 241 for generating a slope compensation voltage having a value interlocked with a variable switching frequency of the converter 10 as shown in FIG.

In order for the slope compensation voltage to be interlocked with the variable switching frequency of the converter 10, the driving circuit 20 is configured to use a frequency source that provides the changed frequency information of the driving signal GATE. Here, the frequency source may be an oscillator 330 that provides the PWM signal used to generate the drive signal GATE. Further, the frequency information may use the output of the oscillator 330, and more specifically, either the voltage or the current corresponding to the output of the oscillator 330 may be used.

The slope compensation unit 241 may include a slave current source IS2 and a charging device Cc connected in series and the slave current source IS2 may control the amount of current corresponding to the frequency information, Can be constructed using a capacitor and charges the current provided by the slave current source IS2 and provides the charged voltage as a slope compensation voltage.

The slope compensating unit 241 may be configured to generate a lower slope compensation voltage as the frequency of the driving signal GATE increases.

10, the current source IS1 and the PMOS transistor MS may be understood as corresponding to the summer 242 of FIG. 2, and FIG. 10 is a diagram showing the relationship between the sensing signal SEN and the slope compensator 241, The sum of the slope compensation voltages outputted from the slope compensating circuit is summed up. The summing unit 242 is not limited to FIG. 10 and may be variously implemented by the manufacturer.

10, an unstable sub harmonic oscillation generated when the duty of the drive signal GATE provided to the converter 10 to generate the output voltage is 50% or more is controlled by the slope compensator 241 Can,

In order to vary the switching frequency of the converter 10, the frequency of the driving signal GATE must be variable. That is, the switching frequency of the converter 10 varies depending on the frequency of the driving signal GATE.

When the switching frequency is variable, the value of the inductance of the converter 10 is also changed. At this time, the value of the slope compensation voltage of the slope compensating unit 241 of FIG. 10 is also changed corresponding to the change of the value of the inductance.

More specifically, in order to vary the frequency of the driving signal GATE, the frequency of the PWM signal output from the oscillator 330 must also be varied. Therefore, the oscillator 330 has variable frequency information, and as a result, can be used as a frequency source as described above.

In one example, the slave current source IS2 may be configured to provide the charging device Cc with a current mirroring the output current of the oscillator 330. [ That is, the slave current source IS2 can provide the charging device Cc with a current interlocked with the current corresponding to the PWM signal of the oscillator 330 whose frequency is varied in order to vary the frequency of the driving signal GATE. At this time, the current mirroring decreases the amount of current of the slave current source IS2 when the frequency of the oscillator 330 becomes high due to a high frequency of the oscillator 330 and increases the amount of current of the slave current source IS2 when the frequency of the oscillator 330 becomes low, . ≪ / RTI > The relationship between the frequency of the oscillator 30 and the current of the slave current source IS2 may be determined for slope compensation to reduce sub harmonic oscillation.

In contrast to the above, the slave current source IS2 may be configured to provide the charging device Cc with a current interlocking with the PWM signal of the oscillator 330 or the voltage corresponding to the PWM signal. At this time, the slave current source IS2 decreases the amount of current by the voltage corresponding to the PWM signal or the PWM signal of the oscillator 330 whose frequency is increased, and by the voltage corresponding to the PWM signal or PWM signal of the oscillator 330 whose frequency is lowered And may be configured to increase the amount of current.

The current provided in the slave current source IS2 is charged in the charging element Cc and the voltage charged in the charging element Cc can be provided in the slope compensation voltage. That is, the slope compensation voltage may be provided so as to vary according to the frequency as shown in FIG. FIG. 11 is a graph showing a comparison between a slope compensation voltage according to the present invention and a conventional slope compensation voltage in which a voltage charged by a fixed current is provided as a slope compensation voltage.

Therefore, even if the switching frequency of the converter 10 is variable, the embodiment of the present invention can be realized by a configuration in which a separate terminal is not provided in the driving circuit 20 implemented by a chip, It is possible to provide the slope compensation voltage in conjunction with the frequency variation of the PWM signal output from the oscillator.

Therefore, the function for actively responding to the switching frequency variable of the converter 10 can be simply implemented, and the number of parts and manufacturing cost can be reduced.

The fourth embodiment for ensuring that the LED current of each of the LED channels (CH1 to CH8) included in the LED lamp 50 is maintained over a predetermined amount can be exemplified as shown in FIG. In FIG. 12, the same components as those of FIG. 2 are denoted by the same reference numerals, and a duplicate description thereof will be omitted.

12 includes an output sensing circuit 60 for sensing the output voltage VOT of the converter 10 and the output sensing circuit 60 is connected in series with the resistors RV1 and RV2 connected in series to the converter 10 In parallel. The output sensing circuit 60 provides the driving circuit 20 with a voltage applied to the node between the resistors RV1 and RV2 connected in series and the voltage supplied to the driving circuit 20 in the output sensing circuit 60 is Output sensing voltage. The output sensing circuit 60 may be configured to be either internal or external to the driving circuit 20. [

The drive circuit 20 includes linear regulators 201 to 208, a detection voltage generation circuit 220, a reference voltage generation circuit 221, a comparator 223, a capacitor Cd, a slope compensation unit 240, A comparator 242, a comparator 244, and an SR latch 250.

The driving circuit of Fig. 12 includes a reference voltage generating circuit 221 differently from Fig. The reference voltage generation circuit 221 receives the detection voltage V _D and the internal reference voltage VREFi of the detection voltage generation circuit 22 and uses the external capacitor Cs and outputs the reference voltage VREF to the comparator 223 in the negative direction.

The reference voltage generating circuit 221 generates at least one of the feedback voltages FB1 to FB8 corresponding to the bias voltages of the LED channels LED1 to LED8 with an internal reference voltage VREFi), the reference voltage VREF whose level increases is generated. The reference voltage generating circuit 221 is preferably configured to generate a reference voltage that increases until all the feedback voltages FB1 to FB8 are equal to or greater than the internal reference voltage VREFi. The reference voltage generating circuit 221 is configured to charge or discharge the reference voltage VREF using an external capacitor Ce.

The configuration of the reference voltage generating circuit 221 in more detail will be described later with reference to Fig.

2, the driving circuit 20 of FIG. 12 is configured such that the comparator 223 compares the reference voltage VREF with the output sensing voltage of the output sensing circuit 60 to output the compensation voltage Vc. The reference voltage VREF is applied to the negative terminal (-) of the comparator 223 and the output sensing voltage of the output sensing circuit 60 is applied to the positive terminal (+) of the comparator 223.

2, the driving circuit 20 of FIG. 12 is configured such that the comparator 244 compares the comparison voltage Vs of the summer 242 with the compensation voltage Vc and outputs it. The compensation voltage Vc is applied to the negative terminal (-) of the comparator 244 and the comparison voltage Vs is applied to the positive terminal (+) of the comparator 244.

With the above configuration, the SR latch 250, which is a pulse generator, generates the drive signal GATE corresponding to the output of the comparator 244 whose level is determined corresponding to the compensation voltage Vc. That is, the SR latch 25 generates the drive signal GATE whose on-time is adjusted in response to the compensation voltage Vc and provides the drive signal GATE to the converter 10 for power conversion.

The configuration of the reference voltage generation circuit 221 will be described in more detail with reference to FIG.

The reference voltage generating circuit 221 performs charging or discharging using an external capacitor Ce and charging is performed when at least one of the feedback voltages FB1 to FB8 is equal to or lower than the internal reference voltage VREFi, Is performed until all the feedback voltages FB1 to FB8 are equal to or greater than the internal reference voltage VREFi and is configured to output the voltage charged in the capacitor Ce as the reference voltage VREF.

To this end, the reference voltage generating circuit 221 includes a comparator 225 and a current control circuit. The comparator 225 compares the switching control voltage VCT obtained by comparing the detection voltage V _D with the internal reference voltage VREFi, And the current control circuit includes a switch SW that is switched in accordance with the switching control voltage VCT and provides a current for charging the capacitor Ce when the switch SW is turned on. The comparator 225 is a detection voltage (V _D) may output a switching control voltage (VCT) is less than the internal reference voltage (VREFi) to 0V with a low level of example, the detection voltage (V _D), the voltage is inside the reference (VREFi), the switching control voltage VCT can be output to the constant voltage VDD as an example of the high level. When the switching control voltage VCT is at a low level, the switch SW is turned on and when the switching control voltage VCT is at a high level, the switch SW is turned off.

The current control circuit may further include a plurality of PMOS transistors MP1 to MP7 to control the supply of current to the capacitor Ce by the turn-on of the switch SW. The plurality of PMOS transistors MP1 to MP7 may be configured to have a current mirror structure for controlling the current supplied to the capacitor Ce by the operation of the switch SW.

That is, the PMOS transistors MP1 and MP2 form a first path including a constant current source, the PMOS transistors MP3, MP4, and MP5 form a second path that provides a copied current, and the PMOS transistors MP6, The switch SW and the PMOS transistor MP7 form a third path for controlling the current supplied to the capacitor Ce by the current of the second path. In the first to third paths, the transistors included therein are connected in series, and the first path to the third path are configured in parallel with respect to the constant voltage VDD.

The amount of current flowing through the PMOS transistors MP3 and MP4 in the second path is controlled by the resistance ratio (channel ratio) between the PMOS transistors MP3 and MP4 and the PMOS transistors MP1 and MP2, Can be controlled on the basis of the amount of current flowing in the transistors MP1 and MP2. The amount of current flowing in the PMOS transistor MP6 can also be controlled based on the amount of current flowing in the PMOS transistor MP1 in the first path. The amount of current flowing in the PMOS transistor MP7 can be controlled based on the amount of current flowing in the PMOS transistor MP5 in the second path.

The operation of the reference voltage generating circuit 221 configured as shown in FIG. 13 will be described with reference to FIG.

When the detection voltage VD is lower than the internal reference voltage VREFi in the reference voltage generation circuit 221, the switching control voltage VCT of the comparator 225 becomes low level. As a result, the switch SW is turned on do.

When the switch SW is turned on, the flow of the current Ir1 is started, the current Ir3 is supplied to the capacitor Ce, and the voltage charged by the current Ir3 rises in the capacitor Ce. The voltage charged in the capacitor Ce is the reference voltage VREF output from the reference voltage generating circuit 221. [ The amount of current of the current Ir3 in the above-described manner can be determined as "the amount of the current Ir1" - "the amount of the current Ir2 of the PMOS transistor MP7".

The detection voltage V _D is the lowest feedback voltage among the mode feedback voltages FB1 to FB8. The switching control voltage VCT of the comparator 225 transitions to a high level when all of the feedback voltages FB1 to FB8 are equal to or higher than the internal reference voltage VREFi. Therefore, the reference voltage VREF charged in the capacitor Ce is also charged until all the feedback voltages FB1 to FB8 are equal to or higher than the internal reference voltage VREFi, and the level is raised.

Thereafter, when all of the feedback voltages FB1 to FB8 are equal to or higher than the internal reference voltage VREFi, the switching control voltage VCT is shifted to the high level, and the switch SW is turned off. When the switch SW is turned off, the flow of the current Ir1 is stopped.

After the current Ir1 stops flowing, the capacitor Ce starts discharging, so that the level of the reference voltage VREF output from the reference voltage generating circuit 221 gradually decreases.

As described above, the reference voltage VREF provided in the reference voltage generating circuit 221 may be increased or decreased depending on the states of the feedback voltages FB1 to FB8.

When the reference voltage VREF increases, it is necessary to compensate for the amount of the LED current for the normal light emission of the LED channels CH1 to CH8. At this time, the output voltage VOUT rises by the increasing reference voltage VREF. When the reference voltage VREF decreases, the amount of the LED current of the LED channels CH1 to CH8 corresponds to the case where the amount of the LED current can maintain normal light emission.

A series of operations in which the output voltage VOUT is raised by raising the reference voltage VREF will be described in more detail. When the reference voltage VREF rises, the comparator 223 compares the output sensing voltage of the output sensing circuit 60 with the raised reference voltage VREF. As a result, when the output sensing voltage of the output sensing circuit 60 is lower than the reference voltage VREF, the compensation voltage Vc is applied to the negative terminal (-) of the comparator 244 at a negative level. When the compensation voltage Vc is applied at the negative level, the output of the comparator 244 rises. When the output of the comparator 244 rises, the SR latch 25 generates the drive signal GATE whose on time has been increased. As a result, the output voltage VOUT output from the converter 10 rises.

As described above, the output voltage VOUT is regulated to be maintained above a certain level by the increasing reference voltage VREF.

The fourth embodiment of the present invention can be regulated by the reference voltage VREF at which the output voltage VOUT is changed as described above.

Therefore, the bias voltages of the LED channels CH1 to CH8 are different from each other due to the characteristic variation, and the lowest feedback voltage of the LED channels CH1 to CH8 is changed when the LED channels CH1 to CH8 are respectively lit The fourth embodiment of the present invention can stably maintain the output voltage VOUT, and as a result, it is possible to prevent the occurrence of audible noise.

The fifth embodiment of the present invention can be configured as shown in FIG. 15 in order to reduce the number of components and manufacturing cost by sharing components such as a converter.

The embodiment shown in Fig. 15 exemplifies a configuration in which driving circuits are formed in a multichip for one converter 10, and a driving circuit for providing the driving signal GATE to the converter 10 for distinguishing the driving circuits is a master driving circuit (M20), and the remaining drive circuits are referred to as a slave drive circuit S20.

The embodiment of Fig. 15 differs from the embodiment of Fig. 15 in that the converter 10 performs power conversion to output an output voltage VOUT corresponding to the input voltage VIN and to provide the output voltage VOUT to the LED lamps M50 and S50 .

The LED lamps M50 and S50 each include a plurality of LED channels CH1 to CH8 arranged in parallel as shown in FIG. 1, and a plurality of LED channels CH1 to CH8 of the LED lamps M50 and S50, Is emitted by the output voltage VOUT.

On the other hand, an overvoltage detection circuit 70 for detecting the level of the output voltage VOUT is configured at the output terminal of the converter 10. [ The overvoltage detection circuit 70 outputs the voltage applied to the node between the resistors ROVT1 and ROVT2 connected in series as an overvoltage detection signal and the overvoltage detection signal is outputted to the master drive circuit M20 and the slave drive circuit S20 Over-voltage detection stage (OVP).

The master driving circuit M20 controls the level of the output voltage VOUT by controlling the output of the driving signal GATE or controls the level of the output voltage VOUT by the LED lamp M50 Can be controlled. Further, if it is determined that the output voltage VOUT is in the overvoltage state by the overvoltage detection signal, the slave driving circuit S20 can control the light emitting state of the LED lamp S50.

The master drive circuit M20 and the slave drive circuit S20 have substantially the same configuration as the drive circuit 20 of FIG. 1 except that the common terminal CON and the high ground terminal HGND are formed. Duplicate descriptions are omitted. The master drive circuit M20 and the slave drive circuit S20 may be configured as multi-chips. That is, the master drive circuit M20 and the slave drive circuit S20 may be configured using chips having the same structure.

The common terminal CON of the master driving circuit M20 and the common terminal of the slave driving circuit S20 are electrically connected to each other. The high ground terminal HGND of the master driving circuit M20 and the slave driving circuit S20 is set to a state where a constant voltage is biased by using the capacitor CH.

The master driving circuit M20 performs linear regulation on the LED channels CH1 to CH8 of the LED lamp M50 and performs the linear regulation on the feedback voltages FB1 to CH8 of the LED channels CH1 to CH8 of the LED lamp 50, FB8 and generates a detection voltage V _D corresponding to a lower one of a second minimum feedback voltage shared through the common terminal CON and the first minimum feedback voltage Generates a drive signal GATE corresponding to the detection voltage V _D and provides a drive signal GATE to the converter 10 for power conversion. In the above description, the master driving circuit M20 generates the driving signal GATE using the detection voltage V _{D in} various manners, such as the embodiment of FIGS. 1 and 2 or the embodiment of FIG. 12 A detailed description thereof will be omitted.

The slave driving circuit S20 performs linear regulation on the LED channels CH1 to CH8 of the LED lamp S50 and performs the linear regulation on the LEDs S50, Level, and shares the second minimum feedback voltage with the master driving circuit M20 via the shared terminal CON.

The slave driving circuit S20 has input / output terminals related to generation and output of driving signals like the master driving circuit M20. However, the slave driving circuit S20 does not generate and output the driving signal GATE. Therefore, at least a part (VIN, SEN, GATE) of the input / output terminals is partially masked with respect to generation and output of the input / output terminals drive signal GATE of the slave drive circuit S20. Here, The processing means that the input level is fixed by the high level voltage charged in the capacitor CH by the input voltage VIN or is fixed at the ground level of the capacitor CIN, and the floating state can also be included.

The master drive circuit M20 and the slave drive circuit S20 described above may include a detection voltage generation circuit 220 for generating a detection voltage, respectively. The configuration and operation of the detection voltage generation circuit 220 of the master drive circuit M20 and the slave drive circuit S20 will be described with reference to FIG. 16 schematically shows the detection voltage generating circuit 220 and the linear regulators 201 to 208 of the master driving circuit M20 and the slave driving circuit S20.

The feedback voltages FB1 to FB8 of the master driving circuit M20 and the slave driving circuit S20 are voltages applied to the respective linear regulators 201 to 208, respectively. Since each of the linear regulators 201 to 208 is the same as that of FIG. 2, detailed description of the configuration and operation thereof will be omitted.

The feedback voltages FB1 to FB8 are applied to the detection voltage generating circuit 220 in the master driving circuit M20 and the slave driving circuit S20.

The detection voltage generating circuit 220 of the master driving circuit M20 and the slave driving circuit S20 may include the transistors TFB1 to TFB8 and the switches SFB1 to SFB8 by the paths of the feedback voltages FB1 to FB8 have.

The transistors TFB1 to TFB8 transmit the feedback voltages FB1 to FB8 to the switches SFB1 to SFB8 when the switches SFB1 to SFB8 are turned on and the switches SFB1 to SFB8, And the feedback voltages FB1 to FB8 that are switched by the switches FBS1 to FBS8 and are transmitted through the transistors TFB1 to TFB8 to the output terminal of the detection voltage generation circuit 220. [

The output terminal of the detection voltage generation circuit 220 is a node connected to the switches SFB1 to SFB8 to output the detection voltage V _D. The constant current can be supplied by the constant current source as illustrated.

The detection voltage generation circuit 220 may include a circuit (not shown) for comparing the levels of the feedback voltages FB1 to FB8 to determine the lowest level feedback voltage (minimum feedback voltage). The circuit described above can be easily constructed by using a conventional comparator, level detector, or the like to understand the technical concept of the present invention, so that a detailed description thereof will be omitted.

The detection voltage generation circuit 220 may provide the switching control signals FBS1 to FBS8 to the switches SFB1 to SFB8 for outputting only the minimum feedback voltage as the detection voltage V _D.

The detection voltage generating circuit 220 of the master driving circuit M20 turns on only the switch SFB1 when the feedback voltage FB1 is determined as the first minimum feedback voltage and the other switches SFB2 to SFB8 Turn off. As a result, the feedback voltage FB1 determined as the first minimum feedback voltage can be transmitted to the output terminal of the detection voltage generating circuit 220 of the master driving circuit M20.

As described above, the detection voltage generating circuit 220 of the master driving circuit M20 and the slave driving circuit S20 can transmit the first minimum feedback voltage and the second minimum feedback voltage to the output stage, respectively.

The output terminals of the detection voltage generating circuit 220 of the master driving circuit M20 and the slave driving circuit S20 are electrically connected through the respective sharing terminals CON. Therefore, the first minimum feedback voltage and the second minimum feedback voltage, which are transmitted to the output terminals of the detection voltage generating circuit 220 of the master driving circuit M20 and the slave driving circuit S20, are shared.

As a result, the detection voltage generation circuit 220 of the master drive circuit M20 can output the detection voltage V _D generated by sharing the first minimum feedback voltage and the second minimum feedback voltage.

The master driving circuit M20 can generate the driving signal GATE as in the embodiment of Figs. 1 and 2 or the embodiment of Fig. 12 corresponding to the detection voltage V _D generated as described above, (GATE) to the converter 10 for power conversion.

The master driving circuit M20 and the slave driving circuit S20 of the slave driving circuit S20 constitute the feedback voltages of the LED channels CH1 to CH8 of the LED lamp S50 FB1 to FB8 and a linear regulator for the LED channels CH1 to CH8 of the LED lamp S50. In this case, the master driving circuit M20 may be referred to as a first circuit, and the slave driving circuit S20 may be referred to as a second circuit.

As described above, the driving circuits of the present invention can be configured as multi-chips corresponding to a large number of LED channels. Therefore, it shares the lowest feedback voltage for the LED channels corresponding to each of the driving circuits, detects the lowest feedback voltage for all the LED channels, and uses the lowest feedback voltage for all the LED channels, To control the output voltage provided to the channels.

As a result, components such as a converter can be shared, and the number of parts and manufacturing cost can be reduced.

The present invention can be implemented in order to secure an effective duty of the driving signal for controlling the dimming irrespective of the switching frequency of the converter 10. [ To this end, a sixth embodiment for ensuring the minimum on-time of the converter 10 regardless of the switching frequency of the converter 10 may be configured as shown in Figs. In addition, a seventh embodiment for assuring the minimum off-time of the converter 10 regardless of the switching frequency of the converter 10 may be configured as shown in Figs. 20 to 22. Fig.

First, a sixth embodiment will be described in detail with reference to FIGS. 17 to 19. FIG.

The driving signal GATE in the driving circuit 20 can be generated using the PWM signal of the oscillator 330. [ The generation of the driving signal GATE by using the PWM signal can be understood by the above description with reference to FIG. 2, and a description thereof will be omitted. Hereinafter, the PWM signal of the oscillator 330 is described as an oscillation signal.

The switching frequency of the converter 10 can be determined by the driving signal GATE and the driving circuit 20 provides the driving signal GATE to the converter 10 that can guarantee the minimum ON time of the converter 10 do.

To this end, the driving circuit 20 includes a constant current supply unit 80, a control current supply unit 82, a charging device CN, a switch SWT, a comparator 86, a NAND gate 88 and an inverter IV1).

The constant current supply part 80 is for providing a constant current by the constant voltage VDD to the charging element CN. To this end, the constant current supply unit 80 copies the currents flowing in the series-connected PMOS transistors MS1 and MS2 to the PMOS transistors MS3 and MS4 by mirroring and supplies the currents flowing through the PMOS transistors MS3 and MS4 And is configured to provide a current to the charging element CN.

The control current supply unit 82, the charging element CN, and the switch SWT are included in the control voltage generating circuit described later.

The control current supply unit 82 is configured to provide a control current to the charge element CN using the oscillator current iosc generated by the oscillation signal output from the oscillator 330. [ To this end, the control current supply unit 82 is controlled such that the current corresponding to the oscillator current iosc flows and the currents flowing in the PMOS transistors MC1 and MC2 and the PMOS transistors MC1 and MC2 connected in series are copied by mirroring And includes PMOS transistors MC3 and MC4 connected in series. Here, the current flowing through the PMOS transistors MC3 and MC4 is provided to the charging element CN.

The oscillator current (iosc) can be varied in proportion to the frequency change of the oscillating signal. Therefore, the control current supply section 82 can be changed in accordance with the frequency change of the transfer oscillation signal of the control current supplied to the charge element CN.

More specifically, when the frequency of the oscillation signal is high, the amount of the oscillator current iosc is increased and the amount of the control current of the control current supply section 82 is also increased. Conversely, when the frequency of the oscillation signal is low, the amount of the oscillator current iosc is reduced, and the amount of the control current of the control current supply portion 82 is also reduced.

The switch SWT is connected in parallel to the charging element CN and blocks the supply of current to the charging element CN when turned on. That is, it is regulated by the switch SWT to supply current to the charging element CN. The switch SWT is switched by the drive signal GATE inverted input through the inverter IV1. That is, the switch SWT is turned off during the turn-on period of the converter 10, and turned on during the turn-off period of the converter 10. [ Accordingly, the charging element CN is charged during the turn-on period of the converter 10, and discharged during the turn-off period of the converter 10. [

The charging device CN can perform charging by the current supplied from the constant current supply part 80 and the control current supply part 82 and generate the control voltage. Particularly, the charging device CN generates the control voltage by the control current of the control current supply part 82 whose amount is changed in proportion to the frequency change of the oscillation signal, .

More specifically, when the frequency of the oscillation signal is high, the amount of the control current of the control current supply section 82 is increased, and the speed at which the control voltage is charged into the charging element CN is fast. Conversely, when the frequency of the oscillation signal is low, the amount of the control current of the control current supply section 82 is reduced, and the control voltage is charged to the charging element CN at a slow rate.

The comparator 86 compares the control voltage of the charge element CN applied to the positive terminal (+) with the reference voltage VREF applied to the negative terminal (-) and outputs the control pulse VA as shown in Fig. 18 . More specifically, the comparator 86 outputs a control pulse VA that transitions to a high level when the control voltage reaches the reference voltage VREF and maintains the transition state while the control voltage maintains the reference voltage VREF or higher do. The comparator 86 performing the above operation corresponds to a control pulse generating circuit described later.

When the frequency of the oscillation signal is high and the control voltage of the capacitor CN is quickly charged, the comparator 86 outputs a control pulse VA having a high level transition timing. On the contrary, when the frequency of the oscillation signal is low and the control voltage of the capacitor CN is charged so as to be increased, the comparator 86 outputs the control pulse VA whose level transition timing is late.

The NAND gate 88 combines the control pulse VA and the inverted drive signal GATE in NAND and outputs the minimum ON time pulse ON_MIN as shown in FIG. The inverted drive signal (GATE) is used to determine the turn-on period of the converter (10).

That is, the NAND gate 88 defines the minimum ON time including the end time of the minimum ON time from the start time of the turn on of the converter 10 using the control pulse VA in the turn ON period of the converter 10 And generates a minimum ON time pulse (ON_MIN). The NAND gate 88 performing the above operation corresponds to a minimum ON time determination unit described later.

When the frequency of the oscillation signal is high and the comparator 86 outputs a control pulse VA having a high level transition timing, the end time of the minimum ON time is advanced. As a result, the NAND gate 88 is turned on, And outputs a time pulse ON_MIN. Conversely, when the frequency of the oscillation signal is low and the comparator 86 outputs a control pulse VA having a low level transition timing, the end point of the minimum ON time is slowed. As a result, the NAND gate 88 has a pulse width of And outputs a wide minimum ON time pulse (ON_MIN).

That is, in the embodiment of FIG. 17, the width of the minimum ON time pulse ON_MIN can be adjusted corresponding to the frequency change of the oscillation signal as shown in FIG. The width of the minimum ON time pulse ON_MIN means the minimum ON time that can be guaranteed for the turn on of the converter 10. [ That is, the minimum on-time for turning on the converter 10 in response to the frequency change of the oscillation signal may be changed.

Therefore, the embodiment of FIGS. 17 to 19 can ensure an effective duty to control the dimming irrespective of the switching frequency of the converter 10. FIG.

The embodiment of FIG. 17 described above can be described as including a termination time generation unit and a minimum ON time determination unit.

The end point generation section generates a control pulse VA representing the end point of the minimum ON time following the frequency change of the oscillation signal by using the oscillation signal used for generation of the drive signal GATE in the turn- .

The end point generation section can be described as including a control voltage generation circuit and a control pulse generation circuit.

Here, the control voltage generating circuit is configured to generate a control voltage whose increase time varies according to the frequency change of the oscillation signal by using the oscillation signal used for generation of the drive signal GATE in the turn-on period of the converter 10 do. The control pulse generating circuit corresponds to the above-described comparator 86,

The control voltage generating circuit may include a control current supply unit 82, a charging device CN, and a switch SWT.

The seventh embodiment will be described in detail with reference to FIGS. 20 to 22. FIG.

The embodiment of Fig. 20 is for ensuring the minimum off time of the converter 10 regardless of the switching frequency of the converter 10 and the driving circuit 20 is for driving the inverter 10 to ensure the minimum off- And provides the signal (GATE) to the converter (10).

To this end, the driving circuit 20 includes a constant current supply unit 80, a control current supply unit 82, a charging device CN, a switch SWT, a comparator 86, an AND gate 89 and an inverter IV2).

Compared with the embodiment of Fig. 17, the embodiment of Fig. 20 differs from the configuration of the AND gate 89 and the inverter IV2 in that the charging capacity of the charging element CN is different. The remaining components in FIG. 20 are the same as those in FIG. 17, so duplicate descriptions are omitted.

In Fig. 20, the switch SWT is switched by the non-inverted input drive signal GATE. That is, the switch SWT is turned off during the turn-off period of the converter 10, and is turned on during the turn-on period of the converter 10. [ Accordingly, the charging element CN is charged during the turn-off period of the converter 10, and discharged during the turn-on period of the converter 10. [

The charging element CN may be configured to have a charging capacity larger than that of Fig.

The comparator 86 outputs a control pulse VA as shown in Fig. More specifically, the embodiment of Fig. 20 is slower than the embodiment of Fig. 17 due to the difference in the charging capacity of the charging element CN when the control voltage reaches the reference voltage VREF. Therefore, the control pulse VA output from the comparator 86 is delayed for a certain time after the start of the turn-off interval of the converter 10, and the transition level is maintained until the turn-on interval of the converter 10 is started . The comparator 86 outputs a control pulse VA that maintains the transition state while the control voltage maintains the reference voltage VREF or more.

The AND gate 89 ANDs the control pulse VA and the inverted drive signal GATE to output the minimum OFF time pulse OFF_MIN as shown in FIG. The inverted drive signal (GATE) is used to determine the turn-off interval of the converter (10).

That is, the AND gate 88 uses the control pulse VA to set the minimum OFF time including the turn-off end point of the converter 10 from the start point of the minimum OFF time in the turn-off interval of the converter 10 (OFF_MIN) which defines the minimum off-time pulse. The AND gate 89 that performs the above operation corresponds to a minimum OFF time determination unit described later.

When the frequency of the oscillation signal is high and the comparator 86 outputs a control pulse VA having a high level transition timing, the start time of the minimum off time becomes fast. As a result, And outputs a time pulse OFF_MIN. On the other hand, when the frequency of the oscillation signal is low and the comparator 86 outputs the control pulse VA having a low level transition timing, the start point of the minimum off time is slowed. As a result, the AND gate 89 has a pulse width And outputs a narrow minimum OFF time pulse (OFF_MIN).

That is, in the embodiment of FIG. 20, the width of the minimum OFF time pulse OFF_MIN can be adjusted in response to the frequency change of the oscillation signal as shown in FIG. The width of the minimum off-time pulse (OFF_MIN) means the minimum off-time that can be guaranteed for the turn-off of the converter 10. [ That is, the minimum off time for turning off the converter 10 in response to the frequency change of the oscillation signal can be changed.

Therefore, the embodiment of FIGS. 20 to 22 can ensure an effective duty of the driving signal GATE for controlling dimming irrespective of the switching frequency of the converter 10. FIG.

The above-described embodiment of FIG. 20 can be described as including a start point generating unit and a minimum off time determining unit.

The start point generating unit generates a control pulse VA (n) representing the start point of the minimum off time following the frequency change of the oscillation signal by using the oscillation signal used for generation of the drive signal GATE in the turn- ).

The start point generating section can be described as including a control voltage generating circuit and a control pulse generating circuit.

Here, in the turn-off period of the converter 10, the control voltage generating circuit generates the control voltage whose increase time varies with the frequency change of the oscillation signal by using the oscillation signal used for generation of the drive signal GATE . The control pulse generating circuit corresponds to the above-described comparator 86,

The control voltage generating circuit described above may include a control current supply unit 82, a charging device CN, and a switch SWT.

On the other hand, the present invention can be implemented by applying the embodiment of Fig. 17 and the embodiment of Fig. 20 to the driving circuit 20 in the same manner. In this case, the minimum on-time of the turn-on interval and the minimum off-time of the turn-off interval of the converter 10 can be ensured simultaneously regardless of the switching frequency.

Claims (12)

A lighting device for providing an output voltage to lighting loads,
A converter for providing the output voltage to the loads by driving a switching element using a driving signal; And
A drive circuit for generating a control voltage at a level corresponding to a load change of the loads at a time of a load change and providing the drive signal having an on time adjusted to correspond to the control voltage at the load change time; And a light source. The method according to claim 1,
Wherein the drive circuit provides the drive signal whose duty is controlled to have the ON time corresponding to the load change at the time of the load change. The method according to claim 1,
Wherein the driving circuit determines the load change time point by using a load current control voltage of a load current control resistor acting on the entire loads. The driving circuit according to claim 1,
A control voltage providing circuit for providing the control voltage at a predetermined level corresponding to a digital value provided as a preset value for each load change time point; And
And a pulse generator for generating and supplying the drive signal whose on-time is adjusted in accordance with the control voltage. 5. The method of claim 4,
The driving circuit further includes a load change detecting circuit,
Wherein the load change detection circuit detects a change time point of a load current control voltage of a load current control resistor acting on the entire loads as the load change time point and provides the digital value to the control voltage supply circuit Lt; / RTI > The driving circuit according to claim 4,
A detection voltage generation circuit for providing a minimum voltage among the feedback voltages applied to the linear regulators configured in the loads as a detection voltage;
A first comparator for providing a compensation voltage comparing the detection voltage and the reference voltage; And
Further comprising: a summer for generating a regulated voltage that is a sum of the compensation voltage and the control voltage,
Wherein the pulse generator generates and provides the driving signal using the adjustment voltage corresponding to the control voltage. The method according to claim 6,
Wherein the driving circuit further includes a second comparator for generating a comparison voltage that is a sum of a slope compensation voltage for compensating for the slope of the driving signal and a sensing signal for sensing the input voltage and for comparing the adjustment voltage and the comparison voltage,
Wherein the pulse generator generates and provides the driving signal by an output of a second comparator generated using the regulated voltage. A driving circuit of an illumination apparatus for providing the driving signal to a converter that provides an output voltage to lighting loads by driving a switching element using a driving signal,
A control voltage providing circuit for providing a control voltage corresponding to a change in the load of the loads at the time of changing the load of the loads; And
And a drive signal providing circuit for providing the drive signal compensated for the load change of the loads at the time of the load change by controlling an on time of the drive signal in response to the control voltage Of the lighting device. 9. The method of claim 8,
Further comprising a load change detection circuit for determining the load change time point using a load current control voltage of a load current control resistor acting on the entire loads and providing a digital value preset for each load change time point,
And the control voltage providing circuit provides the control voltage at a predetermined level corresponding to the digital value at the time of changing the load of the loads. 9. The method of claim 8,
And the driving signal providing circuit generates and supplies the driving signal whose on-time is adjusted in accordance with the control voltage. 11. The driving circuit according to claim 10,
A detection voltage generating circuit for providing a minimum voltage among the feedback voltages applied to the linear regulators configured corresponding to the loads as a detection voltage; And
A comparator for providing a compensation voltage comparing the detection voltage and a reference voltage; And
And an adder for adding the compensation voltage and the control voltage to generate a regulated voltage,
Wherein the pulse generator provides the driving signal in response to the control voltage to which the control voltage is reflected. 12. The method of claim 11,
Wherein the drive signal providing circuit provides the drive signal so that the drive signal has the on time changed by comparing the adjustment voltage with a comparison voltage reflecting at least the slope compensation voltage for compensating the slope of the drive signal.

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