KR102383271B1 - Lamp apparatus and driving circuit for the lamp apparatus - Google Patents

Abstract

The present invention discloses a lighting device that can be used as a lighting lamp, wherein the lighting device includes a drive circuit for controlling power conversion of a converter that provides an output voltage to an LED lamp including a plurality of LED channels, the drive circuit includes a reference voltage generation circuit that generates a reference voltage whose level increases when at least one of the feedback voltages corresponding to the bias voltage of each LED channel is equal to or less than an internal reference voltage having a preset value, and using the reference voltage The output voltage is regulated by controlling the converter's power conversion.

Description

LAMP APPARATUS AND DRIVING CIRCUIT FOR THE LAMP APPARATUS

The present invention relates to a lighting device, and more particularly, to a lighting device that can be used as a lighting lamp, such as a rear combination lamp of a vehicle, and a driving circuit of the lighting device.

In general, a vehicle is provided with lighting devices for various purposes indoors or outdoors. As an example of the lighting device, a rear combination lamp installed at both rear sides of the vehicle may be exemplified.

The rear combination lamp includes a direction indicator lamp, a brake lamp, a tail lamp, a reverse lamp, and the like, and is used as a means to notify the driver of another vehicle located at the rear of the vehicle's intention or driving condition.

Recently, a lighting device using a high-brightness LED (Light Emitted Diode) has been developed, and a rear combination lamp employing the LED as a lighting device for a vehicle is being developed. As the LED is used as a light source, the rear combination lamp is changed into various designs, and the number of LEDs used in the rear combination lamp is gradually increasing according to the design change.

A lighting device such as the above-described rear combination lamp needs to be operated stably, can save power, and needs to be developed to be implemented with a small number of parts.

A lighting device using LEDs may be configured to provide an output voltage to a plurality of LED channels. When the number of emitting LED channels is changed, a load amount change may occur in the lighting device, and the output voltage of the lighting device provided to the LED channels may be temporarily unstable at the time when the load amount change occurs.

In response to the change in the output voltage, the lighting device may compensate the change in the output voltage according to the change in the load amount and stabilize the output voltage by compensating the output voltage using the feedback voltage and linear regulation using the sensing signal.

However, a general lighting device takes a lot of time to compensate and stabilize the output voltage in response to the change in the load amount. When it takes a lot of time to stabilize the output voltage, the change in the output voltage may affect the illuminance.

Therefore, it is necessary to improve the lighting device using the LED so that the output voltage can be stabilized even when the amount of load is changed.

In addition, the lighting device performs power conversion using a converter including a switching element, and provides an output voltage generated as a result of power conversion. The converter of the lighting device may be configured as, for example, a buck converter.

The converter consumes a lot of power at the time of switching for power conversion, and thus EMI (Electro Magnetic Interference) may occur. EMI generated from the above converter may affect the operation of the lighting device, so it should be reduced. Therefore, there is a need to develop a driving technology for a converter in which EMI can be reduced.

Also, when the duty of a driving signal driving the converter to provide an output voltage is 50% or more, unstable sub-harmonic oscillation may occur in the converter of the lighting device. The unstable sub-harmony oscillation may act as a factor destabilizing the operation of the lighting device.

The unstable sub-harmony oscillation of the converter may be controlled by compensating for a SLOP of a driving signal driving the converter. The slope compensation of the driving signal means controlling the slopes of the rising edge and the falling edge of the driving signal, and the slope compensation is implemented by a slope compensation voltage charged with a fixed current.

In the buck converter, the variable range of the switching frequency may be set to be large, for example, the variable range may be set from 100KHz to 1MHz. The switching frequency of the buck converter may be determined by a driving signal provided from a driving circuit. If the variable range of the switching frequency is large, the value of the inductance of the buck converter must also be set to match the variable switching frequency. However, when the value of the inductance of the buck converter is changed, the value of the slope compensation voltage for controlling the sub-harmony oscillation must be changed.

In general, the value of the slope compensation voltage is provided based on the fixed current as described above. Therefore, the driving circuit needs to externally receive a voltage or current for changing the slope compensation voltage in accordance with the variable switching frequency, and a connection terminal for receiving the external current or voltage is additionally required for the driving circuit. can In addition, in order to generate a voltage or current for changing the slope compensation voltage, there is a problem in that an additional circuit including many components is required.

In addition, as described above, the LED channels of the lighting device are configured to emit light at different times in order to concentrate power and thereby eliminate EMI. In addition, it should be ensured that the LED current of each LED channel is maintained over a certain amount for normal light emission.

In order to ensure that the LED current of each LED channel is maintained over a certain amount, the lighting device detects the lowest voltage among the feedback voltages of each LED channel as a detection voltage, compares the detection voltage with a reference voltage of a fixed level, The output voltage can be controlled based on the comparison result. As described above, a technique for controlling the output voltage of a lighting device has been disclosed in Korean Patent Registration No. 10-0941509.

The bias voltages of the LED channels may vary depending on the characteristic deviation. For example, when the bias voltages of the LED channels are all different, the lowest feedback voltage of the LED channels may be changed each time the LED channels emit light.

Therefore, the level of the output voltage generated by the converter may be changed at any time. When the output voltage is unstable as described above, audible noise corresponding to the change in the output change may be generated in the converter.

In addition, when a large number of LED channels are configured in the lighting device, it is difficult to cover all the LED channels with one driving circuit. Therefore, in order to control the light emission of a large number of LED channels, it is necessary to configure a plurality of driving circuits. In this case, the driving circuits may be implemented as a multi-chip.

When the driving circuits are implemented as a multi-chip, there is a need to reduce the number of parts and the manufacturing cost by sharing parts such as a converter.

As described above, when the driving circuits are configured with a multi-chip in response to a large number of LED channels, a lighting device capable of sharing parts such as a converter is proposed in order to solve the need to reduce the number of parts and the manufacturing cost. is required

In addition, the converter switched by the driving signal must ensure a minimum on time and a minimum off time. The minimum on time means the shortest time during which the switch of the converter can be turned on, and the minimum off time means the shortest time during which the switch of the converter can be turned off. In general, the minimum on time for turning on the converter and the minimum off time for turning off the converter are fixed.

However, when the switching frequency of the converter is changed, it may be difficult to secure an effective duty of a driving signal for controlling dimming due to the fixed minimum on-time. More specifically, as the switching frequency of the converter increases, the fixed minimum on-time gradually occupies a large portion of the turn-on period of the converter. As a result, it becomes increasingly difficult to sufficiently secure the duty of the driving signal to be used for dimming.

In addition, when the switching frequency of the converter is changed, it may be difficult to secure an effective duty of a driving signal for controlling dimming due to a fixed minimum off time. More specifically, as the switching frequency of the converter increases, the minimum off time gradually occupies a large portion within one period of the driving signal. As a result, it becomes increasingly difficult to sufficiently secure the duty of the driving signal to be used for dimming.

Therefore, it is necessary to propose a method capable of securing an effective duty of a driving signal for controlling dimming of an LED lamp regardless of a change in the switching frequency of the converter.

An object of the present invention is to stably maintain an output voltage provided to loads in response to a change in the load amount of lighting loads such as LEDs for stable operation of a lighting device.

The present invention quickly compensates the on time of a driving signal for generating an output voltage to a preset value at a time when the load amount of the lighting loads included in the lighting device changes to a preset value, thereby stabilizing the output voltage in a fast time and stabilizing it in response to the change in the load amount. for other purposes.

Another object of the present invention is to reduce EMI generated in a power conversion process for generating an output voltage to be provided to lighting loads of a lighting device.

The present invention disperses the switching timing of the converter by controlling a driving signal provided for power conversion of a converter in a lighting device to have a distributed frequency to which a distributed spectrum is applied, and solves the problem of concentrating power consumption at the switching timing of the converter, and EMI Another purpose is to reduce

Another object of the present invention is to provide a slope compensation voltage in response to a change in a switching frequency for power conversion of a converter in a lighting device, thereby controlling subharmony oscillation that may occur according to a duty state of an output voltage. .

In the present invention, when a switching frequency for power conversion of a converter in a lighting device is varied, the switching frequency is linked to a change in current or voltage corresponding to a change in the switching frequency of an oscillation circuit that provides a PWM signal used to generate a driving signal. Another object of the present invention is to provide a slope compensation voltage corresponding to the variation of .

The present invention is such that a configuration for actively responding to a switching frequency variation for power conversion of a converter in a lighting device can be implemented simply by an interlocking structure inside a driving circuit composed of a chip without the need to configure separate terminals or components. serve another purpose.

The present invention raises the reference voltage when the feedback voltage of the minimum level among the feedback voltages corresponding to the bias voltages of each LED channel falls below a preset level, and the output voltage generated by the converter using the raised reference voltage. Another purpose is to stabilize

The present invention generates a reference voltage by charging/discharging according to the feedback voltage of the minimum level among the feedback voltages corresponding to the bias voltages of each LED channel, and regulating the output voltage using the charging/discharging reference voltage, thereby generating in the converter. It has another purpose to stabilize the output voltage.

Another object of the present invention is to solve the audible noise that may be generated in the converter due to the unstable output voltage by controlling the output voltage from being unstable due to the difference in the bias voltage of each LED channel.

Another object of the present invention is to reduce the number of parts and manufacturing cost by sharing parts such as a converter when a plurality of driving circuits are configured to correspond to a large number of LED channels.

Another object of the present invention is to drive the LED channels using one converter when a plurality of driving circuits are configured to correspond to a large number of LED channels.

In the present invention, when a plurality of driving circuits are configured to correspond to a large number of LED channels, the lowest feedback voltage for LED channels corresponding to each driving circuit is shared, and the lowest feedback voltage for all LED channels. , and controlling the output voltage provided to the LED channels using the lowest feedback voltage for all LED channels.

Another object of the present invention is to secure an effective duty of a driving signal for controlling dimming of an LED lamp even when a switching frequency of a converter is changed.

Another object of the present invention is to secure an effective duty of a driving signal for dimming control regardless of a change in the switching frequency of the converter by changing the minimum on time in response to a change in the switching frequency of the converter.

Another object of the present invention is to secure an effective duty of a driving signal for dimming control regardless of a change in the switching frequency of the converter by changing the minimum off time in response to a change in the switching frequency of the converter.

A driving circuit of a lighting device for controlling power conversion of a converter that provides an output voltage to an LED lamp including a plurality of LED channels of the present invention, at least one of the feedback voltages corresponding to the bias voltage of each LED channel is preset and a reference voltage generation circuit that generates a reference voltage whose level increases when the value is less than or equal to an internal reference voltage, and performs regulation on the output voltage by controlling power conversion of the converter using the reference voltage do it with

A driving circuit of a lighting device for controlling power conversion of a converter that provides an output voltage to an LED lamp including a plurality of LED channels of the present invention receives feedback voltages corresponding to bias voltages of each LED channel, and the feedback a detection voltage generating circuit that provides a feedback voltage of a minimum level among voltages as a detection voltage; a reference voltage generating circuit that generates a reference voltage whose level increases when the detected voltage is equal to or less than an internal reference voltage having a preset value; a comparator comparing the reference voltage and an output sensing signal sensing the output voltage and generating a compensation voltage corresponding to the comparison result; and a pulse generator that provides a driving signal to the converter in response to the compensation voltage, wherein the output voltage is regulated by using the reference voltage.

The present invention provides an output voltage to the lighting loads using the LED, and has an effect of stably maintaining the output voltage by quickly performing compensation in response to a change in the load amount of the loads.

In addition, the present invention provides an output voltage to the lighting loads by power conversion using a driving signal, and quickly compensates the on-time of the driving signal to a preset value in response to a change in the load amount of the loads, thereby stabilizing the output voltage in a quick time and to keep it stable.

According to the present invention, power conversion for providing an output voltage can be performed using a driving signal having a dispersed frequency, and the switching time of the converter for power conversion is dispersed by the dispersed frequency of the driving signal and reduced power consumption. Concentration can be alleviated, and there is an effect that EMI can be reduced.

According to the present invention, sub-harmony oscillation that may occur depending on the state of the voltage output from the converter of the lighting device can be controlled, and the slope compensation voltage that is actively changed even when the switching frequency for power conversion of the converter is changed can be provided so that the sub-harmony oscillation can be effectively controlled.

According to the present invention, since the configuration of the driving circuit for actively responding to the switching frequency variation for power conversion of the converter of the lighting device can be simply implemented by the internal interlocking structure, the number of parts and the manufacturing cost can be reduced. .

According to the present invention, by changing the reference voltage according to the change of the minimum level of the feedback voltage, the output voltage generated by the converter can be stabilized using the changed reference voltage, and the audible noise caused by the unstable output voltage can be eliminated. .

According to the present invention, it is possible to stabilize the output voltage generated by the converter by generating a reference voltage by charging and discharging according to a change in the minimum level of the feedback voltage and regulating the output voltage using the reference voltage generated by charging and discharging. and can eliminate audible noise caused by unstable output voltage.

According to the present invention, a plurality of driving circuits may be configured to correspond to a large number of LED channels in the driving circuits, and parts such as a converter may be shared, thereby reducing the number of parts and manufacturing cost.

According to the present invention, it is possible to drive the LED channels by using a single converter to correspond to a large number of LED channels, thereby reducing the number of parts and manufacturing cost.

According to the present invention, share the lowest feedback voltage for LED channels corresponding to each driving circuit, detect the lowest feedback voltage for all LED channels, and determine the lowest feedback voltage for all LED channels It can be used to control the output voltage provided to the LED channels.

According to the present invention, even if the switching frequency of the converter is changed, the corrected minimum on time or the corrected minimum off time can be applied, so that an effective duty for controlling the dimming of the LED lamp can be secured.

According to the present invention, since the minimum on time is corrected in response to a change in the switching frequency of the converter, it is possible to switch the converter while ensuring effective duty even when the switching frequency of the converter is changed.

According to the present invention, since the minimum off time is corrected in response to a change in the switching frequency of the converter, it is possible to switch the converter while ensuring effective duty even when the switching frequency of the converter is changed.

1 is a view for explaining embodiments of a lighting device of the present invention.
Fig. 2 is a detailed circuit diagram corresponding to Fig. 1 for explaining the first embodiment of the present invention;
3 is a waveform diagram illustrating an operation of a general lighting device.
Fig. 4 is a waveform diagram for explaining the operation of the first embodiment of Fig. 2;
5 is a waveform diagram illustrating that the center frequency Fc of a driving signal is varied.
6 is a waveform diagram illustrating a bandwidth of a frequency-modulated waveform of a drive signal;
7 is a circuit diagram for explaining a second embodiment of the present invention;
8 is a timing diagram illustrating that a PWM signal is adjusted according to the embodiment of FIG. 7 .
9 is a waveform diagram illustrating a frequency dithered driving signal.
Fig. 10 is a circuit diagram for explaining a third embodiment of the present invention;
11 is a graph illustrating a slope compensation voltage according to the third embodiment.
12 is a circuit diagram for explaining a fourth embodiment of the present invention;
Fig. 13 is a circuit diagram illustrating the reference voltage generation circuit of Fig. 12;
FIG. 14 is a waveform diagram of voltages of the reference voltage generating circuit of FIG. 13;
Fig. 15 is a block diagram for explaining a fifth embodiment of the present invention;
FIG. 16 is a circuit diagram illustrating linear regulators and a detection voltage generating circuit of the master driving circuit and the slave driving circuit of FIG. 15;
Fig. 17 is a circuit diagram for explaining a sixth embodiment of the present invention;
Fig. 18 is a waveform diagram for explaining the operation of the embodiment of Fig. 17;
19 is a graph illustrating a frequency change versus a minimum ON time according to the embodiment of FIG. 17 .
Fig. 20 is a circuit diagram for explaining a seventh embodiment of the present invention;
Fig. 21 is a waveform diagram for explaining the operation of the embodiment of Fig. 20;
22 is a graph illustrating a frequency change versus a minimum off time according to the embodiment of FIG. 20 .

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The terms used in the present specification and claims are not limited to a conventional or dictionary meaning, and should be interpreted in a meaning and concept consistent with the technical matters of the present invention.

The embodiments described in this specification and the configurations shown in the drawings are preferred embodiments of the present invention, and do not represent all of the technical spirit of the present invention, so various equivalents and modifications that can replace them at the time of the present application there may be

1 is a view for explaining embodiments of the present invention. Referring to FIG. 1 , the lighting device includes a converter 10 and a driving circuit 20 . In addition, the lighting device may include a vehicle control unit 30 , a path unit 40 , and an LED lamp 50 . In the above configuration, the driving circuit 20 may be implemented as a one-chip.

The LED lamp 50 may be configured for a vehicle, and as a specific example, a rear combination lamp installed on both sides of the rear of the vehicle may be applied. The above-described LED lamp 50 is an example of a light source used as a load, and a light source using various optical devices may be used as a load.

The LED lamp 50 includes a plurality of LED channels (CH1 to CH8), each LED channel (CH1 to CH8) includes one or more LEDs, and a plurality of LED channels (CH1 to CH8) can be configured in parallel. there is.

1 illustrates that one driving circuit 20 drives a plurality of LED channels CH1 to CH8 included in the LED lamp 50 . When the LED lamp 50 is a rear combination lamp, it may be divided into a type in which the LED channels are configured only on the vehicle body and a type in which the LED channels are dispersed in the door of the vehicle body and the trunk depending on the vehicle model. The LED lamp 50 of FIG. 1 is not limited to a specific type and may be defined as including LED channels configured in various types. The current of each LED channel (CH1~CH8) is indicated as “ICH1~ICH8”.

The vehicle control unit 30 may be configured to include a micro controller unit (MCU) 32 , and the MCU 32 performs a main MCU providing various control signals necessary for driving the vehicle or some functions required for driving the vehicle. In order to do this, it can be understood as an auxiliary MCU that provides an auxiliary control signal in conjunction with the main MCU.

The vehicle control unit 30 of FIG. 1 controls the battery voltage VB to be transmitted to the converter 10 in response to the direction indication signal T/S of the MCU 32, and controls the battery voltage VB in response to the sudden braking signal ESS. The voltage VB is controlled to be transmitted to the converter 10 and the driving circuit 20 . In this case, the battery voltage VB transmitted to the driving circuit 20 in response to the sudden braking signal ESS may be defined as a dim signal DIM. The direction indication signal T/S and the sudden braking signal ESS are examples of control signals provided from the MCU 32 . However, the present invention is not limited thereto, and may be configured to provide voltages corresponding to various control signals for driving the LED lamp 50 to at least one of the converter 10 and the driving circuit 20 according to the needs of the manufacturer. .

A path unit 40 may be configured between the vehicle control unit 30 , the converter 10 , and the driving circuit 20 . The path unit 40 includes paths D1 and D2 through which the battery voltage VB is transmitted to the converter 10 and a path D3 through which the dim signal DIM is transmitted to the driving circuit 20 . When the direction indication signal T/S is activated, the battery voltage VB is transmitted to the converter 10 through the path D1. And when the sudden braking signal ESS is activated, the battery voltage VB is transmitted to the converter 10 through the path D2. The battery voltage VB is transmitted as a dim signal DIM through the path D3 , and the activated dim signal DIM is input to the driving circuit 20 . For example, the path D3 may include a circuit outputting the dim signal DIM having a logic level corresponding to the battery voltage VB. The battery voltage VB transferred from the path unit 40 to the converter 10 may be defined as an input voltage.

The converter 10 generates an output voltage VOUT and an internal voltage VDIN by using the input voltage VIN, supplies the output voltage VOUT to the LED lamp 50, and supplies the internal voltage VDIN to the driving circuit (20) is supplied. As an example, the converter 10 may use various power conversion circuits such as a buck converter or a flyback converter.

The driving circuit 20 is configured to sense and control the converter 10 and the LED lamp 50 .

The driving circuit 20 may receive the internal voltage VDIN and the sensing signal SEN from the converter 10 , and may provide the driving signal GATE to the converter 10 . Here, the internal voltage VDIN is a voltage for the operation of the controller 20 , and the sensing signal SEN determines the level of the input voltage VIN or the operating state or output voltage VOUT state of the converter 10 . is a voltage for sensing directly or indirectly, and the driving signal GATE is a signal for use in a switching operation for power conversion of the converter 10 and may be provided as a pulse width modulation (PWM) signal. .

In addition, the driving circuit 20 includes feedback voltages FB1 to FB8 of the LED channels CH1 to CH8 of the LED lamp 50 and regulation resistors R1 to for linear regulation of the LED channels CH1 to CH8. Regulation voltages RCH1 to RCH8 applied to R8 and the bin voltage BIN applied to the bin resistor RBIN for controlling dimming of all LED channels CH1 to CH8 of the LED lamp 50 are can receive

Here, the bin resistor RBIN may be defined as a load current control resistor acting on all of the LED channels CH1 to CH8 as loads, and the bin voltage BIN applied to the bin resistor RBIN changes the load amount. It can be used to determine the timing and can be defined as the load current control voltage.

More specifically, each of the LED channels CH1 to CH8 may be configured to emit light at different times for load distribution, and the vacant voltage ( BIN) can be changed. The change times of the bin voltage BIN may be determined as load amount change times.

Illustratively, the bin voltage (BIN) of a state in which one LED channel emits light is higher than a state in which all of the LED channels are turned off, and the bin voltage (BIN) in a state in which two LED channels are emitted is higher than that in a state in which one LED channel is emitted. BIN) is high. The time point at which the bin voltage BIN is changed may be determined as the load amount change time point as described above.

As a result, the driving circuit 20 may determine a load amount change time point using the bin voltage BIN and generate a control voltage V _N corresponding to the load amount after the load amount change time point. The control voltage V _N may be generated corresponding to a preset value, and a detailed description thereof will be described later with reference to the control voltage providing circuit 230 .

According to the configuration of FIG. 1 described above, the converter 10 provides the output voltage VOUT to the LED channels CH1 to CH8, which are loads, using the driving signal GATE.

Hereinafter, detailed configurations of the converter 10 and the driving circuit 20 configured in the embodiment of the present invention will be described with reference to FIG. 2 .

The converter 10 includes a switching element Qb, an input voltage VIN is transferred to the switching element Qb through a resistor Rb, and the voltage across both ends of the resistor Rb is sensed by the amplifier 110 . and is configured to be output as a sensing signal SEN. The switching element Qb may be formed of an NMOS transistor, and an FET may be used. In addition, the inductor Lb and the capacitor Cb are connected in series to the switching element Qb, the diode Db is connected in parallel between the switching element Qb and the inductor L, and the diode Db is It is configured such that a current flows in a reverse direction to the current flow provided from the switching element Qb.

The converter 10 performs power conversion by periodic turn-on and turn-off of the switching element Qb, and the turn-on and turn-off of the switching element Qb may be determined by the driving signal GATE.

When the switching element Qb is turned on, a current loop including the switching element Qb, the inductor Lb, and the capacitor Cb is formed, and a current flows into the inductor Lb to accumulate energy, and the current is It flows in increasing numbers through the capacitor Cb. At this time, the LED channels CH1 to CH8, which are loads, are connected in parallel with the capacitor Cb and receive an increasing current like the capacitor Cb.

And, when the switching element Qb is turned off, a current loop including the diode Db, the inductor Lb, and the capacitor Cb is formed, and the inductor current, which is energy accumulated in the inductor Lb, is converted into a capacitor It is supplied as (Cb). At this time, the inductor current gradually decreases, and the LED channels CH1 to CH8 connected in parallel with the capacitor Cb are also supplied with the gradually decreasing current.

In the converter 10 described above, the voltage accumulated in the capacitor Cb and output is the output voltage VOUT, which is the same as the voltage applied to the LED channels LED1 to LED8.

On the other hand, the driving circuit 20 provides a control voltage V _N corresponding to the load amount changed for each load amount change time of the LED channels CH1 to CH8, and uses the control voltage V _N to provide the control voltage V _NC ) and provides the converter 10 with the driving signal GATE compensated for the load amount change by having an on time corresponding to the control voltage V _NC . In addition, the driving circuit 20 generates a detection voltage V _D corresponding to the minimum voltage among the feedback voltages FB1 to FB8 of the LED channels CH1 to CH8, and generates a detection voltage V _D corresponding to the detection voltage V D . A compensation voltage Vc may be generated. In addition, the driving circuit 20 may generate the control voltage V _N by adding the compensation voltage Vc to the control voltage V _N .

As described above, the feedback voltages FB1 to FB8 are voltages applied to the linear regulators 201 to 208 . The driving circuit 20 includes the linear regulators 201 to 208, and the LED channels CH1 to CH8 feedback to monitor whether the output voltage VOUT maintains more than the minimum voltage for normally maintaining the lighting. The voltages FB1 to FB8 are received, and the received feedback voltages FB1 to FB8 are provided to the detection voltage generating circuit 220 inside the driving circuit 20 .

The linear regulators 201 to 208 are respectively configured between the regulation resistors R1 to R8 and the LED channels CH1 to CH8. The linear regulator 201 includes a comparator 211 and an NMOS transistor M1. The comparator 211 compares the regulation voltage RCH1 applied to the regulation resistor R1 with a preset reference voltage VREF1, and the NMOS transistor M1 responds to the voltage output from the comparator 211 to the LED channel ( It controls the current flowing between LED1) and the regulation resistor (R1). The linear regulators 202 to 208 also include comparators 212 to 218 and NMOS transistors M2 to M8, respectively, like the linear regulator 201 .

The linear regulators 201 to 208 control the current flowing through the LED channels CH1 to CH8 in response to a result of comparing the regulation voltages RCH1 to RCH8 with the reference voltage VREF1, respectively. carry out Due to the linear regulation operation, the amount of current of the LED channels CH1 to CH8 may be limited by the reference voltage VREF1.

1 or 2, LED channels CH1 to CH8, linear regulators 201 to 208, comparators 211 to 218, NMOS transistors M1 to M8, regulation resistors R1 to R8, Some of the regulation voltages RVH1 to RCH8 and the feedback voltages FB1 to FB8 are omitted for simplicity.

The driving circuit 20 further includes a detection voltage generation circuit 220 , a control voltage providing circuit 230 , a load change detection circuit 232 , and a driving signal providing circuit as well as the above linear regulators 201 to 208 . .

The detection voltage generating circuit 220 detects a feedback voltage having a minimum value among the feedback voltages FB1 to FB8 and provides the feedback voltage having a minimum value as the detection voltage V _D .

The load amount change detection circuit 232 detects a load amount change timing using the bin voltage BIN. The load amount change detection circuit 232 not only detects the load amount change time point, but also provides the control voltage providing circuit 230 with a digital value N corresponding to the load amount after the bin voltage BIN is changed, that is, the load amount after the load amount change time point. can do.

The level of the bin voltage BIN may be changed when the number of emitting LED channels CH1 to CH8 is changed, that is, when the load amount is changed. For example, the load change detection circuit 232 may output a binary code “0000” when all of the LED channels CH1 to CH8 are extinguished, and a time point at which the number of the emitting LED channels CH1 to CH8 increases. can be output by increasing the digital value (N) expressed in binary code by 1 bit, and when the number of emitting LED channels (CH1 to CH8) decreases, the digital value (N) is decreased by 1 bit and output can do.

That is, when the number of emitting LED channels CH1 to CH8 increases, the digital value N is (0000) ₂ , (0001) ₂ , (0010) ₂ , (0011) ₂ , (0100) ₂ , ( 0101) ₂ , (0110) ₂ , (0111) ₂ , (1000) ₂ may be sequentially increased and output. Conversely, when the number of emitting LED channels CH1 to CH8 decreases, the digital value N is (1000) ₂ , (0111) ₂ , (0110) ₂ , (0101) ₂ , (0100) ₂ , (0011) ₂ , (0010) ₂ , (0001) ₂ , (0000) ₂ may be sequentially reduced and output.

For example, when one of the LED channels CH1 to CH8 is changed from being extinguished to a state in which one is emitted, the load amount change detection circuit 232 detects a load amount change time by a change in the bin voltage BIN. . A digital value (N) corresponding to a state in which all of the LED channels (CH1 to CH8) are extinguished is (0000) ₂ , and a digital value (N) corresponding to a state in which one of the LED channels (CH1 to CH8) emits light. When this is (0001) ₂ , the load amount change detection circuit 232 changes the digital value N from (0000) ₂ to (0001) ₂ and outputs it.

The control voltage providing circuit 230 outputs a control voltage V _N corresponding to the digital value N, and when the digital value N increases, outputs an increased level of the control voltage V _N , When the value N is decreased, the control voltage V _N of the decreased level is output. For example, when the digital value N is (0001) ₂ than when the digital value N is (0000) ₂ , the control voltage providing circuit 230 outputs a higher level control voltage V _N . As described above, the control voltage V _N may be determined by the digital value N input to the control voltage providing circuit 230 , and the control voltage providing circuit 230 is a control voltage corresponding to the digital value N . A digital-to-analog converter that outputs (V _N ) may be configured as a Digital-Analog Converter.

Meanwhile, the driving signal providing circuit generates a compensation voltage Vc corresponding to the detection voltage V _D , and adds the control voltage V _N and the compensation voltage Vc to generate a control voltage V _NC , and adjusts It is configured to generate the driving signal GATE by using a result of comparing the voltage V _NC and the comparison voltage Vs as a reset signal. Here, the comparison voltage Vs is the sum of the sensing signal SEN provided from the converter 10 and the slope compensation voltage provided from the slope compensator 240 , and the driving signal GATE is the comparison signal Vs. Assuming that it has a fixed value, the On Time is determined in response to the control voltage V _NC .

To this end, the driving signal providing circuit may include a comparator 222 , an summer 234 , a slope compensator 240 , a summer 242 , a comparator 244 , and an SR latch 250 . Here, the SR latch 250 is configured as a pulse generator for generating a gate signal, and may be configured as an SR flip-flop.

The comparator 222 compares the detection voltage V _D0 output from the detection voltage generating circuit 220 with the reference voltage VREF2 having a preset level to output the compensation voltage Vc. In this case, the compensation voltage Vc may be stabilized by the capacitor Cd connected to the output terminal of the comparator 222 . And, in an embodiment of the present invention, the comparator 222 is configured such that the detection voltage V _D0 is applied to the negative terminal (-) and the reference voltage VREF2 is applied to the positive terminal (+).

The summer 234 generates a control voltage V _NC by adding the control voltage V _N provided from the control voltage providing circuit 230 and the compensation voltage Vc output from the comparator 222 to the control voltage V N , V _NC ) is output to the negative terminal (-) of the comparator 244 .

On the other hand, the embodiment of the present invention may include a slope compensator 240, and the slope compensator 240 compensates for the slope when it is necessary to adjust the slope of the rising edge of the driving signal GATE. output the slope compensation voltage for

The summer 242 sums the slope compensation voltage of the slope compensator 240 and the sensing signal SEN output from the converter 10 and outputs it as a comparison voltage Vs.

The comparator 244 outputs a result of comparing the comparison voltage Vs and the control voltage V _NC . In one embodiment of the present invention, the comparator 244 is configured such that the comparison voltage Vs is applied to the positive terminal (+) and the adjustment voltage V _NC is applied to the negative terminal (-). By the configuration of the comparator 244 and the summer 242 described above, the driving signal GATE may have a waveform reflecting the slope compensation voltage of the slope compensator 240 and the sensing signal SEN of the converter 10 . and the on time may be determined by the control voltage (V _NC ).

The SR latch 250 receives a PWM signal including a periodic pulse at a set terminal S and receives an output of the comparator 244 at a reset terminal R. The SR latch 250 outputs the driving signal GATE through the output terminal Q, and the driving signal GATE is applied to the gate of the switching element Qb. The PWM signal may be provided from an oscillator circuit such as an oscillator (not shown), and the oscillation circuit may be configured inside or outside the driving circuit 20 . Due to the configuration of the SR latch 250 described above, the output of the comparator 244 acts as a reset signal that determines the on time of the driving signal GATE. That is, the SR latch 250 has an ON time at which the driving signal GATE is output to the output terminal Q by reset by the output of the comparator 244 , and a periodic pulse is passed through the output terminal Q after the ON time point. A PWM signal including these is output as a driving signal GATE.

When the control voltage providing circuit 230 according to the embodiment of the present invention is not configured, the correlation between the output current IL, the output voltage VOUT, and the compensation voltage Vc may be described as shown in FIG. 3 . In FIG. 3 , Real Vc shows the change in the compensation voltage Vc, and Ideal Vc shows the ideal compensation voltage Vc corresponding to the changed load amount.

That is, when the number of LED channels emitting light from the LED lamp 50 increases, the output voltage VOUT temporarily decreases due to an increase in the load amount. When the output voltage VOUT decreases, the feedback voltages FB1 to FB8 also decrease, and the detection voltage V _D output from the detection voltage generating circuit 220 also decreases.

The comparator 222 outputs a compensation voltage Vc having a level increased in proportion to an increase in the difference between the reference voltage VREF2 and the detection voltage V _D , and is output from the SR latch 250 by the compensation voltage Vc. The on-time of the driving signal GATE becomes faster. When the on-time of the driving signal GATE is increased, the level of the output voltage VOUT output from the converter 10 increases.

When the compensation of the output voltage VOUT is performed as described above, the amount of decrease in the feedback voltages FB1 to FB8 and the detection voltage V _D is reduced, and the compensation voltage Vc is gradually increased, so that the output voltage VOUT is It may return to a normal level after a certain period of time.

Conversely, when the number of LED channels emitting light from the LED lamp 50 decreases, the output voltage VOUT temporarily increases due to a decrease in the load amount. The temporary increase of the output voltage VOUT due to the reduction in the load is gradually compensated because the compensation voltage Vc is gradually decreased by the increase of the feedback voltages FB1 to FB8 and the detection voltage V _D , and the output voltage ( VOUT) may return to a normal level.

However, since the compensation of the output voltage VOUT by the above-described compensation voltage Vc proceeds slowly in response to a change in the load amount, it is difficult to stably maintain the output voltage VOUT.

In addition, when the output voltage VOUT is severely low, it may be difficult to ensure a minimum voltage at which the LED channels CH1 to CH8 can stably maintain light emission, so that it may be difficult to maintain a stable lighting state.

According to the embodiment of the present invention, the output voltage VOUT can be stably maintained even when a load amount is changed by the operation of the control voltage providing circuit 230 . The output current IL according to the embodiment of the present invention described above. A correlation between the adjustment voltage V _NC , the compensation voltage Vc and the output voltage VOUT may be described as illustrated in FIG. 4 .

That is, when the number of LED channels emitting light from the LED lamp 50 increases, the load amount detection circuit 232 provides the control voltage providing circuit 230 with a digital value N corresponding to the increased load amount when the load amount changes. In addition, the control voltage providing circuit 230 provides the control voltage V _N having an increased level corresponding to the increased load amount from the time of the load amount change. Due to the change in the control voltage V _N , the control voltage V _Nc also rises from the load amount change time, and the SR latch 250 controls the output voltage VOUT from the load amount change time point by the adjustment voltage V _Nc . A driving signal GATE having a changed ON time point that can be stably maintained is output.

In addition, when the number of LED channels emitted from the LED lamp 50 decreases, the load amount detection circuit 232 provides the control voltage providing circuit 230 with a digital value N corresponding to the reduced load amount when the load amount changes. In addition, the control voltage providing circuit 230 provides the control voltage V _N having a lowered level corresponding to the reduced load amount from the load amount change time point. Due to the change of the control voltage V _N , the control voltage V _Nc also falls from the load amount change time point, and the SR latch 250 receives the output voltage VOUT from the load amount change time point by the adjustment voltage V _Nc . A driving signal GATE having a changed ON time point is output to be stably maintained.

The above-described compensation of the output voltage VOUT according to the embodiment of the present invention proceeds quickly in response to a change in the amount of load, so that the output voltage VOUT may be stably maintained. Meanwhile, as the output voltage VOUT is stably maintained, the feedback voltages FB1 to FB8 are also stabilized, and as a result, the compensation voltage Vc also has a waveform maintaining a constant level without change.

Therefore, according to the embodiment of the present invention, the output voltage VOUT can be stably maintained by quickly performing compensation corresponding to the change in the load amount of loads, and a good lighting state can be maintained.

In the above-described embodiment of the present invention, the driving signal GATE is generated using a PWM signal including a periodic pulse. When the driving signal GATE includes a pulse of a fixed frequency by the PWM signal of a constant frequency, the converter 10 of the lighting device may consume a lot of power at the switching time by the driving signal GATE and reduce EMI. can cause

In order to reduce the above EMI, the present invention discloses an embodiment in which the frequency of the PWM signal used to generate the driving signal GATE can be changed according to time by a spread spectrum method. According to the above-described embodiment of the present invention, the driving signal GATE may have a pulse of a dispersed frequency. By the pulse of the dispersed frequency of the driving signal GATE, the converter 10 can perform power conversion according to the distributed switching timing, and by the distributed switching timing, power consumption can be distributed and EMI can be reduced. there is.

The frequency of the PWM signal can be distributed using Carson's rule. 5 shows that the center frequency fc varies with time within a constant variable frequency Δf range according to Carson's law. 6 illustrates a bandwidth of a frequency-modulated waveform according to Carson's law, where the modulation frequency of the variable frequency ?f is denoted by "fm".

The spread spectrum can be implemented as “center frequency fc±variable frequency Δf” or “center frequency fc-variable frequency Δf”. An embodiment of the present invention may be implemented using “center frequency fc±variable frequency Δf”.

The variable frequency Δf may be exemplarily adjusted to a variable amount by non-dithering, 5%, 10%, 20%, or 30% using option information. Non-dithering means maintaining the original frequency, and the option information means setting to change the resistance value of the dithering resistor Rf, which will be described later.

The modulation frequency fm of the variable frequency Δf is a frequency changed by changing the frequency reference voltage FREF, and the frequency reference voltage FREF is exemplarily variable to 5 msec, 10 msec, or 40 msec using digital control. can do. The digital control means that the step control unit 304, which will be described later, is controlled by the dithering control signal DMOD.

By applying the above-described spread spectrum, the frequency of the pulse included in the driving signal FATE may be changed according to time. An embodiment for this may be exemplified as shown in FIG. 7 .

Referring to FIG. 7 , an embodiment of the present invention may include a dithering controller 300 , filters 310 and 320 , and an oscillator 330 .

The dithering control unit 300 exemplarily has a configuration for changing the frequency reference voltage FREF in 64 steps, and a dithering resistor Rf and a dithering control signal DMOD whose resistance value is changed according to option information. and a step control unit 304 for changing the frequency reference voltage. In addition, the dithering control unit 300 further includes a comparator 302 , a PMOS transistor Qp, and a resistor string.

First, the resistor string includes series-connected resistors Rd1 to Rd64 corresponding to 64 steps, respectively, and a dithering resistor Rf connected in series to the above-described resistors Rd1 to RD64. The dithering resistor Rf is positioned at an end of the resistor string to be grounded, and is preferably composed of a variable resistor whose resistance value can be changed in response to option information. The resistors Rd1 to Rd64 are divided into a lower resistance group Rd1 to Rd32 of 32 steps and an upper resistance group Rd33 to Rd64 of 32 steps.

The comparator 302 outputs a voltage corresponding to the result of comparing the voltages Vf1 and Vf2, and the PMOS transistor Qp is driven by the voltage output from the comparator 302, and a driving voltage VDD is applied to the resistor string. to convey Here, the voltage Vf1 input to the negative terminal (−) of the comparator 302 may be provided with a fixed level of voltage. In addition, the voltage Vf2 input to the positive terminal (+) of the comparator 302 may use a voltage applied to a node between the lower resistance group Rd1 to Rd32 and the upper resistance group Rd33 to Rd64 .

The step control unit 304 includes switches respectively connected in parallel to nodes between the resistors Rd1 to Rd64 of the resistor string. The switches of the step control unit 304 are configured with the same number as the resistors Rd1 to Rd64. Switches are individually controlled for switching by a dithering control signal DMOD having a digital value, and the dithering control signal DMOD has the number of bits that can be allocated by one bit for each switch.

In the step control unit 304, one end of the switches is respectively connected to the nodes between the resistors Rd1 to Rd64 of the resistor string as described above, and the other end of the switches is connected in common to output the frequency reference voltage FREF. An output terminal of the dithering control unit 300 is formed.

The dithering control unit 300 configured as described above may be understood as a digital-to-analog converter providing a frequency reference voltage FREF expressed as an analog value in response to the dithering control signal DMOD having a digital value.

The step controller 304 sequentially turns on the switches connected to the lower resistance groups Rd1 to Rd32, and as a result, the frequency reference voltage FREF rises stepwise from a low level to a high level. Thereafter, the step control unit 304 sequentially turns on the switches connected to the upper resistance groups Rd33 to Rd64, and as a result, the frequency reference voltage FREF is gradually decreased from a high level to a low level. Under the control of the step control unit 304, the frequency reference voltage FREF has a triangular waveform in which a rising section of 32 steps and a falling section of 32 steps are formed.

The period of the frequency reference voltage FREF may be controlled by adjusting the switching period of 64 steps of the step control unit 304 . That is, if the period in which the dithering control signal DMOD is provided is changed, the period of the frequency reference voltage FREF may be changed in response thereto. In the embodiment of the present invention, the frequency reference voltage FREF is changed in units of each period. It can be configured to change the period.

In addition, the period of the frequency reference voltage FREF may be controlled by adjusting the voltage change width for each step. The voltage change width for each step may be adjusted in response to option information provided to the dithering resistor Rf.

The sum of the height change of each step according to the change in the resistance value of the dithering resistor Rf is expressed as the height change of the triangular waveform of the frequency reference voltage FREF. Therefore, the height of the triangular waveform of the frequency reference voltage FREF may be controlled by the resistance value of the dithering resistor Rf, which is varied by option information.

More specifically, when the height of the triangular waveform of the frequency reference voltage VREF increases, it takes more time for the frequency reference voltage FREF to rise from the lowest level to the highest level and to fall from the highest level to the lowest level. That is, the period of the frequency reference voltage FREF may be long. Conversely, when the height of the triangular waveform of the frequency reference voltage VREF decreases, the time for the frequency reference voltage FREF to rise from the lowest level to the highest level and the time for the frequency reference voltage FREF to fall from the highest level to the lowest level are reduced. That is, the period of the frequency reference voltage FREF may be shortened.

The step control unit 304 configured in the embodiment of the present invention may change the shape of the frequency reference voltage VREF.

As described above, the frequency reference voltage FREF of the triangular waveform output from the dithering control unit 300 is applied to the filter 310, and by the action of the filter 310 in which a resistor and a capacitor are connected in parallel, the frequency reference voltage ( FREF) steps are relaxed.

In addition, the frequency reference voltage FREF is applied to the filter 320 via the filter 310 , and the filter 320 applies the oscillation signal VOSC shaped into a triangular waveform to the oscillator 330 .

The oscillator 330 may output a PWM signal having a periodic pulse waveform by comparing the triangular waveform oscillation signal VOSC with an internal reference voltage (not shown).

The above-described embodiment of FIG. 7 may be applied to the driving circuit 20, and the frequency of the PWM signal may be changed according to a change in the shape of the oscillation signal Vosc. When the oscillation signal Vosc is changed in every period, the oscillator 330 provides a PWM signal having a frequency dispersed in each period. As a result, the driving circuit 20 may provide the converter 10 with the driving signal GATE having pulses in which frequencies are dispersed by frequency dithering. Accordingly, the converter 10 may perform switching for power conversion at a time point dispersed by the frequency-dithered driving signal Gate, and as a result, concentration of power consumption may be alleviated and EMI may be reduced.

Referring to FIG. 8 , DIM_EN is a dimming control enable signal of a lighting device, JIT_EN is a frequency dithering enable signal, and MAX and MIN are triangular waveform oscillation signals (Vosc) to control the time point having the highest or lowest value. is a signal for

After the lighting device is powered on, the oscillation signal Vosc maintains a constant level. After that, when the dimming control enable signal DIM_EN is enabled, the lighting device outputs the oscillation signal Vosc having a triangular waveform. can be configured.

Before the frequency dithering enable signal JIT_EN is enabled, the oscillation signal Vosc is output to have a uniform triangular waveform. That is, the period T of the oscillation signal Vosc at this time is uniform.

After the frequency dithering enable signal JIT_EN is enabled, a frequency reference according to a change in the magnitude of the frequency reference voltage FREF or a change in the dithering control signal DMOD due to a change in option information applied to the dithering resistor Rf At least one of a magnitude and a period of the triangular waveform of the oscillation signal Vosc may be changed in units of each period due to a change in the period of the voltage FREF.

The driving circuit 20 configured in the embodiment of the present invention may store a plurality of values corresponding to the option information or the dithering control signal DMOD in the storage, and an option to change the frequency reference voltage FREF regularly or irregularly. It may provide information or a dithering control signal (DMOD).

In addition, the dithering control unit 300 of the driving circuit 20 activates the first section in which a predetermined time elapses from the start of the enable of the driving signal GATE and a predetermined time before the enable of the driving signal GATE ends. It may be configured to perform frequency dithering at a time including at least any one of the second period in which the ABLE is terminated.

In addition, the driving circuit 20 may perform frequency dithering on the driving signal GATE by periodically changing the option information or the dithering control signal DMOD and providing it to the dithering controller 300 . In addition, the driving circuit 20 changes the option information or the dithering control signal DMOD in a pattern repeated in units of a plurality of cycles and provides it to the dithering control unit 300 to perform frequency dithering on the driving signal GATE. can In addition, the driving circuit 20 may perform frequency de-dilug by changing the frequency reference voltage VREF in a pattern for gradually changing the frequency.

Due to the frequency dithering of the driving signal GATE, a peak value of the driving signal GATE may be reduced by frequency dithering as shown in FIG. 9 and frequencies may be dispersed. Accordingly, in the converter 10, the switching timing for power conversion can be distributed, so that concentration of power consumption can be alleviated, and EMI can be reduced.

Meanwhile, as shown in FIG. 10 , the driving circuit 20 of the present invention may include a slope compensating unit 241 that generates a slope compensating voltage of a value linked to a variable switching frequency of the converter 10 .

In order for the slope compensation voltage to be linked to the variable switching frequency of the converter 10 , the driving circuit 20 is configured to use a frequency source that provides information about the changing frequency of the driving signal GATE. Here, as the frequency source, the oscillator 330 providing a PWM signal used to generate the driving signal GATE may be used. In addition, the frequency information may use the output of the oscillator 330 , and more specifically, any one of a voltage or a current corresponding to the output of the oscillator 330 may be used.

The slope compensator 241 may include a series-connected dependent current source IS2 and a charging element Cc, and the dependent current source IS2 has an amount of current controlled in response to frequency information, and a charging element Cc. can be configured using a capacitor and charges the current provided from the dependent current source IS2 and provides the charged voltage as a slope compensation voltage.

The slope compensating unit 241 may be configured to generate a low slope compensating voltage as the frequency of the driving signal GATE increases.

Meanwhile, in FIG. 10 , the current source IS1 and the PMOS transistor MS may be understood as configurations corresponding to the summer 242 of FIG. 2 , and FIG. 10 shows the sensing signal SEN and the slope compensator 241 . It is exemplarily shown that the slope compensation voltages output from . The above-described summer 242 is not limited to FIG. 10 and may be variously implemented by a manufacturer.

As illustrated in FIG. 10 , unstable sub-harmony oscillation occurring when the duty of the driving signal GATE provided to the converter 10 to generate an output voltage is 50% or more is to be controlled by the slope compensator 241. can,

In order to vary the switching frequency of the converter 10 , the frequency of the driving signal GATE needs to be varied. That is, the switching frequency of the converter 10 varies depending on the frequency of the driving signal GATE.

In addition, when the switching frequency is changed, the value of the inductance of the converter 10 is also changed. In this case, the value of the slope compensation voltage of the slope compensator 241 of FIG. 10 is also changed in response to the change in the inductance value.

More specifically, in order to vary the frequency of the driving signal GATE, the frequency of the PWM signal output from the oscillator 330 must also be varied. Therefore, the oscillator 330 has variable frequency information and as a result can be used as a frequency source as described above.

For example, the dependent current source IS2 may be configured to provide a current mirroring the output current of the oscillator 330 to the charging element Cc. That is, the dependent current source IS2 may provide the charging element Cc with a current corresponding to the PWM signal of the oscillator 330 of which the frequency has been changed in order to change the frequency of the driving signal GATE. At this time, in the current mirroring, when the frequency of the oscillator 330 increases and the output current increases, the amount of current of the dependent current source IS2 is reduced, and when the frequency of the oscillator 330 decreases and the output current decreases, the amount of current of the dependent current source IS2 is increased. It can be configured to The relationship between the frequency of the oscillator 30 and the current of the dependent current source IS2 may be determined for slope compensation for reducing sub-harmony oscillation.

Unlike the above, the dependent current source IS2 may be configured to provide a PWM signal of the oscillator 330 or a current corresponding to a voltage corresponding to the PWM signal to the charging element Cc. At this time, the dependent current source IS2 reduces the amount of current by the PWM signal or a voltage corresponding to the PWM signal of the oscillator 330 having a higher frequency, and by using the PWM signal or a voltage corresponding to the PWM signal of the oscillator 330 having a lower frequency. It may be configured to increase the amount of current.

A current provided from the dependent current source IS2 may be charged in the charging element Cc, and a voltage charged in the charging element Cc may be provided as a slope compensation voltage. That is, the slope compensation voltage may be provided to vary according to the frequency as shown in FIG. 11 . 11 is a graph illustrating a comparison between a conventional slope compensation voltage in which a voltage charged by a fixed current is provided as a slope compensation voltage and a slope compensation voltage according to the present invention.

Therefore, even if the switching frequency of the converter 10 is changed, the embodiment of the present invention is a frequency source without the need to configure a separate terminal in the driving circuit 20 implemented as a chip or to configure an additional circuit outside the chip. A slope compensation voltage may be provided in association with the frequency change of the PWM signal output from the oscillator.

Therefore, a function for actively responding to a change in the switching frequency of the converter 10 can be simply implemented, and the number of parts and manufacturing cost can be reduced.

In addition, the fourth embodiment for ensuring that the LED current of each of the LED channels CH1 to CH8 included in the LED lamp 50 is maintained at a predetermined amount or more may be exemplified as shown in FIG. 12 . In FIG. 12 , the same reference numerals are used for the same parts as those of FIG. 2 , and redundant description of the configuration and operation thereof will be omitted.

The lighting device of FIG. 12 includes an output sensing circuit 60 for sensing an output voltage VOT of the converter 10 , and the output sensing circuit 60 includes series-connected resistors RV1 and RV2 in the converter 10 . ) is connected in parallel to the output terminal of the The output sensing circuit 60 provides a voltage applied to a node between the series-connected resistors RV1 and RV2 to the driving circuit 20 , and the voltage provided from the output sensing circuit 60 to the driving circuit 20 is This is called the output sensing voltage. The above-described output sensing circuit 60 may be configured either inside or outside the driving circuit 20 .

The driving circuit 20 includes the linear regulators 201 to 208, the detection voltage generating circuit 220, the reference voltage generating circuit 221, the comparator 223, the capacitor Cd, the slope compensator 240, and the summer. 242 , a comparator 244 , and an SR latch 250 .

Unlike FIG. 2 , the driving circuit of FIG. 12 includes a reference voltage generating circuit 221 . The reference voltage generation circuit 221 receives the detection voltage V _D and the internal reference voltage VREFi of the detection voltage generation circuit 22, uses the external capacitor Cs, and converts the reference voltage VREF to the comparator ( 223) is configured to output to the negative terminal (-).

According to the above configuration, the reference voltage generating circuit 221 has an internal reference voltage ( VREFi) or less, the level of the reference voltage VREF is increased. The reference voltage generating circuit 221 is preferably configured to generate an increasing reference voltage until all of the feedback voltages FB1 to FB8 are equal to or greater than the internal reference voltage VREFi. The reference voltage generating circuit 221 is configured to charge or discharge the reference voltage VREF using the external capacitor Ce.

A more detailed configuration of the reference voltage generating circuit 221 will be described later with reference to FIG. 13 .

Also, unlike in FIG. 2 , the driving circuit 20 of FIG. 12 is configured such that the comparator 223 compares the reference voltage VREF with the output sensing voltage of the output sensing circuit 60 to output the compensation voltage Vc. The reference voltage VREF is applied to the negative terminal (-) of the comparator 223 , and the output sensing voltage of the output sensing circuit 60 is applied to the positive terminal (+) of the comparator 223 .

Also, unlike in FIG. 2 , the driving circuit 20 of FIG. 12 is configured such that the comparator 244 compares the compensation voltage Vc with the comparison voltage Vs of the summer 242 and outputs the comparison. The compensation voltage Vc is applied to the negative terminal (-) of the comparator 244 , and the comparison voltage Vs is applied to the positive terminal (+) of the comparator 244 .

With the above configuration, the SR latch 250 as a pulse generator generates a driving signal GATE in response to the output of the comparator 244 whose level is determined in response to the compensation voltage Vc. That is, the SR latch 25 generates a driving signal GATE whose on-time is adjusted in response to the compensation voltage Vc and provides the driving signal GATE to the converter 10 for power conversion.

Meanwhile, the configuration of the reference voltage generating circuit 221 will be described in more detail with reference to FIG. 13 .

The reference voltage generating circuit 221 performs charging or discharging using an external capacitor Ce, and charging is performed when one or more of the feedback voltages FB1 to FB8 is less than or equal to the internal reference voltage VREFi, and discharge is performed. is performed until all of the feedback voltages FB1 to FB8 are equal to or greater than the internal reference voltage VREFi, and is configured to output the voltage charged in the capacitor Ce as the reference voltage VREF.

To this end, the reference voltage generating circuit 221 includes a comparator 225 and a current control circuit, and the comparator 225 is a switching control voltage VCT obtained by comparing the detection voltage V _D and the internal reference voltage VREFi. , and the current control circuit includes a switch SW that is switched according to the switching control voltage VCT, and provides a current for charging the capacitor Ce when the switch SW is turned on. The comparator 225 may output the switching control voltage VCT as a low-level example of 0V when the detection voltage V _D is less than the internal reference voltage VREFi, and the detection voltage V _D is the internal reference voltage VREFi. If it is greater than (VREFi), the switching control voltage VCT may be output as a high level, for example, a constant voltage VDD. When the switching control voltage VCT is at a low level, the switch SW is turned on, and when the switching control voltage VCT is at a high level, the switch SW is turned off.

The current control circuit may further include a plurality of PMOS transistors MP1 to MP7 to control the supply of current to the capacitor Ce by turning on the switch SW. The plurality of PMOS transistors MP1 to MP7 may be configured to have a current mirror structure for controlling the current provided to the capacitor Ce by the operation of the switch SW.

That is, the PMOS transistors MP1 and MP2 form a first path including a constant current source, the PMOS transistors MP3, MP4, and MP5 form a second path providing the radiated current, and the PMOS transistors MP6, The switch SW and the PMOS transistor MP7 form a third path for controlling the current provided to the capacitor Ce by the current of the second path. The first to third paths are configured such that respective transistors included therein are connected in series, and the first to third paths are configured in parallel with respect to the constant voltage VDD.

Depending on the resistance ratio (channel ratio) of the PMOS transistors MP3 and MP4 and the PMOS transistors MP1 and MP2, the amount of current flowing through the PMOS transistors MP3 and MP4 of the second path is determined by the PMOS transistor of the first path. It may be controlled based on the amount of current flowing through the MP1 and MP2. Also, the amount of current flowing through the PMOS transistor MP6 may be controlled based on the amount of current flowing through the PMOS transistor MP1 of the first path. In addition, the amount of current flowing through the PMOS transistor MP7 may be controlled based on the amount of current flowing through the PMOS transistor MP5 of the second path.

The operation of the reference voltage generating circuit 221 configured as shown in FIG. 13 will be described with reference to FIG. 14 .

In the reference voltage generating circuit 221 , when the detection voltage VD is less than the internal reference voltage VREFi, the switching control voltage VCT of the comparator 225 becomes low level, and as a result, the switch SW is turned on. do.

When the switch SW is turned on, the flow of the current Ir1 starts, the current Ir3 is provided to the capacitor Ce, and the voltage charged by the capacitor Ce by the current Ir3 increases. The voltage charged in the capacitor Ce is the reference voltage VREF output from the reference voltage generating circuit 221 . As described above, the amount of the current Ir3 may be determined as “the amount of the current Ir1” - “the amount of the current Ir2 of the PMOS transistor MP7”.

The detection voltage V _D is the lowest feedback voltage among the mode feedback voltages FB1 to FB8 . The switching control voltage VCT of the comparator 225 transitions to a high level when all of the feedback voltages FB1 to FB8 are equal to or greater than the internal reference voltage VREFi. Therefore, the reference voltage VREF charged in the capacitor Ce is also charged until all of the feedback voltages FB1 to FB8 are equal to or greater than the internal reference voltage VREFi, and the level is increased.

Thereafter, when all of the feedback voltages FB1 to FB8 are equal to or greater than the internal reference voltage VREFi, the switching control voltage VCT transitions to a high level, and the switch SW is turned off. When the switch SW is turned off, the flow of the current Ir1 is stopped.

After the flow of the current Ir1 is stopped, the capacitor Ce starts to discharge, and accordingly, the level of the reference voltage VREF output from the reference voltage generating circuit 221 is gradually decreased.

As described above, the reference voltage VREF provided from the reference voltage generating circuit 221 may increase or decrease according to the states of the feedback voltages FB1 to FB8 .

A case in which the reference voltage VREF increases corresponds to a case in which it is necessary to compensate the amount of LED current for normal light emission of the LED channels CH1 to CH8. At this time, the output voltage VOUT increases by the increasing reference voltage VREF. A case in which the reference voltage VREF is decreased corresponds to a case in which the amount of LED current of the LED channels CH1 to CH8 can maintain normal light emission.

A series of operations in which the output voltage VOUT is increased by the increase of the reference voltage VREF will be described in more detail. When the reference voltage VREF increases, the comparator 223 compares the output sensing voltage of the output sensing circuit 60 with the increased reference voltage VREF. As a result, when the output sensing voltage of the output sensing circuit 60 is lower than the reference voltage VREF, the compensation voltage Vc is applied to the negative terminal (−) of the comparator 244 at a negative level. When the compensation voltage Vc is applied to a negative level, the output of the comparator 244 rises. When the output of the comparator 244 rises, the SR latch 25 generates a driving signal GATE with an increased on-time. As a result, the output voltage VOUT output from the converter 10 rises.

As described above, the output voltage VOUT is regulated to maintain a certain level or more by the increasing reference voltage VREF.

In the fourth embodiment of the present invention, as described above, the output voltage VOUT may be regulated by the reference voltage VREF.

Therefore, the bias voltages of the LED channels CH1 to CH8 are different due to characteristic deviation, and the lowest feedback voltage of the LED channels CH1 to CH8 changes each time the LED channels CH1 to CH8 emit light. In response to the possible environment, the fourth embodiment of the present invention can stably maintain the output voltage VOUT, and as a result, it is possible to prevent audible noise from being generated.

Meanwhile, the fifth embodiment of the present invention may be configured as shown in FIG. 15 in order to reduce the number of parts and manufacturing cost by sharing parts such as a converter.

The embodiment of FIG. 15 exemplifies that the driving circuits are configured as a multi-chip for one converter 10, and the driving circuit that provides the driving signal GATE to the converter 10 to distinguish the driving circuits is the master driving circuit. It is referred to as (M20), and the remaining driving circuits are referred to as slave driving circuits (S20).

In the embodiment of FIG. 15 , the converter 10 performs power conversion to output an output voltage VOUT corresponding to the input voltage VIN, and provides the output voltage VOUT to the LED lamps M50 and S50. is composed

The LED lamps M50 and S50 each include a plurality of LED channels CH1 to CH8 configured in parallel as shown in FIG. 1 , and a plurality of LED channels CH1 to CH8 of the LED lamps M50 and S50. is emitted by the output voltage VOUT.

Meanwhile, an overvoltage detection circuit 70 for detecting the level of the output voltage VOUT is configured at the output terminal of the converter 10 . The overvoltage detection circuit 70 outputs a voltage applied to a node between the series-connected resistors ROVT1 and ROVT2 as an overvoltage detection signal, and the overvoltage detection signal is the master driving circuit M20 and the slave driving circuit S20. It is shared with the overvoltage detection stage (OVP).

When it is determined that the output voltage VOUT is in the overvoltage state by the overvoltage detection signal, the master driving circuit M20 controls the level of the output voltage VOUT by adjusting the output of the driving signal GATE or the LED lamp M50 ) can control the light emission state. In addition, when it is determined that the output voltage VOUT is in the overvoltage state by the overvoltage detection signal, the slave driving circuit S20 may control the light emission state of the LED lamp S50 .

In addition, the master driving circuit M20 and the slave driving circuit S20 have substantially the same configuration as the driving circuit 20 of FIG. 1 except that the common terminal CON and the high ground terminal HGND are formed. A duplicate description will be omitted. The master driving circuit M20 and the slave driving circuit S20 may be configured as a multi-chip. That is, the master driving circuit M20 and the slave driving circuit S20 may be configured using chips having the same structure.

The common terminal CON of the master driving circuit M20 and the common terminal of the slave driving circuit S20 are electrically connected to each other. In addition, the high ground terminal HGND of the master driving circuit M20 and the slave driving circuit S20 is set in a state in which a constant voltage is biased using the capacitor CH.

The master driving circuit M20 performs linear regulation on the LED channels CH1 to CH8 of the LED lamp M50, and feedback voltages FB1 to the LED channels CH1 to CH8 of the LED lamp 50 FB8) detects a first minimum feedback voltage of the lowest level, and generates a detection voltage V _D corresponding to a lower level among the first minimum feedback voltage and the second minimum feedback voltage shared through the common terminal CON and generates a driving signal GATE in response to the detection voltage V _D , and provides the driving signal GATE to the converter 10 for power conversion. As described above, generating the driving signal GATE by the master driving circuit M20 using the detection voltage V _D may be variously implemented, such as the embodiment of FIGS. 1 and 2 or the embodiment of FIG. 12 . Therefore, a detailed description thereof will be omitted.

The slave driving circuit S20 performs linear regulation on the LED channels CH1 to CH8 of the LED lamp S50, and is the lowest among the feedback voltages of the LED channels CH1 to CH8 of the LED lamp S50. The second minimum feedback voltage of the level is detected, and the second minimum feedback voltage is shared with the master driving circuit M20 through the common terminal CON.

The slave driving circuit S20 includes input/output terminals related to generation and output of driving signals in the same way as the master driving circuit M20. However, the slave driving circuit S20 generates and does not output the driving signal GATE. Therefore, at least some (VIN, SEN, GATE) of the input/output terminals related to generation and output of the input/output terminals driving signal GATE of the slave driving circuit S20 are masked. Processing means that the input level is fixed by the high-level voltage charged in the capacitor CH by the input voltage VIN, or the input level is fixed to the ground level of the capacitor CIN, and a floating state may also be included.

The above-described master driving circuit M20 and slave driving circuit S20 may each include a detection voltage generating circuit 220 for generating a detection voltage. The configuration and operation of the detection voltage generating circuit 220 of the master driving circuit M20 and the slave driving circuit S20 will be described with reference to FIG. 16 . 16 schematically illustrates the detection voltage generating circuit 220 and the linear regulators 201 to 208 of the master driving circuit M20 and the slave driving circuit S20.

The feedback voltages FB1 to FB8 of the master driving circuit M20 and the slave driving circuit S20 are voltages applied to the respective linear regulators 201 to 208 . Since each of the linear regulators 201 to 208 is the same as that of FIG. 2 , detailed configuration and operation description thereof will be omitted.

The above-described feedback voltages FB1 to FB8 are applied to the detection voltage generating circuit 220 in the master driving circuit M20 and the slave driving circuit S20 .

The detection voltage generating circuit 220 of the master driving circuit M20 and the slave driving circuit S20 may include transistors TFB1 to TFB8 and switches SFB1 to SFB8 for each path of the feedback voltages FB1 to FB8. there is.

The transistors TFB1 to TFB8 transfer the feedback voltages FB1 to FB8 to the switches SFB1 to SFB8 when the switches SFB1 to SFB8 are turned on, and the switches SFB1 to SFB8 transmit a switching control signal This is to transfer the feedback voltages FB1 to FB8 switched by the FBS1 to FBS8 and transferred through the transistors TFB1 to TFB8 to the output terminal of the detection voltage generating circuit 220 .

Here, the output terminal of the detection voltage generation circuit 220 means a node to which the switches SFB1 to SFB8 are commonly connected to output the detection voltage V _D , and the output terminal of the detection voltage generation circuit 220 is shown in FIG. 16 . As illustrated, a constant current may be supplied by a constant current source.

The detection voltage generating circuit 220 may include a circuit (not shown) that compares the levels of the feedback voltages FB1 to FB8 and determines the feedback voltage (minimum feedback voltage) of the lowest level. The above-described circuit can be easily configured by a person who understands the technical idea of the present specification using a conventional comparator or level detector, so a specific example will be omitted.

The detection voltage generating circuit 220 may provide the switching control signals FBS1 to FBS8 for outputting only the minimum feedback voltage as the detection voltage V _D to the switches SFB1 to SFB8 .

For example, the detection voltage generating circuit 220 of the master driving circuit M20 turns on only the switch SFB1 when it is determined that the feedback voltage “FB1” is the first minimum feedback voltage, and the other switches SFB2 to SFB8 are turn off As a result, the feedback voltage FB1 determined as the first minimum feedback voltage may be transmitted to the output terminal of the detection voltage generating circuit 220 of the master driving circuit M20 .

As described above, the detection voltage generating circuit 220 of the master driving circuit M20 and the slave driving circuit S20 may transmit the first minimum feedback voltage and the second minimum feedback voltage to the output terminal, respectively.

The output terminals of the detection voltage generation circuit 220 of the master driving circuit M20 and the slave driving circuit S20 are electrically connected through respective common terminals CON. Therefore, the first minimum feedback voltage and the second minimum feedback voltage transmitted to the output terminals of the detection voltage generating circuit 220 of the master driving circuit M20 and the slave driving circuit S20 are shared.

As a result, the detection voltage generation circuit 220 of the master driving circuit M20 may output the detection voltage V _D generated by sharing the first minimum feedback voltage and the second minimum feedback voltage.

The master driving circuit M20 may generate a driving signal GATE as in the embodiment of FIGS. 1 and 2 or the embodiment of FIG. 12 in response to the detected voltage V _D generated as described above, and the driving signal (GATE) may be provided to the converter 10 for power conversion.

On the other hand, among the master driving circuit M20 and the slave driving circuit S20 configured in the embodiment of the present invention, the slave driving circuit S20 is the feedback voltage of the LED channels CH1 to CH8 of the LED lamp S50 ( It may be configured to perform only a function of detecting the second minimum feedback voltage of the lowest level among FB1 to FB8 and linear regulation of the LED channels CH1 to CH8 of the LED lamp S50. In this case, the master driving circuit M20 may be referred to as a first circuit, and the slave driving circuit S20 may be referred to as a second circuit.

As described above, in the present invention, the driving circuits may be configured as a multi-chip corresponding to a large number of LED channels. Therefore, sharing the lowest feedback voltage for LED channels corresponding to each driving circuit, detecting the lowest feedback voltage for all LED channels, and using the lowest feedback voltage for all LED channels It is possible to control the output voltage provided to the channels.

As a result, parts such as a converter can be shared, and the number of parts and manufacturing cost can be reduced.

The present invention may be implemented to secure an effective duty of a driving signal for controlling dimming regardless of the switching frequency of the converter 10 . To this end, a sixth embodiment for ensuring the minimum on-time of the converter 10 irrespective of the switching frequency of the converter 10 may be configured as shown in FIGS. 17 to 19 . In addition, the seventh embodiment for ensuring the minimum off time of the converter 10 irrespective of the switching frequency of the converter 10 may be configured as shown in FIGS. 20 to 22 .

First, a sixth embodiment will be described in detail with reference to FIGS. 17 to 19 .

In the driving circuit 20 , the driving signal GATE may be generated using a PWM signal of the oscillator 330 . The generation of the driving signal GATE using the PWM signal can be understood by the above description with reference to FIG. 2 , and thus a description thereof will be omitted. Hereinafter, the PWM signal of the oscillator 330 will be described as an oscillation signal.

The switching frequency of the converter 10 may be determined by the driving signal GATE, and the driving circuit 20 provides the converter 10 with the driving signal GATE capable of ensuring the minimum on-time of the converter 10 . do.

To this end, the driving circuit 20 includes a constant current supply unit 80, a control current supply unit 82, a charging element CN, a switch SWT, a comparator 86, a NAND gate 88 and an inverter as shown in FIG. IV1).

The constant current supply unit 80 is to provide a constant current by the constant voltage VDD to the charging element CN. To this end, the constant current supply unit 80 copies the current flowing through the series-connected PMOS transistors MS1 and MS2 to the PMOS transistors MS3 and MS4 by mirroring, respectively, and flows through the PMOS transistors MS3 and MS4. configured to provide a current to the charging element CN.

The control current supply unit 82, the charging element CN, and the switch SWT are included in a control voltage generating circuit to be described later.

Among them, the control current supply unit 82 is configured to provide a control current to the charging element CN by using the oscillator current iosc by the oscillation signal output from the oscillator 330 . To this end, in the control current supply unit 82, a current corresponding to the oscillator current iosc flows, and the current flowing through the serially connected PMOS transistors MC1 and MC2 and the PMOS transistors MC1 and MC2 is copied by mirroring. flowing and includes PMOS transistors MC3 and MC4 connected in series. Here, the current flowing through the PMOS transistors MC3 and MC4 is provided to the charging element CN.

The amount of the oscillator current iosc may be changed in proportion to a change in the frequency of the oscillation signal. Therefore, the amount of the control current provided by the control current supply unit 82 to the charging element CN may be changed in proportion to the change in the frequency of the oscillation signal.

More specifically, when the frequency of the oscillation signal is high, the amount of the oscillator current iosc increases, and the amount of the control current of the control current supply unit 82 also increases. Conversely, when the frequency of the oscillation signal is low, the amount of the oscillator current iosc is reduced, and the amount of the control current of the control current supply unit 82 is also reduced.

In addition, the switch SWT is connected in parallel to the charging element CN, and when turned on, blocks the supply of current to the charging element CN. That is, the supply of current to the charging element CN is regulated by the switch SWT. The switch SWT is switched by the driving signal GATE which is inverted input through the inverter IV1. That is, the switch SWT is turned off during the turn-on period of the converter 10 , and is turned on during the turn-off period of the converter 10 . Accordingly, the charging element CN is charged during the turn-on period of the converter 10 and discharged during the turn-off period of the converter 10 .

The charging element CN may perform charging by the current supplied from the constant current supply unit 80 and the control current supply unit 82 and generate a control voltage. In particular, the charging element CN generates a control voltage by the control current of the control current supply unit 82 whose amount is changed in proportion to the change in the frequency of the oscillation signal, and the charging rate of the control voltage in proportion to the change in the frequency of the oscillation signal. may vary.

More specifically, when the frequency of the oscillation signal is high, the amount of control current of the control current supply unit 82 increases, and the rate at which the control voltage is charged in the charging element CN is high. Conversely, when the frequency of the oscillation signal is low, the amount of the control current of the control current supply unit 82 is reduced, and the rate at which the control voltage is charged in the charging element CN is slow.

The comparator 86 compares the control voltage of the charging element CN applied to the positive terminal (+) with the reference voltage VREF applied to the negative terminal (-) and outputs a control pulse VA as shown in FIG. 18 . . More specifically, the comparator 86 outputs a control pulse VA that transitions to a high level when the control voltage reaches the reference voltage VREF and maintains the transition state while the control voltage remains above the reference voltage VREF. do. The comparator 86 performing the above operation corresponds to a control pulse generating circuit to be described later.

When the control voltage of the capacitor CN is rapidly charged because the frequency of the oscillation signal is high, the comparator 86 outputs the control pulse VA having a fast level transition time. Conversely, when the frequency of the oscillation signal is low and the control voltage of the capacitor CN is charged to increase, the comparator 86 outputs the control pulse VA having a late level transition time.

The NAND gate 88 outputs the minimum on-time pulse ON_MIN as shown in FIG. 18 by performing a NAND combination of the control pulse VA and the inverted driving signal GATE. The inverted driving signal GATE is used to determine the turn-on period of the converter 10 .

That is, the NAND gate 88 uses the control pulse VA within the turn-on period of the converter 10 to define the minimum on time including the end time of the minimum on time from the turn-on start time of the converter 10. Generates the minimum on-time pulse (ON_MIN). The NAND gate 88 performing the above operation corresponds to a minimum on-time determination unit to be described later.

When the frequency of the oscillation signal is high and the comparator 86 outputs the control pulse VA having a fast level transition time, the end point of the minimum on time is quicker, and as a result, the NAND gate 88 has a narrow minimum on time pulse width. Time pulse (ON_MIN) is output. Conversely, when the frequency of the oscillation signal is low and the comparator 86 outputs a control pulse VA having a slow level transition time, the end time of the minimum on time is slowed, and as a result, the NAND gate 88 has a pulse width Outputs a wide minimum on-time pulse (ON_MIN).

That is, in the embodiment of FIG. 17 , as shown in FIG. 19 , the width of the minimum on-time pulse ON_MIN may be adjusted in response to a change in the frequency of the oscillation signal. The width of the minimum on-time pulse ON_MIN means the minimum on-time that can be guaranteed for turning on the converter 10 . That is, the minimum on time for turning on the converter 10 may be changed in response to a change in the frequency of the oscillation signal.

Therefore, in the embodiment of FIGS. 17 to 19 , it is possible to secure an effective duty for controlling dimming regardless of the switching frequency of the converter 10 .

The above-described embodiment of FIG. 17 may be described as including an end time generation unit and a minimum on time determination unit.

The end time generation unit uses the oscillation signal used to generate the driving signal GATE within the turn-on section of the converter 10 to express the end time of the minimum on time following the frequency change of the oscillation signal VA. is configured to create

The end time generation unit may be described as including a control voltage generation circuit and a control pulse generation circuit.

Here, the control voltage generating circuit is configured to generate a control voltage whose increase time varies according to a change in the frequency of the oscillation signal using the oscillation signal used to generate the driving signal GATE within the turn-on period of the converter 10 . do. And, the control pulse generating circuit corresponds to the above-described comparator 86,

The above-described control voltage generating circuit may include a control current supply unit 82 , a charging element CN, and a switch SWT.

Meanwhile, a seventh embodiment will be described in detail with reference to FIGS. 20 to 22 .

The embodiment of FIG. 20 is for ensuring the minimum off time of the converter 10 irrespective of the switching frequency of the converter 10 , and the driving circuit 20 is a driving capable of ensuring the minimum off time of the converter 10 . A signal GATE is provided to the converter 10 .

To this end, the driving circuit 20 includes a constant current supply unit 80, a control current supply unit 82, a charging element CN, a switch SWT, a comparator 86, an AND gate 89 and an inverter as shown in FIG. IV2).

Compared with the embodiment of FIG. 17 , the configuration of the AND gate 89 and the inverter IV2 is different in the embodiment of FIG. 20 , and there is a difference in the charging capacity of the charging element CN. Since the remaining components of FIG. 20 are the same as those of FIG. 17, a redundant description will be omitted.

In FIG. 20 , the switch SWT is switched by the non-inverting input driving signal GATE. That is, the switch SWT is turned off during the turn-off period of the converter 10 , and is turned on during the turn-on period of the converter 10 . Accordingly, the charging element CN is charged during the turn-off period of the converter 10 and discharged during the turn-on period of the converter 10 .

The charging element CN may be configured to have a charging capacity larger than that of FIG. 17 .

The comparator 86 outputs the control pulse VA as shown in FIG. More specifically, in the embodiment of FIG. 20 , the time for the control voltage to reach the reference voltage VREF is slower than the embodiment of FIG. 17 due to the difference in the charging capacity of the charging element CN. Therefore, the control pulse VA output from the comparator 86 is transitioned with a delay of a predetermined time after the turn-off section of the converter 10 starts, and the transitioned level is maintained until the turn-on section of the converter 10 starts. . The comparator 86 outputs a control pulse VA that maintains a transition state while the control voltage remains above the reference voltage VREF.

The AND gate 89 AND-combines the control pulse VA and the inverted driving signal GATE to output the minimum off-time pulse OFF_MIN as shown in FIG. 21 . The inverted driving signal GATE is used to determine a turn-off period of the converter 10 .

That is, the AND gate 88 uses the control pulse VA within the turn-off section of the converter 10 to determine the minimum off time including the start time of the minimum off time and the end time of the turn off of the converter 10 . Creates a defining minimum off-time pulse (OFF_MIN). The AND gate 89 performing the above operation corresponds to a minimum off-time determining unit to be described later.

When the frequency of the oscillation signal is high and the comparator 86 outputs the control pulse VA with a fast level transition time, the start time of the minimum off time is increased, and as a result, the AND gate 88 has a wide minimum off time of the pulse width. Time pulse (OFF_MIN) is output. On the contrary, when the frequency of the oscillation signal is low and the comparator 86 outputs a control pulse VA having a slow level transition time, the start time of the minimum off time is slowed, and as a result, the AND gate 89 has a pulse width Outputs a narrow minimum off-time pulse (OFF_MIN).

That is, in the embodiment of FIG. 20 , as shown in FIG. 22 , the width of the minimum off-time pulse OFF_MIN may be adjusted in response to a change in the frequency of the oscillation signal. The width of the minimum off-time pulse OFF_MIN means the minimum off-time that can be guaranteed for turning off the converter 10 . That is, the minimum off time for turning off the converter 10 may be changed in response to a change in the frequency of the oscillation signal.

Therefore, in the embodiment of FIGS. 20 to 22 , an effective duty of the driving signal GATE for controlling dimming can be secured regardless of the switching frequency of the converter 10 .

The above-described embodiment of FIG. 20 may be described as including a start time generator and a minimum off-time determiner.

The start time generator uses the oscillation signal used to generate the driving signal GATE within the turn-off section of the converter 10 to express the start time of the minimum off time following the frequency change of the oscillation signal VA. ) is configured to create

The start time generation unit may be described as including a control voltage generation circuit and a control pulse generation circuit.

Here, the control voltage generating circuit generates a control voltage whose increase time varies according to a change in the frequency of the oscillation signal using the oscillation signal used to generate the driving signal GATE within the turn-off section of the converter 10 . is composed And, the control pulse generating circuit corresponds to the above-described comparator 86,

The above-described control voltage generating circuit may include a control current supply 82 , a charging element CN, and a switch SWT.

Meanwhile, the present invention may be implemented by applying the embodiment of FIG. 17 and the embodiment of FIG. 20 to the driving circuit 20 together. In this case, the minimum on time of the turn-on period of the converter 10 and the minimum off time of the turn-off period of the converter 10 may be simultaneously guaranteed regardless of the switching frequency.

Claims (13)

In the driving circuit of a lighting device for controlling power conversion of a converter that provides an output voltage to an LED lamp including a plurality of LED channels,
a reference voltage generating circuit that generates a reference voltage whose level increases when at least one of the feedback voltages corresponding to the bias voltage of each LED channel is equal to or less than an internal reference voltage having a preset value;
A driving circuit of a lighting device that regulates the output voltage by controlling power conversion of the converter using the reference voltage. According to claim 1,
The reference voltage generating circuit is a driving circuit of a lighting device to generate the reference voltage that increases until all of the feedback voltages are equal to or greater than the internal reference voltage. According to claim 1,
a comparator comparing the reference voltage and an output sensing voltage sensing the output voltage, and generating a compensation voltage corresponding to a result of the comparison; and
A pulse generator that generates a driving signal whose on-time is adjusted in response to the compensation voltage and provides the driving signal to the converter for power conversion;
A driving circuit of a lighting device that regulates the output voltage. 4. The method of claim 3,
Further comprising an output sensing circuit for sensing the output voltage,
The output sensing circuit provides a voltage applied to a node between series-connected resistors by the output voltage as the output sensing voltage. 4. The method of claim 3,
The output sensing voltage is provided from an external output sensing circuit,
The output sensing circuit provides a voltage applied to a node between series-connected resistors by the output voltage of the converter as the output sensing voltage. 4. The method of claim 3,
The pulse generator generates the driving signal in response to a result of comparing the compensation voltage and the comparison voltage, and the comparison voltage is a sensing signal sensing an input voltage of the converter and a slope compensation for compensating for a slope of the driving signal. A driving circuit of a lighting device provided by summing voltages. According to claim 1,
The reference voltage generating circuit performs charging or discharging using an external capacitor, the charging is performed when at least one of the feedback voltages is equal to or less than the internal reference voltage, and the discharging is performed when all of the feedback voltages are equal to or less than the internal reference voltage. A driving circuit of a lighting device that is performed until the voltage is higher than the voltage, and outputs the voltage charged in the capacitor as the reference voltage. 8. The method of claim 7,
A detection voltage generating circuit that receives feedback voltages corresponding to bias voltages of each LED channel and provides a feedback voltage of a minimum level among the feedback voltages as a detection voltage;
The reference voltage generation circuit,
a comparator outputting a switching control voltage obtained by comparing the detection voltage and the internal reference voltage; and
and a current control circuit including a switch switched according to the switching control voltage, and providing a current for charging the capacitor when the switch is turned on. In the driving circuit of a lighting device for controlling power conversion of a converter that provides an output voltage to an LED lamp including a plurality of LED channels,
a detection voltage generating circuit that receives feedback voltages corresponding to bias voltages of each LED channel and provides a feedback voltage of a minimum level among the feedback voltages as a detection voltage;
a reference voltage generating circuit that generates a reference voltage whose level increases when the detected voltage is equal to or less than an internal reference voltage having a preset value;
a comparator comparing the reference voltage and an output sensing voltage sensing the output voltage, and generating a compensation voltage corresponding to a result of the comparison; and
a pulse generator for providing a driving signal to the converter in response to the compensation voltage;
The driving circuit of a lighting device, characterized in that the regulation is performed on the output voltage by using the reference voltage. 10. The method of claim 9,
The reference voltage generating circuit is a driving circuit of a lighting device to generate the reference voltage that increases until all of the feedback voltages are equal to or greater than the internal reference voltage. 10. The method of claim 9,
The output sensing voltage is provided from an external output sensing circuit,
The output sensing circuit provides a voltage applied to a node between series-connected resistors by the output voltage of the converter as the output sensing voltage. 10. The method of claim 9,
The reference voltage generating circuit performs charging or discharging using an external capacitor, the charging is performed when at least one of the feedback voltages is equal to or less than the internal reference voltage, and the discharging is performed when all of the feedback voltages are equal to or less than the internal reference voltage. A driving circuit of a lighting device that is performed until the voltage is higher than the voltage, and outputs the voltage charged in the capacitor as the reference voltage. 13. The method of claim 12,
The reference voltage generation circuit,
a comparator outputting a switching control voltage obtained by comparing the detection voltage and the internal reference voltage; and
and a current control circuit including a switch switched according to the switching control voltage, and providing a current for charging the capacitor when the switch is turned on.

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