KR20160113142A - 동적 언어들로 된 인라인 캐시들에 대한 하드웨어 가속 - Google Patents

동적 언어들로 된 인라인 캐시들에 대한 하드웨어 가속 Download PDF

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Publication number
KR20160113142A
KR20160113142A KR1020167021009A KR20167021009A KR20160113142A KR 20160113142 A KR20160113142 A KR 20160113142A KR 1020167021009 A KR1020167021009 A KR 1020167021009A KR 20167021009 A KR20167021009 A KR 20167021009A KR 20160113142 A KR20160113142 A KR 20160113142A
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KR
South Korea
Prior art keywords
instance
software operation
dynamic software
processor
coprocessor
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Abandoned
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KR1020167021009A
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English (en)
Korean (ko)
Inventor
베흐남 로바트밀리
게오르게 칼린 카스카발
마두카르 나가라자 케드라야
그라시아 다리오 수아레스
Original Assignee
퀄컴 인코포레이티드
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Publication of KR20160113142A publication Critical patent/KR20160113142A/ko
Abandoned legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/4431—
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/448—Execution paradigms, e.g. implementations of programming paradigms
    • G06F9/4488—Object-oriented
    • G06F9/449—Object-oriented method invocation or resolution
    • G06F9/4491—Optimising based on receiver type
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/452—Instruction code

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
  • Devices For Executing Special Programs (AREA)
  • Stored Programmes (AREA)
KR1020167021009A 2014-01-23 2015-01-22 동적 언어들로 된 인라인 캐시들에 대한 하드웨어 가속 Abandoned KR20160113142A (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201461930808P 2014-01-23 2014-01-23
US61/930,808 2014-01-23
US14/262,852 US9710388B2 (en) 2014-01-23 2014-04-28 Hardware acceleration for inline caches in dynamic languages
US14/262,852 2014-04-28
PCT/US2015/012527 WO2015112762A1 (en) 2014-01-23 2015-01-22 Hardware acceleration for inline caches in dynamic languages

Publications (1)

Publication Number Publication Date
KR20160113142A true KR20160113142A (ko) 2016-09-28

Family

ID=53544933

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020167021009A Abandoned KR20160113142A (ko) 2014-01-23 2015-01-22 동적 언어들로 된 인라인 캐시들에 대한 하드웨어 가속

Country Status (6)

Country Link
US (1) US9710388B2 (enExample)
EP (1) EP3097478A1 (enExample)
JP (1) JP6293910B2 (enExample)
KR (1) KR20160113142A (enExample)
CN (1) CN106415485B (enExample)
WO (1) WO2015112762A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9740504B2 (en) 2014-01-23 2017-08-22 Qualcomm Incorporated Hardware acceleration for inline caches in dynamic languages
US10489178B2 (en) * 2015-04-28 2019-11-26 Altera Corporation Network functions virtualization platforms with function chaining capabilities
US10031760B1 (en) * 2016-05-20 2018-07-24 Xilinx, Inc. Boot and configuration management for accelerators
CN111966333A (zh) * 2020-07-28 2020-11-20 锐达互动科技股份有限公司 一种插入动态模板背景的实现方法、装置、设备和介质
CN117008810A (zh) * 2022-04-27 2023-11-07 华为技术有限公司 一种数据处理方法、装置及相关设备
CN115167922A (zh) * 2022-06-28 2022-10-11 北京奕斯伟计算技术股份有限公司 指令处理方法、装置、电子设备及计算机可读存储介质

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020087798A1 (en) * 2000-11-15 2002-07-04 Vijayakumar Perincherry System and method for adaptive data caching
US7353364B1 (en) 2004-06-30 2008-04-01 Sun Microsystems, Inc. Apparatus and method for sharing a functional unit execution resource among a plurality of functional units
US7949826B2 (en) 2007-07-05 2011-05-24 International Business Machines Corporation Runtime machine supported method level caching
US9250938B2 (en) * 2008-10-15 2016-02-02 Microsoft Technology Licensing, Llc Caching runtime generated code
US9063749B2 (en) * 2011-05-27 2015-06-23 Qualcomm Incorporated Hardware support for hashtables in dynamic languages
US9009686B2 (en) * 2011-11-07 2015-04-14 Nvidia Corporation Algorithm for 64-bit address mode optimization
US9128732B2 (en) 2012-02-03 2015-09-08 Apple Inc. Selective randomization for non-deterministically compiled code
US9251071B2 (en) 2013-08-30 2016-02-02 Apple Inc. Concurrent inline cache optimization in accessing dynamically typed objects
US9740504B2 (en) 2014-01-23 2017-08-22 Qualcomm Incorporated Hardware acceleration for inline caches in dynamic languages

Also Published As

Publication number Publication date
CN106415485B (zh) 2019-11-22
US9710388B2 (en) 2017-07-18
EP3097478A1 (en) 2016-11-30
JP6293910B2 (ja) 2018-03-14
WO2015112762A1 (en) 2015-07-30
US20150205726A1 (en) 2015-07-23
CN106415485A (zh) 2017-02-15
JP2017507411A (ja) 2017-03-16

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Patent event date: 20170728

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Patent event date: 20171116

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