KR20160112894A - Regulator Circuit and Semiconductor Memory Apparatus Having the Same - Google Patents

Regulator Circuit and Semiconductor Memory Apparatus Having the Same Download PDF

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Publication number
KR20160112894A
KR20160112894A KR1020150064844A KR20150064844A KR20160112894A KR 20160112894 A KR20160112894 A KR 20160112894A KR 1020150064844 A KR1020150064844 A KR 1020150064844A KR 20150064844 A KR20150064844 A KR 20150064844A KR 20160112894 A KR20160112894 A KR 20160112894A
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KR
South Korea
Prior art keywords
voltage
level
switching signal
output voltage
output
Prior art date
Application number
KR1020150064844A
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Korean (ko)
Inventor
이은진
권이현
Original Assignee
에스케이하이닉스 주식회사
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Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to US14/740,400 priority Critical patent/US9520163B2/en
Priority to CN201510627565.7A priority patent/CN105989892B/en
Publication of KR20160112894A publication Critical patent/KR20160112894A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/142—Contactless power supplies, e.g. RF, induction, or IR
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G11C5/146—Substrate bias generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits

Abstract

According to an embodiment of the present invention, a regulator circuit includes: a comparison unit which compares a reference voltage with a feedback voltage to generate a first switching signal; a current supply unit which receives a pumping voltage and determines a level of a second switching signal in response to the first switching signal; an output driver which controls the level of the second switching signal in response to an output voltage, and receives the pumping voltage to generate an output voltage in response to the second switching signal; and a feedback signal generation unit which detects a level of the output voltage to generated the feedback voltage.

Description

(Regulator Circuit and Semiconductor Memory Apparatus Having the Same)

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a regulator circuit and a semiconductor device having the same.

A semiconductor integrated circuit is a complex electronic device of a very small structure in which a large number of electronic devices are bonded on a substrate. Power is required to operate the semiconductor integrated circuit. The voltage supply unit is a circuit unit that converts an external power supply to an internal power supply, thereby supplying a predetermined level of power to each element on the substrate.

Generally, a low level voltage is supplied to the semiconductor integrated circuit. However, in many cases, a semiconductor integrated circuit requires a high voltage in order to actually operate the semiconductor integrated circuit. Accordingly, the voltage supply unit may include a pump capable of pumping an external voltage input at a low level to generate a high voltage. And how fast the pump can raise the voltage to the target level can be one of the factors determining the operating speed of the semiconductor integrated circuit.

For example, a flash memory device requires a high voltage during a program or erase operation. The voltage supply unit must be capable of generating a predetermined level of the program voltage or the erase voltage in accordance with the operation mode of the flash memory device. Also, as the time required to generate and provide the program voltage or erase voltage of a predetermined level is reduced, the total time for performing the program or erase can be reduced.

The output voltage of the voltage supply unit must be kept constant at a desired level, and a regulator circuit may be used for this purpose.

The regulator circuit detects the pumped voltage and determines whether the pump operates according to a comparison of the detected voltage with a reference voltage.

The required voltage level of the semiconductor integrated circuit varies depending on the operation mode. Thus, depending on the mode of operation, the pump must generate a predetermined high level of voltage, and the generated high level voltage must be maintained at that level in the regulator circuit. In addition, when the required voltage level changes and the output voltage of the pump changes, the regulator circuit is also required to maintain a high voltage at the changed level in response.

This series of high-voltage supply operation can be an element that determines operation reliability as well as operation speed of a semiconductor integrated circuit.

Embodiments of the present invention can provide a regulator circuit capable of stably generating an internal voltage and a semiconductor device having the regulator circuit.

A regulator circuit according to an embodiment of the present invention includes a comparator for comparing a reference voltage and a feedback voltage to generate a first switching signal; A current supplier receiving a pumping voltage and determining a level of a second switching signal in response to the first switching signal; An output driver for controlling a level of the second switching signal in response to an output voltage and receiving the pumping voltage to generate the output voltage in response to the second switching signal; And a feedback signal generator for detecting the level of the output voltage to generate the feedback voltage.

According to another aspect of the present invention, there is provided a regulator circuit including: an output unit receiving a pumping voltage and being driven according to a switching signal to generate an output voltage; And a control unit for controlling the level of the switching signal based on the level of the output voltage.

A semiconductor device according to an embodiment of the present invention includes a controller; A memory circuit portion controlled by the controller; And a voltage supply unit for providing an output voltage to the memory circuit unit under the control of the controller, wherein the voltage supply unit comprises: a comparator for comparing the reference voltage and the feedback voltage to generate a first switching signal; A current supplier receiving a pumping voltage and determining a level of a second switching signal in response to the first switching signal; An output driver for controlling the level of the second switching signal in response to the output voltage and receiving the pumping voltage to generate the output voltage in response to the second switching signal; And a feedback signal generator for detecting the level of the output voltage to generate the feedback voltage.

According to this technique, an internal voltage can be stably generated.

1 is a configuration diagram of a regulator circuit in one embodiment.
2 is a configuration diagram of an output driver according to an embodiment.
3 is a configuration diagram of a comparison unit according to an embodiment.
4 is a configuration diagram of a current supply unit according to an embodiment.
5 is a block diagram of a feedback signal generator according to an embodiment of the present invention.
6 is a configuration diagram of a semiconductor device according to an embodiment.
7 is a graph for explaining the operation of the regulator circuit according to one embodiment.
8 is a configuration diagram of an electronic system according to an embodiment.

Hereinafter, embodiments of the present technology will be described in more detail with reference to the accompanying drawings.

1 is a configuration diagram of a regulator circuit in one embodiment.

The regulator circuit 10 shown in FIG. 1 may include a comparator 110, a current supplier 120, an output driver 130, and a feedback signal generator 140.

The comparator 110 may compare the reference voltage VREF with the feedback voltage VFB. In one embodiment, the comparator 110 is enabled when the level of the feedback voltage VFB is higher than the level of the reference voltage VREF. When the level of the feedback voltage VFB is lower than the level of the reference voltage VREF And may be configured to generate a first switching signal SW1 that is disabled.

The current supply unit 120 may be configured to receive the pumping voltage PMP_SOURCE and to determine the voltage level of the second switching signal SW2 in response to the first switching signal SW1. In one embodiment, when the first switching signal SW1 is enabled, the pumping voltage PMP_SOURCE is discharged to lower the voltage level of the second switching signal SW2, and when the first switching signal SW1 is disabled The voltage level of the second switching signal SW2 is increased by an amount of current based on the pumping voltage PMP_SOURCE.

The output driver 130 may be configured to receive the pumping voltage PMP_SOURCE and to generate the output voltage VTARGET in response to the second switching signal SW2 and the output voltage VTARGET.

The output driver 130 may include, for example, an output section 132 and a control section 134. The output 132 may receive the pumping voltage PMP_SOURCE and may generate the output voltage VTARGET in response to the second switching signal SW2. The control unit 134 can control the potential level of the output unit 132 in synchronization with the output voltage VTARGET. In one embodiment, the control unit 134 may control the potential level of the output unit 132 in such a manner as to control the potential level of the second switching signal SW2 according to the level of the output voltage VTARGET.

The feedback signal generator 140 detects the level of the output voltage VTARGET and generates the feedback voltage VFB. The feedback voltage VFB may be provided to the comparator 110 described above.

In one embodiment, the output driver 130 has a level of the output voltage VTARGET based on the level of the output voltage VTARGET in addition to the level of the second switching signal SW2 generated by the current supply unit 120 .

It is assumed that the semiconductor device to which the regulator circuit 10 is applied is changed from the first operation mode to the first operation mode at the first level and then from the first operation mode to the second operation mode operation at the second operation level lower than the first operation level. The regulator circuit 10 maintains the output voltage VTARGET at the first high voltage in the first operation mode and changes and maintains the output voltage VTARGET to the second high voltage lower than the first high voltage when the mode is changed to the second operation mode shall. The output driver 130 can determine the level of the output voltage VTARGET in synchronization with the changed output voltage VTARGET when the output voltage VTARGET is changed from the first high voltage to the second high voltage, To the target level can be minimized.

In one embodiment, the output driver 130 determines the level of the output voltage VTARGET in synchronization with the changed output voltage VTARGET, which means that the control unit 134 generates a control signal based on the output voltage VTARGET , But the present invention is not limited thereto, and the output unit 132 may generate the output voltage VTARGET at the target level based on the control signal.

2 is a configuration diagram of an output driver according to an embodiment.

Referring to FIG. 2, the output driver 20 according to an exemplary embodiment may include an output unit 200 and a control unit 220.

The output unit 200 may include a first dischage unit 210, a source current supply unit 220, a second dispatch unit 230, and a feedback dispatch unit 240.

The first dischage section 210 may be configured to discharge the charge of the second switching signal SW2 supply terminal in response to the discharge signal REG_DISCH. In one embodiment, the first discreet portion 210 may include a switching element N11 connected between the second switching signal SW2 supply terminal and the ground terminal and driven in response to the discharge signal REG_DISCH, But is not limited thereto. During the discharge operation, the discharge signal REG_DISCH is enabled, so that the potential level of the second switching signal SW2 supply terminal can be lowered.

The source current supply 220 may be configured to receive the pumping voltage PMP_SOURCE and to generate the output voltage VTARGET in response to the second switching signal SW2. In one embodiment, the source current supply 220 may include a switching element N12 connected between the pumping voltage PMP_SOURCE supply terminal and the output voltage VTARGET and driven in response to the second switching signal SW2. However, the present invention is not limited thereto.

The second dischage unit 230 may be configured to discharge the charge of the output terminal (VTARGET) in response to the discharge enable signal DISCH_N and the discharge signal REG_DISCH. In one embodiment, the second discharge section 230 includes a switching element N13 connected to the power supply voltage supply terminal VCCE and driven in response to the discharge enable signal DISCH_N, And a switching element N14 connected between the ground terminals and driven in response to the discharge signal REG_DISCH. However, the present invention is not limited thereto. The discharge enable signal DISCH_N is disabled and the discharge signal REG_DISCH can be enabled during the discharge operation so that the potential level of the output terminal VTARGET can be lowered.

The feedback discard section 240 can be configured to control the level of the second switching signal SW2 based on the control voltage FBD generated based on the level of the output voltage VTARGET. In one embodiment, if the level of the output voltage VTARGET is abnormally high, the feedback dispatcher 240 may charge the second switching signal SW2 through the second dispatcher 230, Can be charged. For example, the feedback discard unit 240 may include a switching element N15 connected between the second switching signal SW2 supply terminal and the ground terminal and driven in response to the control voltage FBD, no.

Meanwhile, the control unit 220 may be configured to generate the control voltage FBD based on the level of the output voltage VTARGET. In one embodiment, the control unit 220 may include, but is not limited to, a switching element N16 diode-connected to the output terminal VTARGET to generate the control voltage FBD.

The control unit 220 shown in Fig. 2 can generate the control voltage FBD by subtracting the threshold voltage VTH1 of the switching element N16 from the level of the output voltage VTARGET. That is, it can have a level of [FBD = VTARGET-VTH1].

When the output voltage VTARGET of the regulator circuit 10 is kept constant at the target level, the threshold voltage VTH1 of the switching element N16 is set such that the switching element N15 constituting the feedback discarding section 240 is turned Off < / RTI > level.

The potential difference between the level of the output potential level of the source current supply section 220 and the level of the control voltage FBD is lower than the threshold voltage VTH2 of the switching element N15 when the output voltage VTARGET is kept constant at the target level, The element N15 is turned off. Then, the source current supply unit 220 can generate the output voltage VTARGET that is kept constant at the output voltage VTARGET.

On the other hand, when a bouncing phenomenon occurs in which the output voltage VTARGET abnormally rises, the discharge signal REG_DISCH is enabled to perform the discharging operation. In addition, the control voltage FBD generated by the control unit 220 rises and the switching element N15 constituting the feedback discard unit 240 is turned on. Accordingly, the potential of the second switching signal SW2 supply terminal is rapidly discharged through the second dischitching portion 230, and the level of the output voltage VTARGET generated from the source current supply portion 220 can also be rapidly lowered .

That is, in this embodiment, the level of the second switching signal SW2, which is the driving voltage of the source current supply unit 220, can be controlled in synchronization with the level of the output voltage VTARGET. Therefore, when the bouncing phenomenon occurs, the level of the output voltage VTARGET can be controlled at high speed.

3 is a configuration diagram of a comparison unit according to an embodiment.

The comparing unit 30 may be configured to include a comparing circuit 310 for comparing the reference voltage VREF with the feedback voltage VFB and outputting the first switching signal SW1. In one embodiment, the comparison circuit 310 is enabled when the level of the feedback voltage VFB is higher than the level of the reference voltage VREF. When the level of the feedback voltage VFB is lower than the level of the reference voltage VREF And may be configured to generate a first switching signal SW1 that is disabled.

4 is a configuration diagram of a current supply unit according to an embodiment.

The current supply unit 40 according to the embodiment may be configured to receive the pumping voltage PMP_SOURCE and to determine the voltage level of the second switching signal SW2 in response to the first switching signal SW1. In one embodiment, the current supply unit 40 includes a resistance element 410 connected between the pumping voltage supply terminal PMP_SOURCE and the output terminal of the second switching signal SW2, and a second switching signal SW2 connected between the resistance element 410 and the ground terminal, And a switching element 420 driven in response to the signal SW1.

Therefore, when the first switching signal SW1 is enabled, the switching element 420 is turned on, and accordingly, the pumping voltage PMP_SOURCE is discharged to lower the voltage level of the second switching signal SW2. On the other hand, when the first switching signal SW1 is disabled, the switching element 420 is turned off, and the voltage level of the second switching signal SW2 is increased by an amount of current based on the pumping voltage PMP_SOURCE, have.

5 is a block diagram of a feedback signal generator according to an embodiment of the present invention.

The feedback signal generator 50 according to the embodiment detects the level of the output voltage VTARGET to generate the feedback voltage VFB. To this end, the feedback signal generator 50 may be configured to include a resistor chain 510 connected in series between the output terminal (VTARGET) and the ground terminal. The feedback voltage VFB may be provided to the comparator 110 described above.

The configurations of the comparator 30, the current supply unit 40, and the feedback signal generator 50 shown in FIGS. 3 to 5 are merely examples, and the design change may be made to include other components capable of performing the respective functions Of course it is possible.

Regardless of how each constituent unit is structured in detail, the regulator circuit 10 according to the present embodiment configures the output drivers 13 and 20 so that the level of the output voltage VTARGET depends on the level of the output voltage VTARGET . Therefore, when the discharge voltage VTARGET rises abnormally, the output voltage VTARGET can be returned to the normal level at a high speed.

6 is a configuration diagram of a semiconductor device according to an embodiment.

The semiconductor device 60 according to one embodiment may include a memory circuit portion 610, a controller 620, and a voltage supply portion 630.

The memory circuit unit 610 may include a column control unit and a row control unit. The semiconductor memory device may further include a plurality of memory cells connected between the plurality of word lines and the plurality of bit lines.

The controller 620 can control the operation of the memory circuit unit 610, for example, program, erase, read operation, and the like.

The voltage supply unit 630 may supply the memory circuit unit 610 with an output voltage VTARGET that is maintained at a constant level by pumping the external voltage VEXT.

The voltage supply unit 630 includes a high voltage generation circuit 631 for pumping the external voltage VEXT to generate the pumping voltage PMP_SOURCE and a regulator circuit 633 for generating the pumping voltage PMP_SOURCE to an output voltage VTARGET of a certain level ).

The regulator circuit 633 may be the regulator circuit described with reference to Figs.

7 is a graph for explaining the operation of the regulator circuit according to one embodiment.

The output voltage VTARGET generated by the regulator circuit 10 may be maintained at a constant level and abnormally raised due to the bouncing phenomenon. In this case, the discharge operation is performed by enabling the discharge signal REG_DISCH as shown in the graph (a), but a time (T1) of several microseconds is required until returning to the normal level (VTARGET). Since the semiconductor device can operate normally after this time Tl, the operation speed can be lowered.

On the other hand, in this embodiment, the level of the output voltage VTARGET is controlled according to its own level. That is, as shown in FIG. 2, the charge of the supply terminal of the second switching signal SW2 is discharged by the control voltage FBD generated according to the level of the output voltage VTARGET, 220) reacts rapidly.

Accordingly, immediately after the bouncing (T2), the output voltage (VTARGET) applying end can be immediately returned to the normal level (VTARGET), and the semiconductor device can perform normal operation at high speed.

8 is a configuration diagram of an electronic system according to an embodiment.

The electronic system 70 according to one embodiment includes a processor 710, a memory controller 720, a memory device 721, an IO controller 730, an IO device 731, a disk controller 740 and a disk driver 741 ).

At least one processor 710 may be provided and may operate independently or in conjunction with another processor. The processor 710 has an environment capable of communicating with other elements, such as a memory controller 720, an IO controller 730, and a disk controller 740 via a bus (control bus, address bus, data bus) have.

The memory controller 720 is connected to at least one memory device 721. Memory controller 720 receives the request from processor 710 and controls at least one memory device 721 based thereon.

The memory device 721 may be, for example, the semiconductor memory device shown in Fig. 6 described above.

The IO controller 730 is connected between the processor 710 and the IO device 731 and transfers the input from the IO device 731 to the processor 710 or the processing result of the processor 710 to the IO device 731 . The IO device 731 may include an input device such as a keyboard, a mouse, a touch screen, a microphone, etc., and an output device such as a display, a speaker, and the like.

The disk controller 740 may control at least one disk driver 741 under the control of the processor 710.

In this electronic system 70, when the memory device 721 is operated under the control of the processor 710, the voltage supply portion provided in the semiconductor memory device 721 is, for example, Circuit. ≪ / RTI > Therefore, it is possible to control the potential level of the output terminal VTARGET in synchronization with the level of the output voltage VTARGET. Therefore, when the bouncing phenomenon occurs and the level of the output voltage VTARGET rises abnormally, the level of the output voltage VTARGET can be returned to the normal level at a high speed.

Thus, those skilled in the art will appreciate that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

10: Regulator circuit
130, 20: Output driver
200: Output section
220:
110, 30:
120, 40: current supply unit
140, 50: a feedback signal generator
60: Semiconductor device
630:
70: Electronic system

Claims (15)

A comparator comparing the reference voltage and the feedback voltage to generate a first switching signal;
A current supplier receiving a pumping voltage and determining a level of a second switching signal in response to the first switching signal;
An output driver for controlling a level of the second switching signal in response to an output voltage and receiving the pumping voltage to generate the output voltage in response to the second switching signal; And
A feedback signal generator for detecting the level of the output voltage to generate the feedback voltage;
And a regulator circuit. The method according to claim 1,
The output driver comprising: an output receiving the pumping voltage and generating the output voltage in response to the second switching signal; And
A control unit for controlling the level of the second switching signal based on the level of the output voltage;
And a regulator circuit. The method according to claim 1,
Wherein the output driver comprises: a first despatcher for controlling a potential level of the second switching signal supply terminal in response to a discharge signal;
A source current supply unit receiving the pumping voltage and generating the output voltage in response to the second switching signal;
A second despatching unit for controlling a potential level of the output voltage applying stage in response to the discharge signal; And
A feedback discovery section for controlling a potential level of the second switching signal in response to a control voltage generated based on a level of the output voltage;
And a regulator circuit. The method of claim 3,
And a switching element diode-connected to the output voltage applying terminal to generate the control voltage. 5. The method of claim 4,
Wherein the threshold voltage of the switching element is determined to disable the feedback discharge section when the output voltage maintains a predetermined target level. The method according to claim 1,
Wherein the current supply unit lowers the level of the second switching signal by discharging the pumping voltage when the first switching signal is enabled and when the first switching signal is disabled, A regulator circuit configured to raise the level of a signal. An output unit receiving the pumping voltage and being driven according to the switching signal to generate an output voltage; And
A control unit for controlling a level of the switching signal based on a level of the output voltage;
And a regulator circuit. 8. The method of claim 7,
And the control unit is configured to include a switching element diode-connected to the output voltage applying terminal to generate a control signal. 9. The method of claim 8,
And the output section is configured to include a feedback discharge section that is driven in response to the control signal to control a level of the switching signal. 10. The method of claim 9,
Wherein the threshold voltage of the switching element is determined to disable the feedback discharge section when the output voltage maintains a predetermined target level. controller;
A memory circuit portion controlled by the controller; And
And a voltage supply unit for providing an output voltage to the memory circuit unit under the control of the controller,
The voltage supply unit may include: a comparator that compares a reference voltage with a feedback voltage to generate a first switching signal;
A current supplier receiving a pumping voltage and determining a level of a second switching signal in response to the first switching signal;
An output driver for controlling the level of the second switching signal in response to the output voltage and receiving the pumping voltage to generate the output voltage in response to the second switching signal; And
A feedback signal generator for detecting the level of the output voltage to generate the feedback voltage;
The semiconductor device comprising: a semiconductor substrate; 12. The method of claim 11,
The output driver comprising: an output receiving the pumping voltage and generating the output voltage in response to the second switching signal; And
A control unit for controlling the level of the second switching signal based on the level of the output voltage;
. 12. The method of claim 11,
Wherein the output driver comprises: a first despatcher for controlling a potential level of the second switching signal supply terminal in response to a discharge signal;
A source current supply unit receiving the pumping voltage and generating the output voltage in response to the second switching signal;
A second despatching unit for controlling a potential level of the output voltage applying stage in response to the discharge signal; And
A feedback discovery section for controlling a potential level of the second switching signal in response to a control voltage generated based on a level of the output voltage;
The semiconductor device comprising: a semiconductor substrate; 14. The method of claim 13,
And a switching element diode-connected to the output voltage applying terminal to generate the control voltage. 15. The method of claim 14,
Wherein the threshold voltage of the switching element is determined to disable the feedback discharge section when the output voltage maintains a predetermined target level.
KR1020150064844A 2015-03-19 2015-05-08 Regulator Circuit and Semiconductor Memory Apparatus Having the Same KR20160112894A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US14/740,400 US9520163B2 (en) 2015-03-19 2015-06-16 Regulator circuit and semiconductor memory apparatus having the same
CN201510627565.7A CN105989892B (en) 2015-03-19 2015-09-28 Regulator circuit and semiconductor memory device having the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20150038195 2015-03-19
KR1020150038195 2015-03-19

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