KR20160112894A - Regulator Circuit and Semiconductor Memory Apparatus Having the Same - Google Patents
Regulator Circuit and Semiconductor Memory Apparatus Having the Same Download PDFInfo
- Publication number
- KR20160112894A KR20160112894A KR1020150064844A KR20150064844A KR20160112894A KR 20160112894 A KR20160112894 A KR 20160112894A KR 1020150064844 A KR1020150064844 A KR 1020150064844A KR 20150064844 A KR20150064844 A KR 20150064844A KR 20160112894 A KR20160112894 A KR 20160112894A
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- South Korea
- Prior art keywords
- voltage
- level
- switching signal
- output voltage
- output
- Prior art date
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/142—Contactless power supplies, e.g. RF, induction, or IR
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
- G11C5/146—Substrate bias generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
Abstract
Description
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a regulator circuit and a semiconductor device having the same.
A semiconductor integrated circuit is a complex electronic device of a very small structure in which a large number of electronic devices are bonded on a substrate. Power is required to operate the semiconductor integrated circuit. The voltage supply unit is a circuit unit that converts an external power supply to an internal power supply, thereby supplying a predetermined level of power to each element on the substrate.
Generally, a low level voltage is supplied to the semiconductor integrated circuit. However, in many cases, a semiconductor integrated circuit requires a high voltage in order to actually operate the semiconductor integrated circuit. Accordingly, the voltage supply unit may include a pump capable of pumping an external voltage input at a low level to generate a high voltage. And how fast the pump can raise the voltage to the target level can be one of the factors determining the operating speed of the semiconductor integrated circuit.
For example, a flash memory device requires a high voltage during a program or erase operation. The voltage supply unit must be capable of generating a predetermined level of the program voltage or the erase voltage in accordance with the operation mode of the flash memory device. Also, as the time required to generate and provide the program voltage or erase voltage of a predetermined level is reduced, the total time for performing the program or erase can be reduced.
The output voltage of the voltage supply unit must be kept constant at a desired level, and a regulator circuit may be used for this purpose.
The regulator circuit detects the pumped voltage and determines whether the pump operates according to a comparison of the detected voltage with a reference voltage.
The required voltage level of the semiconductor integrated circuit varies depending on the operation mode. Thus, depending on the mode of operation, the pump must generate a predetermined high level of voltage, and the generated high level voltage must be maintained at that level in the regulator circuit. In addition, when the required voltage level changes and the output voltage of the pump changes, the regulator circuit is also required to maintain a high voltage at the changed level in response.
This series of high-voltage supply operation can be an element that determines operation reliability as well as operation speed of a semiconductor integrated circuit.
Embodiments of the present invention can provide a regulator circuit capable of stably generating an internal voltage and a semiconductor device having the regulator circuit.
A regulator circuit according to an embodiment of the present invention includes a comparator for comparing a reference voltage and a feedback voltage to generate a first switching signal; A current supplier receiving a pumping voltage and determining a level of a second switching signal in response to the first switching signal; An output driver for controlling a level of the second switching signal in response to an output voltage and receiving the pumping voltage to generate the output voltage in response to the second switching signal; And a feedback signal generator for detecting the level of the output voltage to generate the feedback voltage.
According to another aspect of the present invention, there is provided a regulator circuit including: an output unit receiving a pumping voltage and being driven according to a switching signal to generate an output voltage; And a control unit for controlling the level of the switching signal based on the level of the output voltage.
A semiconductor device according to an embodiment of the present invention includes a controller; A memory circuit portion controlled by the controller; And a voltage supply unit for providing an output voltage to the memory circuit unit under the control of the controller, wherein the voltage supply unit comprises: a comparator for comparing the reference voltage and the feedback voltage to generate a first switching signal; A current supplier receiving a pumping voltage and determining a level of a second switching signal in response to the first switching signal; An output driver for controlling the level of the second switching signal in response to the output voltage and receiving the pumping voltage to generate the output voltage in response to the second switching signal; And a feedback signal generator for detecting the level of the output voltage to generate the feedback voltage.
According to this technique, an internal voltage can be stably generated.
1 is a configuration diagram of a regulator circuit in one embodiment.
2 is a configuration diagram of an output driver according to an embodiment.
3 is a configuration diagram of a comparison unit according to an embodiment.
4 is a configuration diagram of a current supply unit according to an embodiment.
5 is a block diagram of a feedback signal generator according to an embodiment of the present invention.
6 is a configuration diagram of a semiconductor device according to an embodiment.
7 is a graph for explaining the operation of the regulator circuit according to one embodiment.
8 is a configuration diagram of an electronic system according to an embodiment.
Hereinafter, embodiments of the present technology will be described in more detail with reference to the accompanying drawings.
1 is a configuration diagram of a regulator circuit in one embodiment.
The
The
The
The
The
The
In one embodiment, the
It is assumed that the semiconductor device to which the
In one embodiment, the
2 is a configuration diagram of an output driver according to an embodiment.
Referring to FIG. 2, the
The
The
The source
The
The feedback discard
Meanwhile, the
The
When the output voltage VTARGET of the
The potential difference between the level of the output potential level of the source
On the other hand, when a bouncing phenomenon occurs in which the output voltage VTARGET abnormally rises, the discharge signal REG_DISCH is enabled to perform the discharging operation. In addition, the control voltage FBD generated by the
That is, in this embodiment, the level of the second switching signal SW2, which is the driving voltage of the source
3 is a configuration diagram of a comparison unit according to an embodiment.
The comparing
4 is a configuration diagram of a current supply unit according to an embodiment.
The
Therefore, when the first switching signal SW1 is enabled, the switching
5 is a block diagram of a feedback signal generator according to an embodiment of the present invention.
The
The configurations of the
Regardless of how each constituent unit is structured in detail, the
6 is a configuration diagram of a semiconductor device according to an embodiment.
The
The
The
The
The
The
7 is a graph for explaining the operation of the regulator circuit according to one embodiment.
The output voltage VTARGET generated by the
On the other hand, in this embodiment, the level of the output voltage VTARGET is controlled according to its own level. That is, as shown in FIG. 2, the charge of the supply terminal of the second switching signal SW2 is discharged by the control voltage FBD generated according to the level of the output voltage VTARGET, 220) reacts rapidly.
Accordingly, immediately after the bouncing (T2), the output voltage (VTARGET) applying end can be immediately returned to the normal level (VTARGET), and the semiconductor device can perform normal operation at high speed.
8 is a configuration diagram of an electronic system according to an embodiment.
The
At least one
The
The
The
The
In this
Thus, those skilled in the art will appreciate that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.
10: Regulator circuit
130, 20: Output driver
200: Output section
220:
110, 30:
120, 40: current supply unit
140, 50: a feedback signal generator
60: Semiconductor device
630:
70: Electronic system
Claims (15)
A current supplier receiving a pumping voltage and determining a level of a second switching signal in response to the first switching signal;
An output driver for controlling a level of the second switching signal in response to an output voltage and receiving the pumping voltage to generate the output voltage in response to the second switching signal; And
A feedback signal generator for detecting the level of the output voltage to generate the feedback voltage;
And a regulator circuit.
The output driver comprising: an output receiving the pumping voltage and generating the output voltage in response to the second switching signal; And
A control unit for controlling the level of the second switching signal based on the level of the output voltage;
And a regulator circuit.
Wherein the output driver comprises: a first despatcher for controlling a potential level of the second switching signal supply terminal in response to a discharge signal;
A source current supply unit receiving the pumping voltage and generating the output voltage in response to the second switching signal;
A second despatching unit for controlling a potential level of the output voltage applying stage in response to the discharge signal; And
A feedback discovery section for controlling a potential level of the second switching signal in response to a control voltage generated based on a level of the output voltage;
And a regulator circuit.
And a switching element diode-connected to the output voltage applying terminal to generate the control voltage.
Wherein the threshold voltage of the switching element is determined to disable the feedback discharge section when the output voltage maintains a predetermined target level.
Wherein the current supply unit lowers the level of the second switching signal by discharging the pumping voltage when the first switching signal is enabled and when the first switching signal is disabled, A regulator circuit configured to raise the level of a signal.
A control unit for controlling a level of the switching signal based on a level of the output voltage;
And a regulator circuit.
And the control unit is configured to include a switching element diode-connected to the output voltage applying terminal to generate a control signal.
And the output section is configured to include a feedback discharge section that is driven in response to the control signal to control a level of the switching signal.
Wherein the threshold voltage of the switching element is determined to disable the feedback discharge section when the output voltage maintains a predetermined target level.
A memory circuit portion controlled by the controller; And
And a voltage supply unit for providing an output voltage to the memory circuit unit under the control of the controller,
The voltage supply unit may include: a comparator that compares a reference voltage with a feedback voltage to generate a first switching signal;
A current supplier receiving a pumping voltage and determining a level of a second switching signal in response to the first switching signal;
An output driver for controlling the level of the second switching signal in response to the output voltage and receiving the pumping voltage to generate the output voltage in response to the second switching signal; And
A feedback signal generator for detecting the level of the output voltage to generate the feedback voltage;
The semiconductor device comprising: a semiconductor substrate;
The output driver comprising: an output receiving the pumping voltage and generating the output voltage in response to the second switching signal; And
A control unit for controlling the level of the second switching signal based on the level of the output voltage;
.
Wherein the output driver comprises: a first despatcher for controlling a potential level of the second switching signal supply terminal in response to a discharge signal;
A source current supply unit receiving the pumping voltage and generating the output voltage in response to the second switching signal;
A second despatching unit for controlling a potential level of the output voltage applying stage in response to the discharge signal; And
A feedback discovery section for controlling a potential level of the second switching signal in response to a control voltage generated based on a level of the output voltage;
The semiconductor device comprising: a semiconductor substrate;
And a switching element diode-connected to the output voltage applying terminal to generate the control voltage.
Wherein the threshold voltage of the switching element is determined to disable the feedback discharge section when the output voltage maintains a predetermined target level.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/740,400 US9520163B2 (en) | 2015-03-19 | 2015-06-16 | Regulator circuit and semiconductor memory apparatus having the same |
CN201510627565.7A CN105989892B (en) | 2015-03-19 | 2015-09-28 | Regulator circuit and semiconductor memory device having the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR20150038195 | 2015-03-19 | ||
KR1020150038195 | 2015-03-19 |
Publications (1)
Publication Number | Publication Date |
---|---|
KR20160112894A true KR20160112894A (en) | 2016-09-28 |
Family
ID=57101955
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR1020150064844A KR20160112894A (en) | 2015-03-19 | 2015-05-08 | Regulator Circuit and Semiconductor Memory Apparatus Having the Same |
Country Status (1)
Country | Link |
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KR (1) | KR20160112894A (en) |
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2015
- 2015-05-08 KR KR1020150064844A patent/KR20160112894A/en unknown
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