KR20160109986A - Vertical memory devices and methods of manufacturing the same - Google Patents

Abstract

A vertical memory device includes: a substrate; gate lines stacked from the upper surface of the substrate in a vertical direction to be placed apart from each other, each of the gate lines including a stair portion protruding in a horizontal direction; channels penetrating the gate lines in the vertical direction; contacts disposed on the stair portions of the gate lines; and a contact spacer selectively formed on each of the side walls of some of the contacts. Therefore, the vertical memory device can prevent the damage to a contact profile.

Description

TECHNICAL FIELD [0001] The present invention relates to a vertical memory device and a method of manufacturing the same,

The present invention relates to a vertical memory device and a method of manufacturing the same. More particularly, the present invention relates to a vertical memory device including gate lines stacked in a vertical direction and a method of manufacturing the same.

Recently, vertical memory devices in which memory cells are vertically stacked from the substrate surface are being developed for high integration of memory devices. In the vertical memory device, a column or cylinder shaped channel vertically protruding from the upper surface of the substrate is provided, and a plurality of gate lines and insulating films in contact with the channel may be stacked.

In order to increase the capacity of the vertical memory device, it is possible to stack more gate lines and insulating films in the vertical direction, but higher process reliability may be required.

It is an object of the present invention to provide a vertical memory device having high mechanical and structural reliability.

An object of the present invention is to provide a method of manufacturing a vertical type memory device having high mechanical and structural reliability.

However, the problems to be solved by the present invention are not limited to the above-mentioned problems, and can be variously extended without departing from the spirit and scope of the present invention

According to another aspect of the present invention, there is provided a vertical memory device including a substrate, gate lines stacked vertically from the upper surface of the substrate and including a stepped portion protruding in a horizontal direction, A plurality of contact spacers formed on the sidewalls of the plurality of contacts, and a plurality of contact spacers formed on the sidewalls of the plurality of contacts, respectively.

In exemplary embodiments, the contact spacers may comprise silicon nitride or silicon oxynitride.

In exemplary embodiments, the vertical memory device may further include a mold passivation layer covering the upper surfaces and sides of the steps and including silicon oxide.

In exemplary embodiments, the contact spacer may receive the contacts and may penetrate the mold protection film. The contacts of the contacts, other than the contacts partially formed with the contact spacers, may directly contact the mold protecting film and penetrate the mold protecting film.

In exemplary embodiments, the substrate may include a channel region in which the channels are arranged, and a first region and a second region that are sequentially arranged in the horizontal direction from the channel region. The contacts may include first contacts that are seated on the steps included in the first region and second contacts that are seated on the steps that are included in the second region.

In exemplary embodiments, a first contact spacer may be formed on each sidewall of the first contacts.

In exemplary embodiments, the gate lines may include a ground selection line (GSL), word lines, and a string selection line (SSL) that are sequentially stacked from the top surface of the substrate. The first contacts may be electrically coupled to the SSL, and to a predetermined number of upper word lines adjacent to the SSL among the word lines.

In the exemplary embodiments, the second contacts may be electrically connected to the remaining word lines except the upper word lines, and GSL. The contact spacers may be omitted on the sidewalls of the second contacts.

In exemplary embodiments, the substrate further includes a third region extending from the second region, the contacts further including third contacts electrically connected to the steps included in the third region can do.

In the exemplary embodiments, the first area, the second area, and the third area may be allocated according to the photo process sequence. A second contact spacer is formed on each sidewall of the second contacts, and the contact spacers may be omitted on the sidewalls of the third contacts.

In the exemplary embodiments, the vertical memory device includes a peripheral circuit disposed at a periphery of the substrate, a top surface and sides of the top and bottom portions, and a mold protection film covering the peripheral circuit, And a peripheral circuit contact which is in contact with and is electrically connected to the peripheral circuit through the mold protection film.

In the exemplary embodiments, the contacts may be arranged in a zigzag fashion along the horizontal direction.

In exemplary embodiments, some of the contacts formed with the contact spacers may be selectively arranged on odd-numbered or even-numbered ones of the steps.

According to an aspect of the present invention, a vertical memory device includes a substrate, a gate line structure, gate line contacts, a peripheral circuit contact, and a contact spacer. The substrate includes a channel region, a contact region, and a peripheral circuit region. Wherein the gate line structure includes gate lines arranged on the channel region and the contact region and stacked vertically on the substrate and including a stepped portion protruding into the contact region, And channels that pass through the gate lines and the interlayer dielectric film patterns in the vertical direction on the channel region. The gate line contacts are electrically connected to the gate lines on the contact region. The peripheral circuit contacts are disposed on the peripheral circuit area. The contact spacers are selectively formed only on the sidewalls of the contacts of the gate line contacts and some of the peripheral circuit contacts.

In exemplary embodiments, the contact spacers may be selectively formed only on the sidewalls of the gate line contacts of some of the gate line contacts.

In exemplary embodiments, the contact spacers may be selectively formed only on the sidewalls of the predetermined number of upper gate line contacts of the gate line contacts.

In exemplary embodiments, the gate line contacts may be arranged in a horizontal direction with respect to an upper surface of the substrate so that a contact row may be defined. A plurality of the contact rows may be arranged on one of the gate line structures.

In exemplary embodiments, the gate line contacts belonging to different contact rows may be arranged in a zigzag fashion from one another on the same plane.

In exemplary embodiments, the same gate line contacts belonging to the same contact row may be mounted in a frustum form on the steps.

In exemplary embodiments, the contact rows include a first contact row comprised of the gate line contacts formed with the contact spacer, and a second contact row comprised of the gate line contacts excluded from the contact spacer .

According to another aspect of the present invention, there is provided a method of manufacturing a vertical type memory device, comprising: forming a stepped mold structure in which a plurality of films are stacked on a substrate; Forming channels through the stepped mold structure. Thereby forming a mold protecting film at least partially covering the stepped mold structure. And a gate line structure is formed by replacing the films of a part of the stepped mold structure with gate lines. Through the plurality of photo processes, contact holes are formed through the mold protecting film to expose the gate lines. And selectively forming contact spacers on sidewalls of the contact holes formed through a specific photo process of the plurality of photo processes. Thereby forming contacts within the contact holes.

In exemplary embodiments, the specific photo process may comprise an initial photo process of the plurality of photo processes.

In exemplary embodiments, the plurality of photo processes include a first photo process, a second photo process, and a third photo process, wherein the specific photo process includes the first photo process and the second photo process can do.

In exemplary embodiments, peripheral circuitry may be formed on the substrate prior to forming the stepped mold structure. A peripheral circuit contact hole may be formed through the mold protective film to at least partially expose the peripheral circuit. To form peripheral circuit contacts that fill the peripheral circuit contact holes.

In exemplary embodiments, the peripheral circuit contact holes may be formed through a photo process included in the plurality of photo processes.

In exemplary embodiments, the peripheral circuit contact holes may be formed through a final photo process of the plurality of photo processes.

In exemplary embodiments, the peripheral circuit contact holes may be formed through the same photolithography process as at least some of the contact holes in which the contact spacers are not formed.

According to another aspect of the present invention, there is provided a method of manufacturing a vertical type memory device including a channel region, a contact region, and a peripheral circuit region. Interlayer insulating films and sacrificial films are alternately and repeatedly laminated on the substrate to form a mold structure. The mold structure portion formed on the peripheral circuit region is removed. The side of the mold structure formed on the contact area is partially etched to form a stepped mold structure. A mold protecting film is formed to cover the side portions of the stepped mold structure. Forming channels through the stepped mold structure. And replacing the sacrificial layers included in the stepped mold structure with gate lines. And the first contact holes are formed through the mold protective film to expose the upper surfaces of gate lines of a part of the gate lines. A contact spacer is formed on each side wall of the first contact holes. And second contact holes are formed through the mold protection film to expose top surfaces of gate lines excluding the gate lines where the first contact holes are formed. A peripheral circuit contact hole is formed through the mold protecting film to expose the peripheral circuit region. Thereby forming contacts that fill the first contact holes, the second contact holes, and the peripheral circuit contact holes.

In exemplary embodiments, contacts formed in at least a portion of the second contact holes and in the peripheral circuit contact hole of the contacts may be in direct contact with the mold protection layer.

In exemplary embodiments, the at least a portion of the second contact holes and the peripheral circuit contact hole may be formed through the same photo process.

In exemplary embodiments, the gate lines may include a ground selection line (GSL), word lines, and a string selection line (SSL) that are sequentially stacked from the top surface of the substrate. And the upper surface of the SSL can be exposed by the first contact holes. The peripheral circuit contact hole may be formed through the same photolithography process as the contact hole exposing the upper surface of the GSL among the second contact holes.

According to the above-described exemplary embodiments, contact spacers may optionally be formed on the sidewalls of the contacts of some of the contacts that are connected to the stepped pads of the vertical memory device. For example, after forming the first contact holes exposing the pads of the upper steps by the first photolithography process, the contact spacers may be formed on the sidewalls of the first contact holes. Thus, etching gas or the like generated from the first contact hole can be blocked while the subsequent photolithography process is performed, and contact profile damage can be prevented.

1 and 2 are a cross-sectional view and a plan view, respectively, showing a vertical memory device according to exemplary embodiments.
FIGS. 3 to 29 are cross-sectional views and plan views for explaining a method of manufacturing a vertical type memory device according to exemplary embodiments.
30 and 31 are cross-sectional views and plan views, respectively, illustrating a vertical memory device according to some exemplary embodiments.
32 to 38 are sectional views for explaining a method of manufacturing a vertical type memory device according to some exemplary embodiments.
39 is a cross-sectional view illustrating a vertical memory device according to exemplary embodiments.
40 to 46 are sectional views for explaining a method of manufacturing a vertical type memory device according to exemplary embodiments.
Figures 47-49 are top and cross-sectional views illustrating a vertical memory device according to exemplary embodiments.
Figures 50-52 are top and cross-sectional views illustrating a vertical memory device in accordance with exemplary embodiments.
FIGS. 53 to 61 are a plan view and a cross-sectional view for explaining a method of manufacturing a vertical type memory device according to exemplary embodiments.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, The present invention should not be construed as limited to the embodiments described in Figs.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It is to be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but on the contrary, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprise", "having", and the like are intended to specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, , Steps, operations, components, parts, or combinations thereof, as a matter of principle.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be construed as meaning consistent with meaning in the context of the relevant art and are not to be construed as ideal or overly formal in meaning unless expressly defined in the present application .

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 and 2 are a cross-sectional view and a plan view, respectively, showing a vertical memory device according to exemplary embodiments. For example, FIG. 1 is a cross-sectional view taken along line I-I 'of FIG. 2 in a first direction.

In FIGS. 1 and 2, a direction substantially perpendicular to the upper surface of the substrate is defined as the first direction. Two directions parallel to the upper surface of the substrate and intersecting with each other are defined as a second direction and a third direction, respectively. For example, the second direction and the third direction may be substantially perpendicular to each other. The direction indicated by the arrow in the figure and the direction opposite thereto are described in the same direction. The definition of the above-mentioned direction can be applied equally to all subsequent drawings.

1 and 2, the vertical memory device includes a channel 123, a dielectric film structure 120, and a first buried film pattern 125 that protrude from the upper surface of the substrate 100 in the first direction, Gate lines 150 that are stacked in a step-like manner around the vertical channel structure and along the first direction, and contacts 190 and 195 that are electrically connected to the gate lines 150, . ≪ / RTI >

The substrate 100 may comprise a semiconductor material, such as, for example, silicon, germanium. In some embodiments, the substrate 100 may comprise monocrystalline silicon. For example, the substrate 100 may function as a p-type well of the vertical memory device.

According to exemplary embodiments, the substrate 100 may include a channel region C, a first region I, and a second region II. For example, the vertical channel structure may be disposed in the channel region C. First contacts 190 may be disposed in the first region I. And second contacts 195 may be disposed in the second region II. The first region I and the second region II may be the first contact region and the second contact region assigned for the formation of the contacts 190 and 195. [ The first region I and the second region II may be a first photo region and a second photo region for the formation of the contacts 190 and 195. The first region I and the second region II may be sequentially arranged in the third direction from the channel region C. [

In some embodiments, the first region I and the second region II may be arranged symmetrically with respect to each other with the channel region C therebetween. For example, a central portion of the substrate 100 is assigned to a channel region C, and a first region I and a second region II may be assigned to both sides of the channel region C, respectively.

The channel 123 may be disposed on the channel region C of the substrate 100 and may contact the upper surface of the substrate 100. The channel 123 may have an internal hollow or cup shape. The channel 123 may include polysilicon or monocrystalline silicon, and may include a p-type impurity such as boron (B) in some regions.

A first buried film pattern 125 having a pillar shape or a hollow cylindrical shape may be formed in the inner space of the channel 123. The first buried film pattern 125 may include an insulating material such as silicon oxide. In one embodiment, the channel 123 may have a pillar or hollow cylindrical shape. In this case, the first buried film pattern 125 may be omitted.

The dielectric film structure 120 may surround the outer wall of the channel 123 and may have a cup shape or a straw shape substantially opened at the bottom center portion.

The dielectric film structure 120 may include a tunnel insulating film, a charge storage film, and a blocking film sequentially stacked from the outer wall of the channel 123, though not specifically shown. The blocking film may comprise silicon oxide, or a metal oxide such as hafnium oxide or aluminum oxide. The charge storage layer may include a nitride or a metal oxide such as silicon nitride, and the tunnel insulating layer may include an oxide such as silicon oxide. For example, the stacking structure of the blocking film, the charge storage film, and the tunnel insulating film may have an ONO (Oxide-Nitride-Oxide) structure in which an oxide-nitride film-oxide film is sequentially laminated.

In one embodiment, a semiconductor pattern (not shown) disposed between the top surface of the substrate 100 and the bottom surface of the channel 123 may be additionally formed. In this case, the channel 123 may be provided on the upper surface of the semiconductor pattern, and the dielectric layer structure 120 may be provided on the peripheral portion of the upper surface of the semiconductor pattern. The semiconductor pattern may comprise, for example, monocrystalline silicon or polysilicon.

The pad 130 may be formed on the dielectric film structure 120, the channel 123, and the first buried film pattern 125. For example, the pad 130 may have a shape to cap the dielectric film structure 120, the channel 123, and the first buried film pattern 125 thereon.

The pad 130 may function as a source / drain, for example, electrically connected to the bit line 199 and moving charge into the channel 123. The pad 130 may comprise polysilicon or monocrystalline silicon And may further include n-type impurities such as phosphorus (P), arsenic (As), and the like.

A plurality of pads 130 may be arranged in the third direction in the channel region C to define pad rows and a plurality of the pad rows may be arranged along the second direction. The vertical channel structure including the dielectric film structure 120, the channel 123, and the first buried film pattern 125 may also be arranged in accordance with the arrangement of the pads 130. For example, a plurality of the vertical channel structures may be arranged in the third direction in the channel region C to define a channel row, and a plurality of the channel rows may be arranged along the second direction.

Gate lines 150 (e.g., 150a-150k) may be formed on the outer wall of dielectric layer structure 120 and stacked to be spaced apart from one another along the first direction. According to exemplary embodiments, each gate line 150 may extend in the third direction, partially surrounding the channels 123 or the vertical channel structures included in the plurality of channel rows.

In some embodiments, one gate line 150 may surround and extend the channel rows formed corresponding to, for example, four of the pad rows. In this case, the gate line structure can be defined by the four channel lines and the gate lines 150 surrounding the channel lines. A plurality of the gate line structures may be arranged along the second direction.

According to exemplary embodiments, the gate lines 150 may be stacked in a shape that decreases in length or width along the third direction sequentially from the upper surface of the substrate 100. For example, as shown in FIG. 1, a plurality of gate lines 150 may be stacked in a pyramid shape or a step shape along the first direction. Accordingly, the gate line 150 of each layer may include a step portion protruding in the third direction from the gate line 150 of the upper layer, and the step portion of the gate line 150 of each layer may include the contact 190, 195 may be provided as a pad for seating.

The gate lines 150 may include a ground selection line (GSL), a word line, and a string selection line (SSL). For example, the lowermost gate line 150a may be provided with the GSL, and the uppermost two gate lines 150j and 150k may be provided with the SSL. The gate lines 150b to 150i between the GSL and the SSL may be provided as the word lines. As shown in FIG. 1, in one of the gate line structures, eight layers of gate lines 150 may be provided in the word line. However, the word lines may be stacked in a high-rise structure such as 16 layers, 24 layers, 32 layers, 48 layers, etc. in consideration of the circuit design design and / or the capacity or integration degree of the vertical memory device.

The gate line 150 may comprise a metal or a metal nitride. For example, the gate line 150 may comprise a low resistance metal or metal nitride such as tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, platinum, and the like. In some embodiments, the gate line 150 may have a multilayer structure in which a barrier film comprising a metal nitride and a metal film comprising a metal are stacked.

Interlayer insulating layer patterns 106 (for example, 106a to 1061) may be provided between adjacent gate lines 150 along the first direction. The interlayer insulating film pattern 106 may include an oxide-based material such as silicon oxide (SiO ₂ ), silicon oxycarbide (SiOC), or silicon oxyfluoride (SiOF). The gate lines 150 included in one of the gate line structures can be insulated from each other by the interlayer insulating film patterns 106. According to exemplary embodiments, the interlayer insulating film patterns 106 may be stacked along the first direction in a pyramid shape or a step shape substantially identical to or similar to the gate lines 150. [

A mold protecting layer 110 may be formed on the substrate 100 to protect the sides of the gate line structure. For example, the mold protective film 110 may contact the steps of the gate lines 150. The mold protection film 110 may include an insulating material such as silicon oxide.

A second embedded film pattern 160 may be disposed between adjacent gate line structures. For example, the second buried film pattern 160 may have a line pattern shape that cuts the gate lines 150, the interlayer insulating film patterns 106, and the mold protecting film 110 and extends in the third direction . The second buried film pattern 160 may be provided in a gate line cut pattern to define the gate line structure.

An impurity region 101 (see FIG. 18) may be formed on the substrate 100 under the second buried film pattern 160. The impurity region 101 extends in the third direction and may be provided as a common source line (CSL) of the vertical memory device.

The first contacts 190 and the second contacts 195 may be arranged on the first region I and the second region II of the substrate 100, respectively. The first contacts 190 may be in contact with or electrically connected to the stepped portions of the gate lines 105 through the uppermost interlayer insulating film pattern 1061 or the mold protecting film 110. [

According to exemplary embodiments, the stepped portions of the upper gate lines 150 included in the gate line structure may be included in the first region I. Accordingly, the first contacts 190 can be seated on the stepped portions of the predetermined number of gate lines (for example, 150f to 150k) in the upper portion. For example, the first contacts 190 may be seated on the SSL and some word lines at the top.

In the exemplary embodiments, first contact spacers 182 may be formed on the sidewalls of first contacts 190, respectively. In this case, the first contact spacer 182 may have a straw shape that passes through the uppermost interlayer insulating film pattern 1061 or the mold protecting film 110 to surround the first contact 190.

For example, the first contact spacer 182 may comprise silicon nitride or silicon oxynitride.

In the second region II, the steps of the remaining gate lines 150 may be included except for the gate lines 150 covered by the first region I. For example, the second contacts 195 may pass through the mold protection layer 110 and may be electrically connected to the stepped portions of lower gate lines (e.g., 150a-150e) included in the gate line structure Can be connected. For example, the second contacts 195 may be seated on the remaining word lines and the GSL.

According to exemplary embodiments, contact spacers may not be formed on the sidewalls of the second contacts 195. [ Thus, the sidewall of the second contact 195 may be in direct contact with the mold protective film 110.

As shown in FIG. 2, on the mold protective film 110, contacts 190 and 195 belonging to the different gate line structures and placed on the same layer or level of the gate lines 150 are electrically connected to each other The wirings 197 can be disposed. For example, the wiring 197 may extend in the second direction and may be electrically connected to the plurality of contacts 190 and 195.

The bit line 199 may be disposed on the channel region C of the substrate 100 to electrically connect the plurality of pads 130. For example, the bit line 199 may extend in the second direction on the uppermost interlayer insulating layer pattern 1061, and electrically connect the pads 130 belonging to different channel rows to each other. In some embodiments, a bit line contact may be further disposed between the pad 130 and the bit line 199.

The first and second contacts 190 and 195, the wiring 197 and the bit line 199 may comprise a conductive material such as a metal, a metal nitride, or a metal silicide.

According to the exemplary embodiments described above, the contact spacers can be selectively formed only on the sidewalls of some of the contacts that are connected to the gate lines 150. [ For example, on the sidewalls of the first contacts 190 that are seated on the stepped portions of the upper gate lines 150 included on the first region I, a first contact spacer 182 ) Can be formed. According to exemplary embodiments, it is possible to selectively form the contact spacers by selecting the contacts in which the gate lines 150 can cause defects as the number of layers increases.

FIGS. 3 to 29 are cross-sectional views and plan views for explaining a method of manufacturing a vertical type memory device according to exemplary embodiments. For example, FIGS. 3 to 29 are views for explaining a method of manufacturing the vertical type memory device shown in FIG.

Specifically, FIGS. 6, 10, 11, 17, 19, 22, 24, 27, and 29 are plan views for explaining the manufacturing method. 3, 4, 5, 7, 8, 9, 13, 15, 20, 21, 23, 25, 26, In the first direction. Figs. 12, 14, 16 and 18 are cross-sectional views taken along the line II-II 'shown in Figs. 11, 17 and 19 in the first direction.

Referring to FIG. 3, a mold structure can be formed by alternately and repeatedly laminating interlayer insulating films 102 (for example, 102a to 102l) and sacrificial films 104a to 104k on a substrate 100.

As the substrate 100, a semiconductor substrate including a semiconductor material such as monocrystalline silicon, germanium, or the like can be used. The substrate 100 may be divided into a channel region C, a first region I, and a second region II. (See FIG. 8), the first contact 190 (see FIG. 28), and the second contact (second channel) in the channel region C, the first region I and the second region II, 195, Fig. 28) can be formed.

According to exemplary embodiments, the interlayer insulating films 102 may be formed using an oxide-based material such as silicon oxide, silicon carbonitride, or silicon oxyfluoride. The sacrificial films 104 may have an etching selectivity to the interlayer insulating film 102 and may be formed using a material that can be easily removed by a wet etching process. For example, the sacrificial films 104 may be formed using a nitride based material such as silicon nitride (SiN) or silicon boron nitride (SiBN).

The interlayer insulating layer 102 and the sacrificial layer 104 may be formed by a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, a high density plasma- (HDP-CVD) process, an atomic layer deposition (ALD) process, or a sputtering process.

In one embodiment, the lowermost interlayer insulating film 102a may be formed by performing a thermal oxidation process on the upper surface of the substrate 100. [ In one embodiment, the uppermost interlayer insulating film 102l may be formed to have a relatively thick thickness.

The sacrificial films 104 may be removed through a subsequent process to provide space for GSL, word lines, and SSL to be formed. Therefore, the number of stacks of the interlayer insulating films 102 and the sacrificial films 104 may be varied depending on the number of GSLs, word lines, and SSL formed later. 3, the sacrificial layers 104 and the interlayer insulating layers 102 are illustrated as being formed of 11 layers and 12 layers, respectively. However, in consideration of the degree of integration of the vertical type memory device, .

Referring to FIG. 4, a stepped mold structure may be formed by partially etching the side portions of the mold structure step by step.

For example, a photoresist pattern (not shown) covering the entirety of the channel region C and the first region I and partially covering the second region II is formed on the uppermost interlayer insulating film 102l . Both ends of the interlayer insulating films 102l to 102a and the sacrificial films 104k to 104a can be etched using the photoresist pattern as an etching mask. Thereafter, portions of both ends of the photoresist pattern are partially removed to reduce the width of the photoresist pattern, and then used as an etching mask to remove the amount of the interlayer insulating films 102l to 102b and the sacrificial films 104k to 104b The end portion can be etched. By repeating the etching process in a similar manner, the stepped mold structure as shown in Fig. 4) can be formed.

Then, a mold protecting film 110 may be formed on the substrate 100 to cover the sides or steps of the stepped mold structure. For example, an insulating film covering the stepped mold structure is formed on the substrate 100 through an CVD process or a spin coating process using an insulating material such as silicon oxide. Then, the upper part of the insulating film may be planarized until the interlayer insulating film 102l of the uppermost layer is exposed, thereby forming the mold protecting film 110. [ The planarization process may include a chemical mechanical polishing (CMP) process and / or an etch-back process.

Referring to FIGS. 5 and 6, a channel hole 115 may be formed in the channel region C to pass through the stepped mold structure.

For example, a hard mask (not shown) is formed on the uppermost interlayer insulating film 102l and the mold protecting film 110, and a dry etching process using the hard mask as an etch mask The interlayer insulating films 102 and the sacrificial films 104 may be etched to form the channel holes 115. [ The channel hole 115 extends in the first direction from the upper surface of the substrate 100 and the upper surface of the substrate 100 can be exposed by the channel hole 115. The hard mask may be formed using, for example, a silicon-based or carbon-based spin-on hard mask (SOH) material or a photoresist material.

In some embodiments, a plurality of channel holes 115 may be formed along the third direction so that a channel hole row may be defined, and a plurality of the channel hole rows may be formed along the second direction. The channel hole rows 115 may be formed in a zig-zag manner along the second direction. In FIG. 6, for convenience of description, only one channel hole 115 included in each channel hole row is shown.

After formation of the channel hole 115, the hard mask may be removed through an ashing and / or strip process.

Referring to FIG. 7, a dielectric layer structure 120 may be formed on the sidewalls of each channel hole 115.

According to exemplary embodiments, a dielectric film may be formed on the sidewalls and bottoms of the uppermost interlayer insulating film 102l and the mold protecting film 110, and the channel holes 115. [ The dielectric layer may be formed by sequentially laminating a blocking layer, a charge storage layer, and a tunnel insulating layer. The blocking film may be formed using an oxide such as silicon oxide, and the charge storage film may be formed using a nitride such as silicon nitride or a metal oxide, and the tunnel insulating film may be formed using an oxide such as silicon oxide . According to some embodiments, the dielectric layer may be formed to have an ONO structure. The blocking film, the charge storage film, and the tunnel insulating films may be formed using a CVD process, a PECVD process, or an ALD process, respectively.

For example, the dielectric film portion formed on the bottom surfaces of the channel holes 115 through the CMP process and / or the etch-back process, and the interlayer dielectric film 102l on the uppermost layer and the dielectric film portion 102d formed on the mold protective film 110 Can be removed. Thus, for example, a dielectric film structure 120 having a straw shape may be formed on the sidewall of each channel hole 115.

Referring to FIG. 8, a channel 123 and a first buried film pattern 125 filling the remaining portions of each channel hole 115 may be formed.

According to exemplary embodiments, a channel film is formed on the uppermost interlayer insulating film 102l, the mold protecting film 110, the side walls of the dielectric film structure 120 and the bottom surfaces of the channel hole 115, A first buried layer filling the remaining portions of the channel holes 115 can be formed. The channel layer may be formed using an impurity-doped polysilicon or amorphous silicon. Alternatively, the channel layer may be formed using polysilicon or amorphous silicon, and then may be converted into single crystal silicon by heat treatment or laser beam irradiation. The first buried layer may be formed using an insulating material such as silicon oxide or silicon nitride. The channel film and the first buried film may be formed using, for example, a CVD process, a PECVD process, a sputtering process, or an ALD process.

Thereafter, the first buried film and the upper portion of the channel film are planarized by, for example, a CMP process until the upper surface of the uppermost interlayer insulating film 102l or the mold protective film 110 is exposed, The channel 123 and the first buried film pattern 125 may be formed in the hole 115. [

A channel 123 may be formed on the sidewalls of the dielectric film structure 120 to contact the upper surface of the substrate 100. For example, the channel 123 may have a substantially cup shape. The first buried film pattern 125 may have a pillar shape accommodated in the channel 123.

A channel 123 and a first buried film pattern 125 are sequentially stacked from the sidewall of the channel hole 115 in the respective channel holes 115 by the above- A structure may be formed. Corresponding to the arrangement of the channel holes 115 described above, a plurality of the vertical channel structures may be arranged in the third direction so that a channel row may be defined, and a plurality of the channel rows may be arranged along the second direction have.

In some embodiments, a semiconductor pattern may be formed that fills the bottom of the channel hole 115 prior to formation of the dielectric film structure 120. The semiconductor pattern may be formed through selective epitaxial growth (SEG) using the upper surface of the substrate 100 exposed by the channel hole 115 as a seed. Alternatively, after forming an amorphous silicon film filling the bottom of the channel hole 115, a laser epitaxial growth (LEG) process or a solid phase epitaxy (SPE) process is performed on the amorphous silicon film May be performed to form the semiconductor pattern. The dielectric layer structure 120 and the channel 123 may be formed on the upper surface of the semiconductor pattern.

Referring to FIGS. 9 and 10, a pad 130 for capping the upper portion of the channel hole 115 may be formed.

For example, the upper portion of the dielectric film structure 120, the channel 123, and the first buried film pattern 125 may be removed through an etch-back process to form a recess. A pad film filling the recess can be formed on the first buried film pattern 125, the channel 123, the dielectric film structure 125, the uppermost interlayer insulating film 1021, and the mold protecting film 110. The pad 130 may be formed by planarizing the upper surface of the uppermost interlayer insulating film 102l and / or the upper surface of the mold protecting film 110 through the CMP process. The pad film may be formed using polysilicon or polysilicon doped with, for example, an n-type impurity. Alternatively, the pad film may be formed by forming a preliminary pad film using amorphous silicon and then crystallizing the preliminary pad film.

A plurality of pads 130 can form pad rows in the uppermost interlayer insulating film 1021 corresponding to the above-described arrangement of channel rows.

Referring to FIGS. 11 and 12, an opening 135 may be formed to cut and extend the stepped mold structure.

For example, a hard mask (not shown) for partially exposing the mold interlayer insulating film 102l and the mold interlayer 110 between the uppermost layer of the channel rows, which covers the pads 260 and is adjacent in the third direction, Can be formed. The opening 135 may be formed by etching the mold protecting film 110, the interlayer insulating films 102, and the sacrificial films 104 through a dry etching process using the hard mask as an etching mask. The hard mask may be formed using, for example, a photoresist or an SOH material, and may be removed through an ashing and / or strip process after formation of the opening 135.

The openings 135 may extend in the third direction, for example, and a plurality of openings 135 may be formed along the second direction. Accordingly, a predetermined number of the channel rows may be disposed between the neighboring openings 135 in the second direction. For example, as shown in FIG. 11, four of said channel rows may be included between neighboring openings 135. However, the number of the channel rows can be adjusted in consideration of circuit design, integration degree, and the like of the vertical memory device.

12, the interlayer insulating films 102 and the sacrificial films 104 are formed on the interlayer insulating film patterns 106 (for example, 106a to 1061) and the sacrificial film patterns 106 (E.g., 108a through 108k). The interlayer insulating layer patterns 106 and the sacrificial layer patterns 108 of each layer may have a plate shape extending along the third direction. The upper surface of the substrate 100 may be exposed through the opening 135 and the sidewalls of the interlayer insulating film pattern 106 and the sacrificial film pattern 108 may be exposed.

Referring to FIGS. 13 and 14, the sacrificial film patterns 108 in which the side walls are exposed by the openings 135 can be removed. According to exemplary embodiments, the sacrificial layer pattern 108 may be removed through a wet etch process where an etchant having an etch selectivity to silicon nitride is used. For example, an acidic solution such as phosphoric acid and / or sulfuric acid may be used as the etchant.

As the sacrificial layer patterns 108 are removed, a gap 140 is formed between the interlayer dielectric layer patterns 106 of each layer, and the outer wall of the dielectric layer structure 120 is partially Can be exposed.

15 through 17, gate lines 150 (e.g., 150a through 150k) may be formed in the gaps 140 of each layer. Thus, the sacrificial film 104 or the sacrificial film pattern 108 of each layer can be replaced with the gate line 150. [

According to exemplary embodiments, the outer surfaces of the exposed dielectric layer structure 120, the surfaces of the interlayer dielectric layer patterns 106, the upper surface of the substrate 100 exposed by the openings 135, The gate electrode film can be formed along the upper surface of the gate electrode layer. The gate electrode film completely fills the gaps 140 and may be formed to partially fill the openings 135. In addition, the gate electrode film may cover the upper surface of the mold protection film 110 together.

The gate electrode film may be formed using a metal or a metal nitride. For example, the gate electrode film may be formed using a metal such as tungsten, aluminum, copper, titanium, tantalum, or a nitride of the metal. According to one embodiment, the gate electrode film may be formed of a multilayer film in which a barrier film including a metal nitride and a metal film including a metal are stacked. The gate electrode film may be formed using a CVD process, a PECVD process, an ALD process, a PVD process, or a sputtering process.

In one embodiment, before forming the gate electrode film, along the surfaces of the interiors of the gaps 140 and the surfaces of the interlayer insulating film patterns 106, an additional blocking film (e.g., silicon oxide or metal oxide) ) Can be further formed.

Thereafter, the gate electrode film may be partially removed to form the gate line 150 in the gap 140 of each layer.

For example, the upper portion of the gate electrode film can be planarized by, for example, a CMP process until the uppermost interlayer insulating film pattern 1061 and / or the upper surface of the mold protecting film 110 are exposed. The gate lines 150 may then be formed by etching the portion of the gate electrode film formed within the opening 135 and on the top surface of the substrate 100. The gate electrode film may be partially etched through a wet etching process that includes, for example, hydrogen peroxide (H ₂ O ₂ ).

The gate lines 150 may include a GSL, a word line, and a SSL formed sequentially from the upper surface of the substrate 100 along the first direction. For example, the lowest gate line 150a may be provided with the GSL. The gate lines (e.g., 150a to 150i) above the GSL may be provided as the word lines. Two layers of gate lines 150j and 150k above the word line may be provided by the SSL.

The gate line 150 of each layer may extend around a predetermined number of the channel rows, for example, four channel rows. Thus, a gate line structure can be defined by the gate lines 150 which surround a predetermined number of the channel rows and extend in the third direction, and are stacked in the first direction. A plurality of the gate line structures may be separated by the openings 135 and arranged along the second direction.

According to exemplary embodiments, the gate line structure may have a pyramid or a stepped structure that is substantially the same as or similar to the stepped mold structure. For example, the gate line 150 of each layer may include a stepped portion protruding from the upper gate line 150 in the third direction.

18 and 19, the impurity region 101 may be formed on the substrate 100 exposed by the opening 135, and the second buried film pattern 160 may be formed to fill the opening 135 have.

For example, the impurity region 101 can be formed by implanting an n-type impurity such as phosphorus or arsenic through the opening 135. The impurity region 101 extends in the third direction and may be provided as a CSL of the vertical memory device. In one embodiment, a metal silicide pattern such as a nickel silicide pattern or a cobalt silicide pattern may be further formed on the impurity region 101 to lower the resistance of the CSL.

Thereafter, a buried film filling the opening 135 is formed on the impurity region 101, the uppermost interlayer insulating film pattern 1061, the pad 130 and the mold protecting film 110, and the upper portion of the insulating film is covered with the uppermost interlayer insulating film pattern The second buried film pattern 160 can be formed by planarization through an etch-back process and / or a CMP process until the exposed portions 1061 are exposed. The buried layer may be formed using an insulating material such as silicon oxide.

20, a first mask film 170 is formed on the upper surface of the uppermost interlayer insulating film pattern 106l, the mold protecting film 110 and the pads 130, and the first mask film 170 The first photoresist film 172 can be formed.

The first mask film 170 may comprise, for example, an amorphous carbon film. The first mask film 170 and the first photoresist film 172 are formed by sequentially and continuously covering the channel region C, the first region I and the second region II on the plurality of gate line structures. can do.

Referring to FIGS. 21 and 22, the first photoresist film 172 formed on the first region I may be partially removed through the exposure and development processes to form the first photoresist pattern 174 .

Thereafter, the first mask film 170 is partially removed by using the first photoresist pattern 174 as an etching mask, and the uppermost interlayer insulating film pattern 1061 and the mold protecting film 110, The first contact holes 180 may be formed.

According to exemplary embodiments, the top surfaces of the steps of the gate lines (e.g., 150k-150f) included in the first region I may be exposed by each of the first contact holes 180 .

Referring to FIGS. 23 and 24, the first photoresist pattern 174 and the first mask film 170 can be removed, for example, by an ashing and / or strip process. A first contact spacer 182 may then be formed on the sidewalls of each of the first contact holes 180.

For example, the uppermost interlayer insulating film pattern 1061, the mold protecting film 110, and the upper surface of the pads 130 are conformally formed along the sidewalls and bottom surfaces of the first contact holes 180, A film can be formed. The first spacer film may be formed by a CVD process, a PECVD process, a sputtering process, or an ALD process using silicon nitride or silicon oxynitride.

Thereafter, the uppermost interlayer insulating film pattern 106l, the mold protecting film 110, the upper surfaces of the pads 130, and the upper surface of the first contact holes 180 formed on the lower surfaces of the first contact holes 180 are etched through the etch- 1 spacer film portions can be removed. Thus, the first contact spacers 182 formed on the sidewalls of each of the first contact holes 180 by the remaining first spacer film portions can be defined. Also, the top surfaces of the steps of the gate lines 150 may be exposed again.

25, a second mask film 171 for capping the first contact holes 180 is formed on the top surfaces of the uppermost interlayer insulating film pattern 106l, the mold protecting film 110 and the pads 130 . A second photoresist film 173 can be formed on the second mask film 171.

The second mask film 171 may comprise an amorphous carbon film that is substantially the same as or similar to the first mask film 170.

Referring to FIGS. 26 and 27, a second photoresist film 173 formed on the second region II may be partially removed through an exposure and development process to convert the second photoresist film 173 into a second photoresist pattern. The second contact holes 183 may be formed by partially removing the second mask film 171 and the mold protecting film 110 by using the second photoresist pattern as an etching mask.

According to exemplary embodiments, the top surfaces of the steps of the gate lines (e.g., 150e to 150a) included in the second region II may be exposed by each of the second contact holes 183 .

After the formation of the second contact holes 183, the second photoresist pattern and the second mask film 171 may be removed by an ashing and / or stripping process.

According to exemplary embodiments, the contact holes formed on the step portions of the gate lines 150 as described above may be formed through a two-step photo process. For example, the first contact holes 180 may be formed by the first photolithography process, and the second contact holes 183 may be formed by the second photolithography process.

In the comparative example, when the contact holes are collectively formed through a single photo process, it may be difficult to form the contact holes having different heights by the step-like structure. For example, while forming the contact hole formed on the lowermost gate line 150a, the uppermost gate line 150k may be continuously exposed to the etching process and damaged, and the profile of the upper contact holes may be damaged . As the number of layers of the gate line structure increases, the problem caused by the single-photolithography process can be further exacerbated.

However, according to exemplary embodiments, contact holes having a uniform sidewall profile can be formed while preventing damage to the gate lines 150 by dividing the contact holes by a plurality of photo processes.

According to exemplary embodiments, a first contact spacer 182 may be formed on the sidewalls of the first contact hole 180. Thus, the diffusion of etch residues such as etch gases generated in the formation of the first contact holes 180 can be blocked by the first contact spacers 182. Accordingly, during the etching process for forming the second contact hole 183, damage to the second mask film 171 and the second photoresist film 173 due to the etching residue can be prevented have. Therefore, the sidewall profile of the first contact hole 180 can be uniformly maintained.

In the comparative example, it may be considered to form the contact spacers collectively on the sidewalls of the entire contact holes. However, in the etch-back process of the spacer film for forming the contact spacer, for example, the spacer film portion formed on the bottom surface of the contact holes may be unevenly removed depending on the height difference of the contact holes 180 and 183, The gate lines 150 may be damaged.

However, in accordance with exemplary embodiments, the first contact spacers 182 may be selectively formed only on the sidewalls of the first contact holes 180 formed by the first photolithography process, . Thus, the structural and mechanical reliability of the gate lines 150 and the contact holes 180 and 183 can be optimized in combination with the above-described plurality of photo processes.

Referring to FIGS. 28 and 29, the first contact 190 and the second contact 195 may be formed in the first contact hole 180 and the second contact holes 183, respectively.

For example, a conductive film for embedding the first and second contact holes 180 and 183 can be formed on the upper surfaces of the uppermost interlayer insulating film pattern 106l, the mold protecting film 110 and the pads 130 have. The conductive film may be formed through a sputtering process or an ALD process using, for example, a metal, a metal nitride, and / or doped polysilicon.

Thereafter, the upper portion of the conductive film is planarized through the CMP process until the upper surfaces of the uppermost interlayer insulating film pattern 106l, the mold protecting film 110, and / or the pads 130 are exposed, (190, 195) can be formed.

In some embodiments, as described with reference to FIG. 2, electrically connected to the first contacts 190 and the second contacts 195 on the first region I and the second region II, respectively, And further extend the wirings 197. Further, a bit line 199, which is electrically connected to the plurality of pads 130 and extends on the channel region C, may be further formed.

30 and 31 are cross-sectional views and plan views, respectively, illustrating a vertical memory device according to some exemplary embodiments. For example, FIG. 31 is a cross-sectional view taken along line I-I 'of FIG. 30 in the first direction.

A detailed description of substantially the same or similar structures and / or structures as those described with reference to FIGS. 1 and 2 is omitted, and the same reference numerals are used for the same configurations.

For convenience of explanation, the gate line structure is shown in FIGS. 30 and 31 as having the same number of layers or the same number of levels as the gate line structure shown in FIG. 1 and FIG. However, the gate line structures shown in FIGS. 30 and 31 may have more steps than the gate line structures shown in FIGS.

30 and 31, the substrate 100 of the vertical memory device may include a channel region C, a first region I, a second region II, and a third region III. have. In the first region I, the second region II and the third region III, the stepped portions of the gate lines 150 may be dispersed. For example, some of the steps of the upper layer may be included in the first region I, some of the intermediate layers may be included in the second region II, May be included.

The first contacts 192 and the second contacts 194 may be respectively seated on the step portions of the gate lines 150 included in the first region I and the second region II. A first contact spacer 181 and a second contact spacer 185 may be formed on the sidewalls of the first contact 192 and the second contact 194, respectively.

Third contacts 196 may be seated on the stepped portions of the gate lines 150 included in the third region III. In the exemplary embodiments, the contact spacers may be omitted on the sidewalls of the third contacts 196. In this case, the third contact 196 may be in direct contact with the mold protecting film 110.

As described above, when the number of layers of the vertical memory device or the gate line structure is increased, the regions of the substrate 100 may be further divided, and the regions where the contact spacers are formed may be selected in consideration of the process order and the process number. 30 and 31 illustrate that the step portions are dispersed in three regions. However, the step portions may be dispersed into four or more regions in consideration of the number of layers of the vertical memory device or the gate line structure.

32 to 38 are sectional views for explaining a method of manufacturing a vertical type memory device according to some exemplary embodiments. For example, FIGS. 32 to 38 are views for explaining the method of manufacturing the vertical type memory device shown in FIGS. 30 and 31. FIG.

Detailed descriptions of processes and materials that are substantially the same as or similar to those described with reference to Figs. 3 to 29 are omitted.

Referring to FIG. 32, processes substantially the same as or similar to the processes described with reference to FIGS. 3 to 20 can be performed.

According to exemplary embodiments, a gate line structure may be formed on a substrate 100 that includes a channel region C, a first region I, a second region II, and a third region III. have. The gate line structure includes interlayer insulating film patterns 106 and gate lines 150 stacked in a stepped structure and interlayer insulating film patterns 106 and gate lines 150 are formed to penetrate in the first direction Lt; RTI ID = 0.0 > a < / RTI > vertical channel structure. The vertical channel structure includes a dielectric film structure 120, a channel 123 and a first buried film pattern 125. A pad 130 is formed to form the dielectric film structure 120, the channel 123, The upper portion of the pattern 125 can be capped.

The first mask film 170a is formed on the top surfaces of the uppermost interlayer insulating film pattern 106l, the pads 130 and the mold protecting film 110. A first photoresist film (172a) can be formed.

Referring to FIG. 33, a process substantially similar to the process described with reference to FIG. 21 can be performed. For example, the first photoresist film 172a of the first region I may be partially etched to form the first photoresist pattern 174a. The first mask film 170a is etched through the first photoresist pattern 174a and the first contact holes 180a are formed by partially etching the uppermost interlayer insulating film pattern 1061 or the mold protective film 110 .

The upper surfaces of the steps of the gate lines (for example, 150k to 150h) included in the first region I can be exposed by the first contact holes 180a. After the formation of the first contact holes 180a, the first photoresist pattern 174a and the first mask film 170a may be removed through an ashing and / or strip process.

Referring to FIG. 34, a first contact spacer 181 may be formed on a sidewall of each of the first contact holes 180a through a process substantially the same as or similar to the process described with reference to FIG.

The second mask film 170b for capping the first contact holes 180a may be formed on the top surfaces of the uppermost interlayer insulating film pattern 106l, the pads 130 and the mold protecting film 110 . A second photoresist film 172b may be formed on the second mask film 170b.

Referring to FIG. 35, a process substantially the same as or similar to the process described with reference to FIG. 33 can be repeated for the second region II.

Thus, the second photoresist film 172b formed on the second region II can be partially etched to form the second photoresist pattern 174b. The second contact holes 180b can be formed by partially removing the second mask film 170b and the mold protecting film 110 by using the second photoresist pattern 174b as an etching mask.

The upper surfaces of the stepped portions of the gate lines (e.g., 150g, 150f, and 150e) included in the second region II can be exposed by the second contact holes 180b.

Referring to FIG. 36, a second contact spacer 185 may be formed on the sidewalls of each of the second contact holes 180b. In some embodiments, a spacer film is formed along the surfaces of the second photoresist pattern 174b and the second mask film 170b, and the sidewalls and bottoms of the second contact holes 180b, The film may be partially removed through an etch-back process to form a second contact spacer 185.

After the formation of the second contact spacer 185, the second photoresist pattern 174b and the second mask film 170b may be removed through a CMP process, an ashing and / or a strip process.

In some embodiments, the first and second contact spacers 181, 185 may be formed substantially simultaneously. For example, after forming the first contact hole 180a, the second contact hole 180b can be formed. After forming a spacer film continuously extending in common on the sidewalls and bottoms of the first and second contact holes 180a and 180b, the spacer film is partially removed through an etch-back process to form first and second contact Spacers 181 and 185 may also be formed.

After the formation of the second contact hole 180b and the second contact spacer 185, the first and second contacts 110a and 110b are formed on the upper surfaces of the uppermost interlayer insulating film pattern 106l, the pads 130 and the mold protecting film 110, A third mask film 170c for capping the holes 180a and 180b can be formed. A third photoresist film 172c may be formed on the third mask film 170c.

Referring to FIG. 37, a process substantially the same or similar to the process described with reference to FIG. 33 can be repeated for the third region III.

Accordingly, the third photoresist film 172c formed on the third region III may be partially etched to form the third photoresist pattern 174c. The third contact holes 180c can be formed by partially removing the third mask film 170c and the mold protecting film 110 by using the third photoresist pattern 174c as an etching mask.

The upper surfaces of the steps of the gate lines (for example, 150d to 150a) included in the third region III can be exposed by the third contact holes 180c. After the third contact hole 180c is formed, the third photoresist pattern 174c and the third mask film 170c may be removed through an ashing and / or strip process.

Referring to Fig. 38, a process substantially the same as or similar to the process described with reference to Figs. 28 and 29 can be performed to form contacts.

For example, a conductive film for embedding the first to third contact holes 180a, 180b and 180c is formed on the upper surfaces of the uppermost interlayer insulating film pattern 106l, the mold protecting film 110 and the pads 130 can do. Thereafter, the upper portion of the conductive film is planarized by the CMP process until the upper surfaces of the uppermost interlayer insulating film pattern 106l, the mold protecting film 110, and / or the pads 130 are exposed to form the first contact hole 180a, The second contact 194 and the third contact 196 may be formed in the second contact hole 180b and the third contact hole 180c, respectively.

In some embodiments, as described with reference to FIG. 2, the first to third contacts 192, 194, 196 are electrically connected to the first to third contacts 192, 194, 196 on the first to third regions I to III, Can be further formed. Further, a bit line that is electrically connected to the plurality of pads 130 and extends on the channel region C may be further formed.

According to the exemplary embodiments described above, as the number of layers of the vertical memory device or the gate line structure increases, the photo process for forming the contact hole (or contact) formed on the step portion of the gate line is further divided can do. For example, as described with reference to FIGS. 32 to 39, the first to third contact holes 180a, 180b and 180c may be formed through the first to third photo processes. In some embodiments, by selectively forming contact spacers for the contact holes (e.g., the first contact hole 180a and the second contact hole 180b) exposed to the plurality of divided photo processes, The structural and mechanical reliability of the contact hole and the gate line can be improved.

Even when the photo process is divided into four or more processes, the contact spacers can be selectively formed in consideration of the order and frequency of the divided processes.

39 is a cross-sectional view illustrating a vertical memory device according to exemplary embodiments.

The vertical memory device shown in Fig. 39 may have substantially the same or similar structure and / or structure as the vertical memory device described with reference to Figs. 1 and 2, except for the addition of a peripheral circuit region or a peripheral circuit . Therefore, a detailed description of the redundant configuration and / or structure is omitted, and the same or similar reference numerals are used for the same or similar configurations.

Referring to FIG. 39, the substrate 100 may include a channel region C, a first region I, a second region II, and a peripheral circuit region P.

A gate line structure substantially the same as or similar to that described with reference to FIGS. 1 and 2 may be disposed on the channel region C, the first region I and the second region II of the substrate 100.

Vertical channel structures passing through the gate lines 150 and the interlayer insulating film patterns 106 and including the dielectric film structure 120, the channel 123 and the first buried film pattern 125 are formed on the channel region C .

The step portions of the gate lines 150 may be disposed on the first region I and the second region II. The first contacts 190 and the second contacts 195 may be seated on the stepped portions included in the first region I and the second region II, respectively. According to exemplary embodiments, a first contact spacer 182 may be optionally formed on the sidewalls of each of the first contacts 190. [

The peripheral circuit region P may be assigned to the outer portion of the substrate 100, for example. A peripheral circuit of the vertical memory device may be disposed on the peripheral circuit area P. The peripheral circuit may comprise, for example, a transistor. The peripheral circuit may be covered by the peripheral circuit protection film 250.

For example, a gate structure 240 in which a gate insulating film pattern 215, a gate electrode 225, and a gate mask 235 are stacked may be disposed on the peripheral circuit region P of the substrate 100. A source / drain region 205 may be formed on the substrate 100 adjacent to the gate structure 240. The transistor can be defined by gate structure 240 and source / drain region 205. Gate spacers 245 may be further formed on the sidewalls of the gate structure 240.

The peripheral circuit protection layer 250 may be formed on the peripheral circuit region P of the substrate 100 to cover the gate structure 240, the gate spacers 245 and the source / drain regions 205.

The peripheral circuit contact 260 penetrates the mold protecting film 110 and the peripheral circuit protecting film 250 on the peripheral circuit region P and can be electrically connected to the peripheral circuit. For example, the peripheral circuit contacts 260 may be in contact with or electrically connected to the source / drain regions 205.

According to exemplary embodiments, the contact spacers may be omitted on the sidewalls of the peripheral circuit contacts 260. Thus, the side walls of the peripheral circuit contacts 260 can be in direct contact with the mold protective film 110.

40 to 46 are sectional views for explaining a method of manufacturing a vertical type memory device according to exemplary embodiments. Detailed descriptions of processes and / or materials that are substantially the same as or similar to those described with reference to Figs. 3 to 29 are omitted.

Referring to FIG. 40, a peripheral circuit can be formed on the peripheral circuit region P of the substrate 100.

For example, a gate insulating film, a gate electrode film, and a gate mask film can be sequentially formed on the substrate 100. [ The gate mask film is partly etched to form a gate mask 235 and the gate electrode film and the gate insulating film are etched using the gate mask 235 as an etching mask to form the gate electrode 225 and the gate insulating film pattern 215 can be formed. The gate structure 240 including the gate insulating film pattern 215, the gate electrode 225 and the gate mask 235 sequentially stacked on the substrate 100 can be formed.

The gate insulating layer may be formed using silicon oxide or a metal oxide. The gate electrode film may be formed using a metal, a metal nitride, or doped polysilicon. The gate mask film may be formed using silicon nitride. The gate insulating film, the gate electrode film, or the gate mask film may be formed using at least one of a CVD process, a PECVD process, an HDP-CVD process, an ALD process, and a sputtering process. The gate insulating layer may be formed by performing a thermal oxidation process on the upper surface of the substrate 100.

The source / drain region 205 can be formed on the substrate 100 of the peripheral circuit region P adjacent to the gate structure 240 through an ion implantation process using the gate structure 240 as an ion implantation mask. A transistor disposed in the peripheral circuit region P by the gate structure 240 and the source / drain region 205 can be defined.

In some embodiments, after forming a spacer film over the gate structure 240 on the substrate 100, the spacer film is anisotropically etched to further form gate spacers 245 covering the sidewalls of the gate structure 240 can do.

Thereafter, a peripheral circuit protection layer 250 for protecting the transistor may be further formed. For example, after forming a protective film covering the source / drain region 205, the gate structure 240 and the gate spacer 245 on the substrate 100, the channel region C, the first region I, The peripheral circuit protection film 250 may be formed by removing the protective film portion formed on the second region II. The protective film may comprise an insulating material such as, for example, silicon oxide.

Referring to FIG. 41, a mold structure can be formed by alternately and repeatedly laminating the interlayer insulating films 102 and the sacrificial films 104 through a process substantially the same as or similar to the process described with reference to FIG.

Each of the interlayer insulating films 102 and the sacrificial films 104 may be formed consecutively in common on the channel region C, the first region I, the second region II and the peripheral circuit region P . In some of the peripheral circuit region P and the second region II, the mold structure may be protruded by a step formed by the peripheral circuit protection film 250.

Referring to FIG. 42, a stepped mold structure can be formed through a process that is substantially the same as or similar to the process described with reference to FIG.

The mold structure may be substantially removed on the peripheral circuit region P and the uppermost interlayer insulating film 102l may be exposed on the channel region C. [ The steps of the stepped mold structure may be exposed on the first region I and the second region II.

Then, a mold protecting layer 110 may be formed to cover the side portions of the stepped mold structure and the peripheral circuit protecting layer 250.

Referring to FIG. 43, substantially the same or similar processes as those described with reference to FIGS. 5 to 20 can be performed.

According to exemplary embodiments, the stepped mold structure may be formed on the channel region C in a first direction and may include a dielectric film structure 120, a channel 123 and a first buried film pattern 125, A vertical channel structure can be formed. A pad 130 for capping the vertical channel structure may be formed on the dielectric film structure 120, the channel 123, and the first buried film pattern 125.

Thereafter, the sacrificial films 104 may be replaced with the gate lines 150 to form gate line structures in which the interlayer insulating film patterns 106 and the gate lines 150 are alternately stacked in a stepped manner.

A first mask layer 170 may be formed on the gate line structure and the mold protection layer 110 and a first photoresist layer 172 may be formed on the first mask layer 170. A first photoresist film 172 is formed on the first mask film 170 in common on the channel region C, the first region I, the second region II and the peripheral circuit region P .

Referring to Fig. 44, substantially the same or similar processes as those described with reference to Figs. 21 to 25 can be performed.

Accordingly, the first contact holes 180 are formed to expose the step portions of the gate lines (for example, 150k to 150f) included in the first region I, and the first contact holes 180 The first contact spacer 182 may be formed on the sidewall of the first contact spacer 182. After forming the first contact hole 180 and / or the first contact spacer 182, the first photoresist film 172 and the first mask film 170 may be removed through an ashing and / or strip process.

Thereafter, a second mask film 171 for capping the first contact holes 180 may be formed on the top surfaces of the uppermost interlayer insulating film pattern 106l and the mold protecting film 110. [ A second photoresist film 173 can be formed on the second mask film 171.

Referring to Fig. 45, a process substantially similar to the process described with reference to Figs. 26 and 27 can be performed.

According to the exemplary embodiments, the second photoresist pattern 173a can be formed by partially removing the second photoresist film 173 on the second region II and the peripheral circuit region P. The second mask film 171 and the mold protection film 110 are partially etched using the second photoresist pattern 173a as an etch mask to form the second contact hole 183 and the peripheral circuit contact hole 255 can do.

The step portions of the gate lines (for example, 150e to 150a) included in the second region II can be exposed by the second contact hole 183. The source / drain region 205 can be exposed by the peripheral circuit contact hole 255.

After the formation of the second contact hole 183 and the peripheral circuit contact hole 255, the second photoresist pattern 173a and the second mask film 171 may be removed through an ashing and / or strip process.

According to exemplary embodiments, the second contact hole 183 and the peripheral circuit contact hole 255 may be formed simultaneously through substantially the same photo process. For example, the contact hole through which the GSL is exposed and the peripheral circuit contact hole 255 can be formed simultaneously through substantially the same photolithography process.

In some embodiments, after forming the second contact hole 183, the peripheral circuit contact hole 255 may be formed through a separate photolithography process.

Referring to FIG. 46, a process substantially the same as or similar to the process described with reference to FIGS. 26 and 27 can be performed.

For example, a conductive film that sufficiently fills the first contact hole 180, the second contact hole 183, and the peripheral circuit contact hole 255 can be formed. The upper portion of the conductive film is planarized until the upper surface of the uppermost interlayer insulating film pattern 106l and the mold protective film 110 are exposed and the first contact hole 180, the second contact hole 183, and the peripheral circuit contact hole 255 The first contact 190, the second contact 195, and the peripheral circuit contact 260 may be formed in the first and second contact holes 190 and 260, respectively.

In some embodiments, wires may be further formed on the first region I and the second region II to electrically connect the first contacts 190 and the second contacts 195. Peripheral circuit wirings electrically connected to the peripheral circuit contacts 260 may be further formed on the peripheral circuit region P. [ A bit line electrically connected to the pads 130 may be formed on the channel region C.

According to the exemplary embodiments described above, the contact spacers can be selectively formed on some of the contact sidewalls, taking into account the photo process for forming the peripheral circuit contact holes 255.

Figures 47-49 are top and cross-sectional views illustrating a vertical memory device according to exemplary embodiments. Specifically, Figure 47 is a plan view of a vertical memory device in accordance with exemplary embodiments. 48 and 49 are cross-sectional views taken along the line I-I 'and II-II' shown in FIG. 47, respectively, in the first direction.

The vertical memory device shown in Figs. 47-49 can have substantially the same or similar structure and / or structure as the vertical memory device described with reference to Figs. 1 and 2, except for the arrangement of contacts. Therefore, a detailed description of the redundant configuration and / or structure is omitted, and the same reference numerals are used for the same configurations.

Referring to FIGS. 47 to 49, a plurality of gate line structures separated by the second buried film pattern 160 may be disposed on the substrate 100, as described with reference to FIG. 1 and FIG. The gate line structure may include interlayer insulation film patterns 106 and gate lines 150 which are stacked in a pyramid or step-like shape.

A plurality of vertical channel structures including a dielectric film structure 120, a channel 123 and a first embedded film pattern 125 are formed on a channel region C of the substrate 100, (130) may be formed.

The stepped portions of the gate lines 150 may be dispersed in the first region I and the second region II of the substrate 100. [

According to exemplary embodiments, the contacts 310 and 320 may be arranged in zigzag fashion with respect to each other along the third direction.

In some embodiments, contacts 310 and 320 may be arranged in a frustum shape with respect to the steps on the same vertical cross-section. For example, as shown in FIG. 48, in the cross-section according to the line II ', the contacts 310 and 320 are connected to the ends of the odd-numbered gate lines (e.g., 150a, 150c, 150e, 150g, 150i, Can be arranged on the parts. As shown in FIG. 49, in the cross section according to the line II-II ', the contacts 310 and 320 are formed on the stages of the even-numbered gate lines (for example, 150b, 150d, 150f, 150h, and 150j) Lt; / RTI >

As described above, by distributing the contacts 310, 320 in a zigzag fashion, the distance between neighboring contacts 310, 320 can be increased. Therefore, an alignment margin can be additionally secured during the photolithography process.

Contacts 310 and 320 include first contacts 310 that are seated on the steps of the gate lines (e.g., 150k to 150f) included in the first region I, And second contacts 320 that are seated on the steps of the gate lines (e.g., 150e to 150a) included in the first contacts 320a. The first contacts 310 and the second contacts 320 may be arranged in a zigzag fashion with respect to each other.

According to exemplary embodiments, the first contact spacers 305 may be selectively formed only on the sidewalls of the first contacts 310.

According to the exemplary embodiments described above, the contacts 310 and 320 may be arranged in a staggered arrangement to ensure alignment margins of the photolithography process, while at the same time providing a contact spacer for the first contacts 310 It is possible to suppress defects due to the generation of etching residues.

Figures 50-52 are top and cross-sectional views illustrating a vertical memory device in accordance with exemplary embodiments. Specifically, Figure 50 is a plan view of a vertical memory device in accordance with exemplary embodiments. 51 and 52 are cross-sectional views taken along the line I-I 'and II-II' shown in FIG. 50, respectively, in the first direction.

The vertical memory device shown in Figs. 50 to 52 may have substantially the same or similar structure and / or structure as the vertical memory device described with reference to Figs. 47 to 49 except for the arrangement of contact spacers. Therefore, a detailed description of the redundant configuration and / or structure is omitted, and the same reference numerals are used for the same configurations.

Referring to Figures 50-52, contacts may be arranged in a zigzag fashion along the third direction, as described with reference to Figures 47-49.

The contacts may include first contacts 410 and second contacts 420. The first contacts 410 may be arranged along the third direction, for example, to define a first contact row. The second contacts 420 may be arranged along the third direction to define a second contact row. The first contact row and the second contact row are arranged on different vertical cross sections and the contacts belonging to the first and second contact rows may be arranged in the zigzag form in the planar direction as shown in Figure 50 have.

As shown in FIG. 51, the first contacts 410 included in the first contact row may be arranged on a section cut along the line I-I '. For example, the first contacts 410 may be arranged on the steps of the odd gate lines (e.g., 150a, 150c, 150e, 150g, 150i, 150k). According to exemplary embodiments, a first contact spacer 405 may be formed on each sidewall of the first contacts 410.

As shown in FIG. 52, the second contacts 420 included in the second contact row may be arranged on a section cut along a line II-II '. For example, the second contacts 420 may be arranged on the steps of even-numbered gate lines (e.g., 150b, 150d, 150f, 150h, 150j). According to exemplary embodiments, the contact spacers may be omitted on the sidewalls of the second contacts 420.

FIGS. 53 to 61 are a plan view and a cross-sectional view for explaining a method of manufacturing a vertical type memory device according to exemplary embodiments. For example, FIGS. 53 to 61 are views for explaining a method of manufacturing the vertical memory device shown in FIGS. 50 to 52. FIG.

53, 55, 57, 59, and 61 are plan views for explaining the manufacturing method. 54 is a vertical cross-sectional view for explaining the above manufacturing method. 56 and 58 are cross-sectional views taken along the line I-I 'shown in FIGS. 55 and 57 in the first direction. 60 is a cross-sectional view cut along the line II-II 'shown in FIG. 59 in the first direction.

A detailed description of the process and / or materials described with reference to Figs. 3 to 29 is omitted.

Referring to Figs. 53 and 54, substantially the same or similar processes as those described with reference to Figs. 3 to 19 can be performed.

According to exemplary embodiments, a plurality of gate line structures may be formed on substrate 100 that are separated by a second buried film pattern 160. The gate line structure includes interlayer insulating film patterns 106 and gate lines 150 stacked in a stepped structure and interlayer insulating film patterns 106 and gate lines 150 are formed to penetrate in the first direction Lt; RTI ID = 0.0 > a < / RTI > vertical channel structure. The vertical channel structure includes a dielectric film structure 120, a channel 123 and a first buried film pattern 125. A pad 130 is formed to form the dielectric film structure 120, the channel 123, The upper portion of the pattern 125 can be capped. The mold protection film 110 may be formed on the side of the gate line structure.

55 and 56, first contact holes 400 may be formed by partially removing the uppermost interlayer insulating film pattern 1061 or the mold protecting film 110 through a first photo process, for example.

According to exemplary embodiments, the first contact holes 400 may be arranged along the third direction to define a first row of contact holes. The first contact holes 400 may be formed in a frustum shape. For example, the top surfaces of the steps of the odd gate lines (e.g., 150a, 150c, 150e, 150g, 150i, and 150k) may be exposed by the first contact holes 400. [

Referring to FIGS. 57 and 58, a first contact spacer 405 may be formed on the sidewalls of each of the first contact holes 400.

For example, a spacer film including silicon nitride can be formed on the uppermost interlayer insulating film pattern 106l and the upper surface of the mold protecting film 110, and on the sidewalls and bottom surfaces of the first contact holes 400. [ The upper and lower portions of the spacer film may be removed through the etch-back process to form the first contact spacer 405. [

Referring to FIGS. 59 and 60, the mold protecting layer 110 of the uppermost layer may be partially removed through the second photolithography process, for example, to form the second contact holes 415.

According to exemplary embodiments, second contact holes 415 may be arranged along the third direction to define a second row of contact holes. The second contact holes 415 may be formed in a frustum shape. For example, the upper surfaces of the steps of the even-numbered gate lines (e.g., 150b, 150d, 150f, 150h, and 150j) may be exposed by the second contact holes 415. [

As described above, the first contact holes 405 and the second contact holes 415 can be formed by the first and second photolithography processes, respectively, which are divided on the basis of the contact hole row. In addition, the first contact holes 405 and the second contact holes 415 may be alternately arranged along the first direction and arranged in a staggered manner with respect to each other. Therefore, the alignment margin of the photo process for forming the contact holes can be additionally secured.

According to exemplary embodiments, the contact spacers may be selectively formed only on the sidewalls of the first contact holes 405 formed first by the first photo process and included in the first row of contact holes . Thus, for example, defects due to the etch residue generated during the second photolithography process can be prevented.

Referring to FIG. 61, the first contacts 410 and the second contacts 420 may be formed in the first contact holes 405 and the second contact holes 415, respectively.

For example, a conductive film which sufficiently fills the first contact holes 405 and the second contact holes 415 can be formed on the upper surface of the uppermost interlayer insulating film patterns 106l and the mold protective film 110. [ The upper portion of the conductive film is planarized by the CMP process until the upper surface of the uppermost interlayer insulating film patterns 1061 and / or the mold protective film 110 is exposed, thereby forming the first contacts 410 and the second contacts 420 Can be formed substantially simultaneously.

The first contacts 410 and the second contacts 420 are arranged alternately along the first direction in a zigzag manner according to the arrangement of the first contact holes 405 and the second contact holes 415, May be seated on the steps of lines 150.

In some embodiments, as described with reference to FIG. 2, additional wirings may be formed that are electrically connected to the first contacts 410 and the second contacts 420 and extend therefrom. Further, a bit line that is electrically connected to the plurality of pads 130 and extends may be further formed.

The vertical memory device and its manufacturing method according to the above-described exemplary embodiments can be applied to a three-dimensional semiconductor device including, for example, a 30-layer or 40-layer or higher-layer step structure to improve the electrical and mechanical reliability .

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the following claims. It can be understood that it is possible.

100: substrate 101: impurity region
102: interlayer insulating film 104: sacrificial film
106: Interlayer insulating film pattern 108: Sacrificial film pattern
110: mold protective film 115: channel hole
120: dielectric film structure 123: channel
125: First Embedded Film Pattern 130: Pad
135: opening 140: gap
160: second embedded film pattern 170, 170a: first mask film
170b, 171: second mask film 170c: third mask film
172, 172a: first photoresist film 172b, 173: second photoresist film
172c: a third photoresist film
174 and 174a: a first photoresist pattern
173a and 174b: a second photoresist pattern
174c: Third photoresist pattern
180, 180a, 400: first contact hole
181, 182, 305, 405: a first contact spacer
180b, 183, 415: second contact hole 180c: third contact hole
185: second contact spacer 190, 192, 310, 410: first contact
194, 195, 320, 420: second contact 196: third contact
197: Wiring 199: Bit line
205: source / drain region 215: gate insulating film pattern
225: gate electrode 235: gate mask
240: gate structure 245: gate spacer
250: peripheral circuit protection film 255: peripheral circuit contact hole
260: peripheral circuit contact

Claims (10)

Board;
Gate lines stacked in a vertical direction from the upper surface of the substrate and including stepped portions each projecting in a horizontal direction;
Channels passing through the gate lines in the vertical direction;
Contacts arranged on the steps of the gate lines; And
And a contact spacer selectively formed on sidewalls of some of the contacts, respectively. 2. The vertical memory device of claim 1, wherein the contact spacers comprise silicon nitride or silicon oxynitride. 3. The vertical memory device of claim 2, further comprising a mold protection layer covering the top surfaces and sides of the steps and including silicon oxide. 4. The mold of claim 3, wherein the contact spacer receives the contacts and penetrates the mold protection film,
Wherein the contacts of the contacts, except for the contacts partially formed with the contact spacers, are in direct contact with the mold protection film and through the mold protection film. The method of claim 1, wherein the substrate includes a channel region in which the channels are arranged, and a first region and a second region that are sequentially arranged in the horizontal direction from the channel region,
Wherein the contacts include first contacts that are seated on the stepped portions included in the first region and second contacts that are seated on the stepped portions that are included in the second region. 6. The vertical memory device of claim 5, wherein a first contact spacer is formed on each sidewall of the first contacts. 7. The method of claim 6, wherein the gate lines comprise a ground selection line (GSL), word lines and a string selection line (SSL) that are sequentially stacked from the top surface of the substrate,
Wherein the first contacts are electrically connected to the upper word lines of the SSL and a predetermined number of layers adjacent to the SSL of the word lines. 8. The method of claim 7, wherein the second contacts are electrically connected to the remaining word lines and the GSL except for the upper word lines,
And wherein the contact spacers are eliminated on the sidewalls of the second contacts. 7. The method of claim 6, wherein the substrate further comprises a third region extending from the second region, wherein the contacts further comprise third contacts electrically connected to the steps included in the third region, Type memory device. 10. The method of claim 9, wherein the first region, the second region, and the third region are allocated in accordance with a photo-
A second contact spacer is formed on a sidewall of each of the second contacts and the contact spacers are excluded on sidewalls of the third contacts.

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