KR20160099440A - Integrated circuit structure with substrate isolation and un-doped channel - Google Patents

Abstract

An integrated circuit (IC) structure is provided. The IC structure comprises: a first substrate having a plurality of conductive features formed on the substrate; and a plurality of chips mechanically bonded and electrically coupled to the first substrate. A first chip among the chips has a first bump attached to a first conductive feature among the conductive features. The first bump has an elongated cross-sectional surface unit which is formed on a surface in parallel to a surface of the first substrate. The first substrate and the first chip are bonded to have a configuration where a longitudinal shaft of the first bump is oriented to indicate a center position of the first substrate and indicate the direction deviated from the center position of the first chip.

Description

[0001] INTEGRATED CIRCUIT STRUCTURE WITH SUBSTRATE ISOLATION AND UN-DOPED CHANNEL [0002]

preference

This disclosure relates to U. S. Patent Application No. 24061.1647, entitled " Centripetal Layout for Low Stress CHIP Package, "filed October 21, 2010, the disclosure of which is incorporated herein by reference for all purposes herein Incorporated herein by reference as if fully set forth herein.

An integrated circuit is typically formed on a substrate such as a semiconductor wafer. The bump-on-trace is part of the interconnect structure of the integrated circuit. The bump provides an interface to the integrated circuit device, through which an electrical connection to the device can be made. Conventional techniques can be used to provide connections from package terminals to integrated circuits using thermocompression or thermal ultrasonic wire bonding and other techniques known in the art.

Chip interconnection techniques such as flip chips, known as controlled collapse chip connections, abbreviated as C4, interconnect semiconductor devices to external circuits using solder tips deposited on chip output contacts. The solder bumps are deposited on the chip pads on the top side of the wafer during the final wafer processing step. In order to mount the chip to an external circuit (e.g., a circuit board or other chip or wafer), the chip is turned upside down with the top side facing down, the contact pad lying in alignment with the pad on the external circuit, Flows between the substrate and the inverted chip supporting the external circuitry to complete the interconnection. This is in contrast to wire bonding where, in wire bonding, the chip is mounted straight and the wire is used to interconnect chip pads to external circuitry. As a result, the completed flip chip package is much smaller than conventional carrier based systems, because the chip is sitting directly on the circuit board. If the interconnect wires are much shorter, the inductance and thermal resistance are greatly reduced. Therefore, flip chip allows high speed devices.

Recent trends in high density flip chip interconnection have led to the use of copper pillar solder bumps such as circular or circular for CPU and GPU packaging. Copper pillar solder bumps are an attractive alternative to conventional solder bumps because the copper pillar solder bumps provide a fixed stand-off that is independent of the bonding wire pitch. This is important because most of the high density circuits are underfilled with various polymeric adhesive mixtures, and smaller standoffs can make it difficult to keep the underfill adhesive flowing under the die.

However, conventional circular copper post solder bumps have several disadvantages. One disadvantage is that the size of the circular copper pillar solder bumps is added to the interconnect structure, which limits the pitch dimension of the metal trace lines for interconnections. Therefore, current round solder bumps will eventually become a bottleneck in the ongoing device shrinking of the IC industry.

Another disadvantage is the mechanical stress in the underlying layer as well as in the packaging circuitry. This stress is caused by the inconsistent thermal expansion of the chip and the packaging structure. The stress is particularly important for circuits with extra low K (ELK) dielectric layers where K is less than 3. Packaging becomes increasingly fragile, leading to layer separation.

In addition, large current densities at the solder bump-to-pad interface contribute to electromigration and electrical stress. Examples of types of damage from electromigration include peeling of the bonding layer and microcracking of the solder joint.

Thus, a low stress interconnect circuit that allows a high density pitch is required.

The present disclosure provides IC structures in accordance with some embodiments. The IC structure is a first substrate, having a plurality of conductive features formed on a surface thereof; And a plurality of chips mechanically bonded to and electrically coupled to the first substrate. The first of the plurality of chips has a first bump attached to the first one of the plurality of conductive features. The first bump has an elongated cross-section in a plane parallel to the surface of the first substrate. The first substrate and the first chip are bonded in such a configuration that the long axis of the first bump indicates the center position of the first substrate and is oriented to point in a direction deviating from the center of the first chip.

The present disclosure also provides IC structures in accordance with some embodiments. The IC structure is a first substrate, having a plurality of interconnect features formed on a surface; And a plurality of chips mechanically bonded to and electrically coupled to the first substrate. The first of the plurality of chips each has a first subset of conductive bumps attached to a first subset of the plurality of interconnect features. The first subset of conductive bumps have an elongate cross-section in a plane parallel to the surface. The first chip and the first substrate are oriented such that the center position of the first chip is offset from the center position of the first substrate in a plan view and the first subset of conductive bumps are substantially pointing to the center position of the first substrate And is bonded with a configuration having individual long axes.

The present disclosure also provides a method of manufacturing an IC structure in accordance with some embodiments. The method includes receiving an IC design layout defining a plurality of conductive bumps; And re-forming the first conductive bump of the plurality of conductive bumps on the IC design layout according to the configuration between the chip and the packaging substrate when the chip is bonded to the packaging substrate, thereby creating a modified IC design layout , And a re-forming step. The first conductive bump has an elongated cross section having a first length along a first major axis, the first major axis having a first orientation parallel to the first direction defined in the configuration from the first conductive bump of the chip to the center position of the packaging substrate, Respectively.

According to the present invention, it is possible to provide an integrated circuit structure having substrate separation and undoped channels.

Embodiments of the present disclosure are best understood by reading the following detailed description together with the accompanying drawings. Note that according to standard practice in the industry, various features are not shown in scale. In fact, the dimensions of the various features may be increased or decreased arbitrarily for clarity of explanation.
1 is a plan view of an integrated circuit structure constructed in accordance with some embodiments.
Figure 2 is a cross-sectional view of the integrated circuit structure of Figure 1 constructed in accordance with some embodiments.
Figure 3a is a cross-sectional view of a portion of the integrated circuit structure of Figure 1 configured in accordance with some embodiments.
3B is a cross-sectional view of a portion of the integrated circuit structure of FIG. 1 configured in accordance with some other embodiments.
4 to 8 are plan views of a bump on trace structure of the IC structure of Fig. 1 constructed in accordance with various embodiments.
Figure 9 is a top view of a portion of the integrated circuit structure of Figure 1 constructed in accordance with some embodiments.
10 is a plan view of an integrated circuit structure constructed in accordance with some embodiments.
11 is a plan view of an integrated circuit structure constructed in accordance with some embodiments.
12 is a top view of an integrated circuit structure constructed in accordance with some other embodiments.
Figure 13 is a cross-sectional view of a portion of the integrated circuit structure of Figure 12 constructed in accordance with some embodiments.
14 is a flow diagram of an integrated circuit fabrication method, in accordance with some embodiments.
15 is a flow diagram of a method, in accordance with some embodiments.

The present disclosure relates generally to integrated circuit (IC) structures and corresponding fabrication, and more specifically to multichip modules.

The following inventive disclosures provide a number of different embodiments, or examples, that implement the different features of the present invention. Specific examples of components and arrangements are described below to simplify disclosure of the present invention. Of course, this description is for illustrative purposes only, and not for limitation. For example, in the following description, formation of a first feature on a second feature or on a second feature may include embodiments in which a first feature and a second feature are formed in direct contact, and the first feature and the second feature 2 features may be formed between the first feature and the second feature so that the second feature is not in direct contact. In addition, the disclosure of the present invention may repeat the reference numerals and / or characters in various examples. Such repetition is for simplicity and clarity and does not itself dictate the relationship between the various embodiments and / or configurations discussed.

Moreover, in the ensuing description, the formation of the first feature on the second feature or on the second feature may include embodiments in which the first feature and the second feature are formed in direct contact, wherein the first feature and the second feature May also include embodiments in which additional features are formed interposing the first feature and the second feature such that the first feature and the second feature are not in direct contact. Additionally, technical terms such as top / bottom, top / bottom, and vertical / horizontal are used for ease of description and do not provide any limit to the absolute direction. For example, the upper and lower layers may exhibit individual relationships relative to an integrated circuit or substrate formed on the substrate, rather than an absolute direction.

Figure 1 shows a top view of an integrated circuit (IC) structure 100 constructed in accordance with some embodiments. 2 is a cross-sectional view of an IC structure 100, in accordance with some embodiments. The IC structure includes a first substrate 102. In some embodiments, the first substrate 102 is a substrate selected from the group consisting of a packaging substrate, a printed circuit board, an interposer, and a semiconductor substrate. In some other embodiments, the first substrate 102 is a substrate selected from the group consisting of a packaging substrate, a printed circuit board, an interposer, a semiconductor substrate, a dielectric substrate, a ceramic substrate, and a glass substrate.

IC structure 100 includes two or more IC chips 104, such as exemplary 104A, 104B, and 104C shown in FIG. The IC chip 104 is bonded to the first substrate 102 and electrically coupled to the first substrate 102. Each IC chip 104 is an integrated circuit formed on a single semiconductor substrate. Each IC chip 104 is a part of a semiconductor wafer and has an integrated circuit formed thereon. For example, after fabrication of a semiconductor wafer, the wafer is separated into a plurality of chips by cutting through a scribe line on the wafer. In some embodiments, each IC chip 104 has an individual circuit formed thereon.

As an example for illustration, the chip 104 includes a semiconductor substrate, various devices formed thereon, and interconnect structures formed on the device and connected to the device to form an integrated circuit. In some embodiments, the device may be a memory device such as a transistor (e.g., a field effect transistor), a sensor (e.g., an imaging sensor), a memory cell (e.g., a random access memory cell), a diode, a passive device ) And / or other devices. Each chip 104 (e.g., 104A, 104B, and 104C) may include different circuits. A plurality of chips 104 are bonded to the first substrate 102 and are electrically connected to the first substrate 102 to form a functional circuit for a desired function. In some embodiments, the chip 104 has a circuit formed on an individual front surface, the circuit being flipped to be sandwiched between the first substrate 102 and the chip semiconductor substrate, Bonded.

The IC structure 100 further includes a bump on trace bonding structure 106 that functions as both an electrical connection and a bonding feature between the first substrate 102 and the chip 104. In particular, each chip 104 includes a plurality of conductive bumps 108 formed on the bonding surface of the chip. Conductive bump 108 is connected to the device of the chip via the interconnect structure. The first substrate 102 includes a plurality of conductive features (traces or interconnect features) 110 formed on the bonding surface of the first substrate 102. The first substrate 102 may further include an interconnect structure formed thereon. For example, a printed circuit board can be used as the first substrate and includes the interconnect structure. The trace 110 is connected to the interconnect structure of the first substrate 102 and extends to a position to be bonded with one bump. The bumps 108 and traces 110 are mechanically bonded together and electrically connected to form the bump on trace bonding structure 106.

In some embodiments, the traces may be formed of copper, a copper / nickel alloy, copper-IT (immersion Sn), copper -ENEPIG (electroless nickel electroless palladium dip gold) / Silicon / copper alloy, titanium, titanium nitride, tungsten, polysilicon, metal silicide, copper alloy, tantalum, tantalum nitride, and combinations thereof.

The first substrate 102 has a geometric center 112 in plan view, as illustrated in Fig. In comparison, in a plan view, each chip 104 has its own geometric center (not shown in FIG. 1). For example, a chip with a rectangular geometry has a geometric center located at the same distance from the opposite edge (along each of the major and minor axes). In these embodiments, the geometric center of the chip 104 does not overlap the geometric center 112 of the first substrate 102, or is spaced away from one another in a top view. In one particular example, one chip 104 may have a center that overlaps with the center 112 of the first substrate 102. Since the various chips are placed directly at different locations of the first substrate 102 and directly bonded to the first substrate 102, the remaining chips can not be centered with the first substrate 102 in plan view. Generally, the center of the chip 104 does not overlap with the center 112.

The bumps 108 of the chip 104 are not visible in plan view as they are covered by individual chip semiconductor substrates, but are also shown in FIG. 1 for better description. Bump 108 has an elongated shape in cross-section (or in plan view). Thus, each bump 108 has a major axis and a minor axis. Furthermore, each bump 108 is oriented so that its long axis is directed toward the center 112 of the first substrate 102. [ The dotted line in Fig. 1 indicates that the long axis of one bump 108 is oriented in the direction pointing to the center 112. Because the center of the chip 104 does not overlap with the center 112, the bumps 108 of the chip are not substantially oriented toward the center of the chip. When a small number of bumps of one chip point to the center 112 but most of the bumps 108 are oriented to point out of the center of the chip, Lt; / RTI > However, all of the bumps 108 of the chip 104 substantially point to the center 112. This is further illustrated in FIG. 9 as a top view of a portion of the IC structure 100, in accordance with some embodiments. In particular, when the chip 104A is bonded to the first substrate 102, the center 166 of the chip 104A is configured to be away from the center 112 of the first substrate 102 in plan view. Taking the bump 108A as an example, the elongate bump 108A is oriented such that its long axis 168 is oriented to point at the center. However, direction 170 from bump 108 to chip center 166 is not parallel to longitudinal axis 168 and has an angle.

Moreover, each bump has its own individual orientation. Because the various bumps are located at different locations and all are oriented at the center 112, the bumps have individual orientations to meet these requirements.

The traces 110 formed on the first substrate 102 are paired with the bumps 108 of the chip 104 incorporated in the first substrate 102. In this embodiment, Each of the paired bumps 108 and traces 110 are bonded together to form a bump on trace bonding structure 106 thereby forming a chip on the first substrate 102 to form a multi- (104). The paired bumps 108 and traces 110 are positioned such that when the chip 104 is bonded to the first substrate 102 the bump 108 overlaps the paired traces 110 for proper bonding As it overlaps the ends of the paired traces 110). In some embodiments, the bumps 108 and the conductive features 110 may be formed on the first substrate 102 such that when the chip 104 is flipped and placed on the first substrate 102, the paired bumps 108 and traces 110 The bonding portions are each designed to substantially overlap. During subsequent bonding processes, a thermal processing process may be used and may cause bonding stresses between the bumps and the conductive features due to the different thermal expansion coefficients of the first substrate 102 and the chip 104. The chip 104 and / or the first substrate 102 are configured such that the bonded portions of the paired bumps 108 and the traces 110 are bonded to the first substrate 102 and the chip (not shown) 104 so as to compensate for the mismatch between them.

The traces 110 are also designed to have a long shape and the bonded portions of the traces 110 are each coaxially oriented with the paired bumps 108. In particular, the long axis of the bonded portion of the trace 110 is oriented along the long axis of the paired bumps 108, thereby forming a bump-on-trace bonding structure 106 that maximizes the bonding area and bonding strength.

Figure 3a is a cross-sectional view of a portion of an IC structure 100 configured in accordance with some embodiments. In particular, exemplary chip 104 and exemplary bump-on trace bonding structure 106 (e.g., within dashed line 113 of FIG. 2) are included in FIG. 3 to indicate a more detailed feature. The IC structure 100 is further described with reference to Figures 1-3.

The chip 104 includes a chip substrate 114. In some embodiments, the chip substrate 114 is a semiconductor substrate, such as a portion of a semiconductor wafer. In this example, the chip substrate 114 is a silicon substrate. In some other instances, the chip substrate 114 includes a semiconductor substrate (e.g., a sapphire substrate including other semiconductor materials such as germanium, silicon germanium, silicon carbide, or gallium arsenide) -on-insulator (SOI) substrate. The chip 104 also includes various devices (e.g., transistors, diodes, sensors, and / or passive devices) formed on the chip substrate 114.

The chip 104 is formed on a chip substrate and further includes an interconnect structure 116 designed to connect the device to a functional circuit. The interconnect structure 116 includes various conductive features (e.g., metal lines, metal contacts, and metal via features) for electrical connection and one or more dielectric materials for isolation. In some embodiments, the interconnect structure 116 includes a plurality of metal layers. In particular, the interconnect structure 116 includes a conductive feature 118 coupled with the bump 108. In some instances, the conductive feature 118 is a metal feature in one metal layer (e.g., the top metal layer) of the interconnect structure 116. In some other examples, the conductive feature 118 is a bonding pad electrically connected to the interconnect structure 116. Conductive features 118 may include copper, aluminum, other suitable conductive materials, or combinations thereof. The chip 104 is also formed on the interconnect structure 116 and is designed to provide passivation to the circuit (device and interconnect structure 116) so that the circuit is prevented from environmental damage (e.g., moisture degradation).

The bump on trace bond structure 106 is formed after the bonding process and includes bumps 108 and traces (conductive features) 110 bonded together. In some embodiments, the bumps 108 include conductive columns 121, such as copper columns, or conductive columns of other metals or metal alloys. The conductive pillar 121 electrically connects to one end of the conductive feature 118 (e.g., through the passivation layer 120, or more specifically, through the opening in the passivation layer 120). The conductive pillar 121 is attached to the solder tip 124 through the interfacial layer 122 at the other end. The chip 104 is then flipped to face the traces 110 of the first substrate 102. In some embodiments, the first substrate 102 further includes a solder resist layer (or solder mask layer) 125 for protection, such as protecting the unbonded areas of the first substrate 102 from the solder . To enhance the embodiment, the solder resist layer 125 is patterned to form openings, such that the traces 110 are exposed for bonding with the bumps 108. As shown in FIG.

The bump-on-trace bonding structure 106 may have different designs, such as different material layers, and other integration considerations, such as electrical connection and passivation, for a better bonding effect. FIG. 3B shows a cross-sectional view of a portion of an IC structure 100 constructed in accordance with some other embodiments. The conductive pillar 121 is connected to the interconnect structure 116 (particularly to the conductive feature 118) via one or more additional layers of conductive material 126, such as under bump metallization (UBM). The UBM 126 provides a low resistance electrical connection to the conductive feature 118 and is well attached to both the conductive feature 118 and the passivator layer 120 and is hermetically sealed, Prevents diffusion of the bump metal, and can be wetted by the bump metal. The UBM requires a number of different metal layers, such as an adhesive layer, a diffusion barrier layer, a solderable layer, and an oxidation barrier layer. In some instances, UBM 126 includes each of the multi-film stacks as titanium, chromium, aluminum, copper, nickel, gold, an alloy of one or more of the foregoing metals, or a combination of such metals and alloys. To enhance the example, the UBM 126 may include an adhesive layer (e.g., a Ti / Cr / Al layer); A diffusion barrier layer (e.g., a Cr: Cu layer); And a solder wetting layer (e.g., a Cu / Ni: V layer).

The geometry of the bumps 108 and traces 110 and the relative positions and sizes of the bumps 108 and traces 110 are further described with reference to other figures, in accordance with different embodiments.

Referring to Fig. 4, as a top view of a portion of the IC structure 100, in accordance with some embodiments. The bumps 108 are disposed on the bonded portion of the paired traces 110. The bump 108 has a long shape extending over the first dimension D1 in the first direction 128A and the second dimension D2 in the second direction 128B. D1 is larger than D2. The axis of the bump 108 along the first direction 128A is referred to as the major axis and the axis of the bump 108 along the second direction 128B is referred to as the minor axis. In some embodiments, along the minor axis, the bonded portion of the trace 110 spans a dimension that is less than the corresponding dimension D2 of the bump 108. The bumps 108 may have different shapes.

Referring now to FIG. 5, there is shown a top view of three exemplary structures consistent with an embodiment of a long bump-on trace bonding structure. The structure 130 includes a bump 108 formed on the trace 110, and the bump is shaped as a rectangle having two convex curved surfaces. The long, elongate axis runs coaxially, i.e. parallel or substantially parallel to the axis of the trace 110. The structure 132 includes an elliptical bump 108 formed on the trace 110. The major axis of the ellipse is also coaxial to the trace 110. Similarly, the structure 134 includes a capsule-shaped bump 108 formed on the trace 110. The long axis of the bump 108 is also coaxial to the trace 110. The long axis of the elongated bump aligns in the trace line direction to maximize the space on the bump side for the nearest neighbor trace. The features described above in this embodiment allow for more dense pattern bumping and bonding pitches, allowing for tighter metal spacing design rules.

In some embodiments, the IC structure 100 includes a subset of the chips 104 having the elongated bumps 108 configured and oriented as described, and a subset of chips 104, such as bumps having a circular or square shape in plan view, Lt; RTI ID = 0.0 > 104 < / RTI > 10 shows a top view of an IC structure 100 having a hybrid configuration. 10, the IC structure 100 includes exemplary chips 104A and 104B that are designed to have elongate bumps that are oriented toward the center 112 of the first substrate 102. In FIG. IC structure 100 further includes an exemplary chip 180 having a conventional bump 182, such as a bump having other shapes with a substantially similar dimension on a round, square, or orthogonal axis, Are collectively referred to as symmetrical bumps. In the hybrid IC structure 100, the chip 104 with the elongate bumps is designed similar to that shown in Fig. For example, the elongate bump 108 is oriented toward the center 112 and is coaxial with the corresponding trace 110.

Figure 6 shows a top view of a bump on trace bonding structure of various embodiments. In particular, the bumps may be elongated in a subset of the chips, or symmetrical in another subset of the chips. The structure 136 includes bumps 108 and traces 110 having the same dimensions in the minor axis (the bumps 108 are not visible because they completely overlap the traces 110). The structure 138 includes a bump 108 and traces 110 having a rounded shape. The structure 140 includes bumps 108 and traces 110 having a square shape. In other constructions, such as 142, 144, and 146, the bumps 108 have different shapes, as shown in FIG.

In the bump-on-trace bonding structure, bumps 108 and traces 110 may have different relative sizes. Figure 7 shows a top view of a bum-on trace bonding structure, in accordance with various embodiments. In the structure 150, the elongated bump 108 has a dimension greater than that of the trace in the minor axis. In the structure 152, the elongated bump 108 has the same dimensions as the trace in the minor axis. In the structure 154, the elongated bump 108 has a smaller dimension than the trace in the minor axis.

In the bump-on-trace bonding structure, the bumps 108 and the traces 110 can be arranged and overlapped in different configurations. Figure 8 shows the relative position of the capsule bump relative to the trace line. The elongated bump may protrude from the center of the trace (at 160), overlap at only one portion of the trace at one side (at 162), or centered (at 164) at the trace.

An IC structure 100 having a bump-on-trace bonding structure and its construction, according to some embodiments, is additionally shown in Fig. In Fig. 11, the various chips are not shown, and bump 108 and corresponding trace 110 appear for better understanding as compared to other IC structures to be introduced later. To enhance the embodiment, the routability of the trace 110 is limited by the bump 108.

The IC structures described above in various embodiments include bump on trace bonding structures, but this is not intended to limit the scope of the disclosure of the present invention. Other bonding structures, such as bump-on pad bonding structures, may be included. According to some embodiments, an IC structure 190 is shown in Figure 12 in plan view and Figure 13 in cross-sectional view. IC structure 190 includes a bump-on pad bonding structure for bonding a plurality of chips 104 to a package substrate 102. In Fig. 12, similarly, various chips are not shown, and bump 108 and corresponding pad 192 are shown for better understanding. The IC structures 190 shown in Figures 12 and 13 are fabricated by substantially the same steps and processes and are described in greater detail for the various figures (Figures 1 - 2, 3a, 3b, 4 - 10) And substantially similar structures as described and shown. Thus, the features and steps for the fabrication of the structures shown in Figures 12 and 13, as described above, are not repeated herein to avoid redundant explanations, but are entirely applicable to this embodiment. Elements similar or substantially similar to those shown in Figures 1 - 2, 3A, 3B, 4 - 10 are numbered equally or similarly and are numbered 1 - 2, 3 A - 3 B, 4 - - have the same or similar structures, functions, and manufacturing procedures as described above with respect to FIG. In particular, the bumps 108 have a long shape with a long axis that is oriented toward the center 112 of the packaging substrate 102. In some embodiments, the IC structure 190 further includes a first subset of chips 104 having elongated bumps oriented in the center 112 and a second subset of chip (s) having conventional bumps And has a hybrid structure. In some embodiments, the conductive features 118 (also bumps 108) are pre-shifted for thermal compensation.

The packaging substrate 102 includes a plurality of bonding pads 192 (instead of traces) designed in a configuration that pairs with the bumps 108 of the chip 104. Each chip 104 has a plurality of bumps 108 that are bonded to the corresponding pads 192 of the packaging substrate 102. 13 the solder resist layer 125 is patterned to have a solder resist opening 194 such that the underlying pad 192 is not covered and is bonded to the bump 108 by soldering. Thus, a plurality of chips 104 are bonded to the packaging substrate 102 via the bump-on pad structure. Since the limitation of the trace 110 can be avoided, the bump 108 has a greater design freedom and therefore has greater design possibilities.

Figure 14 is a flow diagram of a method 200 of making an IC structure 100 (e.g., the IC structure of Figure 1 or Figure 10), in accordance with some embodiments. Additional steps may be provided before method 200, during method 100, and after method 100, and some of the steps described below may be replaced or removed for further embodiments of the method . While the following description is for a bump on trace structure, it is practically applicable to a bump on pad structure.

The method 200 begins at operation 202 and at operation 202 an integrated circuit or portion thereof is formed on the chip 104 or partially formed. Operation 202 includes forming a plurality of chips 104 (e.g., 104A, 104B, etc.) having individual circuits. In the following description, it is understood that although only one chip is mentioned, many chips can be manufactured with similar technology. In some instances, the various chips are processed in parallel or independently prior to bonding to the substrate 102. Each chip 104 includes a semiconductor substrate, such as a silicon substrate. Alternatively, the substrate may be formed of other elemental semiconductor materials such as SOI, germanium, compound semiconductors such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide, and silicon oxides such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, A mixed crystal semiconductor material such as a phosphide, and / or other substrate compositions known in the art.

An integrated circuit is formed using, for example, a conductive layer, a semiconductor layer, and an insulating layer disposed on a substrate. In operation 204, an opening is formed in the surface of the integrated circuit to create a bonding structure. In operation 206, a metal layer is deposited on the integrated circuit surface and patterned with the desired encapsulated metal column for interconnect, in operation 208, to form a capillary column with a metal layer in operation 210 Is etched. The interconnected pillar structure formed provides electrical contact to the package terminal from the device of the integrated circuit. The conductive pillar of the interconnect structure may be formed of a material selected from the group consisting of aluminum, an aluminum / silicon / copper alloy, titanium, titanium nitride, tungsten, polysilicon, copper, copper alloy, tantalum, tantalum nitride, metal silicide (e.g. nickel silicide, cobalt silicide, , Tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or combinations thereof), and / or other suitable materials. The interconnect column structures may be formed by processes including physical vapor deposition (or sputtering), chemical vapor deposition (CVD), plating, and / or other suitable processes. Other fabrication techniques used to form the interconnect post structures may include photolithography processes and etching to pattern the conductive layer for vertical columns and may be etched back or chemical mechanical polished (CMP) processes Can be followed.

In a next operation 210, a solder tip is deposited on the tip of the column. In operation 212, a chip including an integrated circuit is flipped to face the trace line 110 (or bonding pad 192) to which the solder tip is to be connected.

The method 200 then proceeds to operation 214 where the conductive layer is formed on a separate substrate 102 and the conductive layer is patterned to form a trace (or pad) Then operation 216 follows. The conductive layer may be performed using techniques such as photolithography, baking, exposure, development, wet or dry etching, and / or other suitable processes, including forming a photoresist layer. In some embodiments, a bump on trace structure is formed and the trace lines are routed and connected to other interconnect features of the substrate 102 at different locations. In some other embodiments, a bump-on pad structure is formed and the pads are connected to interconnecting features underlying the substrate 102 at the same location. In order to enhance the embodiment, since the routing of the trace lines is avoided, the bumps 108 gain additional design freedom.

Then, if the solder resist layer is deposited and patterned to form the interconnect opening, the method 200 proceeds to operation 218. The solder resist layer protects from any undesirable interconnection shortages outside the defined openings where the trace lines are exposed to conform to the solder posts. In some other embodiments, a solder resist opening 194 is formed such that a bump-on pad structure is formed and the pad 192 is exposed and bonded to the bump 108 within the solder resist opening 194 by solder.

The method 200 then proceeds to operation 220 where the flip chip is aligned with the second substrate and the column with the solder tip will overlay the conductive trace to form an interconnect . A number of processes, for example, heat air reflow or thermal ultrasonic bonding, can be applied to liquefy the solder tip to form interconnections. Operation 222 completes the bonding to provide insulation, support, and stability, for example, by underfilling the gap around the column with an adhesive of a polymeric material.

15 is a flow diagram of a method 250 of making an IC structure (e.g., IC structure 100 of FIGS. 1 and 10 or IC structure 190 of FIG. 13), according to some embodiments. The IC structure includes various bonding features such as bumps 108 and traces 110 (or bumps 108 and pads 192). The method 250 of the flowchart of FIG. 15 may include a subset of the operations to create the IC structure 100 (or IC structure 190). The method 250 begins at 252 by receiving an IC design for the IC structure. In some embodiments, the IC design includes a conductive structure to be formed on the first substrate 102 and a circuit to be formed on the various chips 104. In particular, the circuit to be formed on the chip 104 includes various conductive features 118 of the chip and the conductive structure to be formed on the first substrate 102 includes traces 110 (or pads 192) do. In some embodiments, the first substrate 102 may further include a circuit or device to be formed thereon. In this case, the IC design also includes circuitry to be formed on the first substrate 102.

The method 250 also includes operation 254 by redesigning the conductive feature 118 using a pre-shift for thermal compensation. The bump 108 is also shifted. In some instances, the conductive feature 118 is not shifted, but the bump 108 is shifted by action 254 if the mismatch is within a certain range. In some instances, the conductive features 118 are not shifted, but the traces 110 (or the pads 192) are shifted by the act 254 so that the traces 110 (or the pads 192) Bump < RTI ID = 0.0 > 108 < / RTI >

The pre-shift can be individually determined according to the difference in thermal expansion between the first substrate 102 and the chip 104 and the location of the bump on trace bonding structure 106 (or bump-on pad structure) with respect to the center 112 have. As described above, the pre-shift may be performed using a conductive feature (e.g., a silicon nitride film) to compensate for the discrepancy between the first substrate 102 and the chip 104 during the bonding process due to the different thermal expansion of the first substrate 102 and the chip 104 118). During the bonding process, the first substrate 102 and the chip 104 are heated to a high temperature and then cooled. The original IC design includes traces 110 and conductive features 118 that are arranged such that each pair is aligned with one another. However, when heated, the first substrate 102 and the chip 104 are inflated differently due to different thermal expansion coefficients. This will result in inconsistencies or stresses after bonding in the order of heating and bonding. The discrepancy (or stress) is determined by the relative configuration of the chip 104 relative to the first substrate 102 of the bonding structure, the coefficient of thermal expansion of the first substrate 102 and the chip 104, and the highest heating temperature of the bonding process . These factors are considered in determining the discrepancy. Because each pair of traces (or pads) and bumps have different locations with respect to the center 112, the corresponding mismatches may be different from each other. Operations 254 for redesign are implemented in each pair individually according to their respective mismatches. In some embodiments, the bonding process may include an order of first heating the first substrate 102 and the chips 104, and then contacting them to bond each other. Thus, at the heated temperature, each pair of bumps 108 and traces 110 (or pads 109) are matched because the mismatch is compensated. The redesign can be implemented differently for a better bonding structure in consideration of positional coincidence, stress, and / or bonding strength.

In some embodiments, operation 254 also includes reshaping the bump 108, as described above. For example, reformation includes modifying the bump 108 such that the long axis of the bump has a long shape that is oriented to point to the center 112 of the bonding structure.

The method 250 may also include an operation 256 by creating a photomask defining a pattern of bumps 108 and another photomask according to a redesigned IC design pattern. Alternatively, when the IC pattern is directly formed on the semiconductor substrate, such as directly recorded by the electron beam, the pattern may be recorded in a data file of a suitable format (e.g., GDS format) to be used by electron beam lithography .

The method 250 proceeds to operation 258 by fabricating the IC structure 100 or 192. The fabrication of the IC structure includes bonding the chip 104 to the first substrate 102. In some embodiments, the fabrication of the IC structure also includes forming a first substrate 102 and a chip 104. In this embodiment, the fabrication of the IC structure is an alternative method that is equivalent to the method 200, or method 200.

The present disclosure provides IC structures and methods of making the same. In some embodiments, the IC structure 100 or 190 includes a plurality of chips 104 bonded to a substrate 102. In particular, a portion of the bump or bump of the chip 104 is designed to have a long shape with a long axis toward the center 112 of the first substrate 102, and the paired traces 110 Structure). In some embodiments, the bumps are pre-shifted to compensate for mismatches due to different thermal expansion coefficients. Various embodiments of the IC structure and its fabrication method can provide various advantages. For example, the formed IC structure has strong bonding strength and less mismatch.

Accordingly, disclosure of the present invention provides an IC structure in accordance with some embodiments. The IC structure is a first substrate, having a plurality of conductive features formed on a surface thereof; And a plurality of chips mechanically bonded to and electrically coupled to the first substrate. The first of the plurality of chips has a first bump attached to the first one of the plurality of conductive features. The first bump has an elongated cross-section in a plane parallel to the surface of the first substrate. The first substrate and the first chip are bonded in such a configuration that the long axis of the first bump indicates the center position of the first substrate and is oriented to point in a direction deviating from the center of the first chip.

The present disclosure also provides IC structures in accordance with some embodiments. The IC structure is a first substrate, having a plurality of interconnect features formed on a surface; And a plurality of chips mechanically bonded to and electrically coupled to the first substrate. The first of the plurality of chips each has a first subset of conductive bumps attached to a first subset of the plurality of interconnect features. The first subset of conductive bumps have an elongate cross-section in a plane parallel to the surface. The first chip and the first substrate are oriented such that the center position of the first chip is offset from the center position of the first substrate in a plan view and the first subset of conductive bumps are substantially pointing to the center position of the first substrate And is bonded with a configuration having individual long axes.

The present disclosure also provides a method of manufacturing an IC structure in accordance with some embodiments. The method includes receiving an IC design layout defining a plurality of conductive bumps; And re-forming the first conductive bump of the plurality of conductive bumps on the IC design layout according to the configuration between the chip and the packaging substrate when the chip is bonded to the packaging substrate, thereby creating a modified IC design layout , And a re-forming step. The first conductive bump has an elongated cross section having a first length along a first major axis, the first major axis having a first orientation parallel to the first direction defined in the configuration from the first conductive bump of the chip to the center position of the packaging substrate, Respectively.

The foregoing has described features of various embodiments to enable those skilled in the art to more fully understand aspects of the disclosure of the present invention. Those skilled in the art will readily appreciate that the present disclosure can readily be used as a basis for designing or modifying structures and other processes that achieve the same benefits of the embodiments introduced herein and / or perform the same purpose. Those skilled in the art should also realize that the equivalent structure does not deviate from the spirit and scope of the disclosure of the present invention, and various changes, substitutions and changes can be made herein without departing from the spirit and scope of the present disclosure.

Claims (10)

In an integrated circuit (IC) structure,
1. A first substrate, comprising: a first substrate having a plurality of conductive features formed on a surface; And
A plurality of chips mechanically bonded to and electrically coupled to the first substrate
/ RTI >
Wherein a first one of the plurality of chips has a first bump attached to a first one of the plurality of conductive features,
Wherein the first bump has an elongated cross-section in a plane parallel to the surface of the first substrate,
Wherein the first substrate and the first chip are bonded with a configuration in which the major axis of the first bump indicates a center position of the first substrate and is oriented to point in a direction deviating from a center position of the first chip, Circuit (IC) structure. 2. The integrated circuit (IC) structure of claim 1, wherein the first conductive feature is elongate and coaxial with the first bump. The method according to claim 1,
The first chip comprising a second bump attached to a second one of the plurality of conductive features and having an elongated cross-section in the plane,
The long axis of the second bump is oriented differently from the long axis of the first bump,
Wherein the major axis of the second bump points to the first substrate center position and to a direction away from a center position of the first chip. The method according to claim 1,
The first bump is attached to the first conductive feature via solder,
Wherein the first substrate further comprises a solder resist layer having an opening exposing the first conductive feature. ≪ RTI ID = 0.0 > 11. < / RTI > 2. The integrated circuit (IC) structure of claim 1, wherein the first bump comprises a conductive pillar and a solder material formed on the conductive pillar. The integrated circuit (IC) structure of claim 1, wherein the first substrate is selected from the group consisting of a packaging substrate, a printed circuit board, an interposer, and a semiconductor substrate. The semiconductor memory device according to claim 1, wherein each of the plurality of chips includes:
A semiconductor substrate,
A plurality of devices formed on the semiconductor substrate, and
An interconnect structure on the plurality of devices, the interconnect structure being configured to couple the plurality of devices to a functional circuit
And an integrated circuit (IC) structure. In an integrated circuit (IC) structure,
1. A first substrate, comprising: a first substrate having a plurality of conductive features formed on a surface; And
A plurality of chips mechanically bonded to and electrically coupled to the first substrate
/ RTI >
Wherein a first one of the plurality of chips has a first subset of conductive bumps attached to a first subset of the plurality of conductive features,
The first subset of the conductive bumps having an elongated cross-section in a plane parallel to the surface,
Wherein the first chip and the first substrate are spaced apart from a central position of the first substrate in a plan view and a first subset of the conductive bumps Wherein each of the first and second longitudinal axes is bonded to a configuration having a respective major axis oriented to be oriented. A method of fabricating an integrated circuit (IC) structure,
Receiving an IC design layout that defines a plurality of conductive bumps; And
Reshape the first conductive bump of the plurality of conductive bumps on the IC design layout in accordance with the configuration between the chip and the packaging substrate when the chip is bonded to the packaging substrate, Lt; RTI ID = 0.0 >
Lt; / RTI >
Wherein the first conductive bump has an elongated end face having a first length along a first major axis and wherein the first major axis is in a first direction defined from the first conductive bump of the chip to the center position of the packaging substrate in the configuration Wherein the first orientation is parallel to the first orientation. 10. The method of claim 9,
Forming the conductive bump on the chip in accordance with the modified IC design layout
≪ / RTI > further comprising the steps of:

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