KR20160084511A - Method for manufacturing flexible electronic device and flexible memory device manufactured by the same - Google Patents
Method for manufacturing flexible electronic device and flexible memory device manufactured by the same Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
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Abstract
A method of manufacturing a flexible memory device, comprising: sequentially depositing a release layer, a buffer oxide layer and a memory element on a rigid substrate; A step of lifting off the buffer layer and the element layer including the memory element by weakening the adhesive force between the hard substrate and the release layer by laser irradiation on the back surface of the hard substrate; And transferring the element layer peeled off by the lift-off onto a flexible substrate.
Description
The present invention relates to a flexible electronic device manufacturing method and a flexible memory device manufactured thereby, and more particularly to a flexible memory device capable of preventing possible thermal damage during laser irradiation, and as a result, To a flexible electronic device manufacturing method capable of large area transfer and a flexible memory device manufactured thereby.
Flexible electronics are being extensively studied to implement system on plastic (SoP) applications as next-generation electronics in a wide range of fields, from consumer electronics to bio-integrated medical devices.
In particular, flexible memory is considered to be an essential component for SoP application due to its significant role in data processing, storage and communication with external devices.
Many researchers have studied a variety of organic material-based flexible memories, including flash memory, ferroelectric memory, and resistive memory, fabricated directly on flexible substrates at relatively low temperatures using spin coating, roll-to-roll, I have.
Although these organic material-based flexible memories have the advantage of making flexible electronic products on a large area in a cost-effective manner, they suffer from insufficient performance due to intrinsic material properties and incompatibility with complementary metal oxide semiconductor (CMOS) processes It is difficult to develop a high performance high density flexible memory.
In order to overcome these limitations, there is a technique of transferring an inorganic material treated at a high temperature on a rigid substrate onto a flexible substrate, as a method of realizing excellent performance of an inorganic material on a flexible substrate. Several conceptual high performance integrated circuit devices such as integrated circuits, inorganic light emitting diodes, and nano-generators have been successfully fabricated by transferring micropatterned inorganic nanomembranes onto flexible substrates. This transfer printing method enables superior electrical performance over conventional methods.
Resistive random access memory (RRAM) was seen as promising next generation nonvolatile memory due to its simple structure, high switching speed, low power consumption, and high packaging density. In a previous study, we have demonstrated two types of flexible RRAMs (ie, one transistor - one memristor (1T-1M) and one diode - one resistor (1D-1R)).
This structure was made from an ultra-thin monocrystalline silicon film printed on a plastic substrate to prevent inter-cell interference. However, the difficulty of multilayer metallization due to inevitable orientation inaccuracies in the transfer process has made it difficult to attempt to reduce the size to nanosize. In particular, aside from the cost of silicon-on-insulator (SOI) wafers, the basic thermal instability of the polymer interfered with integration with other functional electronic materials / devices, which required high temperature processing after transfer printing . These factors have consistently limited the achievement of high density flexible memory for SoPs.
In recent years, there has been a new approach to transfer all devices fabricated on rigid substrates at high temperatures onto flexible substrates. Several excellent methodologies have been explored to achieve mechanical flexibility, high performance, nano-feature size, nano-scale alignment and versatility, such as chemical / mechanical thinning of wafers, epitaxial layer transfer and stress control delamination. Though these studies have positively directed high performance flexible electronic products including static random access memory (SRAM) on flexible substrates, major issues such as complex processes, limited applicability, high cost and unpredictability of transfer It still remains a challenge.
SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a novel flexible memory device fabrication method capable of implementing flexibility with respect to an inorganic-based device and a flexible memory device manufactured thereby.
According to an aspect of the present invention, there is provided a method of manufacturing a flexible electronic device, comprising: sequentially laminating a release layer, a buffer oxide layer and an electronic device on a rigid substrate; A step of lifting off the buffer layer and the element layer including the electronic element by weakening the adhesive force between the hard substrate and the release layer by laser irradiation on the back surface of the hard substrate; And transferring the element layer peeled off by the lift-off onto a flexible substrate.
In one embodiment of the present invention, the electronic device is a memory device.
In one embodiment of the present invention, the release layer and the buffer oxide layer include an inorganic material, and the release layer and the buffer oxide layer do not melt even in a high temperature process of 200 degrees Celsius or more.
In one embodiment of the present invention, the release layer is hydrogenated amorphous silicon (a-Si: H).
In one embodiment of the present invention, the buffer oxide layer has a thickness of 0.5 to 1.5 mu m.
In one embodiment of the present invention, the buffer oxide layer comprises silicon oxide.
In one embodiment of the present invention, the electronic device includes a plurality of
In one embodiment of the present invention, the
The present invention provides a flexible memory device manufactured by the above-described method.
In one embodiment of the present invention, the flexible memory device is a resistive memory device (RRAM)
The resistor RRAM includes a plurality of
The present invention produces inorganic-based flexible memory devices on plastic substrates through inorganic-based laser lift-off (ILLO) processes.
The manufacturing method according to the present invention is capable of preventing possible thermal damage during laser irradiation, and as a result, large-area transfer of the memory device onto a flexible substrate is possible without mechanical damage during the transferring process.
1A schematically shows a process of manufacturing a flexible 1S-1R RRAM on a plastic substrate by a laser irradiation process.
Figure IB shows the simulated temperature distribution between the release layer and the buffer oxide layer during the ILLO process. Through this simulation, it was confirmed that the heat flow generated on the delamination layer by laser irradiation with a high energy density of 500 mJ / cm 2 and a duration of 30 nsec is blocked by the buffer layer of 1.1 μm thickness.
Figure 1C shows a cross-sectional scanning electron microscopy (SEM) image of the overall structure of each layer on a glass substrate prior to the ILLO process.
1D is an enlarged optical image in front (upper region) and rear (lower region) of a 32 x 32 RRAM array after transfer to a flexible substrate.
Figure 1e shows a photograph of a flexible 1S-1R RRAM fabricated on a 50 micrometer thick flexible polyethylene terephthalate (PET) film with an active area of 0.5 x 0.5 cm < 2 & gt ;.
2A shows a schematic structure of a unit cell of vertically stacked 1S-1R RRAM and a material used therein.
FIG. 2B is a diagram showing the symmetrical and nonlinear IV characteristics of a Ni / TiO 2 / Ni selection device in a semi-log scale.
FIG. 2C is a circuit diagram of the IV characteristic of the flexible 1S-1R memory unit cell in the DC sweep mode.
2E to 2F are mechanical reliability evaluation results obtained by measuring changes in electrical properties according to the bending radius and the number of times of the flexible 1S-1R memory of the plastic substrate.
FIG. 2E shows current variation values according to various curvature radii.
Figure 2f shows the results of good mechanical stability during 1000 bending cycles of the device.
FIG. 3A shows the results of the electrical response of the 1S-1R memory and the resistance switching by the voltage pulse according to the input voltage pulse.
FIG. 3B is a graph showing that the 1S-1R element according to an embodiment of the present invention has non-linearity up to 2x10 4 sec as well as excellent retention in data storage.
FIG. 3C shows the cumulative probability at V read and 1 / 2V read obtained from the IV curve of a 40 unit cell.
FIG. 3D shows the statistical distribution of the SET and RESET voltages of the flexible 1S-1R RRAM obtained from the IV curve through a box-whisker plot.
Figure 4A is an illustration of an important function of a select element integrated in a crossbar array.
FIG. 4B shows a result of measuring data stored in the resistance-variable element in a state where a worst case exists in which data leakage paths to all neighboring cells are present.
4C shows the result of the addressing test based on the LRS (logic state "1") and HRS (logic state "0") currents through a 3 x 3 image representing "KAIST ".
Hereinafter, embodiments and examples of the present invention will be described in detail with reference to the accompanying drawings, which will be readily apparent to those skilled in the art to which the present invention pertains.
It should be understood, however, that the present invention may be embodied in many different forms and is not limited to the embodiments and examples described herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.
Throughout this specification, when an element is referred to as "including " an element, it is understood that the element may include other elements as well, without departing from the other elements unless specifically stated otherwise.
The terms "about "," substantially ", etc. used to the extent that they are used throughout the specification are intended to be taken to mean the approximation of the manufacturing and material tolerances inherent in the stated sense, Accurate or absolute numbers are used to help prevent unauthorized exploitation by unauthorized intruders of the referenced disclosure. The word " step (or step) "or" step "used to the extent that it is used throughout the specification does not mean" step for.
Throughout this specification, the term "combination thereof" included in the expression of the machine form means one or more combinations or combinations selected from the group consisting of the constituents described in the expression of the machine form, And the like.
Throughout this specification, the description of "A and / or B" means "A or B, or A and B".
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. A flexible memory of one selected element-one resistor (1S-1R) crossbar structure is fabricated on a plastic substrate through an inorganic laser lift off (ILLO) process.
In one embodiment of the present invention, a 32 32 1S-1R crossbar memory array for 1 kbit flexible memory was fabricated from an inorganic laser reactive release layer on a rigid substrate using a conventional CMOS process, Lt; / RTI >
In order to predict and prevent possible thermal damage during laser irradiation, the structural design was optimized with finite element analysis simulations. Based on these simulations, the dry ILLO process was used for large area transfer of memory devices onto flexible substrates without mechanical damage during the transfer process. Respectively.
Finally, 1S-1R RRAM (resistive memory element) cells formed on a plastic substrate successfully functioned in the worst case affected by leakage path suppression of the integrated select device.
The ILLO method according to an embodiment of the present invention can be applied to various high-performance electronic products such as a display driver circuit and even an electronic device requiring a very high-temperature process.
1A schematically shows a process of manufacturing a flexible 1S-1R RRAM on a plastic substrate by a laser irradiation process.
Referring to FIG. 1A, a unit cell of an RRAM on a glass substrate is composed of a selection device for preventing inter-cell interference and a resistive memory for resistance switching.
In the present invention, a bipolar resistive switching material is used for information storage by using a selector as a selection element for a memory having a high density crossbar structure.
All of the memory cells are interconnected through the lower and upper electrodes electrically isolated by an insulator to form a crossbar structure. That is, as shown in FIG. 1A, an inorganic-based flexible device according to an embodiment of the present invention includes a plurality of
In addition, the inorganic-based flexible element according to an embodiment of the present invention is formed such that the
That is, in order to manufacture a flexible memory device based on an inorganic rather than an organic material, a selective element and a resistance element are provided between electrodes of a crossbar type made of metal, and a laser is irradiated on the back surface to form a thin And an inorganic flexible element is manufactured in such a manner that the inorganic flexible element is peeled off.
In one embodiment of the present invention, a XeCl excimer laser with a wavelength of 308 nm was irradiated through the back surface of the glass substrate to reduce the adhesion between the release layer and the substrate. Consequently, only the upper inorganic layer (103 in Fig. 1A) is selectively removed from the substrate as shown in Figs. 1A-II. This process is explained by the dissociation of the local dissolution, vaporization or laser reactive release layer as a result of the interaction of the laser material.
The
Finally, the peeled layer was transferred to a plastic substrate coated with an ultraviolet (UV) sensitive polyurethane (PU, NOLLAND optical adhesive, No. 73) as an adhesive (corresponding to FIGS. 1A-iii)
The present invention has performed a finite element analysis (FEA) simulation using COMSOL software to determine the structural optimization for the buffer oxide layer to be effective as a thermal barrier to prevent damage to the heat flow induced by laser irradiation.
This analysis was done according to the calculation of the temperature distribution between the release layer and the buffer oxide layer during the ILLO process. Figure 1b shows the simulated temperature distribution between the release layer and the buffer oxide layer during the ILLO process. Through this simulation, it was confirmed that the heat flow generated on the delamination layer by laser irradiation with a high energy density of 500 mJ / cm 2 and a duration of 30 nsec is blocked by the buffer layer of 1.1 μm thickness.
Figure 1C shows a cross-sectional scanning electron microscopy (SEM) image of the overall structure of each layer on a glass substrate prior to the ILLO process.
Referring to FIG. 1C, in one embodiment of the present invention, a 50 nm thick hydrogenated amorphous silicon (a-Si: H) deposited by plasma enhanced chemical vapor deposition (PECVD) . That is, the XeCl laser can pass through a non-alkali glass substrate (Nippon Elcetric Glass, OA-10G, thickness of 500 μm) and has a transmittance of 70% or more at a wavelength of 308 nm. Finally, it reaches the a-Si: H film, where the laser dissolves the a-Si: H film and releases hydrogen to weaken the adhesion between the a-Si: H film and the glass substrate. The resultant weakened adhesion has made it possible to easily and safely separate the entire device layer from the glass substrate without serious mechanical deformation of both the device and the buffer oxide layer.
Based on the simulation of FIG. 1B, a silicon oxide having a thickness of 1.1 mu m was deposited by PECVD between the device and the release layer.
In the present invention, including the peel and buffer oxide layers, all the materials used were inorganic materials that enabled high temperature processing, in contrast to the process of organic materials. In addition, the mechanical stability of the ILLO process in accordance with one embodiment of the present invention has been demonstrated by cross-sectional SEM images after laser irradiation.
Referring to the top inset portion of FIG. 1C, no cracks or wrinkles were found over the entire area of the sample after the optimized ILLO process. It is well known that mechanical instabilities such as cracks and wrinkles are caused by collisions between in-plane and out-of-plane stresses. Thus, the stress relaxation and stability of the ILLO process in the present invention has been achieved by optimizing the laser duration and controlling the thickness of the buffer oxide layer in terms of thermal and mechanical stability.
The lower insertion portion of FIG. 1 (c) shows a detailed cross-sectional bright-field transmission electron microscopy (BFTEM) image of the device layer.
Referring to the lower inset portion of FIG. 1C, the lower electrode BE of the Ti / Ni and the Ni intermediate electrode ME were patterned by radio frequency (RF) sputtering, lithography, and lift-off on a glass substrate.
A 10 nm thick TiO 2 film was deposited by atomic layer deposition (ALD) between the BE and the ME to form a Schottky contact. For resistance switching, NiO x and Pt top electrodes (TE) were formed by O 2 plasma oxidation and RF sputtering, respectively, at room temperature. The resistance switching mechanism of the Ni / NiO X / Ti / Pt resistance switching layer can be explained by the formation and rupture of conductive filaments by the migration and diffusion of oxygen ions.
An enlarged optical image in front (upper region) and rear (lower region) of a 32 x 32 RRAM array after transfer to a flexible substrate is shown in Figure 1d.
Referring to FIG. 1D, a word line WL and a bit line BL corresponding to the Pt upper electrode and the Ni lower electrode form a crossbar structure, and control the logic state change of each memory unit cell.
1D shows the height image of the atomic force microscopy (AFM) of a manufactured RRAM unit cell with a line width of 25 m.
Referring to FIG. 1D, the ME has a rectangular shape with a tolerance of 15 m between TE and BE (55 m 55 m) for electrical isolation of memory cells in adjacent cells.
In the present invention, the stripe pattern was analyzed from the back of the transfer layer, which corresponds to the overlapping regions of the first and second two-dimensional (620 μm x 620 μm) laser irradiation (shots). To clarify this pattern, SIL observation and X-ray photoelectron spectroscopy (XPS) analysis were performed on the overlapping portions of the laser irradiation of the peeled layer after the ILLO process.
The SEM image of the lower inset of FIG. 1d shows that the agglomerated particles are randomly distributed over the overlap of the laser irradiation of the buffer oxide layer. XPS analysis also shows that these aggregated particles are derived from silicon and can be removed by SF 6 plasma.
Figure 1e shows a photograph of a flexible 1S-1R RRAM fabricated on a 50 micrometer thick flexible polyethylene terephthalate (PET) film with an active area of 0.5 x 0.5 cm < 2 & gt ;.
Referring to FIG. 1E, it can be seen that the flexible memory fabricated in accordance with one embodiment of the present invention maintains considerable bendability (flexibility) due to the very thin inorganic material and the optimized device structure thereof.
The inset picture of FIG. 1e shows that the glass substrate is separated from the stripped device after the ILLO process. The above-described method according to the present invention can be easily applied to a wafer-scale substrate. Therefore, the present invention can effectively overcome the limitations on the size which has been a challenge in the field of flexible electronic devices, and after the element layer is separated, the remaining sacrificial substrate can be reused many times, which is cost effective.
2A shows a schematic structure of a unit cell of vertically stacked 1S-1R RRAM and a material used therein.
Referring to FIG. 2A, a selection element of a unit device according to the present invention is composed of a Ni lower electrode line BE, titanium oxide (TiO 2 ), and a rectangular Ni intermediate electrode ME.
The internally inserted TiO 2 layer forms a Schottky barrier between the Ni lower electrode BE and the intermediate electrode ME to provide a nonlinear IV characteristic of the memory cell for suppressing the leakage current.
For resistance switching, a NiO X film is formed monolithically on the ME by an O 2 plasma between the ME and the Pt upper electrode line (TE).
The symmetric and nonlinear IV characteristics of the Ni / TiO 2 / Ni selectors are presented in the left-hand side as a linear scale, in Fig. 2b, as a semi-log scale.
As shown in the inset to the left of Figure 2b, the non-linear current characteristic confirms that the log I to V 1/2 linear fit to the positive voltage range is from the Schottky emission on the Ni / TiO 2 barrier .
The IV characteristic of the flexible 1S-1R memory unit cell in DC sweep mode is shown in FIG. 2c along with its circuit diagram. Basically, Ni / NiO X / Pt shows unipolar resistive switching (URS) in which the switching of the resistance state is "independent" to the voltage polarity. This means that it can act like bipolar switching.
The flexible memory device according to the present invention switches from a high resistance state (HRS) to a low resistance state (LRS) at a negative set voltage (V SET ) of -4.2 V and a positive reset voltage V RESET ) to the HRS.
And linear IV characteristic of the 1R element in the insertion portion in Fig 2c, by contrast, by incorporating a resistive switching element in the selection device, the current is the read voltage (V read from the half of the read voltage (1 / 2V read = 1 V ) = 2 V) by 500 times. This result shows that the leakage current can be minimized effectively in the 1S-1R device as opposed to the 1R device. This is because half-selected cells contribute mainly to leakage current in the cross-point structure where half of the lead voltage is applied.
Theoretically, in order to evaluate the improvement of the read operation of the 1S-1R memory device, a read margin of the crossbar array using one bit-line pull-up (OBPU) .
For lead margin analysis, the I-V curve of the 1S-1R unit cell was fitted using a ninth degree polynomial fitting curve in the low-voltage region (<1 V) and a Schottky emitter and high voltage region. Based on the fitting curves, the numerical solution of the four algebraic Kirchhoff equations was obtained using MATLAB.
A simplified equivalent circuit of the 1S-1R crossbar array using the OBPU scheme is shown in the inset of FIG. 2d. Here, up to the lead margin crossbar determine the size of the array (from V out = V out, HRS V out, LRS, RM = V out / V pu) criteria for at least 10 of the pull-up (pull-up) voltage (V pu) %. Compared to 1R devices, the maximum array size calculated at a minimum 10% lead margin increased sharply to 6.7 x 10 2 (450 kb). This demonstrates the feasibility of the fabricated flexible 32 32 1 kbit 1S-1R memory. The maximum array size is likely to increase to approximately several tens of Mb by using all bit-line pull-up (ABPU) schemes or modulating the tunneling barrier. In particular, it has been difficult to achieve a selective device with a modified energy barrier on a flexible substrate, since a high temperature process is required to control the energy barrier. The mechanical reliability of the flexible 1S-1R memory of the plastic substrate was evaluated through a bending test as a function of bending radius and cycle, and the results are shown in Figures 2e-f.
Figure 2e shows a typical current value for a semi-cylindrical mold with various radius of curvature. The 1S-1R memory has a radius of curvature of 7.5 millimeters [0.33% surface stress (ε = t s / 2R, where t s is the thickness of the substrate and R is the bending deformation) And maintains a constant resistance ratio. However, at a curvature radius of 5 millimeters (corresponding to 0.5% stress) cracks and electrical shorts began to be observed. However, this will be further improved by adopting an encapsulation technique such as a super thin film substrate or a mechanical neutral space.
As shown in Figure 2f, the device exhibits good mechanical stability during bending 1000 repetitions, demonstrating excellent mechanical robustness of the flexible RRAM.
In order to evaluate the reliability of the flexible 1S-1R RRAM according to an embodiment of the present invention, durability and data retention tests were performed under repeated voltage pulses.
The upper graph of FIG. 3A shows the electrical response of the 1S-1R memory to the input voltage pulse. The initial resistance state is set in the HRS and switches from HRS to LRS as voltage pulses of -4.5 V are applied. LRS is maintained during half the reading voltage (1 / 2V read = 1V) and the reading voltage (V read = 2V); Nonlinear IV characteristics can also be observed in pulse mode. The resistance is converted to HRS by applying a voltage pulse of 3.5 V and its resistance state is maintained at half (1/2 V read ) and the read voltage (V read ) of the read voltage.
As shown in the graph at the bottom of FIG. 3A, the resistance switching by the voltage pulse occurs steadily and constantly for over 100 cycles. The retention characteristics of the 1S-1R device were evaluated at a repetitive lead voltage of 2V and half thereof at room temperature.
As shown in FIG. 3B, the 1S-1R element not only has excellent holding power for data storage but also has non-linearity up to 2 x 10 4 sec. A statistical analysis was performed in a 40 unit cell to evaluate the consistency of motion, the results of which are shown in Figures 3c and d.
FIG. 3C shows the cumulative probability of the current at V read and 1 / 2V read obtained from the IV curve of a 40 unit cell.
Referring to FIG. 3C, the HRS and LRS show a narrow distribution without overlap in both V read and 1 / 2V read .
FIG. 3D shows the SET and RESET voltage distributions of the flexible 1S-1R RRAM obtained from the I-V curve through a box-whisker plot.
Referring to FIG. 3D, the programming voltage margin between SET and RESET was stabilized by the selection device integrated compared to the 1R device. This result shows that the integrated selection device plays an important role not only in preventing intercell interference but also as a buffer resistor for suppressing excessive current flow in the SET / RESET process.
An important function of the integrated selection device integrated in the crossbar array is shown in Figure 4a, where a 1-bit line pull-up scheme (OBPU) is considered here for the worst-case read process in which there is a data leakage path to all surrounding cells .:
In this OBPU scheme, the voltage applied on the selected bit line causes a voltage drop of a total of 2V in the device selected in the HRS. On the other hand, the voltage drop of the peripheral cells sharing the bit line with the selected word is less than 1V. Thus, by the integrated selection device with the resistance memory, the current flow through this semi-selected cell was exponentially suppressed due to the nonlinear current characteristics of the selection device.
FIG. 4B shows a result of measuring data stored in the resistance-variable element in a state where a worst case exists in which data leakage paths to all neighboring cells are present.
4C shows the result of the addressing test based on the LRS (logic state "1") and HRS (logic state "0") currents through a 3 x 3 image representing "KAIST ". Referring to the results of FIG. 4C, although there are some variations in the HRS, the results demonstrate that the 1S-1R memory can efficiently operate on the plastic substrate without electrical interference by the selection device with each memory cell.
With reference to the above results, the present invention has introduced a methodology for manufacturing a fully functional flexible memory with a 32 x 32 1S-1R array for high packaging density. The ILLO process used here was able to transfer the memory of the crossbar structure processed on the rigid substrate onto the flexible substrate without any mechanical defects using the existing micromachining in the large area. The inorganic material introduced in this study, including the release / buffer oxide / device layer, can enable high temperature processes that are difficult to realize on conventional plastic substrates. The flexible device developed demonstrates reliable and reproducible resistance switching with excellent mechanical stability on plastic substrates. Finally, an addressing test to confirm the presence of electrical interference was successfully performed under various conditions. I
Experiment
Manufacture of 1S-1R structure resistive memory
The nickel bottom electrode was patterned using radio-frequency (RF) sputtering and a lift-off process. Titanium dioxide TiO 2 (10 nm) was deposited on the nickel bottom electrode by 80 cycles of thermal atomic layer deposition at a substrate temperature of 80 ° C. Tetrakis (dimethylamino) titanium (Ti (N (CH 3) 2) 4, TDMAT) and H 2 O were used as the titanium precursor and oxygen source, respectively. The cycle sequences were TDMAT (1 sec), argon (20 sec), H 2 O (1.5 sec) and argon (20 sec). A rectangular Ni intermediate electrode was formed in the same manner as the lower electrode. The nickel oxide layer was formed on the nickel intermediate electrode by plasma oxidation treatment in an inductively coupled plasma reactive ion etching (ICP-RIE) system with an RF power of 200 W for 5 minutes at room temperature. After formation of the nickel oxide layer, platinum / titanium (250 nm / 10 nm) was deposited as an upper electrode.
Electrical characterization
Electrical characterization and evaluation is performed using Keithley 4200-SCS (DC voltage / current sweep), Keithley 4225-PMU (pulse generator and voltage / current waveform capture) and 4225-RPM (remote amplifier / switch) Respectively.
Claims (12)
Stacking a release layer, a buffer oxide layer and an electronic device on a rigid substrate in this order;
A step of lifting off the buffer layer and the element layer including the electronic element by weakening the adhesive force between the hard substrate and the release layer by laser irradiation on the back surface of the hard substrate; And
And transferring the element layer peeled off by the lift-off onto a flexible substrate.
Wherein the electronic device is a memory device.
Wherein the peeling layer and the buffer oxide layer comprise an inorganic material, and the peeling layer and the buffer oxide layer are not melted even at a high temperature process of 200 DEG C or more.
Wherein the release layer is hydrogenated amorphous silicon (a-Si: H).
Wherein the buffer oxide layer has a thickness of 0.5 to 1.5 占 퐉.
Wherein the buffer oxide layer comprises silicon oxide.
The electronic device includes a plurality of lower electrode lines (110) provided on the buffer oxide layer and spaced apart from each other by a predetermined distance;
A plurality of selection elements (120) stacked on the lower electrode line and spaced apart from each other;
A resistance element 130 laminated on the selection element 120; And
And an upper electrode line (140) formed on the resistance element (130).
Wherein the lower electrode line (110) and the upper electrode line (140) intersect perpendicularly on a plane.
Wherein the flexible memory element is a resistive memory element (RRAM).
A plurality of lower electrode lines 110 provided on the buffer oxide layer and spaced apart from each other by a predetermined distance;
A plurality of selection elements (120) stacked on the lower electrode line and spaced apart from each other;
A resistance element 130 laminated on the selection element 120; And
And an upper electrode line (140) formed on the resistive element (130).
Wherein the buffer oxide layer has a thickness of 0.5 to 1.5 占 퐉.
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| CN114758611B (en) * | 2022-01-26 | 2024-01-05 | 闽都创新实验室 | Basic display driving circuit driven by conductive wire type artificial neuron |
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