KR20160081126A - Device for removing direct current component from digital output - Google Patents

Abstract

Provided is a direct current (DC) removing device comprising: a signal combining unit; a DC offset generating unit; and a DC detecting unit. The signal combining unit receives a digital output signal and a DC offset signal outputted from a digital function block; and generates a summed signal summing the digital output signal and the DC offset signal. The DC offset generating unit generates a DC offset compensating an offset and outputs the DC offset signal to remove a DC component included in the digital output signal. The DC detecting unit receives the summed signal outputted from the signal combining unit and detects whether or not the DC component exists in the summed signal.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a digital output DC elimination device,

The present invention relates to a method and apparatus for removing DC components contained in a digital output.

Frequently, a DC component is included in a digital output outputted from various digital functional blocks. For example, when a digital RF repeater is taken as an example, when a baseband I / Q operation in a digital part is performed, a bit truncation or the like, A DC component may be generated at the output.

If a DC component is included in the digital output from the digital function block, the DC component may adversely affect the performance of the digital part and / or the subsequent signal processing block or the entire system, Or degradation may occur in the service provided by the system.

The present invention is intended to provide a method and apparatus for eliminating DC components contained in a digital output.

According to an aspect of the present invention, a digital output signal and a DC (direct current) offset signal output from a digital functional block are input, and a summed signal obtained by summing the digital output signal and the DC offset signal is generated A signal combiner; A DC offset generator for generating a DC offset to be offset compensated for removing the DC component included in the digital output signal and outputting the DC offset signal; And a DC detection unit for receiving the sum signal output from the signal combining unit and detecting presence or absence of the DC component in the sum signal.

In one embodiment, the DC offset generator may initially generate a DC offset having a predetermined unit size when the DC offset compensation procedure is started.

In one embodiment, each time the DC detection unit determines that a DC component is present in the summation signal, the DC detection unit outputs an output activation signal for outputting a DC offset signal from the DC offset generation unit to the DC offset generation unit Can be delivered to the department.

In one embodiment, the DC offset generator may output a DC offset signal having the unit size to the signal combiner whenever the output activation signal is transmitted from the DC detector.

In one embodiment, the control unit receives the magnitude information of the DC component from the DC detection unit and controls the DC offset value set in the DC offset generation unit to be changed to a DC offset value corresponding to the magnitude information of the DC component delivered from the DC detection unit. The control unit may further include a control unit.

In one embodiment, when the DC detection unit detects that the magnitude of the DC component in the summation signal falls within a predetermined tolerance,

The DC offset generator may store a DC offset accumulation value applied until the time point, and may reflect the DC offset accumulation value in a subsequent DC offset generation.

According to the embodiment of the present invention, the DC component included in the digital output outputted from the various digital functional blocks is minimized, so that the performance of the digital part and / or the downstream signal processing block by the DC component, Deterioration can be prevented.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of a digital repeater to which the present invention is applicable. Fig.
2 is a block diagram of a DC removal device embodied in a digital part in accordance with an embodiment of the present invention.
3 is a flowchart of a DC removal method of a digital output according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention is capable of various modifications and various embodiments, and specific embodiments are illustrated in the drawings and described in detail in the detailed description. It is to be understood, however, that the invention is not to be limited to the specific embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description of the present invention, detailed description of known related arts will be omitted when it is determined that the gist of the present invention may be unnecessarily obscured. In addition, numerals (e.g., first, second, etc.) used in the description of the present invention are merely an identifier for distinguishing one component from another.

Also, in this specification, when an element is referred to as being "connected" or "connected" with another element, the element may be directly connected or directly connected to the other element, It should be understood that, unless an opposite description is present, it may be connected or connected via another element in the middle.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram schematically illustrating an example of a digital repeater to which the present invention is applicable.

Referring to FIG. 1, a down-converter 10, an analog-to-digital converter (ADC) 12, and a digital signal processor (not shown) are connected to a downlink signal transmission path A DAC (Digital to Analog Converter) 14, an up converter 16, and a PAU (Power Amplification Unit) 18 are disposed. (Low Noise Amplifier) 28, a downconverter 26, an ADC 24, a digital signal processor (not shown), and the like, along its signal propagation path on an uplink signal path (i.e., a reverse path) 30, a DAC 22, and an up-converter 20 are disposed.

The down-converter 10 on the downlink signal transmission path receives a radio frequency (RF) signal transmitted from a base station (not shown) by wire or radio, down-converts the RF signal into an IF (Intermediate Frequency) Conversion is performed. The frequency down-converted IF signal is sampled by the ADC 12 and converted into a digital signal having a specific number of bits (for example, 14 bits). The digital signal converted by the ADC 12 is subjected to signal processing by the digital signal processing unit 30 and the digital signal processed signal is input to the DAC 14 and can be converted into an analog signal again. The analog signal output from the DAC 14 is again frequency upconverted to an RF signal by the upconverter 16 and the RF upconverted RF signal is amplified by the PAU 18 and transmitted through a service antenna And may be output to terminals within the coverage.

The uplink signal propagation path may be configured to have the same function as that of the downlink signal propagation path described above, which differs from the signal propagation direction. That is, the LNA 28 on the uplink signal transmission path low-noise amplifies the RF signal input through the service antenna (not shown) and transmits the RF signal to the down converter 26. The down converter 26 converts the RF signal into an IF signal Frequency downconversion. The frequency down-converted IF signal is converted into a digital signal by the ADC 24, and the converted digital signal is subjected to digital signal processing by the digital signal processing unit 30 and then input to the DAC 22. [ The DAC 22 converts a digital signal into an analog signal, and the converted analog signal of the IF band can be frequency-up-converted to an RF signal by the up-converter 20 and transmitted to a base station (not shown).

As described above, in the digital repeater, there is a digital signal processing unit 30 for digital signal processing, and the digital signal processing unit 30 can be implemented by an FPGA (Field Programmable Gate Array) as shown in FIG. 1, the digital signal processing section 30 may be implemented separately on the downlink and uplink, although the digital signal processing section 30 is shown as being implemented in common on the downlink and uplink signal propagation paths.

The digital signal processing section 30 applies a preprogrammed processing algorithm to the digital signal digitally converted by the ADCs 12 and 24 disposed at the front end of the digital signal transmission path to generate image rejection (Digital Signal Processing), FA (Frequency Allocation), or signal processing and multiplexing for each sector. In this way, the digital signal processed by the digital signal processing unit 30 is output to the output device at the end of the digital signal transmission path (in the case of FIG. 1, the downlink signal transmission path and the end of digital signal transmission on the uplink signal transmission path (I.e., a terminal or a base station) through each of the DACs 14 and 22 disposed at the terminating end (i.e., the terminating end).

In the foregoing, a digital RF repeater has been described as an application example to which a DC removing apparatus and method according to an embodiment of the present invention to be described later can be applied. However, in addition to the above, the DC removing apparatus and method according to the embodiment of the present invention may also be applied to each node unit constituting a digital distributed antenna system (i.e., a MU (Main Unit) constituting a head end node, A connected HUB and / or an RU (Remote Unit), etc.). In addition, the DC removing apparatus and method according to embodiments of the present invention may be applied to all applications including digital functional blocks.

2 is a block diagram of a DC removal device implemented in a digital part according to an embodiment of the present invention.

Referring to FIG. 2, a DC elimination apparatus according to an embodiment of the present invention includes a DC offset generator 220, a signal combiner 230, and a DC detector 240. The DC elimination apparatus according to an embodiment of the present invention may further include a controller 250 for controlling the operation of the DC offset generator 220 according to detection information transmitted from the DC detector 240 according to an implementation scheme .

The DC offset generator 220 outputs a DC offset signal for removing a DC component that may be included in the digital output signal output from the digital functional block. Here, the DC offset signal refers to a signal that is generated to perform offset compensation on the DC component to remove (or reduce) the DC component. The DC offset signal thus outputted is input to the signal combining unit 230.

A digital output signal output from the digital functional block and a DC offset signal output from the DC offset generator 220 are input to the signal combining unit 230. The signal combining unit 230 sums the input digital output signal and the DC offset signal and outputs a summed signal (hereinafter referred to as a summed signal).

FIG. 2 illustrates a digital filter 210 as a digital functional block capable of generating a DC component in a digital signal processing or a digital operation. However, it will be understood by those skilled in the art that a functional block capable of generating a DC component in the digital signal processing or digital operation process may be varied. In the following description, it is assumed that the function block for generating the DC component is a digital filter 210 for convenience and concentration of explanation.

2, a digital signal as shown in FIG. 2A is input to the input terminal of the digital filter 210, a DC component is generated as the input signal passes through the digital filter 210, (b) shows a case in which a DC component is included in the digital output. In this case, it is necessary to remove the DC component included in the digital output as shown in Fig. 2 (b). To this end, the DC offset generator 220 generates a DC offset signal to remove the DC component and outputs the DC offset signal to the signal combiner 230. Here, FIG. 2 (c) illustrates the DC offset signal output from the DC offset generator 220. And an example of a digital output in which the DC component is removed according to the DC offset signal is as shown in FIG. 2 (d).

Conceptually, the DC offset signal to be output through the DC offset generator 220 is equal to the magnitude of the DC component included in the digital output from the digital functional block for canceling (canceling) the corresponding DC component And a signal having a phase opposite to that of the signal. 2, a detector for detecting the magnitude of the corresponding DC component between the digital filter 210 and the signal combiner 230 (this is a DC detector disposed at the rear end of the signal combiner 230 in FIG. 2) The detection block 240 may be a functional block having the same or similar function as the detection block 240). The DC offset generating unit 220 generates a DC offset signal having a phase opposite to the magnitude of the DC component received from the DC offset generating unit 220 Output method should be adopted.

However, depending on the design method of the digital part, a case in which the above arrangement and configuration method is difficult to adopt may occur. 2, it may be difficult to increase the interval of the signal transmission path between the digital filter 210 and the signal combiner 230 according to the design method of the digital part, The transmission delay due to the signal transmission path between the signal coupler 210 and the signal combiner 230 may be very short. At this time, if the detection delay due to the detection of the DC component of the DC detector to be disposed in the branch path between the digital filter 210 and the signal combiner 230 becomes longer than the transmission delay, appropriate DC offset compensation may not be achieved. In order to solve the above problem, it is also disadvantageous to employ a method of adding a delay unit for forcibly delaying a signal to be inputted from the digital filter 210 to the signal combiner 230. [

Therefore, the embodiment of the present invention proposes a method capable of performing proper DC offset removal even in a case where it is difficult to adopt the above-described method according to a design method of a digital part.

In the embodiment of the present invention, when the digital output from the digital functional block is input to the signal combining unit 230, the detection of the presence or absence of the DC component in the input digital signal, And a DC component removal process according to a DC offset signal having a predetermined magnitude is first applied. At this time, the detection of the presence of the DC component and / or the magnitude of the DC component is performed for the sum signal after the pre-applied DC offset compensation to verify the effect of the DC offset compensation and the applied DC offset value . As shown in FIG. 2, in the embodiment of the present invention, the DC detection unit 240 is disposed in the branch path at the rear end of the signal coupling unit 230. Accordingly, the DC detector 240 detects whether or not a DC component is present in the sum signal output from the signal combiner 230 and / or the magnitude of the DC component.

Hereinafter, the DC removal method according to the embodiment of the present invention will be more clearly understood from the description of the flowchart of FIG.

3 is a flowchart illustrating a DC removal method of a digital output according to an embodiment of the present invention. Hereinafter, with reference to FIG. 3, a DC removal method according to an embodiment of the present invention will be described with reference to FIG.

As described above, when a digital output from the digital functional block is input to the signal combining unit 230, the DC offset generating unit 220 generates a DC offset signal using a DC offset having a predefined size as in step S110 And outputs it to the signal combining unit 230.

At this time, the DC offset value to be applied (first applied) by the DC offset generator 220 may be determined to be a preset unit size. At this time, the DC offset value of the unit size can be selected experimentally, statistically, or mathematically from the digital output signal output from the corresponding digital functional block. For example, the DC offset value of the unit size can be selected in consideration of the minimum DC size that can be generated in the signal processing or digital operation of the corresponding digital functional block. Here, the minimum DC size can be set to, for example, an average minimum value among values above a magnitude (that is, an allowable value) that does not significantly affect the system despite the DC component included in the digital output. However, the selection method of the unit size may be varied as a matter of course, and it is needless to say that it is not limited to the method specified in this specification.

In accordance with the application of the DC offset, in step S120, the signal combining unit 230 sums the digital output signal output from the digital functional block and the DC offset signal input from the DC offset generating unit 220, and outputs a sum signal .

In step S130, the DC detector 240 detects whether or not a DC component is present in the summation signal output from the signal combiner 230. [ If it is determined that the DC component is not present, the DC removal process through the DC offset generator 220 and the signal combiner 230 may be terminated, but if the digital output continues from the digital function block, It is possible to continue the DC removal process while maintaining the DC offset value of the DC offset value. Here, in the case where it is determined that the DC component does not exist, the case where the DC component has a value within the allowable value may be applicable according to the design method.

Alternatively, if a DC component is detected as a result of the detection, the DC offset generator 220 may output the DC offset signal having the unit size described above to the signal combiner 230 again. If the DC component still exists even though the sum signal is re-output from the signal combining unit 230 in accordance with the re-output of the DC offset signal, the DC offset generating unit 220 outputs the DC offset signal of the unit size again And outputs it to the coupling unit 230. That is, in the embodiment of the present invention, the DC offset signal output (step S110) -> signal summing (step S120) -> DC detection (step S130) may be repeated until the DC component is removed.

For this, each time the DC detection unit 240 determines that the DC component exists in the sum signal according to the detection result, the DC detection unit 240 generates a DC offset signal through the DC offset generation unit 220 and And may transmit an output activation signal to the DC offset generator 220 so that the output is maintained. According to another embodiment, the output activation signal may be generated by the control unit 250 that receives the detection result of the DC detection unit 240 and may be transmitted to the DC offset generation unit 220. Each time the output enable signal is transmitted, the DC offset generator 220 may repeatedly output the unit offset DC offset signal to the signal combiner 230. [

In the above description, the case where the DC detecting unit 240 detects only the presence or absence of the DC component has been described. However, according to the embodiment, the DC detecting unit 240 may detect the magnitude of the DC component. At this time, the magnitude of the detected DC component may be transmitted to the controller 250. In this case, the controller 250 may determine that the DC offset value set in the DC offset generator 220 corresponds to the magnitude of the detected DC component To the DC offset generating unit 220. The DC offset generating unit 220 receives the offset change command from the DC offset generating unit 220, Here, the offset change command may be the control value itself that allows the changed DC offset value to be applied.

When the offset change command is received (step S140), the DC offset generator 220 changes (updates) the set DC offset value to generate and output a DC offset signal corresponding to the changed DC offset value (step S150) .

According to the above-described procedure, when the DC component is removed (or when the size of the DC component falls within an allowable range), the DC offset generator 220 stores the accumulated DC offset applied up to that point, DC offset generation. The following methods can be used as a method of reflecting the cumulative value to future DC offset generation. For example, there may be a method of adjusting the previous unit size up or down considering the accumulated value. As another example, there may be a scheme of substituting (updating) the accumulation value itself with a DC offset value, or applying a DC offset value of several levels lower from the accumulation value to generate a DC offset in the future. Other variations are possible.

Therefore, according to the embodiment of the present invention, the DC offset can be adaptively set by minimizing the DC component by repeating (circulating) the order of the DC offset signal output-> signal summation-> DC detection-> There is an effect.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the following claims And changes may be made without departing from the spirit and scope of the invention.

210: Digital filter
220: DC offset generator
230:
240: DC detector
250:

Claims (6)

A signal combiner for receiving a digital output signal and a DC (direct current) offset signal output from the digital functional block and generating a summed signal by summing the digital output signal and the DC offset signal;
A DC offset generator for generating a DC offset to be offset compensated for removing the DC component included in the digital output signal and outputting the DC offset signal; And
A DC detecting section for receiving the sum signal outputted from the signal combining section and detecting whether the DC component is present in the sum signal,
.
The method according to claim 1,
Wherein the DC offset generator first generates a DC offset having a predetermined unit size when the DC offset compensation procedure is started.
3. The method of claim 2,
Wherein the DC detection unit transmits to the DC offset generation unit an output activation signal for outputting a DC offset signal from the DC offset generation unit whenever a DC component is determined to exist in the sum signal in accordance with the detection result, Removal device.
The method of claim 3,
Wherein the DC offset generator outputs a DC offset signal having the unit size to the signal combining unit whenever the output activation signal is transmitted from the DC detection unit.
The method according to claim 1,
The DC detection unit detects the magnitude of the DC component in the sum signal,
And a controller for receiving size information of the DC component from the DC detector and controlling the DC offset value set in the DC offset generator to be changed to a DC offset value corresponding to the size information of the DC component delivered from the DC detector DC removal device.
The method according to claim 1,
When the magnitude of the DC component in the summation signal falls within a predetermined allowable value as a result of detection by the DC detector,
Wherein the DC offset generator stores an accumulated value of the DC offset applied up to the time point and reflects the DC offset accumulated value to the subsequent DC offset generation.

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