KR20160079402A - Sequential circuit design method and clock gating circuit - Google Patents

Abstract

The present invention relates to a method for designing a semi-conductor circuit and, particularly, to a method for designing a sequential circuit for implementing low power and a clock gating circuit used therein. The method includes the steps of: creating a toggle matrix in which the numbers of times of toggles according to application of clocks to flip-flops constituting a sequential circuit to be designed are counted; creating a dynamic event matrix in which a correlation between flip-flops is calculated with reference to data of the toggle matrix; sequentially creating a virtual cluster group in a scheme of preferentially selecting a flip-flop having the minimum number of times of toggles among a set of the flip-flops, adding the selected flip-flop to a virtual cluster group, searching the dynamic event matrix for a flip-flop having a large correlation with the added flip-flop, and re-adding the discovered flip-flop to the virtual cluster group; and clustering all the flip-flops constituting the sequential circuit into a plurality of groups in a scheme of calculating a reduced value of electric power by connecting, to the clock gating circuit, one or more flip-flops added in the virtual cluster group creation step, and resorting flip-flops belonging to the virtual cluster group into true cluster groups according to the calculated reduced value of electric power.

Description

TECHNICAL FIELD [0001] The present invention relates to a sequential circuit design method for low power implementation, and a clock gating circuit used in the method.

The invention relates to semiconductor circuit design, and more particularly to a sequential circuit design method for low power implementation and a clock gating circuit used in the method.

The biggest problem of a semiconductor chip composed of hundreds of millions of transistors in recent years is a reduction in power consumption. Particularly, portable devices such as mobile phones consume more power than the power supply, which is a power supply, and thus many technologies for saving power consumed in semiconductor chips are being developed.

Many researches and technologies have been developed to reduce power consumption. Recently, however, technology to reduce power consumption by improving the clock circuit, which is the circuit which uses the most consumed power (statistically about 30-40% line) That is, clock gating technology.

In general, a circuit constituting a semiconductor chip is composed of a combinational circuit, a sequential circuit, a bus connecting circuits, and a clock distribution network for providing synchronization of operations.

The combinatorial logic circuit is mainly responsible for the implementation of the functions, and the sequential circuit is responsible for storing the functions, such as flip-flops, latches, etc., temporarily or for outputting.

The most power-consuming circuit in a semiconductor chip is a clock-driven sequential circuit. When the circuit is operating, 30% -40% of the power is consumed in the sequential circuit. Therefore, reducing the power consumption of the clocked sequential circuit reduces the power consumption of the semiconductor chip.

The clock gating technique is a technique that greatly improves power consumption by configuring a clock applying circuit to a sequential circuit because the sequential circuit operates based on the clock. As shown in FIG. 1, the clock gating technique is a method of comparing the input and the output of a sequential circuit and reducing power consumption by disabling a sequential circuit when input and output are the same.

However, since there is a limit to how to reduce the power consumption of the semiconductor circuit by applying the clock gating technique without considering the dynamic operation characteristics of the sequential circuit, the dynamic operation characteristics of the elements constituting the sequential circuit to be designed in the sequential circuit design It is considered that the power consumption reduction effect can be obtained by grouping the devices having similar characteristics and using the same clock gating circuit for each group.

Korean Patent Publication No. 10-2008-0052225 Korean Patent Publication No. 10-2011-0113551

Accordingly, the present invention is an invention invented in accordance with the above-mentioned conception, in which flip-flops having similar dynamic operation characteristics (high correlation) are clustered and flip-flops belonging to each cluster are operated by the same clock gating circuit, The present invention provides a sequential circuit design method for implementing a low power that can be reduced,

Still another object of the present invention is to provide a clock gating circuit that can be used in a sequential circuit design method capable of reducing power consumption.

According to an aspect of the present invention, there is provided a sequential circuit design method for implementing a low-

Generating a toggle matrix by counting the number of toggles according to clock application for each flip-flop constituting a sequential circuit to be designed;

Generating a dynamic event matrix in which correlation between each flip-flop is calculated by referring to the toggle matrix data;

A flip-flop having a minimum number of toggles among the set of flip-flops is first selected and added to a virtual cluster group, and a flip-flop having a large correlation with the added flip-flop is found in the dynamic event matrix, Sequentially creating virtual cluster groups in a manner that adds virtual cluster groups;

The flip-flops belonging to the virtual cluster group are classified into a true cluster group according to the calculated saved power value by connecting one or more flip-flops added in the virtual cluster group generation step to a clock gating circuit to calculate a saved power value. And clustering all the flip-flops constituting the sequential circuit into a plurality of groups.

Further comprising the step of connecting a clock gating circuit to each of the plurality of the clustered groups.

In the sequential circuit design method, the saved power value is calculated by subtracting the power value consumed by the clock gating circuit from the consumed power value saved by the clock gating circuit.

The clock gating circuit available for the sequential circuit design method comprises:

At least one first gating unit for exclusive-ORing the input and the output of the flip-flop;

A second gating unit for performing an OR operation on the at least one first gating unit output;

A latch unit for latching an output of the second gating unit according to an applied clock;

And a third gating unit for performing logical multiplication of the output of the latch unit and the clock to transfer the result to a clock terminal of the flip-flop.

According to the embodiment of the present invention as described above, the present invention can be applied to a flip-flop circuit having clusters in which flip-flops having similar dynamic operation characteristics (high correlation) are arranged and the flip-flops belonging to each cluster are operated by the assigned clock gating circuit, It is possible to obtain a power consumption reduction effect that is higher than that of conventional semiconductor circuits to which a clock gating circuit is simply applied without consideration of dynamic operation characteristics.

1 and 2 show a circuit diagram and a timing diagram to which a general clock gating circuit is added;
BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a method for designing a sequential circuit for low power implementation.
4 is a circuit example with a clock gating circuit according to an embodiment of the present invention.
FIG. 5 is an exemplary diagram illustrating signal timings necessary for explaining an embodiment of the present invention. FIG.
Figure 7 is a table of power consumption for a semiconductor circuit designed in accordance with an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

FIG. 3 is a flowchart illustrating a sequential circuit design method for implementing a low power according to an embodiment of the present invention. FIG. 4 illustrates a circuit diagram to which a clock gating circuit according to an embodiment of the present invention is added And FIG. 5 illustrates a signal timing diagram necessary for explaining an embodiment of the present invention.

As shown in FIG. 4, when the K flip-flops (FF) are clustered and a clock gating circuit is connected, power consumption reduction effect can be obtained. Although this method seems to be the optimal method, there is improvement. The problem with this method is that it does not take into account the correlation. For example, when K = 3, if the number of toggles of the flip flops FF1, FF2, and FF3 is as shown in FIG. 4, FF1 and FF3 have the same number of toggles, and FF2 has two more toggles. 4, the number of toggles of FF1, FF2 and FF3 with respect to the total number of toggles is expressed as TR (1) = 4/14, TR (2) = 6/14 and TR (3) = 4/14 in the clock waveform shown in FIG. .

As a method for finding the optimization of the consumed power, clustering by the number of toggles is performed by {FF1, FF3, FF2}, {FF1, FF3} is clustered and operated by the same clock gating circuit. However, as shown in Fig. 5, when {FF1, FF2} is clustered rather than {FF1, FF3}, it is necessary to compensate for the larger power consumption reduction effect (the number of toggles is small). Accordingly, a method for supplementing the above problem is needed. For this, a dynamic event matrix is used in the embodiment of the present invention. For reference, 'event' in the embodiment of the present invention is defined as a case where the output terminal value of the circuit is changed.

The dynamic event matrix is a cross-correlation of flip-flops in actual operation in a semiconductor circuit. The definition of the flip-flop's correlation during operation is the correlation of the number of toggles between flip-flops during the valid time (t) of the input value using a given input value. That is, when a given input value is valid, the basic idea is to find the similarity between the number of toggles of each flip-flop and the toggle pattern and to cluster the flip-flops. When the number of toggles of the flip-flop shows a remarkable difference, it is judged that there is no similarity.

On the other hand, the configuration of the dynamic event matrix is obtained according to the dynamic operation, and the VCD (Value Change Dump), which is the result of the RTL simulator, is used.

는 각 플립플롭의 토글 횟수, k는 k번째 시뮬레이션 결과를 나타내며,

Is the number of toggles of each flip-flop, k is the kth simulation result,

는 i번째 플립플롭의 토글 횟수, N은 플립플롭의 번호를 나타낸다.

Denotes the number of toggles of the i-th flip-flop, and N denotes the number of the flip-flop.

로 표현된다.N * N of the correlation is the event correlation matrix

Lt; / RTI >

의 각 열은

로 표시할 수 있고,

는 i번째 플립플롭의 k회의 시뮬레이션에 의한 토글 횟수이며, M은 시뮬레이션 총 횟수이다. M횟수의 시뮬레이션 이후 생성되는 매트릭스는 플립플롭 회로의 동적 상관 관계를 표시하며, 대칭 매트릭스이 특성과 사선의 값은 1이다.matrix

Each column of

As shown in FIG.

Is the number of toggles by k simulations of the i-th flip-flop, and M is the total number of simulations. The matrix generated after the M number of simulations shows the dynamic correlation of the flip-flop circuit, and the symmetric matrix characteristic and the oblique line have a value of one.

A sequential circuit design method according to an embodiment of the present invention will be described with reference to FIG.

The sequential circuit according to the embodiment of the present invention (this sequential circuit is merely an example of a semiconductor circuit and may be a cell operated by a clock) is a first step. In the first step, each of the flip- A toggle matrix in which the number of toggles according to clock application is counted is generated (step S10).

In the embodiment of the present invention, it is assumed that the number of flip-flops constituting the sequential circuit to be designed is 3 (FF1, FF2, FF3), and the number of flip- The number of toggles is counted (calculated) to generate a toggle matrix as shown in Table 1 below. The toggle matrix of Table 1 is based on the signal waveform shown in Fig. The VCD is a result file obtained by RTL circuit simulation and is typically used in semiconductor circuit design, and a detailed description thereof will be omitted.

Clock number Number of clocks FF1 toggle count FF2 toggle count FF3 toggle count One 1-2 One One 0 2 3-4 One One 0 3 5-6 One One 0 4 7-8 One One One 5 9-10 0 0 One 6 11-12 0 2 0 7 13-14 0 0 2

When the toggle matrix is generated, a dynamic event matrix is calculated by referring to the toggle matrix data, and a correlation between the flip-flops is calculated (step S20).

The dynamic event matrix constitutes a cross-correlation between flip-flops. The dynamic event matrix generates a correlation matrix between flip-flops in which the correlation coefficient between flip-flops is calculated by first adding the difference in the number of toggles between the flip-flops.

The correlation coefficient between the flip-flops (FFx, FFv) is obtained by the following equation, and it is the flip-flop correlation matrix listed in Table 2 below.

Correlation (FF1, FF2) = ABS (1-1) + ABS (1-1) + ABS (1-1) + ABS (1-1) + ABS (0-0) + ABS (0-0) = 2

Correlation (FF1, FF3) = ABS (1-0) + ABS (1-0) + ABS (1-0) + ABS (1-1) + ABS (0-0) = 6

Flip flop FF1 FF2 FF3 FF1 0 2 6 FF2 2 0 0 FF3 6 8 0

When the inter-flip-flop correlation matrix is created, it is normalized to generate a final dynamic event matrix. The correlation coefficient (A) constituting the dynamic event matrix is calculated by the following equation, Table 3.

A = B / C

A is the correlation coefficient between the flip-flops to be compared.

B (the maximum value among the flip-flop correlation matrices) - (the sum of the correlation coefficient difference values to be compared with each other).

C is the maximum value among the flip-flop correlation matrices.

The correlation coefficient calculation process for constructing the dynamic event matrix based on Table 2 will be described below.

Correlation (FF1, FF2) = {maximum value among the flip-flops (FF1, FF2) correlation matrices} - sum of the correlation coefficient differences between the flip-flops (FF1 and FF2) to be compared} / flip- Maximum value = {8-2} / 8 = 3/4.

Correlation (FF1, FF3) = (maximum value among the flip-flops (FF1, FF3) correlation matrices} - sum of the correlation coefficient difference values between the flip- Maximum value = {8-6} / 8 = 1/4.

Correlation (FF2, FF3) = {maximum value among the flip-flops (FF2, FF3) correlation matrices} - sum of correlation coefficient difference values between flip-flops (FF2 and FF3) to be compared} / flip-flop correlation matrix Maximum value = {8-8} / 8 = 0/4

Flip flop FF1 FF2 FF3 FF1 One 3/4 1/4 FF2 3/4 One 0 FF3 1/4 0 One

When a toggle matrix and a dynamic event matrix are generated by the above-described method, a flip-flop having a minimum number of toggle times among the sets of flip-flops constituting a sequential circuit is first selected in the toggle matrix and added to the virtual cluster group, Flip-flops having a large correlation with the flip-flops are found in the dynamic event matrix and re-added to the virtual cluster group (step S30).

)을 계산(S40단계)하고, 계산된 절감 전력값(

)에 따라(기준치와 비교, S50단계) 상기 가상의 클러스터 그룹에 속한 플립플롭들을 진정한 클러스터 그룹으로 재분류(S60단계)하는 방식으로 순차회로를 구성하는 모든 플립플롭을 다수의 그룹으로 클러스터화한다.However, one or more flip-flops added in the virtual cluster group generation step may be connected to the clock gating circuit shown in Fig.

) (Step S40), and calculates the calculated saved power value (

(Step S50), the flip-flops belonging to the virtual cluster group are reclassified as a true cluster group (step S60), and all the flip-flops constituting the sequential circuit are clustered into a plurality of groups .

More specifically,

First, the actual value of the consumed power saved by the clock gating circuit should be obtained. In order to calculate the power consumption, the power consumption by the additional circuit generated by the clock gating circuit can be accurately calculated to obtain the power consumption on the actual circuit. 4 shows a circuit to which a clock gating circuit is added. The added circuit includes a first gating part (XOR gate) which is an exclusive OR circuit, a second gating part (OR gate) which is an OR circuit, a latch circuit, (AND gate), and the power consumed in each can be obtained as follows.

는 토글 레이트를 나타내며,

은 부하의 커패시턴스 값,

는 단선 때의 커패시턴스 값, f는 동작주파수,

는 공급전압을 나타낸다.

Represents the toggle rate,

Is the capacitance value of the load,

Is the capacitance value during disconnection, f is the operating frequency,

Represents the supply voltage.

The flip-flop generally operates in four stages. The first (Ⅰ) shows the case where the input and the clock change, the second (Ⅱ) the clock changes, the input does not change, the third (Ⅲ) And there is no change. A valid toggle is affected by the phase at which the input and output change.

이다.

는 단계 i의 클럭 토글 레이트,

는 단계 i의 입력 데이터 토글 레이트이며, 단계 i는 플립플롭의 4가지(Ⅰ- Ⅳ)동작 유형을 나타낸 것이다.Thus, the toggle rate of the effective flip-

to be.

Is the clock toggle rate of step i,

Is the input data toggle rate of step i, and step i shows the four (I-IV) operation types of the flip-flop.

Since the clock gating circuit is a concept designed to remove the clock toggle, it exhibits the largest power consumption effect in the operation phase II of the flip-flop. Therefore, the effective toggle rate in step II is

로 표현할 수 있다.

.

는 리니어 함수로 표현할 수 있다. 따라서

로 표현되고, 소모되는 전력값은

이며, 클럭 게이팅 회로에 의해 절감되는 소모 전력은 하기 수식으로 표현 가능하다.Since the operation of step II is a simple increase function,

Can be represented by a linear function. therefore

And the consumed power value is expressed by

, And the power consumed by the clock gating circuit can be expressed by the following equation.

은 회로의 셀라이브러리에 의해 표기되는 값이다. 그리고 도 4에 부가된 회로에 의해 소모되는 전력은,

Is the value indicated by the cell library of the circuit. The power consumed by the circuit added in Fig.

를 취합하면 다음과 같은 수식으로 표현된다.

Is expressed by the following equation.

)은 상기 클럭 게이팅 회로에 의해서 절감된 소모 전력값에서 상기 클럭 게이팅 회로에 의해서 소모된 전력값을 차감하여 산출된다.In summary, the one or more flip-flops added in the virtual cluster group creation step are connected to the clock gating circuit shown in Fig.

Is calculated by subtracting the power value consumed by the clock gating circuit from the consumed power value saved by the clock gating circuit.

)이 양수(미리 설정된 기준치에 해당함)이면 상기 가상의 클러스터 그룹에 추가된 플립플롭들은 같은 클러스터 그룹에 속하게 된다. 이때 클러스터 그룹에 추가된 플립플롭들은 순차회로를 구성하는 플립플롭들의 집합에서 제외된다.If the calculated saved power value (

Is a positive number (corresponding to a preset reference value), the flip-flops added to the virtual cluster group belong to the same cluster group. At this time, the flip-flops added to the cluster group are excluded from the set of flip-flops constituting the sequential circuit.

In this manner, all the flip-flops constituting the sequential circuit are clustered into a plurality of groups until there are no flip-flops remaining in the set of flip-flops, and then a clock gating circuit is connected to each of the plurality of clustered groups To design a low-power sequential circuit.

As described above, according to the present invention, a plurality of flip-flops can be classified into a cluster group using a dynamic event matrix and a saved power value generated in a sequential circuit, which is an example of a semiconductor circuit. Each cluster group is classified into a clock gating Since it can be operated by a circuit, the maximum power consumption can be reduced.

FIG. 7 is a table of power consumption of a semiconductor circuit for verifying the effect of the sequential circuit design method according to the embodiment of the present invention.

Performance comparison and measurement were performed using ISCAS89 benchmark circuit, a standardized IEEE entity, for performance evaluation and measurement of circuits designed according to the embodiment of the present invention. The ISCAS89 benchmark circuit is a circuit established by the IEEE in 1989 and is a prestigious circuit commonly used for performance evaluation of circuit analysis.

In the benchmark results, 'Original' is the power consumption without using the clock gating circuit technique, and the power consumption value of 'ACG' column is obtained by using Synopsys' Design Compiler, .

The benchmark results show that there is a reduction in power consumption in all circuits compared to "Original" and "ACG." The 'performance improvement ratio' in the benchmark table means that the clock gating technology is not applied It is shown that the power consumption ratio of the general circuit and the circuit according to the present invention is shown as 28.3% in comparison with a total of 30 benchmark circuits. It is very encouraging that there is more than average power consumption reduction in the circuit.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the invention. Accordingly, the true scope of the present invention should be determined only by the appended claims.

Claims (6)

Generating a toggle matrix by counting the number of toggles according to clock application for each flip-flop constituting a sequential circuit to be designed;
Generating a dynamic event matrix in which correlation between each flip-flop is calculated by referring to the toggle matrix data;
A flip-flop having a minimum number of toggles among the set of flip-flops is first selected and added to a virtual cluster group, and a flip-flop having a large correlation with the added flip-flop is found in the dynamic event matrix, Sequentially creating virtual cluster groups in a manner that adds virtual cluster groups;
The flip-flops belonging to the virtual cluster group are classified into a true cluster group according to the calculated saved power value by connecting one or more flip-flops added in the virtual cluster group generation step to a clock gating circuit to calculate a saved power value. And clustering all of the flip-flops constituting the sequential circuit into a plurality of groups in a manner of sorting the sequential circuits. The method of claim 1, further comprising: coupling a clock gating circuit to each of the plurality of clustered groups. The method of claim 1 or 2, wherein the saved power value is calculated by subtracting the power value consumed by the clock gating circuit from the consumed power value saved by the clock gating circuit. Way. The method according to claim 1 or 2,
Generating a correlation matrix between flip-flops in which correlation coefficients between flip-flops are calculated by summing differences in the number of toggles between flip-flops, and then normalizing the flip-flop correlation matrix to generate the dynamic event matrix, Wherein the correlation coefficient (A) constituting the dynamic event matrix is calculated by the following equation.
A = B / C
A is the correlation coefficient between the flip-flops to be compared.
B (the maximum value among the flip-flop correlation matrices) - (the sum of the correlation coefficient difference values to be compared with each other).
C is the maximum value among the flip-flop correlation matrices The clock gating circuit according to claim 1 or 2,
At least one first gating unit for exclusive-ORing the input and the output of the flip-flop;
A second gating unit for performing an OR operation on the at least one first gating unit output;
A latch unit for latching an output of the second gating unit according to an applied clock;
And a third gating unit for performing a logical multiplication of the output of the latch unit and the clock to transfer the output to a clock terminal of the flip-flop. CLAIMS 1. A clock gating circuit for reducing power consumption of at least one flip-flop constituting a sequential circuit,
At least one first gating unit for exclusive-ORing the inputs and outputs of the flip-flops;
A second gating unit for performing an OR operation on the at least one first gating unit output;
A latch unit for latching an output of the second gating unit according to an applied clock;
And a third gating unit for performing a logical multiplication of the output of the latch unit and the clock to transfer the result to a clock terminal of the flip-flop.

Images