KR20160056977A - Switching controller and power conveter including the same - Google Patents

Abstract

The purpose of the present invention is to provide a switching controller having high efficiency by controlling a dead time, and a power device having the same. The present invention is to provide a switching controller which does not output first and second switching signals when a voltage level of detecting voltage is within a predetermined range in response to the voltage level of the detecting voltage, and a power device having the same. The power device comprises: a power unit; a detection unit; and a switching control unit.

Description

TECHNICAL FIELD [0001] The present invention relates to a switching control device and a power supply device including the switching control device.

The present invention relates to a switching control device and a power supply device including the same.

Switch mode power supplies such as buck converters and flyback converters are commonly used in a wide range of electronic equipment. In particular, LLC resonant converters are attracting attention because of their high efficiency. The LLC resonant converter operates at high frequencies to reduce overcurrent in the converter during initial and standby operations. When the power switch operates at a high frequency, there is a problem that a switching element is turned on at the same time and a short circuit occurs.

KR 2011-0076351 (released July 20, 2013) KR 2012-0032256 (Released April 4, 2012)

SUMMARY OF THE INVENTION An object of the present invention is to provide a switching control device and a power supply device including the switching control device, which have high efficiency by adjusting a dead time.

A first embodiment of the present invention is directed to a power supply circuit comprising a power supply unit for generating a predetermined voltage by a first switching signal and a second switching signal which are alternately turned on / off, a sensing unit for sensing a voltage generated in the power supply unit, A switching controller for generating a switching signal and a second switching signal and not outputting the first switching signal and the second switching signal when the voltage level of the sensing voltage is within a predetermined range corresponding to the voltage level of the sensing voltage sensed by the sensing unit To provide a power supply that includes the power supply.

A second aspect of the present invention is to provide a switching control device that does not output the first switching signal and the second switching signal when the voltage level of the sensing voltage corresponds to the voltage level of the sensing voltage within a predetermined range.

According to the switching control apparatus and the power supply apparatus including the switching control apparatus according to the present invention, it is possible to prevent the efficiency of the power supply apparatus from being lowered by adjusting the dead time.

1 is a structural diagram showing an embodiment of a power supply device according to the present invention.
2 is a circuit diagram showing an embodiment of the power supply apparatus shown in FIG.
3 is a circuit diagram showing an embodiment of the switching control unit shown in FIG.
4 is a circuit diagram showing one embodiment of the dead time controller shown in FIG.
5 is a timing diagram showing an embodiment of the operation of the power supply apparatus according to the present invention.

The matters relating to the operational effects including the technical configuration of the switching control device and the power supply device including the same according to the present invention will be clearly understood by the following detailed description of the preferred embodiments of the present invention with reference to the drawings, .

In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. In this specification, the terms first, second, etc. are used to distinguish one element from another element, and the element is not limited by these terms.

The following detailed description of the invention refers to the accompanying drawings, which illustrate, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. It should be understood that the various embodiments of the present invention are different, but need not be mutually exclusive. For example, certain features, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the invention in connection with an embodiment. It is also to be understood that the position or arrangement of the individual components within each disclosed embodiment may be varied without departing from the spirit and scope of the invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is to be limited only by the appended claims, along with the full scope of equivalents to which such claims are entitled, if properly explained. In the drawings, like reference numerals refer to the same or similar functions throughout the several views.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the present invention.

FIG. 1 is a structural diagram showing an embodiment of a power supply device according to the present invention, and FIG. 2 is a circuit diagram showing an embodiment of the power supply device shown in FIG.

1 and 2, the power supply unit 100 includes a power supply unit 110 that generates a predetermined voltage by a first switching signal HO and a second switching signal LO that are alternately turned on / off, A sensing unit 120 for sensing a voltage generated by the power supply unit 110 and a second switching signal LO for generating a first switching signal HO and a second switching signal LO, And a switching control unit 130 which does not output the first switching signal HO and the second switching signal LO when the voltage level of the sensing voltage VM corresponding to the input voltage VM is within a predetermined range.

The power supply unit 110 may include a transformer 110a and a first switching device SW1 and a second switching device SW2 for controlling the current flowing in the primary winding L1 of the transformer 110a. The power supply unit 110 includes a rectification unit 110b connected to the secondary side winding L2 of the transformer 110a to rectify the current flowing in the secondary side winding L2, And an output capacitor Cout for supplying the output voltage to the load RL1. The load connected to the output capacitor Cout may be at least one channel in which a plurality of light emitting diodes are connected in series and / or in parallel. However, the load RL1 is not limited thereto.

The power unit 110 includes an input terminal Ni receiving the input voltage V _PFC and a capacitor Cr connected between the input terminal Ni and the transformer 110a and a first inductor Lr, A second inductor LM connected in parallel to the primary winding L1 of the first inductor Lr and connected in series to the first inductor Lr and a first inductor LM connected between the input Ni and the capacitor Cr The first switching element SW1 is connected to the first node N1 and the gate electrode receives the first switching signal HO. The first switching element SW1 is connected to the first node N1, A first diode D1 connected to the secondary side winding L2 of the transformer 110a, and a second diode D1 connected to the second side winding L2 of the transformer 110a. The second switching element SW2 is connected to the ground, A rectifier 110b including two diodes D2 and an output capacitor Cout connected in parallel to the rectifier 110b. In addition, the secondary winding L2 may include a first sub-winding L21 and a second sub-winding L22. In addition, the power supply unit 110 may be an LLC converter, but is not limited thereto. Also, the input voltage V _PFC of the power supply unit 110 may be a voltage delivered from a PFC (Power Factor Correction) converter.

The sensing unit 120 may include a sense winding Ls to which a sense voltage is induced by a current flowing in the primary winding L1 of the transformer 110a. The winding direction of the sensing winding Ls may be opposite to the winding direction of the primary winding L1 of the transformer 110a. The sense voltage VM may be a voltage divided by the resistors RVW1 and RVW2, the voltage induced in the sense winding Ls. The voltage level of the voltage induced in the sense winding Ls can be lowered by dividing the voltage induced in the sense winding Ls so that the sense voltage VM having a lower voltage level can be used in the switching control section 130. [

The switching controller 130 may transmit the first switching signal HO and the second switching device SW2 to the first switching device SW1 and the second switching device SW2 of the power supply unit 110, respectively. The first switching device SW1 and the second switching device SW2 may be turned on at different times by the first switching signal HO and the second switching signal LO which are alternately transmitted. At this time, the first switching device SW1 and the second switching device SW2 can perform a turn-on / turn-off operation at a very high speed and can be turned on at the same time. To solve this problem, the switching controller 130 generates and transmits a dead-time signal (Dead-Out) so that the first switching device SW1 and the second switching device SW2 can be turned off simultaneously for a predetermined time have. At this time, if the time for which the first switching device SW1 and the second switching device SW2 are turned off at the same time due to the dead-time signal is long, the efficiency of the power supply device 100 is low. In order to solve this problem, in the present invention, the first switching device SW1 and the second switching device SW2 are controlled by automatically adjusting a period in which the dead-time signal (Dead-Out) is applied using the voltage level of the sense voltage VM, It is possible to effectively control the length of the dead time interval during which the first and second switches are simultaneously turned off.

The voltage induced in the primary winding L1 of the transformer 110a in the power supply apparatus 100 configured as described above may be expressed by Equation (1).

At this time, when the first switching element SW1 is turned on by the first switching signal HO, the voltage VS of the first node N1 may be equal to the input voltage V _PFC . Therefore, the voltage induced in the primary winding L1 of the transformer 110a can be expressed by the following equation (2).

When the second switching element SW2 is turned on by the second switching signal LO, the voltage of the first node N1 may be 0V. Therefore, the voltage induced in the primary-side winding L1 of the transformer 110a can be expressed by the following equation (3).

In Equations 1 to 3, V _L denotes a voltage induced in the primary winding L1, V _PFC denotes an input voltage transmitted through the input terminal voltage, V _CR denotes a voltage stored in the capacitor Cr, VS means the voltage of the first node N1.

The sensing voltage may be opposite to the polarity of the voltage induced in the primary winding of the transformer, so that the sensing voltage may be expressed by Equation (4) below.

Where, VW is the voltage level of the sensing voltage, N _P1 is the induced voltage in the winding number of the primary side winding (L1) of a transformer (110a), N _P2 is a number of turns of the detection winding (Ls), R _VW1 and R _VW2 is detected winding Quot; means the magnitude of the resistance that divides the voltage.

It can be seen from Equation (4) that the voltage polarity of the first node N1 can be determined using the sense voltage VM.

The voltage polarity of the first node N1 may determine the turn-on time of the first switching device SW1 or the turn-on time of the second switching device SW2. The polarity of the first node N1 may be determined based on the sensing voltage It is possible to determine the turning-on point of the first switching device SW1 and the second switching device SW2 by using the polarity of the sense voltage VM instead of the voltage polarity of the first node N1 . That is, when the sense voltage VM is higher than a certain reference voltage, it is determined that the first switch SW1 has a positive polarity and the negative switch has a negative polarity. And the second switching element SW2 can be turned on in the (-) polarity. At this time, when the sensing voltage VM is lower than the predetermined first threshold value in the case of positive polarity, the first switching device SW1 is turned off, and when the sensing voltage VM in the negative polarity is lower than the predetermined second threshold value VM, The first switching device SW1 and the second switching device SW2 are turned off when the sensing voltage VM has a voltage level between the first threshold value and the second threshold value by turning off the second switching device SW2, It is possible to prevent the first switching device SW1 and the second switching device SW2 from being turned on at the same time. The first switching device SW1 or the second switching device SW2 is turned on in response to the voltage of the sense voltage VM so that the turn-on points of the first switching device SW1 and the second switching device SW2 So that the efficiency of the power supply apparatus 100 can be prevented from being lowered.

3 is a circuit diagram showing an embodiment of the switching control unit shown in FIG.

3, the switching controller 130 includes a switching signal generator 132 for outputting a first switching signal HO and a second switching signal LO, A dead-time signal (Dead-Out) is transmitted to the switching signal generator 132 and the switching signal generator 132 generates a first switching signal HO and a second switching signal And a dead time signal generator 131 for preventing the signal LO from being output.

The switching signal generator 132 includes a signal output unit 132a that generates a first switching signal HO and a second switching signal LO and a first switching signal HO and a dead time signal Dead- And a second NOR gate 132c for performing a NOR operation on the second switching signal LO and the dead-time signal (Dead-Out).

The signal output unit 132a outputs the first state signal Q and the second state signal Qb in an inverted relationship with the first state signal Q to output the first NOR gate 132b and the second NOR gate 132c ). The first NOR gate 132b and the second NOR gate 132c may be connected to the dead time signal generator 131 to receive a dead time signal. The first NOR gate 132b and the second NOR gate 132c are connected to each other when the dead time signal Dead-Out is not received, that is, when the dead time signal (Dead-Out) The first switching signal HO output from the first NOR gate 132b is in the low state because the NOR operation is performed in the first NOR gate 132b when the first state signal Q is low And when the first state signal Q is high, the first switching signal HO may be outputted as a high state. When a dead-time signal (Dead-Out) in a high state is transmitted from the dead-time signal generator 131, the first NOR gate 132b performs a NOR operation. Therefore, the state of the first state signal Q Regardless, the first switching signal HO can be output in a low state.

When the low state signal is transmitted from the dead time signal generator 131, the second NOR gate 132c performs the NOR operation when the second state signal Qb is low. Therefore, the second NOR gate 132c The second switching signal LO may be output in a high state and the second state signal Qb may be in a high state, the second switching signal LO may be output in a low state. When the high-level signal is transmitted from the dead-time signal generator 131, the second switching signal LO is generated by the NOR operation of the second NOR gate 132c regardless of the state of the second state signal Qb. Can be output in the low state, respectively.

Here, it is defined that the first switching signal HO and the second switching signal LO are outputted when the first switching signal HO and the second switching signal LO are outputted in a high state, It can be defined that the first switching signal HO and the second switching signal LO are not outputted when the first switching signal HO and the second switching signal LO are outputted in a low state. The switching signal generator 132 may receive the second switching signal LO and the dead time signal to output the first switching signal HO and the second switching signal LO, The first switching signal HO and the second switching signal LO can be repeated in the high state and the low state, respectively, in accordance with the state change of the dead-state. In one embodiment, the signal output portion 132a may be a D flip flop. However, the present invention is not limited thereto.

The dead time signal generating unit 131 includes a first capacitor C1 for receiving and charging a first current IDEAD from the first current source Is1 and a second capacitor C1 for charging the first capacitor C1 with a first reference voltage and a first transistor T1 for discharging a voltage charged in the first capacitor C1 by a first reset signal SET-PLS. The first comparator 131a compares the first reset signal REF1 with the first reset signal SET-PLS. If the voltage charged in the first capacitor C1 is lower than the first reference voltage ref1, the dead-time signal generator 131 can output a dead-time signal in a high state (Dead-Out) When the voltage charged in the capacitor C1 is higher than the first reference voltage ref1, it is possible to output a dead-time signal Dead-Out in a low state. The first comparator 131a may be connected to the first inverter 131b and may output a dead-time signal by inverting a signal output from the first comparator 131a. The dead time signal generating unit 131 configured as described above is configured to generate the dead time signal having the voltage charged in the first capacitor C1 by charging the first capacitor C1 by the first current IDEAD supplied from the first current source Is1. The voltage level can be increased. The voltage charged in the first capacitor C1 may be input to the positive input terminal of the first comparator 131a. The first reference voltage ref1 is connected to the negative input terminal of the first comparator 131a so that the voltage level of the voltage input to the positive input terminal of the first comparator 131a is the first reference voltage the first comparator 131a can output a signal in a low state. When the voltage level of the voltage charged in the first capacitor C1 rises and the voltage input to the positive input terminal of the first comparator 131a becomes higher than the voltage input to the negative input terminal thereof, 131a can output a signal in a high state. When the first transistor T1 is discharged by the first reset signal SET_PLS, the voltage level of the voltage delivered to the positive input terminal of the first comparator 131a becomes equal to the voltage level of the first reference voltage ref1 So that the first comparator 131a can output a signal in a low state. When the first comparator 131a receives the low state signal from the first comparator 131a, the first comparator 131a inverts and outputs a high dead-time signal (Dead-Out), and the first comparator 131a outputs the high state A dead-time signal (Dead-Out) in a low state can be output. Therefore, the dead time signal generator 131 can output a dead time signal (Dead-Out) in a high state when the voltage charged in the first capacitor C1 is lower than the voltage of the first reference voltage Ref1 have.

The switching signal generator 132 outputs the first switching signal HO in a low state or the second switching signal LO in a low state when a dead time signal of a high state is input, The first switching device SW1 and the second switching device SW2, to which the switching signal HO and the second switching signal LO are respectively transmitted, can be turned off. However, when a dead-time signal (Dead-Out) in a low state is input, the switching signal generator 132 generates a first state signal Q and a second state signal Qb, which are generated in the signal output unit 132a, The first NOR gate 132b and the second NOR gate 132c may output the first switching signal HO or the second switching signal LO in a high state. At this time, the first switching signal HO and the second switching signal LO can alternately turn on the first switching device SW1 and the second switching device SW2, so that the first switching signal HO When the second switching signal LO becomes a low state and the first switching signal HO becomes a low state, the second switching signal may become a high state.

When a dead-time signal (Dead-Out) in a low state is output, the dead-time signal generator 131 maintains a dead-time signal (Dead-Out) in a low state for a first time, ) Or the second switching device SW2 can be kept on for a predetermined time.

The switching controller 130 may include a first signal processor 133 for generating a ramp signal and outputting a first reset signal SET_PLS according to a voltage level of the ramp signal. The first signal processor 133 can determine the first time by the time when the voltage level of the ramp signal is increased to the predetermined voltage level. The first signal processor 133 generates a ramp signal, and the ramp signal can be initialized by the second reset signal SAW-RESET. After the second reset signal SAW-RESET is inputted, And outputs a first reset signal (SET-PLS) when the voltage level of the ramp signal becomes equal to or greater than a predetermined value. The first signal processor 133 includes a second capacitor C2 for charging the second current IsAW from the second current source Is2 and a second capacitor C12 for charging the voltage generated in the second capacitor C2 and the second reference voltage a third comparator 133b for comparing the voltage generated in the second capacitor C2 with the feedback voltage FB and a second comparator 133b for comparing the voltage generated in the second capacitor C2 with the feedback voltage FB, A first AND gate 133c for outputting a first reset signal SET-PLS by ANDing the output signal of the first reset signal 133b and a second transistor T2 for discharging the second capacitor C2 by a second reset signal, . ≪ / RTI > The third comparator 133b receives the third reference voltage ref3 and outputs the voltage generated in the second capacitor C2 when the feedback voltage FB is larger than the third reference voltage ref3, So that the voltage ref3 can be compared. The feedback voltage FB may be a voltage generated by a current flowing in the load RL1 connected to the output capacitor Cout of the power supply unit 110. [

The second comparator 133a of the first signal processor 133 receives the voltage generated by the second capacitor C2 at the positive input terminal and the second reference voltage ref2 at the negative input terminal thereof . The third comparator 133b may receive the voltage generated by the second capacitor C2 at the positive input terminal and the third reference voltage ref3 at the negative input terminal thereof. Also, the feedback voltage FB may be transmitted to the third comparator 133b. The first AND gate 133c is connected to the second comparator 133a and the third comparator 133b and ANDs the output signals of the second comparator 133a and the third comparator 133b to generate a second reset signal SAW-RESET). That is, when the second comparator 133a and the third comparator 133b output the high state signal, the first AND gate 133c can output the second reset signal SAW-RESET in the high state by the AND operation have.

When the first signal processor 133 configured as described above receives the second current ISAW from the second current source Is2 and charges the second capacitor C2, the voltage charged in the second capacitor C2 is It can be increased to a ramp waveform. At this time, if the voltage level of the voltage charged in the second capacitor C2 is higher than the voltage level of the second reference voltage ref2, the second comparator 133a can output the high state. When the voltage level of the voltage charged in the second capacitor C2 continuously increases and becomes the feedback voltage FB, the third comparator 133b outputs the high state, so that the first AND gate 133c is in the high state 2 reset signal SAW-RESET to turn on the first transistor T1 of the dead time signal generator 131 to discharge the first capacitor C1.

When the first capacitor C1 is discharged by the first transistor T1, the first comparator 131a of the dead time signal generator 131 outputs a low state signal, and the first inverter 131b outputs a high state Dead-time signal (Dead-Out) can be output. The first switching signal HO and the second switching signal LO can be outputted in a low state due to the first NOR gate 132b and the second NOR gate 132c by a dead-time signal of a high state (Dead-Out) have. Therefore, the first switching device SW1 and the second switching device SW2 can be turned off at the same time. The third reference voltage ref3 is connected to the negative input terminal of the third comparator 133b so that the voltage charged in the second capacitor C2 is connected to the third reference voltage ref3), the third comparator 133b can output a signal in a high state.

The first signal processing unit 133 may also be turned on during the time when the voltage charged to the second capacitor C2 after the discharge of the second capacitor C2 rises to the feedback voltage FB or the third reference voltage ref3 Since the second reset signal SAW-RESET is not outputted, in order for the first capacitor C1 of the dead time signal generator 131 to be discharged again, the voltage charged in the second capacitor C2 becomes the feedback voltage FB, Or a time to rise to the third reference voltage ref3 may be required. Therefore, a dead-time signal (Dead-Out) in a low state can be maintained for a first time. Here, the first time may correspond to a time when the voltage charged in the second capacitor C2 rises to the feedback voltage FB or the third reference voltage ref3.

In addition, the switching controller 130 may further include a dead time controller 134 for outputting a second reset signal SAW-RESET. The dead time controller 134 may receive a dead time signal (Dead-Out), a second switching signal (LO), and a sense voltage to output a second reset signal (SAW-RESET). Here, the sense voltage VM may be a voltage obtained by dividing a voltage induced in the sense winding Ls in the sense unit 120. [ However, the sensing voltage VM is not limited thereto. When the voltage level of the reference voltage corresponding to the voltage level of the sensing voltage VM is lower than the first threshold value or the voltage level of the reference voltage is higher than the second threshold value lower than the first threshold value, The signal generator 131 may output a second reset signal SAW-RESET when a dead-time signal (Dead-Out) is output.

4 is a circuit diagram showing one embodiment of the dead time controller shown in FIG.

Referring to FIG. 4, the dead time controller 134 outputs a first turn-on signal TRUN_ON_HO when the sense voltage VM is greater than a predetermined level, and outputs a dead time when the second switching signal LO maintains a high state. And outputs a second turn-on signal TRUN_ON_LO when the sense voltage VM is lower than a predetermined level, and outputs a second turn-on signal TRUN_ON_LO when the sense voltage VM is lower than a predetermined level, The second reset signal SAW-RESET can be outputted when a dead-time signal (Dead-Out) occurs when the LO signal is maintained in the low state.

The dead time controller 134 compares the voltage corresponding to the sense voltage VM and the fourth reference voltage ref4 so that the voltage level of the voltage corresponding to the sense voltage VM is lower than the fourth reference voltage ref4 A fourth comparator 1341 for comparing the voltage corresponding to the sense voltage VM with the fifth reference voltage ref5 to output a first turn-on signal TRUN_ON_HO that is higher than the voltage level, A fifth comparator 1342 for outputting a second turn-on signal TRUN_ON_LO in a high state when the voltage level of the voltage corresponding to the fifth reference voltage ref5 is lower than the voltage level of the fifth reference voltage ref5, A second AND gate 1343 for ANDing the output signal of the second comparator 1342 with the second state signal Qb and an output signal of the fifth comparator 1342 and a second state signal Qb inverted by the second inverter 1345 A first OR gate 1346 for receiving the output signals of the second AND gate 1343 and the third AND gate 1344 and performing an OR operation, 1OR an output signal with a dead time signal (Dead-Out) of the gate 1346 may include a first 4AND gate (1347) to the AND operation. The voltage corresponding to the sensing voltage transmitted to the positive input terminal of the fourth comparator 1341 and the negative input terminal of the fifth comparator 1342 is between the first voltage VDD and the sensing voltage VM And the voltage of the second node N2 divided by the first resistor R1 and the second resistor R2 connected to the second node N2. By doing so, the voltage level of the sensing voltage can be increased to make the voltage of the second node N2 transmitted to the fourth comparator 1341 and the fifth comparator 1342 always be a positive voltage. However, the voltage of the second node N2 is not limited to a positive voltage.

The dead time controller 134 further includes a maximum dead time signal generator 1349. The maximum dead time signal generator 1349 receives a dead time signal Dead- The second reset signal SAW-RESET can be generated and output after a predetermined time elapses from the generation of the second reset signal SAW-RESET. The dead time controller 134 further includes a second OR gate 1348 for ORing the output signal of the maximum dead time signal generator 1349 and the output signal of the fourth AND gate 1347, Unit 1349 may generate a second reset signal SAW-RESET after a predetermined time elapses after a dead-time signal (Dead-Out) is generated, and may transmit the second reset signal SAW-RESET to the second OR gate 1348. As a result, it is possible to prevent the dead time from becoming too long.

5 is a timing chart showing an embodiment of the operation of the power supply apparatus shown in Fig.

Referring to FIG. 5, the power supply 100 alternately receives the first switching signal HO and the second switching signal LO. The direction of the current flowing through the primary winding L1 of the transformer 110a is changed by the first switching signal HO and the second switching signal LO to be applied to the primary winding L1 of the transformer 110a The induced voltage can be repeatedly increased and decreased. At this time, the sensing voltage VM generated by the sensing unit 120 may be repeatedly increased or decreased corresponding to the voltage induced in the primary winding L1. First, when the first switching device SW1 is turned on by the first switching signal, the voltage induced in the primary winding L1 of the transformer 110a by the current flow may increase, and the voltage at the first node N1 May be increased to the magnitude of the input voltage VPFC because the first switching device SW1 is turned on. The voltage sensed by the sensing unit 120 may also increase. When a predetermined time has elapsed after the first switching device SW1 is turned on, the voltage induced in the primary winding L1 of the transformer 110a may be reduced. At this time, when the voltage level of the sense voltage VM becomes lower than the voltage level of the fourth reference voltage ref4, the first switching device SW1 can be turned off. When the first switching device SW1 is turned off, the voltage induced in the primary winding L1 of the transformer 110a can be further reduced. When the voltage level of the sense voltage VM becomes smaller than the voltage level of the fifth reference voltage ref5, the second switching device SW2 can be turned on. That is, when the voltage level of the sense voltage VM is between the fourth reference voltage ref4 and the fifth reference voltage ref5, the first switching device SW1 and the second switching device SW2 are both turned off It is possible to prevent the first switching device SW1 and the second switching device SW2 from being turned on at the same time. In this case, the fourth reference voltage ref4 and the fifth reference voltage ref5 may be the first threshold value and the second threshold value in the description of FIGS. 1 and 2, respectively.

In the claims hereof, the elements depicted as means for performing a particular function encompass any way of performing a particular function, such elements being intended to encompass a combination of circuit elements that perform a particular function, Or any form of software, including firmware, microcode, etc., in combination with circuitry suitable for carrying out the software for the processor.

Reference throughout this specification to " one embodiment ", etc. of the principles of the invention, and the like, as well as various modifications of such expression, are intended to be within the spirit and scope of the appended claims, it means. Thus, the appearances of the phrase " in one embodiment " and any other variation disclosed throughout this specification are not necessarily all referring to the same embodiment.

It will be understood that the term " connected " or " connecting ", and the like, as used in the present specification are intended to include either direct connection with other components or indirect connection with other components. Also, the singular forms in this specification include plural forms unless the context clearly dictates otherwise. Also, components, steps, operations, and elements referred to in the specification as " comprises " or " comprising " refer to the presence or addition of one or more other components, steps, operations, elements, and / or devices.

100: Power supply unit 110: Power supply unit
120: sensing unit 130:
HO: first switching signal LO: second switching signal

Claims (38)

A power supply unit generating a predetermined voltage by a first switching signal and a second switching signal which are alternately turned on / off;
A sensing unit for sensing a voltage generated by the power supply unit; And
And generates the first switching signal and the second switching signal, and when the voltage level of the sensing voltage corresponding to the voltage sensed by the sensing unit is within a predetermined range, the first switching signal and the second switching signal are not output And a switching control unit. The method according to claim 1,
Wherein the switching controller includes a dead time signal generator for outputting a dead time signal, and when the dead time signal is output, the first switching signal and the second switching signal are not output. 3. The method of claim 2,
Wherein the dead time signal generator comprises: a first capacitor for receiving and charging a first current from a first current source; a first comparator for comparing a voltage charged in the first capacitor with a first reference voltage; And a first transistor for discharging a voltage charged in the first capacitor, and outputs a signal corresponding to the dead time signal if the voltage charged in the first capacitor is lower than the first reference voltage. The method of claim 3,
Wherein a first inverter is connected to the output terminal of the first comparator and the dead time signal is output through the first inverter. 3. The method of claim 2,
Wherein the dead time signal generator outputs the dead time signal when the magnitude of the sensed voltage detected by the sensing unit is within a predetermined range. 6. The method of claim 5,
Wherein the dead time signal generator is maintained for a first time after the dead time signal is output. The method according to claim 6,
Wherein the switching control unit includes a first signal processing unit for generating a ramp signal, wherein the first signal processing unit determines the first time by a time when the voltage level of the ramp signal is increased. The method according to claim 6,
The switching control unit includes a first signal processing unit for generating a ramp signal and initializing the ramp signal by a second reset signal, and the first signal processing unit generates the ramp signal after the second reset signal is input And outputs a first reset signal for initializing a dead time signal generator when a voltage level of the ramp signal becomes a predetermined value or more. 9. The method of claim 8,
The first signal processor
A second capacitor for charging a second current from a second current source; a second comparator for comparing a voltage generated in the second capacitor with a second reference voltage; and a comparator for comparing the voltage generated in the second capacitor with a feedback voltage An AND gate for outputting the first reset signal by ANDing the output signal of the second comparator and the third comparator; and an AND gate for outputting the voltage charged in the second capacitor by the second reset signal, And a second transistor connected between the first power supply and the second power supply. 3. The method of claim 2,
Wherein the switching controller includes a switching signal generator for generating the first switching signal and the second switching signal,
Wherein the switching signal generator comprises: a signal output unit for generating a first state signal and a second state signal; a first NOR gate for performing NOR operation on the first state signal and the dead time signal to generate the first switching signal; And a second NOR gate for NORing the second state signal and the dead time signal to generate the second switching signal. 11. The method of claim 10,
Wherein the signal output section is a D flip flop. 11. The method of claim 10,
Wherein the switching control unit includes a dead time controller for outputting a second reset signal,
Wherein the dead time controller receives the dead time signal, the second state signal, and the sense voltage corresponding to the output voltage of the sensing unit and outputs the second reset signal. 13. The method of claim 12,
Wherein the dead time controller is configured to control the dead time controller to output the dead time signal to the dead time signal generator when the voltage level of the corresponding voltage corresponding to the voltage level of the sensing voltage is lower than the first threshold value or the voltage level of the corresponding voltage is higher than a second threshold value lower than the first threshold value, And outputs the second reset signal when a dead time signal is output from the second reset signal. 14. The method of claim 13,
Wherein the corresponding voltage is generated by dividing a first power supply voltage and a voltage corresponding to the sensing voltage. 13. The method of claim 12,
The dead time controller
And outputs a first turn-on signal when the detection voltage is greater than a predetermined level, outputs the second reset signal when the dead time signal occurs when the second state signal remains high,
And outputs a second turn-on signal when the detection voltage is lower than a predetermined level, and outputs the second reset signal when the dead time signal occurs when the second state signal is maintained in a low state. 13. The method of claim 12,
The dead time controller
A fourth comparator for comparing a corresponding voltage corresponding to the sensing voltage with a fourth reference voltage and outputting a signal in a high state when the voltage level of the corresponding voltage is higher than the voltage level of the fourth reference voltage;
A fifth comparator for comparing the corresponding voltage with a fifth reference voltage and outputting a high state signal when the voltage level of the corresponding voltage is lower than the voltage level of the fifth reference voltage;
A second AND gate for ANDing the output signal of the fourth comparator and the second state signal,
A third AND gate for ANDing the output signal of the fifth comparator and the inverted second state signal,
A first OR gate for receiving an output signal of the second AND gate and the third AND gate and performing an OR operation,
And a fourth AND gate for ANDing the output signal of the first OR gate with the dead time signal. 16. The method of claim 15,
Wherein the dead time controller further comprises a maximum dead time signal generator and the maximum dead time signal generator generates and outputs the second reset signal after a predetermined time elapses from the generation of the dead time signal. 17. The method of claim 16,
Wherein the dead time controller includes a maximum dead time signal generator, a second OR gate for ORing the output signal of the maximum dead time signal generator and the output signal of the fourth AND gate, and the maximum dead time signal generator comprises: A power supply unit for generating the second reset signal after a predetermined time elapses from the generation of the second reset signal and transmitting the second reset signal to the second OR gate, The method according to claim 1,
Wherein the power supply unit further includes a transformer and controls the current flowing in the primary winding of the transformer by the first switching signal and the second switching signal. 20. The method of claim 19,
Wherein the voltage sensed by the sensing unit corresponds to a voltage induced in the primary winding, the polarity of the voltage being opposite to the voltage induced in the primary winding. 21. The method of claim 20,
Wherein the sensing unit includes a sense winding, and the winding direction of the sense winding is opposite to the winding direction of the primary winding. 22. The method of claim 21,
Wherein the sensing unit divides the voltage induced in the sensing winding and outputs the sensing voltage. A switching signal generator for outputting a first switching signal and a second switching signal; And
And a dead time signal is transmitted to the switching signal generator when the voltage level of the sensing voltage is within a predetermined range so that the first switching signal and the second switching signal are not outputted by the switching signal generator by the dead time signal And a dead time signal generator for generating a dead time signal. 24. The method of claim 23,
Wherein the dead time signal generator comprises: a first capacitor for receiving and charging a first current from a first current source; a first comparator for comparing a voltage charged in the first capacitor with a first reference voltage; And a first transistor for discharging a voltage charged in the first capacitor, and outputs a signal corresponding to the dead time signal when the voltage charged in the first capacitor is lower than the first reference voltage. 25. The method of claim 24,
Wherein the first inverter is connected to the output terminal of the first comparator and the dead time signal is output through the first inverter. 25. The method of claim 24,
Wherein the dead time signal generator outputs the dead time signal when the magnitude of the sense voltage is within a predetermined range. 27. The method of claim 26,
Wherein the dead time signal generator is maintained for a first time after the dead time signal is output in a low state. 28. The method of claim 27,
Wherein the switching control device includes a first signal processing unit for generating a ramp signal, wherein the first signal processing unit determines the first time by a time when the voltage level of the ramp signal is increased. 25. The method of claim 24,
The switching control apparatus includes a first signal processing unit for generating a ramp signal and initializing the ramp signal by a second reset signal, wherein the first signal processing unit generates the ramp signal after the second reset signal is input And outputs the first reset signal when the voltage level of the ramp signal becomes equal to or greater than a predetermined value. 29. The method of claim 28,
The first signal processor
A second capacitor for charging a second current from a second current source; a second comparator for comparing a voltage generated in the second capacitor with a second reference voltage; and a comparator for comparing the voltage generated in the second capacitor with a feedback voltage An AND gate for outputting the first reset signal by ANDing an output signal of the second comparator and the third comparator, and an AND gate for outputting a voltage charged in the second capacitor by a second reset signal, 2 < / RTI > transistors. 24. The method of claim 23,
Wherein the switching signal generator comprises: a signal output unit for generating a first state signal and a second state signal; a first NOR gate for performing NOR operation on the first state signal and the dead time signal to generate the first switching signal; And a second NOR gate for NORing the second state signal and the dead time signal to generate the second switching signal. 32. The method of claim 31,
Wherein the signal output section is a D flip-flop. 32. The method of claim 31,
Wherein the switching control device includes a dead time controller for outputting a second reset signal,
Wherein the dead time controller receives the dead time signal, the second state signal, and a voltage corresponding to the sensing voltage, and outputs the second reset signal. 34. The method of claim 33,
Wherein the dead time controller determines that the voltage level of the corresponding voltage corresponding to the voltage level of the sensing voltage is lower than the first threshold value or the voltage level of the corresponding voltage is higher than the second threshold value lower than the first threshold value, And outputs the second reset signal when a dead time signal is output from the second switching unit. 34. The method of claim 33,
The dead time controller
And outputs a first turn-on signal when the detection voltage is greater than a predetermined level, outputs the second reset signal when the dead time signal occurs when the second state signal remains high,
And outputs a second turn-on signal when the detection voltage is lower than a predetermined level, and outputs the second reset signal when the dead time signal occurs when the second state signal remains in a low state. 34. The method of claim 33,
The dead time controller
A fourth comparator for comparing a corresponding voltage corresponding to the sensing voltage with a fourth reference voltage and outputting a signal in a high state when the voltage level of the corresponding voltage is higher than the voltage level of the fourth reference voltage;
A fifth comparator for comparing the corresponding voltage with a fifth reference voltage and outputting a high state signal when the voltage level of the corresponding voltage is lower than the voltage level of the fifth reference voltage;
A second AND gate for ANDing the output signal of the fourth comparator and the second state signal,
A third AND gate for ANDing the output signal of the fifth comparator and the inverted second state signal,
A first OR gate for receiving an output signal of the second AND gate and the third AND gate and performing an OR operation,
And a fourth AND gate for ANDing the output signal of the first OR gate and the dead time signal. 36. The method of claim 35,
Wherein the dead time controller further comprises a maximum dead time signal generator and the maximum dead time signal generator generates and outputs the second reset signal after a predetermined time elapses from the generation of the dead time signal. 37. The method of claim 36,
Wherein the dead time controller includes a maximum dead time signal generator, a second OR gate for ORing the output signal of the maximum dead time signal generator and the output signal of the fourth AND gate, and the maximum dead time signal generator comprises: And generates the second reset signal after a predetermined time elapses from the generation time point, and transfers the second reset signal to the second OR gate.

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