KR20160047126A - Semiconductor ic monitoring aging and method thereof - Google Patents

Abstract

The present invention relates to a technology for monitoring aging of a semiconductor integrated circuit. The semiconductor integrated circuit includes: a core; and an aging monitoring circuit which adjusts a duty cycle of a clock applied to the core which normally operates to acquire aging monitoring data from the core, and determines the aging of the core based on the acquired aging monitoring data. Accordingly, the present invention can monitor, in real time, the aging of a semiconductor integrated circuit such as an SoC while the semiconductor integrated circuit normally operates.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor integrated circuit for monitoring aging,

The present invention relates to a semiconductor integrated circuit for monitoring aging and a method thereof.

Transistor performance decreases (degrades) over time due to faulty structures such as negative / positive bias temperature instability (NBTI / PBTI), hot carrier injection (HCI) and time dependent isolation breakdown (TDDB).

In the most recent CMOS processing technology, the dominant error structure is NBTI which causes a slow delay error, which results in malfunction of the semiconductor integrated circuit including the transistor or the transistor.

In applications requiring high field reliability, such as medical devices, satellites, airplanes, power plants, etc., performance degradation or malfunction of semiconductor integrated circuits can cause life-threatening disasters. Therefore, aging monitoring technology for preventing such disasters is being developed.

One method of such aging monitoring techniques is self test techniques that perform on-line testing using test patterns previously stored in a nonvolatile memory of the system. This technology utilizes core idle time or power on / off time as test mode and performs scan-based testing with a clock that is faster than the function clock for core operation. If a system on chip (SoC) needs to continue to run without power down, it is not possible to put all the cores in test mode, so a core test scheduling method is needed to select cores to test.

A simple method of such a core test scheduling method is that the scheduler simply waits until the next core becomes idle, which can not give a large number of test opportunities to the core.

As a method to solve this problem, there is a method in which the test is tried as frequently as possible for each core while minimizing the influence on the performance of the application in consideration of the unavailability of the core, and a weighted test scheduling method based on the aging degree have.

The weighted test scheduling scheme can reduce the likelihood of missing system errors by testing more aged cores more frequently. However, in this method, since the scheduler must simultaneously schedule the normal operation, the test operation, and the interface with the processor or the OS, and enter and restore the cores into the test mode, a performance loss is inevitable. Also, unless the power on / off time is long enough, some cores, such as the processor core, are not idle during normal operation and can not be tested even during power on / off times.

In view of the foregoing, it is an object of the present invention to provide a semiconductor integrated circuit and an aging monitoring method capable of real-time monitoring of aging of a semiconductor integrated circuit during normal operation of the semiconductor integrated circuit, such as SoC.

A semiconductor integrated circuit for monitoring aging according to an embodiment of the present invention includes: a core; And an aging monitoring circuit for obtaining aging monitoring data from the core by adjusting a duty cycle of a clock applied to the core in normal operation and determining whether the core is aged based on the acquired aging monitoring data.

According to another aspect of the present invention, there is provided an aging monitoring method for a semiconductor integrated circuit, comprising: acquiring first data at a rising edge of a clock applied to the core in normal operation; Obtaining second data at a falling edge of the clock; And comparing the first data and the second data to determine aging of the core.

As described above, according to the present invention, the aging monitoring can be performed without affecting the operation performance while the semiconductor integrated circuit is operating. In addition, since aging monitoring is performed in real time, aging can be judged more quickly.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram briefly showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention; FIG.
2 is a diagram for explaining a clock of a semiconductor integrated circuit according to an embodiment of the present invention.
3 is a diagram schematically showing a configuration of a core in a semiconductor integrated circuit according to an embodiment of the present invention.
4 is a diagram schematically illustrating an internal structure of a scan cell in a semiconductor integrated circuit according to an embodiment of the present invention.
5 is a diagram showing timing in a core in a semiconductor integrated circuit according to an embodiment of the present invention.
6 is a diagram showing a configuration of an aging monitoring control unit in a semiconductor integrated circuit according to an embodiment of the present invention.
7 is a flowchart showing a method of monitoring the aging of a semiconductor integrated circuit according to an embodiment of the present invention.
FIG. 8 is a diagram illustrating a simulation result of a method for monitoring the aging of a semiconductor integrated circuit according to an embodiment of the present invention.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In the drawings, like reference numerals are used to designate identical or similar elements throughout the drawings. Note that, in the following description of the present invention, The detailed description of the constitution or function will be omitted if it is judged that the detailed description of the constitution or the function may obscure the gist of the present invention.

In this specification, the semiconductor integrated circuit will be described as an SoC (System On Chip) as an example. SoC means that a core that has been designed and has been verified has been built into one chip as a macro cell such as ROM or RAM, and another logic is added to systemize one chip.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram briefly showing a configuration of a semiconductor integrated circuit according to an embodiment of the present invention; FIG.

Referring to FIG. 1, a semiconductor integrated circuit according to an embodiment of the present invention mainly includes a core 10 and an aging monitoring circuit 100. The core 10 includes a scan chain in which a plurality of scan cells SC are connected in series and inputs and outputs data according to the operation of the core 10. [

The aging monitoring circuit 100 generates a clock applied for the operation of the core 10 and applies the generated clock to the core 10. Based on the aging monitoring data SO output from the core 10, It is determined whether or not the core 10 is aged.

The aging monitoring circuit 100 includes a clock generator 110 for generating the clock so that the core 10 can be normally operated and the aging monitoring can be performed, And an aging supervisory control unit 120 for generating and outputting an alarm according to the alarm.

The aging monitoring circuit 100 periodically checks the aging of the core 10, and generates an alarm signal as an alarm when aging is detected and transmits the alarm signal.

The alarm signal allows an administrator or user to take immediate action when aging is detected. The administrator or the user can respond to the alarm signal by, for example, activating the self-recovery mechanism or enhancing the monitoring.

The aging monitoring circuit 100 can perform the aging monitoring operation based on the aging monitoring control information input from the outside. The aging monitoring control information may be set before the semiconductor integrated circuit according to the embodiment of the present invention is released or reset to an on-board state in a system where the integrated circuit is installed.

The core 10 according to the embodiment of the present invention includes a plurality of consecutive scan cells SC as shown in FIG. 3 in order to enable aging monitoring during normal operation without stopping the operation of the core And includes two scan chains for acquiring data at different points in time, and compares data acquired from each scan chain at different points of time to determine whether or not the data is aged.

That is, when data is acquired according to the normal operation speed of the core 10 in any scan chain, data is acquired at a point earlier than the other scan chain in another scan chain.

As a method for acquiring data at a previous point in time while maintaining the normal operation speed of the core 10, a function clock of the core 10 (a clock applied to the core so that the core can perform normal operation) Can be used. However, the physical implementation is much more difficult because a faster clock than the functional clock can cause a skew between the functional clock and the scan control signal.

In view of this point, in the present invention, it is possible to implement the above-described operation by assuming that the core 10 operates as an edge trigger and adjusting the duty cycle of the function clock using the guard band of the clock frequency.

FIG. 2 is a diagram for explaining a clock of a semiconductor integrated circuit according to one embodiment of the present invention. FIG. 2 (a) is a circuit diagram of a semiconductor integrated circuit according to an embodiment of the present invention, FIG. 2B is a diagram showing a waveform of a clock whose duty cycle is adjusted to perform aging monitoring with normal operation. FIG.

In order to obtain data at different points in time from each of the two scan chains, in the semiconductor integrated circuit according to an embodiment of the present invention, the clock generator 110 is preferably a clock generator capable of adjusting the duty cycle of the clock Do.

The clock generator 110 capable of adjusting the duty cycle adjusts the duty cycle of the functional clock of the core 10 so that the falling edge of the functional clock pulse is generated in the frequency guard band of the functional clock And generates a clock whose duty cycle is adjusted.

Guard bands are given to explain the expected performance loss over the lifetime of the device, typically 10-20% of the frequency guard band is used. For example, devices running at 3GHz during the aging test can be commercialized as operating at 2.7GHz.

The range of the guard band w and the duty cycle of the adjusted clock can be determined in consideration of the manufacturing process of the semiconductor integrated circuit and the aging prediction model used in the change of the environmental condition such as the voltage and the temperature.

FIG. 3 is a diagram schematically illustrating the configuration of a core in a semiconductor integrated circuit according to an embodiment of the present invention. FIG. 4 is a cross-sectional view of a semiconductor integrated circuit according to an embodiment of the present invention, Fig.

As shown in FIG. 3, the core 10 includes two scan chains, a first scan chain 20a and a second scan chain 20b. Each of the scan chains 20a and 20b is connected to a plurality of scan cells SC # 1 to SC # n successively. The first scan chain 20a acquires the first data and the second scan chain 20b acquires the second data. The first data is transferred to the data SO1 output according to the function clock of the core 10 And the second data is outputted at a point earlier than the output point of the first data for aging monitoring.

As shown in FIG. 4, each scan cell of the first scan chain includes one MUX and a D flip-flop (hereinafter referred to as a first D flip-flop if necessary). The MUX receives the data SI output from the external or previous cell and outputs the data according to the select signal SE. The data output from the MUX is input to the D flip-flop DFF, The first data SO is output according to the clock signal CLK.

Further, each scan cell in the second scan chain includes two MUXs and one D flip-flop (ECFF, hereinafter referred to as a second D flip-flop if necessary) and an XOR gate. The two MUXs are arranged on the input side and output side of the second D flip flop (ECFF), respectively, around the second D flip flop (ECFF). A first MUX (hereinafter referred to as a first MUX) located at the input side of the second D flip flop ECFF receives data ECSI output from an external or preceding cell and outputs a second D And outputs it to the input terminal of the flip flop (ECFF).

The data output from the second D flip-flop (ECFF) according to the duty-cycle adjusted clock (CLK) is input to the XOR gate. The XOR gate is a logic integrated circuit applied to compare the first data obtained in the first D flip flop (DFF) with the second data obtained in the second D flip flop (ECFF), the XOR gate having a value of the first data 1 'when the values of the first data and the second data are different from each other, and outputs' 0' when the values are equal to each other.

That is, the data input to the core 10 are obtained in the first scan chain 20a and the second scan chain 20b, respectively, at different timings. Therefore, when no aging occurs in the core 10, Data output from the scan chain 20a and the second scan chain 20b are the same, and data of different values may be output when aging occurs.

In this specification, an XOR gate is applied as a logic integrated circuit for comparing the first data and the second data according to convenience, but is not limited thereto.

Data output from the XOR gate may be output (ECSO) to the rear scan cell through a MUX (hereinafter referred to as a second MUX). If the scan cell is the last cell of the second scan chain, And may be input to the monitoring control unit 120. The aging monitoring and controlling unit 120 observes the value of the input data, and when an '1' is sensed, it is determined that aging has occurred and an alarm signal is generated.

In this way, in the semiconductor integrated circuit according to the embodiment of the present invention, the aging monitoring operation can be performed without stopping the operation of the core, so that the occurrence of aging can be determined quickly and accurately. In addition, since the aging is judged on the basis of the data acquired in a time earlier than the time for acquiring data by the function clock, rather than the aging is delayed with respect to the data input to the core, the aging can be judged more quickly have.

5 (a) is a diagram showing a clock waveform in which the duty cycle is adjusted, and FIG. 5 (b) is a timing chart showing the timing in the core of the semiconductor integrated circuit according to the embodiment of the present invention. 5C shows waveforms of the select signal of the second MUX in each cell of the second scan chain. FIG. 5C is a view showing a waveform of the select signal of the first MUX in each cell of the second scan chain, to be.

Referring to FIG. 5, in a semiconductor integrated circuit according to an embodiment of the present invention, when a pulse of a clock whose duty cycle is adjusted (referred to as a primary pulse for convenience) is a falling edge T1, (ECFF) is obtained. The first data is obtained in the first D flip-flop (DFF) when the next pulse (referred to as a secondary pulse for convenience) is the rising edge (T2), and the select signal (ECSE1) 1 '. The comparison result of the first data and the second data at the falling edge T3 of the secondary pulse is obtained in the second D flip flop ECFF and the result of the next pulse When the select signal ECSE2 of the second MUX becomes '1' at the rising edge T4, the comparison result values obtained in the second D flip flop ECFF are shifted by one digit and input to the aging supervision control section 120 .

6 is a diagram showing a configuration of an aging monitoring control unit in a semiconductor integrated circuit according to an embodiment of the present invention.

The aging monitoring control unit 120 includes an ECS controller for controlling operation in the second scan chain 20b and an alarm generator for generating an alarm signal based on the aging monitoring data received from the core 10 Alarm Generator). The scan chain controller ECS Controller may output the select signal ECSE1 of the first MUX and the select signal ECSE2 of the second MUX in the second scan chain 20b.

The aging monitoring control unit 120 may include a shift counter (ECS Shift Counter) for controlling the shift operation with respect to the comparison result value in the second scan chain 20b, and may include a reset generator , The aging monitoring operation can be reset.

More specifically, when the aging monitoring starts, the second scan chain 20b is controlled to acquire data earlier in the first scan chain 20a, and the comparison result is observed.

When data acquisition, scan, and shift operations are completed, the observation is completed, and the aging monitoring session is completed. A time interval between aging monitoring sessions is set from the outside via a separately provided access port. When the Programmable Interval Timer (PIT) reaches the programmed interval time, the scan chain controller (ECS Controller) and the alarm generator are activated (AgMon_En = 1 for one clock cycle) Controller outputs a select signal ECSE1 of the first MUX in a state where data is acquired and a select signal ECSE2 of the second MUX in a shift state. The scan chain controller (ECS Controller) activates the shift counter (ECS Shift Counter) and observes the occurrence of an error (Scan_Out = 1 in the above description) through the aging monitoring data until the counter ends (Shift_Done = 1). If no error is observed throughout the shift operation, the alarm generator will not output an alarm signal and will wait for the next session in the idle state. However, if an error is observed during the shift operation, an alarm signal (Aging_Alarm = 1) for warning of aging is generated.

7 is a flowchart showing a method of monitoring the aging of a semiconductor integrated circuit according to an embodiment of the present invention.

In the method for monitoring the aging of the semiconductor integrated circuit according to the embodiment of the present invention, first, the duty cycle of the function clock is adjusted, and the clock whose duty cycle is adjusted is applied to the core (S10)

When the data is input to the core in the normal operation, the second scan chain acquires the second data at the falling edge of the adjusted clock applied to the core.

Next, in the first scan chain, the first data is acquired at the rising edge of the adjusted clock applied to the core (S30)

In the second scan chain, the acquired first data and second data are compared, and the comparison result is sequentially shifted to check if an error occurs (S40 and S50).

If it is determined that an error has occurred in the shift operation, it is determined that aging has occurred in the core, and an alarm for warning is generated and output (S60)

FIG. 8 is a diagram illustrating a simulation result of a method for monitoring the aging of a semiconductor integrated circuit according to an embodiment of the present invention.

In order to perform the simulation, a first scan chain and a second scan chain of 8 bits are designed and 8-bit data to be input to the scan chain is generated. The semiconductor integrated circuit according to an embodiment of the present invention operates at 2 GHz in the aging test procedure and assumes that a frequency guard band of 20% is used. Therefore, the frequency of the functional clock becomes 1.6 GHz.

Referring to FIG. 7, in the semiconductor integrated circuit according to the embodiment of the present invention, a delay is added to the first (leftmost) data input signal of FIG. 7 as if aging occurred in the data path in order to verify the aging function. As indicated by the dotted rectangle on the left, the first bit has transitioned from '11001110' to '01001110' during the guardband interval.

'11001110' is obtained in the second scan chain at the falling edge of the adjusted clock. And " 01001110 " is obtained in the first scan chain (DO) at the rising edge of the adjusted clock. If the select signal of the first MUX and the select signal of the second MUX are both 1, the comparison result is acquired and shifted in the next scan cell (ECFF) of the second scan chain. Therefore, the first 8 bits in the right dashed box are 01000000, which means that the aging is detected in the first data input signal. As a result, 1 is shifted to output an alarm signal indicating aging.

In the above, each cell of the second scan chain basically includes a flip-flop and an XOR gate. Instead of a flip flop, a latch may be included. In the semiconductor integrated circuit according to the embodiment of the present invention, each cell of the second scan chain has two MUXs and uses a duty-cycle adaptable clock, but does not require a data / clock delay circuit or an additional clock tree Therefore, overhead can be relatively low in large designs.

Further, in the semiconductor integrated circuit according to the embodiment of the present invention, since each cell of the second scan chain operates at the edge of the previous clock and does not generate additional switching activity in the logic to be combined, It is possible to consume less power than conventional methods using a clock tree.

Since the size of the scan chain depends on the number of scan cells, it is apparent that the total area and the power consumption are varied as the number of scan cells is increased or decreased. However, the aging monitoring method according to an embodiment of the present invention is directed to a system that supports an electronic lifetime or a system that is relatively large and high-end (high-end). In such a system, A slight increase is acceptable if the reliability and stability of the system is guaranteed.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention as defined by the appended claims. The embodiments of the present invention are not intended to limit the scope of the present invention but to limit the scope of the present invention.

10: Core
20a: First scan chain
20b: second scan chain
100: aging monitoring circuit
110: clock generator
120: aging monitoring control unit

Claims (8)

core; And
An aging monitoring circuit for determining aging of the core based on the obtained aging monitoring data by adjusting the duty cycle of a clock applied to the core in normal operation to obtain aging monitoring data from the core,
And a semiconductor integrated circuit. The method according to claim 1,
The aging monitoring circuit includes:
An aging monitoring control unit for generating and outputting an alarm according to the aging monitoring data input from the core,
And a semiconductor integrated circuit. The method according to claim 1,
The aging monitoring circuit includes:
A clock generator for generating the clock and applying the clock to the core so that a falling edge of the clock falls within a frequency guard band of the clock set in the core;
And a semiconductor integrated circuit. The method according to claim 1,
The core comprises:
A first scan chain that includes a plurality of consecutive scan cells and acquires first data at a rising edge of the clock whose duty cycle is adjusted; And
A second scan chain that includes a plurality of consecutive scan cells and acquires second data at a falling edge of the clock whose duty cycle is adjusted;
And a semiconductor integrated circuit. 5. The method of claim 4,
Wherein the first data is obtained at a rising edge after the falling edge of the clock at which the second data is obtained. 5. The method of claim 4,
Each cell of the first scan chain including a first flip-flop for acquiring the first data,
Each cell of the second scan chain having a second flip-flop for acquiring the second data, and an output terminal of the first flip-flop and an output terminal of the second flip-flop to compare the first data and the second data The logic integrated circuit comprising: Obtaining first data at a rising edge of a clock applied to the core in normal operation;
Obtaining second data at a falling edge of the clock; And
Comparing the first data and the second data to determine aging of the core
Wherein the aging monitoring method comprises the steps of: 8. The method of claim 7,
Acquiring the first data at a rising edge after the falling edge from which the second data is acquired,
And acquires the comparison result of the first data and the second data at the falling edge of the pulse having the rising edge.

Images