CN117074901A - Test circuitry for testing multi-cycle path circuits - Google Patents

Abstract

Test circuitry for testing a multi-cycle path circuit includes an on-chip clock controller circuit and a first clock adjustment circuit. The on-chip clock controller circuit is used for responding to a reference clock signal, a scanning enabling signal, a plurality of enabling bits and a scanning mode signal to generate an internal clock signal, and responding to the scanning enabling signal, a plurality of first bits and the reference clock signal to generate a first control signal. The first clock adjusting circuit is used for generating a first test clock signal according to the first control signal and the internal clock signal so as to test a multi-cycle path circuit. The first bits are used for setting a first pulse in the first test clock signal so as to prevent a timing violation from occurring in the multi-cycle path circuit.

Description

Test circuitry for testing multi-cycle path circuits

Technical Field

The present disclosure relates to test circuitry, and more particularly to test circuitry for testing multi-cycle path circuits.

Background

In order to ensure that the chip meets the design requirements, the timing analysis can be performed on the chip to ensure that a plurality of circuits in the chip can operate correctly. When a multi-cycle path (multi-cycle path) circuit exists in a chip, in order to avoid timing errors, the conventional test method needs to turn off the multi-cycle path (multi-cycle path) circuit or reduce the speed of a clock signal, which results in a decrease of test coverage. In other related art, in order to obtain test results of a multi-cycle path circuit, an attempt may be made to estimate a clock signal suitable for the multi-cycle path circuit by adjusting test data of an automatic test pattern generator (automatic test pattern generator). However, in practical applications, the above estimation may result in an excessively long running time of the automatic test pattern generator, or the automatic test pattern generator may not generate suitable test data and cannot perform the estimation.

Disclosure of Invention

In some embodiments, one of the purposes of the present disclosure is, but is not limited to, providing test circuitry that can utilize multiple bits to configure a clock signal that tests a multi-cycle path circuit.

In some embodiments, the test circuitry includes an on-chip clock controller circuit and a first clock adjustment circuit. The on-chip clock controller circuit is used for responding to a reference clock signal, a scanning enabling signal, a plurality of enabling bits and a scanning mode signal to generate an internal clock signal, and responding to the scanning enabling signal, a plurality of first bits and the reference clock signal to generate a first control signal. The first clock adjustment circuit is used for generating a first test clock signal according to the first control signal and the internal clock signal so as to test a multi-cycle path (multi-cycle path) circuit. The first bits are used for setting a first pulse in the first test clock signal so as to prevent a timing violation from occurring in the multi-cycle path circuit.

The features, implementation and effects of the present invention are described in detail below with reference to the following preferred embodiments in conjunction with the accompanying drawings.

Drawings

FIG. 1 is a schematic diagram of a test circuitry according to some embodiments of the present disclosure;

FIG. 2 is a schematic diagram of the on-chip clock controller circuit of FIG. 1 according to some embodiments of the present disclosure;

FIG. 3 is a schematic diagram of the scan control circuit of FIG. 2 according to some embodiments of the present disclosure;

FIG. 4 is a schematic diagram of the test clock control circuit of FIG. 2 according to some embodiments of the present disclosure; and

FIG. 5 is a schematic diagram of another test clock control circuit of FIG. 2 according to some embodiments of the present disclosure.

Detailed Description

All terms used herein have their ordinary meaning. The foregoing words are defined in commonly used dictionaries, and the use of any word discussed herein is exemplary only and should not be interpreted as limiting the scope and meaning of the present disclosure. Similarly, the present disclosure is not limited to the various embodiments shown in this specification.

As used herein, "coupled" or "connected" may mean that two or more elements are in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, and may also mean that two or more elements are in operation or action with each other. As used herein, the term "circuitry" may be a single system formed by at least one circuit (circuit), and the term "circuit" may be a device connected in a manner by at least one transistor and/or at least one active and passive component to process a signal.

As used herein, the term "and/or" includes any combination of one or more of the listed associated items. The terms first, second, third, etc. are used herein to describe and identify various elements. Accordingly, a first component may also be referred to herein as a second component without departing from the intent of the present disclosure. For ease of understanding, like components in the various figures will be designated with the same reference numerals.

Fig. 1 is a schematic diagram of a test circuitry 100 according to some embodiments of the present disclosure. The test circuitry 100 may test (e.g., without limitation, scan test, static timing analysis, etc.) the multi-cycle path circuit 100B, the single-cycle (single cycle path) path circuit 100A, and the single-cycle path circuit 100C. In this example, the single-cycle path circuit 100A, the multi-cycle path circuit 100B and the single-cycle path circuit 100C are sequentially coupled in series. In some embodiments, test circuitry 100 may be integrated with multi-cycle path circuit 100B, single-cycle path circuit 100A, and single-cycle path circuit 100C as a single chip.

In some embodiments, at least two cycles are required for a signal (or data) to be transferred between two registers (or flip-flops) in the multi-cycle path circuit 100B to stabilize. In other words, at least two cycles are required between the setup time and the hold time of the multi-cycle path circuit 100B. For example, at least two cycles are required for the transfer between the input of multi-cycle path circuit 100B (e.g., the signal path between single-cycle path circuit 100A and multi-cycle path circuit 100B) and the output of multi-cycle path circuit 100B (e.g., the signal path between multi-cycle path circuit 100B and single-cycle path circuit 100C). In some embodiments, only one cycle is required for a signal (or data) to be transferred between two registers (or flip-flops) in the single-cycle path circuit 100A (or 100C) to stabilize. In various embodiments, each of the multi-cycle path circuit 100A, the single-cycle path circuit 100A, and the single-cycle path circuit 100C may be implemented by a number of digital logic circuits.

The test circuitry 100 includes an on-chip clock (OCC) controller circuit 110, a clock adjustment circuit 120, and a clock adjustment circuit 130.OCC controller circuit 110 generates internal clock signal CLKT in response to reference clock signal CLKR, scan enable signal SEN, a plurality of enable bits EN [0] EN [3] and scan mode signal SM. In some embodiments, the reference clock signal CLKR may be generated by, but is not limited to, a phase-locked loop circuit. Furthermore, the OCC controller circuit 110 can generate the control signal SC1 in response to the scan enable signal SEN, the plurality of bits B1[0] B1[3] and the reference clock signal CLKR, and can generate the control signal SC2 in response to the scan enable signal SEN, the plurality of bits B2[0] B2[3] and the reference clock signal CLKR.

The clock adjustment circuit 120 is configured to generate the test clock signal CLK1 in response to the control signal SC1 and the internal clock signal CLKT to test the multi-cycle path circuit 100B. The clock adjustment circuit 130 is configured to generate the test clock signal CLK2 in response to the control signal SC2 and the internal clock signal CLKT to test the monocycle path circuit 100A and the monocycle path circuit 100C.

In some embodiments, the clock adjustment circuit 120 includes a logic gate circuit 121 and a clock gating circuit 122. The logic gate 121 is configured to generate the enable signal EN1 in response to an inversion of the control signal SC1. For example, the logic gate 121 may be, but is not limited to, an AND gate having an inverting input that receives the control signal SC1 and another input that receives the test signal F1. In some embodiments, the test signal F1 may be, but is not limited to, test data from an automatic test pattern generator (automatic test pattern generator). The clock gating circuit 122 may generate the test clock signal CLK1 in response to the enable signal EN1 and the internal clock signal CLKT. For example, the clock gating circuit 122 may be, but is not limited to, an integrated clock gating cell (integrated clock gating (ICG) cell) that may determine whether to generate pulses of the output test clock signal CLK1 based on the resulting enable signal EN1.

In some embodiments, the clock adjustment circuit 120 and the clock adjustment circuit 130 have the same circuit structure. For example, similar to clock adjustment circuit 120, clock adjustment circuit 130 may include logic gate circuit 131 and clock gating circuit 132. The logic gate circuit 131 is configured to generate the enable signal EN2 in response to an inversion of the control signal SC2. For example, the logic gate 131 may be, but is not limited to, an AND gate having an inverting input that receives the control signal SC2 and another input (i.e., a non-inverting input) that receives the test signal F2. In some embodiments, the test signal F2 may be, but is not limited to, test data from an automatic test pattern generator. The clock gating circuit 132 may generate the test clock signal CLK2 in response to the enable signal EN2 and the internal clock signal CLKT. For example, the clock gating circuit 132 may be, but is not limited to, an integrated clock gating unit that sequentially determines whether to generate a plurality of pulses of the output test clock signal CLK2 according to the resulting enable signal EN2.

With the above arrangement, the bits B1[0] to B1[3] can be used to set at least one pulse of the test clock signal CLK1 to avoid timing violations (timing violations) of the multi-cycle path circuit 100B. In some embodiments, the timing violations may include, but are not limited to, a timing violation of a hold time (hold time violation), a timing violation of a setup time (setup time violation), and so on. In this example, the plurality of bits B1[0] B1[3] and the plurality of bits B2[0] B2[3] can be used to set the intervals between the pulses (e.g., the pulses P1') in the test clock signal CLK1 and the pulses (e.g., the pulses P_0 to P_3) of the test clock signal CLK2 to avoid the timing violations.

For the example of fig. 1, the monocycle path circuit 100A may generate a stable output to the multicycle path circuit 100B in one cycle (corresponding to 1 pulse width) after the monocycle path circuit 100A is triggered by the pulse P0 of the internal clock signal CLKT. Thus, the multi-cycle path circuit 100B may receive the output of the single-cycle path circuit 100A via the pulse P1 trigger of the internal clock signal CLKT and generate a stable output after two cycles (corresponding to 2 pulse widths). Accordingly, the single-cycle path circuit 100C may be triggered by the pulse P3 of the internal clock signal CLKT to receive the output of the multi-cycle path circuit 100B for subsequent operations. In this way, all timing violations can be avoided without reducing the speed of the internal clock signal CLKT to properly test the single-cycle path circuit 100A, the multi-cycle path circuit 100B, and the single-cycle path circuit 100C.

To achieve the above sequence, the bits B1[0] to B1[3] may be sequentially set to a logic value 1, a logic value 0, a logic value 1 and a logic value 1 (denoted as B1[3:0] =1101 in the figure), and the bits B2[0] to B2[3] may be sequentially set to a logic value 0, a logic value 1 and a logic value 0 (denoted as B2[3:0] =0110 in the figure). The OCC controller circuit 110 can generate a control signal SC1 (the waveform of which has a logic value 1, a logic value 0 and a logic value 0 in sequence from left to right) corresponding to a plurality of bits B1[0] to B1[3] and a control signal SC2 (the waveform of which has a logic value 0, a logic value 1 and a logic value 0 in sequence from left to right) corresponding to a plurality of bits B2[0] to B2[ 3]. In this way, the clock adjustment circuit 120 can sequentially output the pulse P1 of the internal clock signal CLKT as the pulse P1' of the test clock signal CLK1 in response to the inversion of the plurality of bits in the control signal SC1.

For example, since bit B1[3] has a logic value of 1, the inversion of bit B1[3] is a logic value of 0, so that logic gate 121 can output the resulting enable signal EN1 having a logic value of 0. Under this condition, the clock gating circuit 122 masks (or disables) the pulse P3 of the internal clock signal CLKT such that the corresponding pulse P3' of the test clock signal CLK1 is removed (drawn in dashed lines). By analogy, in response to bits B1[0] and B1[2], clock gating circuit 122 masks (or disables) pulses P0 and P2 of internal clock signal CLKT such that pulses P0 'and P2' of test clock signal CLK1 are removed (depicted in dashed lines). In contrast, since bit B1[1] has a logic value of 0, the inversion of bit B1[1] is a logic value of 1, so that logic gate 121 outputs the resulting enable signal EN1 having a logic value of 1 (assuming that test signal F1 is a logic value of 1). Under this condition, the clock gating circuit 132 does not mask the pulse P1 of the internal clock signal CLKT and outputs the pulse P1 as the pulse P1' of the test clock signal CLK1. Based on a similar operation, the clock adjustment circuit 130 may output the pulses P0 and P3 of the internal clock signal CLKT as the pulses p_0 and p_3 of the test clock signal CLK2 in response to the anti-dependence of the plurality of bits in the control signal SC2 in sequence, and remove the pulses p_1 and p_2 of the test clock signal CLK2 (drawn with dotted lines). In the equivalent, by setting the plurality of bits B1[0] to B1[3] and the plurality of bits B2[0] to B2[3], the interval between the pulse P1' in the test clock signal CLK1 and the pulses P_0 and P_3 in the test clock signal CLK2 can be set. For example, as shown in fig. 1, the pulses P1', p_0 and p_3 are discontinuous pulses. Thus, timing violations of the circuits under test (e.g., multi-cycle path circuit 100B, single-cycle path circuit 100A, and single-cycle path circuit 100C) can be avoided.

It should be understood that the number of control signals (i.e., the control signals SC1 and SC 2) generated by the OCC controller circuit 110 may be different according to different actual requirements (e.g., different circuit configurations to be tested). In various embodiments, the number of control signals generated by the OCC controller circuit 110 may be at least one. For example, if the circuit to be tested includes only the multi-cycle path circuit 100b, the occ controller circuit 110 may generate only the control signal SC1, and the test circuitry 100 may include only the clock adjustment circuit 120. Therefore, the present disclosure is not limited to the arrangement shown in fig. 1, and various numbers of clock adjustment circuits and/or various numbers of control signals are all intended to be covered.

Fig. 2 is a schematic diagram of the OCC controller circuit 110 of fig. 1 according to some embodiments of the present disclosure. In this example, OCC controller circuit 110 includes scan control circuit 210, test clock control circuit 220, and test clock control circuit 230. The scan control circuit 210 is configured to generate a signal S1 in response to the scan enable signal SEN and the reference clock signal CLKR, and generate an internal clock signal CLKT according to the signal S1, the enable bits EN [0] to EN [3] and the scan mode signal SM. The test clock control circuit 220 is used for generating the control signal SC1 in response to the signal S1, the bits B1[0] to B1[3] and the reference clock signal CLKR. Similarly, the test clock control circuit 230 is configured to generate the control signal SC2 in response to the signal S1, the bits B2[0] to B2[3] and the reference clock signal CLKR. In some embodiments, scan control circuit 210, test clock control circuit 220, and test clock control circuit 230 may be synchronized via signal S1.

It should be appreciated that in other embodiments, the occ controller circuit 110 may only generate the control signal SC1 if the circuit to be tested only includes the multi-cycle path circuit 100b. In this condition, OCC controller circuit 110 may not include test clock control circuit 230.

Fig. 3 is a schematic diagram illustrating the scan control circuit 210 of fig. 2 according to some embodiments of the present disclosure. In some embodiments, scan control circuit 210 includes a D-type flip-flop circuit 305, a plurality of D-type flip-flop circuits 310[0] 310[3], a plurality of inverter circuits 315[0] 315[3], a plurality of logic gate circuits 320[0] 320[3], a logic gate circuit 325, a logic gate circuit 330, a clock gate circuit 335, a logic gate circuit 340, and a multiplexer circuit 345. The D-type flip-flop circuit 305 is triggered according to the reference clock signal CLKR to transmit the scan enable signal SEN as the signal S1. The D-type flip-flop circuits 310[0] to 310[3] are serially connected in sequence and are triggered by the reference clock signal CLKR to sequentially output a plurality of signals S20[0] to S20[3] according to the signal S1. Each of the plurality of inverter circuits 315[0] to 315[3] generates a corresponding one of the plurality of signals S30[0] to S30[3] according to the signal S1 and a corresponding one of the plurality of signals S20[0] to S20[ 2]. For example, inverter circuit 315[0] generates signal S30[0] from signal S1, and inverter circuit 315[1] generates signal S30[1] from signal S20[ 0]. By analogy, the arrangement of the remaining inverter circuits 315[2] and 315[3] should be understood.

Each of the plurality of logic gate circuits 320[0] to 320[3] is configured to generate a plurality of signals S40[0] to S40[3] according to a corresponding one of the plurality of signals S30[0] to S30[3], a corresponding one of the plurality of enable bits EN [0] to EN [3], and a corresponding one of the plurality of signals S20[0] to S20[3]. For example, the logic gate circuit 320[0] generates the signal S40[0] according to the signal S30[0], the enable bit EN [0] and the signal S20[ 0]. The logic gate circuit 320[1] generates the signal S40[1] according to the signal S30[1], the enable bit EN [1] and the signal S20[ 1]. By analogy, the arrangement of the remaining logic gate circuits 320[2] and 320[3] should be understood. In some embodiments, each of the plurality of logic gates 320[0] 320[3] may be, but is not limited to being, an AND gate.

The logic gate circuit 325 is used for generating a signal S5 according to a plurality of signals S40[0] to S40[ 3]. In some embodiments, logic gate 325 may be, but is not limited to being, an OR gate. The logic gate 330 is used for generating a signal S6 according to the signal S5 and the scan mode signal SM. In some embodiments, the logic gate 330 may be, but is not limited to, an OR gate having an inverting input that receives the scan mode signal SM and another input (i.e., a non-inverting input) that receives the signal S5. The clock gating circuit 335 generates the clock signal CK according to the signal S6 and the reference clock signal CLKR. The logic gate circuit 340 generates the switching signal SS according to the scan mode signal SM and the scan enable signal SEN. In some embodiments, the logic gate circuit 340 may be, but is not limited to, an OR gate circuit having an inverting input, and the multiplexer circuit 345 is configured to selectively output the scan clock signal CLKS or the clock signal CK as the internal clock signal CLKT according to the switching signal SS.

Fig. 4 is a schematic diagram of the test clock control circuit 220 of fig. 2 according to some embodiments of the present disclosure. In this example, the test clock control circuit 220 includes a plurality of D-type flip-flop circuits 410[0] to 410[3], a plurality of inverter circuits 415[0] to 415[3], a plurality of logic gate circuits 420[0] to 420[3], and a logic gate circuit 425. The D-type flip-flop circuits 410[0] to 410[3] are serially connected in sequence and are triggered by the reference clock signal CLKR to sequentially output a plurality of signals S21[0] to S21[3] according to the signal S1.

The inverter circuits 415[0] to 415[3] generate a plurality of signals S31[0] to S31[3] according to the signal S1 and a part of the signals S21[0] to S21[3]. In some embodiments, some of the plurality of signals S21[0] to S21[3] do not include the last signal S21[3]. That is, the partial signal may be a plurality of signals S21[0] to S21[2]. Specifically, each of the inverter circuits 415[0] to 415[3] generates a corresponding one of the signals S31[0] to S31[3] according to the signal S1 and the corresponding one of the signals S21[0] to S21[2]. For example, the inverter circuit 415[0] generates the signal S31[0] according to the signal S1, and the inverter circuit 415[1] generates the signal S31[1] according to the signal S21[ 0]. By analogy, the arrangement of the remaining inverter circuits 415[2] and 415[3] should be understood.

Each of the plurality of logic gate circuits 420[0] to 420[3] is configured to generate one of the plurality of signals S41[0] to S41[3] according to one of the plurality of signals S31[0] to S31[3], one of the plurality of bits B1[0] to B1[3], and one of the plurality of signals S21[0] to S21[3]. For example, the logic gate circuit 420[0] generates the signal S41[0] according to the signal S31[0], the bit B1[0] and the signal S21[ 0]. The logic gate circuit 420[1] generates the signal S41[1] according to the signal S31[1], the bit B1[1] and the signal S21[ 1]. By analogy, the arrangement of the remaining logic gate circuits 420[2] and 420[3] should be understood. In some embodiments, each of the plurality of logic gates 420[0] 420[3] may be, but is not limited to being, an AND gate. The logic gate 425 is configured to generate the control signal SC1 according to the plurality of signals S41[0] to S41[ 3]. In some embodiments, logic gate 425 may be, but is not limited to, an OR gate.

By the above arrangement, the bits B1[0] to B1[3] can be used to configure the bits of the control signal SC1. Thus, the clock adjustment circuit 120 of fig. 1 can generate the corresponding test clock signal CLK1 accordingly. In other words, the user can set the logic values of the bits B1[0] to B1[3] according to the required timing of the multi-cycle path circuit 100B to directly adjust the timing of the test clock signal CLK1, thereby avoiding timing violations.

Fig. 5 is a schematic diagram of the test clock control circuit 230 of fig. 2 according to some embodiments of the present disclosure. In some embodiments, test clock control circuit 220 and test clock control circuit 230 may have the same circuit structure. For example, the test clock control circuit 230 includes a plurality of D-type flip-flop circuits 510[0] to 510[3], a plurality of inverter circuits 515[0] to 515[3], a plurality of logic gate circuits 520[0] to 520[3], and a logic gate circuit 525. The D-type flip-flop circuits 510[0] to 510[3] are serially connected in sequence and are triggered by the reference clock signal CLKR to sequentially output a plurality of signals S22[0] to S22[3] according to the signal S1.

The inverter circuits 515[0] to 515[3] generate a plurality of signals S32[0] to S32[3] according to the signal S1 and a part of the signals S22[0] to S22[3]. In some embodiments, some of the plurality of signals S22[0] to S22[3] do not include the last signal S22[3]. That is, the partial signal may be a plurality of signals S22[0] to S22[2]. In detail, each of the inverter circuits 515[0] to 515[3] generates a corresponding one of the signals S32[0] to S32[3] according to the signal S1 and the corresponding one of the signals S22[0] to S22[2]. For example, inverter circuit 515[0] generates signal S32[0] from signal S1, and inverter circuit 515[1] generates signal S32[1] from signal S22[ 0]. By analogy, the arrangement of the remaining inverter circuits 515[2] and 515[3] should be understood.

Each of the logic gate circuits 520[0] to 520[3] is configured to generate one of the plurality of signals S42[0] to S42[3] according to one of the plurality of signals S32[0] to S32[3], one of the plurality of bits B2[0] to B2[3], and one of the plurality of signals S22[0] to S22[3]. For example, the logic gate 520[0] generates the signal S42[0] according to the signal S32[0], the bit B2[0] and the signal S22[ 0]. Logic gate 520[1] generates signal S42[1] based on signal S32[1], bit B2[1] and signal S22[ 1]. By analogy, the arrangement of the remaining logic gate circuits 520[2] and 520[3] should be understood. In some embodiments, each of the plurality of logic gates 520[0] 520[3] may be, but is not limited to, an AND gate. The logic gate 525 is used for generating the control signal SC2 according to the plurality of signals S42[0] to S42[ 3]. In some embodiments, logic gate 525 may be, but is not limited to, an OR gate.

Similarly, by the above arrangement, the bits B2[0] to B2[3] can be used to configure the bits of the control signal SC2. Thus, the clock adjustment circuit 130 of fig. 1 can generate the corresponding test clock signal CLK2 accordingly. In other words, if the circuit to be tested includes a multi-cycle path circuit (e.g., the multi-cycle path circuit 100B of fig. 1) and a single-cycle path circuit (e.g., the single-cycle path circuit 100A and the single-cycle path circuit 100B of fig. 1), the logic values of the bits B1[0] to B1[3] and the bits B2[0] to B2[3] can be set by the user according to the connection between the multi-cycle path circuit and the single-cycle path circuit and the timing required by the connection between the multi-cycle path circuit and the single-cycle path circuit, so as to directly adjust the timings of the test clock signal CLK1 and the test clock signal CLK2, thereby avoiding the timing violation. In this way, full speed testing (at-speed test) can be performed without reducing the speed of the internal clock signal CLKT or turning off the multi-cycle path circuit to obtain higher test coverage.

The circuit arrangement manner shown in the above embodiments is only for example, and the present disclosure is not limited thereto. Circuit arrangements that perform the same or similar functions are within the scope of the present disclosure.

In summary, the test circuitry in some embodiments of the present disclosure may utilize a configurable plurality of bits to set the timing of the test clock signal. Therefore, the time sequence analysis can be performed on the multi-period path circuit without reducing the speed, so that higher test coverage rate can be obtained.

Although the embodiments of the present invention are described above, the embodiments are not limited to the embodiments, and a person skilled in the art may apply variations to the technical features of the present invention according to the explicit or implicit disclosure of the present invention, where all variations may fall within the scope of protection sought herein, in other words, the scope of protection of the present invention shall be defined by the claims of the present application.

[ symbolic description ]

100: test circuit system

100A, 100C: single cycle path circuit

100B: multi-cycle path circuit

110: on-chip clock controller circuit

120: clock adjusting circuit

121. 131: logic gate circuit

122. 132, 335: clock gating circuit

130: clock adjusting circuit

210: scanning control circuit

220. 230: test clock control circuit

305. 310[0] to 310[3], 410[0] to 410[3], 510[0] to 510[3]: d-type flip-flop circuit

315[0] to 315[3], 415[0] to 415[3], 515[0] to 515[3]: inverter circuit

320 < 0 > -320 < 3 >, 420 < 0 > -420 < 3 >, 520 < 0 > -520 < 3 >: logic gate circuit

325. 425, 525: logic gate circuit

330. 340: logic gate circuit

345: multiplexer circuit

B1[0] to B1[3], B1[3:0], B2[0] to B2[3], B2[3:0]: bits

CK: clock signal

CLK1, CLK2: testing clock signals

CLKR: reference clock signal

CLKS: scanning clock signal

CLKT: internal clock signal

EN 0-EN 3: enable bit

EN1, EN2: the resulting enable signal

F1, F2: test signal

P0 to P3, P0 'to P3', p_0 to p_3: pulse

S1: signal signal

S20[0] to S20[3], S21[0] to S21[3], S22[0] to S22[3]: signal signal

S30[0] to S30[3], S31[0] to S31[3], S32[0] to S32[3]: signal signal

S40[0] to S40[3], S31[0] to S31[3], S42[0] to S42[3]: signal signal

S5, S6: signal signal

SC1, SC2: control signal

SEN: scan enable signal

SM: scanning mode signal

SS: and switching the signal.

Claims (10)

1. A test circuitry comprising:

an on-chip clock controller circuit for generating an internal clock signal in response to a reference clock signal, a scan enable signal, a plurality of enable bits, and a scan mode signal, and generating a first control signal in response to the scan enable signal, a plurality of first bits, and the reference clock signal; and

a first clock adjusting circuit for generating a first test clock signal according to the first control signal and the internal clock signal to test a multi-cycle path circuit,

the first bits are used for setting a first pulse in the first test clock signal so as to prevent a timing violation of the multi-cycle path circuit.

2. The test circuitry of claim 1, wherein the on-chip clock controller circuit comprises:

a scan control circuit for generating a first signal in response to the scan enable signal and the reference clock signal, and generating the internal clock signal according to the first signal, the plurality of enable bits, and the scan mode signal; and

and the test clock control circuit is used for responding to the first signal, the plurality of first bits and the reference clock signal to generate the first control signal.

3. The test circuitry of claim 2, wherein the scan control circuit and the test clock control circuit are synchronized via the first signal.

4. The test circuitry of claim 2, wherein the scan control circuit comprises:

the D-type flip-flop circuits are sequentially coupled in series and used for triggering through the reference clock signal and sequentially outputting a plurality of second signals according to the first signal;

a plurality of inverter circuits for generating a plurality of third signals according to the first signal and a part of the second signals;

a plurality of first logic gate circuits, wherein each of the plurality of first logic gate circuits is configured to generate a corresponding one of a plurality of fourth signals according to a corresponding one of the plurality of first bits, a corresponding one of the plurality of third signals, and a corresponding one of the plurality of second signals; and

and the second logic gate circuit is used for generating the first control signals according to the fourth signals.

5. The test circuitry of claim 4, wherein a portion of the plurality of second signals does not include a last signal of the plurality of second signals.

6. The test circuitry of claim 1, wherein the on-chip clock controller circuit is further configured to generate a second control signal in response to the scan enable signal, a plurality of second bits, and the reference clock signal, and the test circuitry further comprises:

the second clock adjusting circuit is used for generating a second test clock signal according to the second control signal and the internal clock signal so as to test a single-period path circuit, wherein the single-period path circuit is coupled to the multi-period path circuit.

7. The test circuitry of claim 6, the first plurality of bits and the second plurality of bits to set a spacing between the first pulse and a second plurality of pulses in the second test clock signal to avoid the timing violation.

8. The test circuitry of claim 7, wherein the first pulse and the second plurality of pulses are discrete pulses.

9. The test circuitry of claim 1, wherein the first clock adjustment circuit comprises:

a logic gate circuit for generating a resulting enable signal in response to an inversion of the first control signal; and

a clock gating circuit generates the first test clock signal in response to the enable signal and the internal clock signal.

10. The test circuit system of claim 9, wherein the logic gate circuit is an and gate circuit having an inverting input for receiving the first control signal.