KR20160043497A - Method and device for implementing symbol lock of IO interface - Google Patents

Abstract

The present invention relates to a method and device for executing a symbol lock operation on an input/output (I/O) interface. On the I/O interface between a memory controller and a memory device, the memory controller transmits a write command, symbol lock patterns, and write data bursts while the memory device receives symbol lock patterns in a preamble section and receives the write data bursts after write latency. The memory device generates a write enable signal from the write command and includes a symbol lock pattern detection unit. The symbol lock pattern detection unit stores multiple symbol lock patterns, detects the symbol lock patterns based on the write enable signal, and searches for the first data of the write data bursts based on the detected symbol lock patterns.

Description

[0001] The present invention relates to a method and apparatus for performing a symbol lock on an input / output interface,

The present invention relates to a semiconductor device, and more particularly, to a symbol lock method and apparatus for finding first data of transmission data in a multi-bit input / output interface.

Semiconductor memory devices can be used to manage and store data and operational instructions in systems such as computers. Particularly, DRAM (Dynamic Random Access Memory) has an advantage of simple memory cell structure and can have a very high storage density at low cost. DRAM can be used in mobile systems such as cell phones, portable computers, and portable multimedia players as well as large electronic systems. The DRAM can be connected to these systems through various interfaces, and can transmit and receive data to be processed in the systems. On the receiving side of the data, the symbol lock method of finding the first data of the symbol data transmitted through the interface is important. Among the symbol lock methods, a method of looping the entire symbol once is not suitable for a high-speed interface because it takes a long time. A fast symbol lock is required for high-speed interfaces.

It is an object of the present invention to provide an input / output interface for finding the first data of a transmitted data burst.

It is another object of the present invention to provide a memory device for finding the first data of a write data burst.

It is yet another object of the present invention to provide a symbol lock method for finding the first data of a transmission data burst.

According to an aspect of the present invention, there is provided an input / output interface including a transmitter for transmitting at least one symbol lock pattern and a data burst through an input / output interface, a symbol lock pattern received through the input / And a receiving unit for searching for the first data of the data burst according to the detected symbol lock pattern.

According to embodiments of the present invention, the receiver may store a plurality of symbol lock patterns, and may compare the received symbol data with stored symbol lock patterns to detect a symbol lock pattern.

According to embodiments of the present invention, the transfer unit is a memory controller that issues a write command, and the receiving unit generates a write enable signal in response to the write command, and searches the first data of the data burst based on the write enable signal, Device.

According to embodiments of the present invention, a memory device receives a clock signal, generates a first clock signal in accordance with even edges of the clock signal, and generates a second clock signal in accordance with the odd edges of the clock signal. A sampler for sequentially inputting and outputting a symbol lock pattern and a data burst transferred through a plurality of data input / output (DQ) signals in response to the first and second clock signals and the write enable signal, and a write FIFO A symbol lock pattern detector for detecting a symbol lock pattern at an output of a sampler and a write FIFO in response to a write enable signal and generating a data latch signal in accordance with the detected symbol lock pattern, And a data arrangement for outputting a data burst in an output of the FIFO in a parallel fashion.

According to embodiments of the present invention, the receiver stores a plurality of symbol lock patterns, compares data received via the input / output interface with stored symbol lock patterns, detects a plurality of symbol lock patterns, And to find the first data of the data burst based on the write enable signal.

According to embodiments of the present invention, a memory device receives a clock signal, generates a first clock signal in accordance with even edges of the clock signal, and generates a second clock signal in accordance with the odd edges of the clock signal. A sampler and a write FIFO for sequentially inputting and serially outputting symbol lock patterns and data bursts transmitted through a plurality of data input / output (DQ) signals in response to first and second clock signals, a sampler and a write A symbol lock pattern detector for detecting symbol lock patterns at the output of the FIFO, generating a write enable signal in accordance with the detected symbol lock patterns, and generating a data latch signal based on the write enable signal, And a data arrangement for outputting the data bursts in a parallel fashion at the output of the sampler and the write FIFO in response.

According to embodiments of the present invention, the transfer unit is a memory device that outputs read data in a data burst in response to a read command, and the receiving unit may be a memory controller that issues a read command and finds the first data of the read data.

According to embodiments of the present invention, the memory controller may store a plurality of symbol lock patterns, and may compare the received symbol data with the received symbol data through the input / output interface to detect the symbol lock pattern.

According to embodiments of the present invention, the input / output interface sets a part of a plurality of data input / output (DQ) signals connected between a transmitting unit and a receiving unit into one group, and groups the patterns of the grouped DQ signals into a symbol lock pattern Can be used.

According to embodiments of the present invention, the input / output interface may use a voltage level applied to a data input / output (DQ) signal connected between a transmitting unit and a receiving unit as a symbol lock pattern.

According to embodiments of the present invention, the receiver stores a plurality of symbol lock patterns, converts the voltage level of the DQ signal received through the input / output interface to a digital signal, compares the converted digital signal with stored symbol lock patterns The symbol lock pattern can be detected.

According to another aspect of the present invention, there is provided a memory device including a command decoder for generating a write enable signal in response to a write command, a command decoder for generating a write enable signal in response to a clock signal, A sampler and a write FIFO for sequentially inputting and outputting a pattern and a write data burst, and a symbol lock pattern detector for finding the first data of the write data burst at the output of the sampler and write FIFO based on the write enable signal.

According to embodiments of the present invention, a memory device receives a clock signal, generates a first clock signal in accordance with even edges of the clock signal, and generates a second clock signal in accordance with the odd edges of the clock signal. And the sampler and write FIFO may serially output the sampler and the output of the write FIFO according to the first and second clock signals.

According to embodiments of the present invention, the symbol lock pattern detector stores a plurality of symbol lock patterns, detects a symbol lock pattern by comparing the output of the sampler and the write FIFO with the stored symbol lock patterns in response to the write enable signal , And the data latch signal can be generated in accordance with the detected symbol lock pattern.

According to embodiments of the present invention, the memory device may further comprise a data arrangement for outputting a write data burst in parallel at the output of the sampler and write FIFO in response to a data latch signal.

According to embodiments of the present invention, the memory device may include a three-dimensional memory array.

According to embodiments of the present invention, a three-dimensional memory array may be monolithically formed on at least one physical level of memory cells having active regions disposed on a silicon substrate.

According to embodiments of the present invention, the three-dimensional memory array includes a plurality of memory cells, and each of the plurality of memory cells may include a charge trap layer.

According to embodiments of the present invention, word lines and / or bit lines in a three-dimensional memory array may be shared between levels.

According to another aspect of the present invention, there is provided a memory device including: a memory for storing a plurality of symbol lock patterns transmitted as a plurality of data input / output (DQ) signals in accordance with a clock signal; And a write FIFO, a plurality of symbol lock patterns are stored, a symbol lock pattern is detected by comparing the outputs of the sampler and write FIFO with stored symbol lock patterns, a write enable signal is generated in accordance with the detected symbol lock patterns And a symbol lock pattern detector for finding the first data of the write data burst according to the write enable signal.

According to embodiments of the present invention, the symbol lock pattern detection section can generate the data latch signal based on the write enable signal.

According to another aspect of the present invention, there is provided a memory device including: a sampler for sequentially inputting and outputting a symbol lock pattern and a write data burst applied at a voltage level of a data input / output (DQ) A plurality of symbol lock patterns are stored, a voltage level of the DQ signal is converted into a digital signal, a symbol lock pattern is detected by comparing the converted digital signal with stored symbol lock patterns, And a symbol lock pattern detecting unit for finding the first data of the data burst.

According to embodiments of the present invention, the symbol lock pattern detector may further include an analog-to-digital converter for converting the voltage level of the DQ signal into a digital signal.

According to another aspect of the present invention, there is provided a symbol lock method including transmitting at least one first symbol lock pattern and a data burst in a transmitter, storing second symbol lock patterns in a receiver, And comparing the first symbol lock pattern and the second symbol lock pattern at the receiver, detecting a symbol lock pattern corresponding to the comparison result, and searching for the first data of the data burst according to the detected symbol lock pattern.

According to embodiments of the present invention, a symbol lock method sets a part of a plurality of data input / output (DQ) signals connected between a transmitting unit and a receiving unit into one group and outputs a pattern of grouped DQ signals as a first symbol It can be used as a rock pattern.

According to embodiments of the present invention, the symbol lock method may use a voltage level applied to a data input / output (DQ) signal connected between a transmitter and a receiver as a first symbol lock pattern.

According to embodiments of the present invention, the receiver may detect a symbol lock pattern by converting the voltage level of the DQ signal into a digital signal, and comparing the converted digital signal with the second symbol lock pattern.

A symbol lock method, a memory device, and an input / output interface according to embodiments of the present invention detect a symbol lock pattern in a preamble section or a symbol lock section before transmission of a data burst, and detect the first data of the data burst according to the detected symbol lock pattern It is possible to reduce the time required for the symbol lock and the complexity of the circuit.

1 is a diagram of a first example of a memory system including a memory device for performing a symbol lock method according to embodiments of the present invention.
2 is a timing diagram illustrating a symbol lock method performed in the memory device of FIG.
FIG. 3 is a first example of a block diagram of a memory device including the symbol lock pattern detecting unit of FIG. 1;
Figures 4 and 5 are block diagrams and timing diagrams illustrating the first lane sampler and write FIFO of Figure 3;
FIGS. 6 to 8 are block diagrams and timing diagrams illustrating the symbol lock pattern detection unit of FIG.
Figures 9 and 10 are block diagrams and timing diagrams illustrating the data arrangement of Figure 3;
11 is a second example of a block diagram of a memory device including the symbol lock pattern detecting unit of FIG.
12 is a timing diagram illustrating a symbol locking method performed in the memory device of FIG.
13 is a second example of a memory system including a memory device for performing a symbol lock method according to embodiments of the present invention.
Figs. 14 and 15 are views for explaining the memory device of Fig.
16 and 17 are diagrams illustrating a memory system including a memory controller that performs a symbol lock method according to embodiments of the present invention.
18 is a view for explaining a memory device performing a symbol lock method according to embodiments of the present invention.
19 is a block diagram illustrating an example of application of a memory device performing a symbol lock method according to embodiments of the present invention to a mobile system.
20 is a block diagram illustrating an example of application of a memory device performing a symbol lock method according to embodiments of the present invention to a computing system.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. The present invention is capable of various modifications and various forms, and specific embodiments are illustrated and described in detail in the drawings. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for similar elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are enlarged or reduced from the actual dimensions for the sake of clarity of the present invention.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a part or a combination thereof is described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

The DRAM recognizes a data burst received from a write command as a data input / output (DQ) signal after a write latency (WL) as a symbol and performs a write operation. The symbol actually refers to a write data burst. The DRAM can accept the DQ data received at the tDQSS time after the write latency (WL) as the start of the symbol to ensure the write operation. The tDQSS time is defined as the delay time from the write latency (WL) to the first rising edge of the data strobe (DQS) signal. A symbol is composed of a plurality of bit data, and one bit data interval may be called a unit interval (UI).

DRAM dominates the memory controller that controls DRAM operation. At the input / output (IO) interface between the memory controller and the DRAM, the DRAM can perform symbol locking using tDQSS time to find the first UI in the symbol of the write data burst provided from the memory controller.

As the speed of the IO interface increases, the DRAM may experience clock skew in the clock path associated with the command and the clock path associated with the data. Thus, in a high speed interface, a DRAM may be difficult to use a symbol lock method that utilizes tDQSS time correlated with a clock signal.

Embodiments of the present invention propose a DRAM that performs a symbol lock method regardless of a clock signal. The symbol lock method detects a predetermined symbol lock pattern between the memory controller and the DRAM and detects the first data of the data burst according to the detected symbol lock pattern.

1 is a diagram of a first example of a memory system including a memory device for performing a symbol lock method according to embodiments of the present invention.

Referring to FIG. 1, a memory system 100 may include a memory controller 110 and a memory device 120. Memory system 100 may allocate program code, which is a collection of instructions and data, to memory device 120 to execute an application program by the processor. The memory controller 110 may be embedded in the processor and may be implemented as a separate chip from the processor and coupled to the processor. The memory controller 110 may support a read and / or write memory transaction to access the memory device 120.

According to an embodiment, the memory controller 110 may perform memory transactions by other chipsets constituting the system 100 other than the processor. For example, when the system 100 is configured as a computing device, the chipset may include basic input / output system firmware (BIOS firmware), keyboards, mice, storage devices, network interfaces, (IC) package or chip that couples components such as a Power Management Integrated Circuit (PMIC) or the like to the processor.

The memory controller 110 may be coupled to the memory device 120 via a bus 130. The command CMD, the address ADDR, the clock signal CLK, the data strobe signal DQS and the data DQ output from the memory controller 110 are transferred to the memory device 120 through the bus 130 . In the bus 130, the command bus and the address bus are implemented as one line CA so that the command CMD and the address ADDR can be transmitted in a time series. The data DQ output from the memory device 120 in response to the command CMD of the memory controller 110 may be transmitted to the memory controller 110 via the bus 130. [

The bus 130 is connected to a line 130 for transmitting control signals such as a clock enable signal CKE, a row address strobe signal / RAS, a column address signal / CAS, a chip select signal / CS, May be included.

The memory device 120 may be comprised of various memory devices that provide addressable storage locations for the memory controller 110 to read and / or write data. The memory device 120 may be implemented as, for example, DRAM devices (Dynamic Random Access Memory devices), SDRAM devices (Synchronous DRAM devices), and DDR (Double Data Rate) SDRAM devices.

The memory controller 110 may access the memory device 120 in response to a read and / or write memory transaction by the processor. The operation of accessing the memory device 120 may be affected by memory read latency and memory write latency.

In general, a memory read latency is a time when the memory controller 110 requests the memory device 120 to retrieve and retrieve data and the memory device 120 provides the read data requested to the memory controller 110 The time between the time points when the data is read. The memory write latency is a time between the time when the memory controller 110 requests the memory device 120 to write the write data and the time when the memory device 120 notifies the memory controller 110 that the writing of the write data is completed . The memory controller 110 and the memory device 120 can operate as a transfer unit or a reception unit for transmitting and receiving data through the DQ bus 130. In view of the memory read latency and the memory write latency,

The memory device 120 includes a memory cell array 122 and a symbol lock pattern detector 124. The memory cell array 122 may include a plurality of memory cells arranged in rows and columns. The memory cell may consist of one access transistor and one storage capacitor. The memory cells are arranged in an inter-sectored arrangement, one at each intersection of the matrix consisting of word lines and bit lines. Write data provided from the memory controller 110 may be written into the memory cells of the memory cell array 122. [

According to an embodiment, the memory cell array 122 may be implemented as a three-dimensional (3D) memory array. The 3D memory array is monolithically formed on at least one physical level of memory cell arrays having an active area disposed on a silicon substrate and circuits associated with operation of the memory cells on the substrate or in the substrate. The term " low " means that layers of each level constituting the array are stacked directly on top of the layers of each lower level of the array.

According to an embodiment, the 3D memory array includes vertical NAND strings arranged in a vertical direction such that at least one memory cell is located above another memory cell. The at least one memory cell may include a charge trap layer.

U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and U.S. Patent Application Publication No. 2011/0233648 disclose that a 3D memory array is constructed at multiple levels and word lines and / Which are incorporated herein by reference in their entirety as those that describe suitable configurations for a 3D memory array in which bit lines are shared between levels.

The symbol lock pattern detection unit 124 may perform an operation of searching for the start point of a write data burst provided from the memory controller 110 connected to the multi-lane IO interface. The multi-lane IO interface is an interface for transmitting a symbol lock pattern through a group among a plurality of DQ data lines constituting the DQ bus 130. [ The symbol lock pattern detecting section 124 can detect the symbol lock pattern in response to the write enable signal WR_EN generated from the write command in the symbol lock interval of the clock signal CLK. The symbol lock pattern detector 124 can find the first UI of the write data burst according to the detected symbol lock pattern.

According to an embodiment, the symbol lock pattern detector 124 detects a plurality of symbol lock patterns during a preamble period of a clock signal in a multi-lane IO interface, and outputs a write enable signal WR_EN in response to the detected symbol lock patterns. Lt; / RTI > The symbol lock pattern detecting section 124 can find the first UI of the write data burst based on the write enable signal WR_EN according to the detected symbol lock patterns.

According to an embodiment, the symbol lock pattern detector 124 may perform an operation of searching for a start point of a write data burst provided from a memory controller 110 connected to a multi-signaling IO interface. The multi-signaling IO interface is an interface for transmitting a symbol lock pattern using a voltage level applied to one of a plurality of DQ data lines constituting the DQ bus 130.

2 is a timing diagram illustrating a symbol lock method performed in the memory device of FIG.

Referring to Figure 2 in conjunction with Figure 1, the memory device 120 may receive a write command WR that is synchronized with the clock signal CLK. The write data burst WR_DATA may be set to be received after the write latency WL from the write command WR. The write data burst WR_DATA may be received as a plurality of DQ data through the DQ bus 130. [ DQ data corresponding to the burst length BL can be received as the write data burst WR_DATA.

In this embodiment, the write data bursts WR_DATA and BL0-BL13 corresponding to BL = 14 received in the three DQ data DQ0, DQ1 and DQ2 will be described for the sake of simplifying the illustration. According to the embodiment, the burst length BL may be set to various values such as 8, 16, 32, and the like.

The symbol lock method for finding the first UI that is the beginning of the write data burst (WR_DATA) can be applied to a multi-lane IO interface. The multi-lane IO interface is an interface that sets a part of a plurality of DQ data into one group and uses patterns of grouped DQ data as symbol lock patterns.

According to an embodiment, the symbol lock method may be applied to a multi-signaling IO interface that utilizes voltage levels applied to one DQ data line as symbol lock patterns. In the multi-signaling IO interface, the voltage level of the DQ data line is converted into a digital signal through the analog-to-digital converter, and the symbol lock pattern can be detected based on the converted digital signal.

As an example of the multi-lane IO interface, data of DQ0, DQ1, and DQ2 may be set as one group. Lines to which DQ0, DQ1, and DQ2 data are respectively transmitted are referred to as LANE_A, LANE_B, and LANE_C lanes, and LANE_A, LANE_B, and LANE_C lanes can constitute a multi-lane. According to an embodiment, the multi-lane may be composed of a combination of lines through which DQ data other than DQ0, DQ1 and DQ2 data are transmitted.

The data BL0 to BL13 corresponding to the write data burst WR_DATA can be received in the multi lanes LANE_A, LANE_B and LANE_C after the write latency WL from the write command WR. During the write latency (WL), symbol lock patterns may be transmitted in multi lanes (LANE_A, LANE_B, LANE_C). The symbol lock pattern may be composed of various combinations of data bits transmitted in a multi-lane (LANE_A, LANE_B, LANE_C).

For example, if the data bits transmitted in the multi lanes (LANE_A, LANE_B, and LANE_C) are 0-0-1, the symbol lock pattern A can be defined. When the data bits transmitted in the multi lanes (LANE_A, LANE_B, LANE_C) are 0-1-0, it is determined as a B pattern, 0-1-1 is set as a C pattern, 1-0-0 is set as a D pattern , 1-0-1, and an F pattern for 1-1-0, respectively.

Symbol lock patterns (AF) each is transmitted to the write burst data (BL0-BL13) is before the transmission, the symbol lock interval (T _{SYMBOL _ LOCK)} multi-lane (LANE_A, LANE_B, LANE_C) while for the (WR_DATA) . BL0-BL13 write data can be transmitted in multi-lane (LANE_A, LANE_B, LANE_C) according to the clock signal (CLK) edge.

Clock signal (CLK) may have a preamble section (T _PREAMBLE) and the symbol lock interval (T _{SYMBOL LOCK _)} before BL0-BL13 write data transfer. Symbol lock interval (T _{SYMBOL _ LOCK)} can be defined as the period of until the preamble period (T _PREAMBLE) is a write enable signal (WR_EN) and enabled after the write data (BL0-BL13) of a clock signal (CLK) transmitted have. According to the embodiment, the preamble section (T _PREAMBLE) and the symbol lock interval (T _{SYMBOL LOCK _)} both may be collectively referred to as the preamble section.

Symbol lock interval (T _{SYMBOL _ LOCK)} in a symbol lock when the pattern symbol lock pattern is transferred to the multi-lane (LANE_A, LANE_B, LANE_C), by the detector 124 is detected, the A pattern, the sixth clock signals from the detection point, (LANE_A, LANE_B, and LANE_C) synchronized with the clock CLK edge can be determined as the first UI (BL0) of the write data burst WR_DATA. When the B symbol lock pattern is detected by the symbol lock pattern detection unit 124, the data synchronized with the fifth clock signal (CLK) edge from the detection time is determined as the first UI (BL0) of the write data burst WR_DATA, When the symbol lock pattern is detected, the data synchronized with the fourth clock signal (CLK) edge from the detection point can be judged as the first UI (BL0) of the write data burst WR_DATA.

When the D symbol lock pattern is detected by the symbol lock pattern detection unit 124, data synchronized with the third clock signal (CLK) edge from the detection point is detected as the second clock signal (CLK ) And an F symbol lock pattern are detected, data synchronized with the first clock signal (CLK) edge from the detection point can be judged as the first UI (BL0) of the write data burst WR_DATA.

In this embodiment it shows a method for determining a first UI (BL0) of the write data burst (WR_DATA) in accordance with the AF lock symbol pattern of the symbol lock interval (T _{SYMBOL LOCK _).} According to the embodiment, the first UI BL0 of the write data burst WR_DATA can be determined using symbol lock patterns other than the AF symbol lock patterns.

FIG. 3 is a first example of a block diagram of a memory device including the symbol lock pattern detecting unit of FIG. 1;

3, the memory device 120 is an enable signal (WR_EN) written from the write command (WR) is generated, and the symbol lock interval (T _{SYMBOL _ LOCK)} the detected symbol lock pattern, and detecting a symbol from the lock The data latch signal PDSD can be generated based on the pattern. The memory device 120 includes a clock generator 310, a command / address sampler 320, a command decoder 330, a sampler and a write-in FIFO (First In First Out) 340, a data arrangement unit 350, And a pattern detector 124.

The clock generator 310 may receive the clock signal CLK to generate the first clock signal CLK_E and the second clock signal CLK_O. The clock generator 310 receives the data strobe signal DQS instead of the clock signal CLK and outputs the first clock signal CLK_E and the second clock signal CLK_E based on the data strobe signal DQS, (CLK_O).

The first clock signal CLK_E may be generated as a signal that transitions from the even edge of the clock signal CLK to a logic high and is toggled per edge. The second clock signal CLK_O may be generated as a signal that transitions from the odd edge of the clock signal CLK to a logic high and toggles on an edge-by-edge basis. 5, the first clock signal CLK_E is synchronized with the even edges (0, 2, 4, ...) of the clock signal CLK according to the clock signal CLK And the second clock signal CLK_O may be a signal generated according to the clock signal CLK in accordance with the odd edges 1, 3, 5, ... of the clock signal CLK.

According to an embodiment, as in the second example (CASE 2) shown in FIG. 5, the first clock signal CLK_E is synchronized with the odd edges 1, 3, 5, ... of the clock signal CLK, And the second clock signal CLK_O may be a signal generated according to the clock signal CLK in accordance with the even edges 0, 2, 4, ... of the clock signal CLK .

The command / address sampler 320 can separate the command CMD and the address from the command / address CA received in a time-series manner. The command CMD is provided to the command decoder 330, and the address can be provided to the address decoder through the address register. The address decoder may activate the word lines and bit lines of the memory cell array 122 (FIG. 1) corresponding to the address. BL_C [2n-1: 0], BL_B [2n-1: 0], and BL_C [2n-1: 0] of the data arrangement unit 350 into the memory cells connected to the activated word line and bit lines, ) Can be written.

The command decoder 330 may decode the command CMD and generate control signals corresponding to the command CMD. The command decoder 330 can generate the write enable signal WR_EN in a logic high in response to the write command WR, as shown in Fig. The write enable signal WR_EN may be provided to the sampler and write FIFO 340.

The sampler and write FIFO 340 includes first to third lane samplers and write FIFOs 341, 342, 343 controlled by first and second clock signals (CLK_E, CLK_O) and a write enable signal WR_EN, . ≪ / RTI >

The first lane sampler and write FIFO 341 are connected to a first lane LANE_A through which DQ0 data is transferred and are responsive to the write enable signal WR_EN and the first and second clock signals CLK_E and CLK_O The first write FIFO output A_E [n-1: 0] and the second write FIFO output A_O [n: 0] can be output based on the DQ0 data.

The second lane sampler and write FIFO 342 are coupled to a second lane LANE_B to which DQ1 data is transferred and are responsive to the write enable signal WR_EN and the first and second clock signals CLK_E and CLK_O The first write FIFO output B_E [n-1: 0] and the second write FIFO output B_O [n: 0] can be output based on the DQ1 data.

The third lane sampler and write FIFO 343 are connected to a third lane LANE_C to which DQ2 data is transferred and are responsive to the write enable signal WR_EN and the first and second clock signals CLK_E and CLK_O The first write FIFO output C_E [n-1: 0] and the second write FIFO output C_O [n: 0] can be output based on the DQ2 data.

The symbol lock pattern detector 124 may store a plurality of symbol lock patterns. The symbol lock pattern detection unit 124 stores the first write FIFO outputs A_E [k], B_E [k], and C_E [k] output from the first to third lane samplers and the write FIFOs 341 to 343 The symbol lock patterns can be compared with each other, and the symbol lock pattern corresponding to the comparison result can be detected. The symbol lock pattern detector 124 may generate the data exchange signal DATA_SWAP and the data latch signal PDSD according to the detected symbol lock pattern.

The data sorting unit 350 receives the outputs A_E [n-1: 0], A_O [n: 0] of the first sampler and the write FIFO 341 in response to the data exchange signal DATA_SWAP and the data latch signal PDSD ]) Can be arranged and output in a parallel fashion. The data arrangement unit 350 receives the outputs B_E [n-1: 0], B_O [n: 0] of the second sampler and write FIFO 342 in response to the data exchange signal (DATA_SWAP) and the data latch signal PDSD ], And parallel output, and outputs (C_E [n-1: 0], C_O [n: 0]) of the third sampler and the write FIFO 343 are aligned and output in parallel.

Figures 4 and 5 are diagrams illustrating the first lane sampler and the write FIFO of Figure 3; FIG. 4 is a circuit diagram illustrating a first lane sampler and a write FIFO, and FIG. 5 is a timing diagram illustrating the operation of the sampler 410 of FIG.

The configuration of the first lane sampler and the write FIFO 341 of FIG. 4 may be the same as the configuration of the second and third lane sampler and write FIFOs 342 and 343 of FIG. 3, respectively. The operation description of the first lane sampler and the write FIFO 341 can be equally applied to the second and third lane sampler and write FIFOs 342 and 343.

4, the first lane sampler and write FIFO 341 may include a sampler 410, a logic circuit 420, and a write FIFO 430. The sampler 410 includes first and second samplers 411 and 412 receiving the DQ0 data of the first lane LANE_A in response to the first clock signal CLK_E and the second clock signal CLK_O .

The first sampler 411 may latch the DQ0 data and output it to the first sampler output SA_E in response to the rising edge of the first clock signal CLK_E. The second sampler 412 may latch the DQ0 data and output the second sampler output SA_O in response to the rising edge of the second clock signal CLK_O.

The sampler 410 is responsive to the rising edge of the first clock signal CLK_E, such as x-B-D-F-BL1-BL3- ..., as in the first example (CASE 1) BL-BL11-BL13, and outputs the first sampler output SA_E in response to the rising edge of the second clock signal CLK_O. -BL10-BL12 to output the second sampler output SA_O. x means unknown data. It can be seen that the first and second sampler outputs SA_E and SA_O are output as a pair of x invalid data and A valid data according to the first clock signal CLK_E or the second clock signal CLK_O edge. x invalid data may be disadvantageous in sorting the serial data into the parallel data in the data arranging unit 350 (FIG. 3).

The sampler 410 is responsive to the rising edge of the first clock signal CLK_E, as in the second example (CASE 2) shown in FIG. 5, to generate a signal x-A-C-E-BL0-BL2- ... -BL-BL10-BL12 and outputs the first sampler output SA_E in response to the rising edge of the second clock signal CLK_O. -BL9-BL11-BL13 to output the first sampler output SA_O. It can be seen that the first and second sampler outputs SA_E and SA_O are A and B valid data output in pairs according to the first clock signal CLK_E or the second clock signal CLK_O edge. The fact that the valid data A and B are outputted in pairs in correspondence with the first clock signal CLK_E or the second clock signal CLK_O is advantageous in arranging the serial data into the parallel data in the data arranging unit 350 .

The logic circuit 420 may logically multiply the write enable signal WR_EN and the first clock signal CLK_E to generate a write enable clock signal WR_EN_CLK. The write enable clock signal WR_EN_CLK is provided to the write FIFO 430 and may be operated to latch the first and second sampler outputs SA_E and SA_O.

The write FIFO 430 sequentially latches the first sampler output SA_E and the second sampler output SA_O in response to the first clock signal CLK_E and the write enable clock signal WR_EN_CLK, have. Write FIFO 430 may include a first write FIFO 440 that latches a first sampler output SA_E and a second write FIFO 450 that latches a second sampler output SA_O.

The first write FIFO 440 sequentially latches the first sampler output SA_E in response to the write enable clock signal WR_EN_CLK to generate a first write FIFO output A_E [n-1: 0], n = BL / 2, and BL = 14). The second write FIFO 450 is configured such that the write FIFO 430 sequentially latches the second sampler output SA_O in response to the first clock signal CLK_E and the write enable clock signal WR_EN_CLK to generate a second write FIFO output (A_O [n: 0]).

The first write FIFO 440 may include a plurality of serially connected flip-flops 441, 442, 443 that sequentially latch a first sampler output SA_E. The first flip-flop 441 may latch and output the first sampler output SA_E in response to the write enable clock signal WR_EN_CLK.

The output (A_E [n-1]) of the first flip-flop 441 is serially supplied to serially connected flip-flops in response to the write enable clock signal WR_EN_CLK, and the third flip- 1] of the second flip-flop 442 and output it to the output A_E [0] of the third flip-flop 443 in response to the enable clock signal WR_EN_CLK.

The first write FIFO 440 serializes the first write FIFO output A_E [n-1: 0] through flip-flops 441, 442, and 443 that sequentially latch the first sampler output SA_E Can be output. The output (A_E [k]) that is output from the first write output symbols lock interval (T _{SYMBOL LOCK _)} of the FIFO (440) may be provided to lock the symbol pattern detector 124 (FIG. 3).

The second write FIFO 450 may include a plurality of serially connected flip-flops 451, 452, 453, 454 that sequentially latch a second sampler output SA_O. The first flip-flop 451 may latch and output the second sampler output SA_O in response to the first clock signal CLK_E.

The second flip-flop 452 of the second write FIFO 450 may latch and output the output A_O [n] of the first flip-flop 451 in response to the write enable clock signal WR_EN_CLK. The output (A_O [n-1]) of the second flip-flop 452 is serially provided in series with the flip-flops in response to the write enable clock signal WR_EN_CLK, and the fourth flip- 1] of the third flip-flop 453 and output it to the output A_O [0] of the fourth flip-flop 454 in response to the enable clock signal WR_EN_CLK.

The second write FIFO 450 serially connects to the second write FIFO output A_O [n: 0] via flip-flops 451, 452, 453, and 454 that sequentially latch the second sampler output SA_O Can be output.

The first lane sampler and write FIFO 341 described in FIGS. 4 and 5 receives the DQ0 data and outputs the DQ0 data in response to the first and second clock signals CLK_E and CLK_O and the write enable clock signal WR_EN_CLK 1 write FIFO output A_E [n-1: 0] and the second write FIFO output A_O [n: 0] can be serially output. Likewise, the second lane sampler and write FIFO 342 (FIG. 3) receives the DQ1 data and generates a first write in response to the first and second clock signals CLK_E, CLK_O and the write enable clock signal WR_EN_CLK The FIFO output B_E [n-1: 0] and the second write FIFO output B_O [n: 0] can be serially output. The third lane sampler and write FIFO 343 (FIG. 3) receives the DQ2 data and provides a first write FIFO output (FIG. 3) in response to the first and second clock signals CLK_E and CLK_O and the write enable clock signal WR_EN_CLK C_E [n-1: 0]) and the second write FIFO output (C_O [n: 0]).

Second lane the symbol lock period of the first write FIFO output (T _{SYMBOL _ LOCK)} output (B_E [k]) outputted from the sampler, and the write FIFO (342) provides a symbol lock pattern detector 124 (FIG. 3) . The third lane the symbol lock period of the first write FIFO output (T _{SYMBOL _ LOCK)} output (C_E [k]) outputted from the sampler, and the write FIFO (343) may be provided at a symbol lock pattern detector 124 . The symbol lock pattern detection section 124 detects the symbol patterns A_E [k] of the first lane sampler and the write FIFO 341, the outputs B_E [k] of the second lane sampler and the write FIFO 342, And the output (C_E [k]) of the write FIFO 343 to determine whether it matches the stored symbol lock patterns.

6 to 8 are diagrams for explaining the symbol lock pattern detecting unit 124 of FIG. FIG. 6 shows a block diagram of the symbol lock pattern detector 124, and FIGS. 7 and 8 are timing diagrams illustrating the operation of the symbol lock pattern detector 124. Referring to FIG.

Referring to FIG. 6, the symbol lock pattern detector 124 may include a symbol lock pattern storage unit 610 and a comparison unit 620. The symbol lock pattern storage unit 610 may store a plurality of symbol lock patterns. The symbol lock pattern storage unit 610 may store A-F symbol lock patterns set to data bits transmitted in the multi lane (LANE_A, LANE_B, LANE_C) described in FIG.

The comparator 620 outputs the second write FIFO outputs A_E [k], B_E (k), and the second write FIFO outputs A_E [k] and B_E in response to the first clock signal CLK_E in the first through third lane samplers and the write FIFOs 341-343 [k], C_E [k]) and the symbol lock pattern stored in the symbol lock pattern storage unit 610 can be compared. The comparing unit 620 can detect a matching symbol lock pattern as a result of the comparison.

According to an embodiment, the comparator 620 may compare the second write FIFO outputs A_O (FIG. 3) output from the first through third lane samplers and the write FIFOs 341-343 (FIG. 3) in response to the second clock signal CLK_O. [k], B_O [k], and C_O [k]) with the symbol lock pattern stored in the symbol lock pattern storage unit 610 and detect the symbol lock pattern.

As a result of comparison, the comparator 620 can generate the data exchange signal (DATA_SWAP) and the data latch signal (PDSD) based on the detected symbol lock pattern. The data exchange signal DATA_SWAP and the data latch signal PDSD may be provided to the data arrangement unit 350 (FIG. 3). The data sorting unit 350 receives the outputs A_E [n-1: 0], A_O [0] of the first sampler and the write FIFO 341 (FIG. 3) in response to the data exchange signal DATA_SWAP and the data latch signal PDSD, n: 0]) can be arranged and output in a parallel fashion. The data arrangement unit 350 receives the outputs B_E [n-1: 0], B_O [n: 1] of the second sampler and write FIFO 342 (FIG. 3) in response to the data exchange signal DATA_SWAP and the data latch signal PDSD, (n: 0) and aligns the outputs C_E [n-1: 0] and C_O [n: 0] of the third sampler and the write FIFO 343 Can be output.

The data exchange signal DATA_SWAP is generated by the first sampler output SA_E and the second sampler output SA_O as the first example CASE 1 described in FIG. The first sampler output SA_E and the second sampler output SA_O are not the same as the first and second sampler outputs SA_E and SA_O, respectively, as in the second example (CASE 2) of FIG. 5, 2 < / RTI > clock signals CLK_E, CLK_O. Because the first sampler output SA_E and the second sampler output SA_O including the uncertain data x in the first example (CASE 1) of FIG. 5 have the data arrangements 350, 3). ≪ / RTI >

The data latch signal PDSD may be generated according to the detection result of the symbol lock pattern of the comparator 620. The data latch signal PDSD may be generated one cycle later of the first clock signal CLK_E when the symbol lock pattern is detected as F-D-B, as shown in FIG. The data latch signal PDSD may be generated one cycle later than the first clock signal CLK_E when the symbol lock pattern is detected as E-C-A, as shown in FIG. This is consistent with the operation of determining the first UI of the write buffer data WR_DATA according to the A-F symbol lock patterns by the symbol lock pattern detector 124 described in FIG.

Fig. 7 is described as an operation corresponding to the first example (CASE 1) described in Fig. Referring to FIG. 7, the first sampler output SA_E and the second sampler output SA_O are output as a pair of invalid data x and valid data a corresponding to the first and second clock signals CLK_E and CLK_O. . A data exchange signal (DATA_SWAP) for outputting the valid data a-b pairs corresponding to the first and second clock signals (CLK_E, CLK_O) may be generated. The data exchange signal DATA_SWAP is activated to a logic high at the rising edge of the second clock signal CLK_E determined as the first UI (BL0) of the write data burst WR_DATA in accordance with the symbol lock pattern detection result of the comparator 620 . The data latch signal PDSD may be generated one cycle later of the first clock signal CLK_E in accordance with the detected symbol lock pattern F-D-B.

Fig. 8 is described as an operation corresponding to the second example (CASE 2) described in Fig. Referring to FIG. 8, since the first sampler output SA_E and the second sampler output SA_O are output in pairs of valid data ab corresponding to the first and second clock signals CLK_E and CLK_O, DATA_SWAP) is disabled to logic low. The data latch signal PDSD may be generated one cycle later of the first clock signal CLK_E in accordance with the detected symbol lock pattern E-C-A.

9 and 10 are views for explaining the data arranging unit of FIG. 9 is a circuit diagram of the data arrangement unit, and Fig. 10 is an operation timing diagram of the data arrangement unit.

The data arrangement unit 350a of FIG. 9 includes first and second write FIFO outputs A_E [n-1: 0] and A_E [n-1: 0] output based on the DQ0 data in the first lane sampler and write FIFO 341, (A_O [n: 0]) are described. The operation of the data arrangement unit 350a is performed by the first write FIFO outputs B_E [n-1: 0] and the second write FIFO outputs The first write FIFO outputs C_E [n-1: 0] and the second write FIFO outputs C_E [n: 0] output based on the DQ2 data in the third lane sampler and the write FIFO 343, The same can be applied to the outputs C_O [n: 0].

9, the data arranging unit 350a includes first and second write FIFO outputs A_E [n-1: 0] and A_E [n-1: 0] in response to a data exchange signal DATA_SWAP and a data latch signal PDSD, The output A_O [n: 0] can be aligned and latched and output as the DQ0 write data BL_A [2n-1: 0] of the first lane LANE_A. The data sorting unit 350a may include a first sorting unit 910 and a second sorting unit 920. [

The first arranging unit 910 selectively outputs the first write FIFO output A_E [n-1: 0] and the second write FIFO output A_O [n: 0] in response to the data exchange signal DATA_SWAP And a plurality of selectors 911-914 that perform the same.

The first selector 911 can select one of the first write FIFO output A_E [0] and the second write FIFO output A_O [0] in response to the data exchange signal DATA_SWAP. The second selector 912 can select one of the first write FIFO output A_E [1] and the second write FIFO output A_O [1] in response to the data exchange signal DATA_SWAP. The third selector 913 selects one of the first write FIFO output A_E [n-1] and the second write FIFO output A_O [n-1] in response to the data exchange signal DATA_SWAP, can do. The fourth selector 914 can select one of the first write FIFO output A_E [n-1] and the second write FIFO output A_O [n] in response to the data exchange signal DATA_SWAP have.

The first arranging unit 910 receives the first write FIFO outputs A_E [n-1: 0] and the second write FIFO outputs A_O [n: 0] in response to the data exchange signal DATA_SWAP, Can be output in pairs corresponding to the first and second clock signals (CLK_E, CLK_O) without data (x). As shown in Fig. 10, the first alignment unit 910 includes BL1, BL3, ... , A first write FIFO output (A_E [n-1: 0]) for outputting BL9, BL11, and BL13 data, and outputs BL0, BL2, ... , And the second write FIFO output (A_O [n-1: 0]) from which BL8, BL10, and BL12 data are output.

The second arranging unit 920 outputs the output of the selectors 911-914 of the first arranging unit 910 as DQ0 write data BL_A [n-1: 0] in response to the data latch signal PDSD Flip-flops 921-924.

The first flip-flop 921 outputs the first write FIFO output A_E [0] or the second write FIFO output A_O [0] output from the first selector 921 in response to the data latch signal PDSD. Can be output as BL_A [0] write data. The second flip-flop 922 outputs either the first write FIFO output A_E [1] or the second write FIFO output A_O [1] output from the second selector 922 in response to the data latch signal PDSD. Can be output as BL_A [1] write data. The third flip-flop 923 outputs the first write FIFO output A_E [n-1] or the second write FIFO output A_O [n-1] output from the third selector 923 in response to the data latch signal PDSD -1] as the BL_A [n-1] write data, and the fourth flip flop 924 outputs the first write FIFO output (FIG. 9B) output from the fourth selector 924 in response to the data latch signal PDSD A_E [n-1]) or the second write FIFO output (A_O [n]) as BL_A [n-1] write data.

The second arranging unit 920 outputs the first write FIFO outputs A_E [n-1] selected in the first arranging unit 910 to the DQ0 write data BL_A [n-1] in response to the data latch signal PDSD. 1: 0], and outputs the second write FIFO outputs A_O [n-1] selected by the first arranging unit 910 as DQ0 write data BL_A [n-1: 0] It can output in parallel. Accordingly, the data sorting unit 350a can output the DQ0 write data BL_A [2n-1: 0] corresponding to the write data bursts WR_DATA and BL0-BL13 in parallel. DQ0 write data BL_A [2n-1: 0] may be written to the memory cell array 122 (Fig. 1).

10, the first write FIFO outputs A_E [n-1] and the second write FIFO outputs A_O [n: 0] correspond to the data latch signal PDSD in response to the data latch signal PDSD. , BL9, BL11, BL13 data and BL0, BL2, ... , And DQ0 write data BL_A [2n-1: 0] that are output in parallel as data BL8, BL10, and BL12.

The first write FIFO outputs A_E [n-1: 0] and the second write FIFO outputs A_O [n: 0] output based on the DQ0 data are generated by the data arrangement unit 350a of FIG. Can be output in parallel to the DQ0 write data BL_A [2n-1: 0]. Similarly, the first write FIFO outputs B_E [n-1: 0] and the second write FIFO outputs B_O [n: 0] output based on the DQ1 data are DQ1 write data BL_B [ 1 [0]) and the second write FIFO outputs C_O [n: 0] output in parallel based on the DQ2 data Can be output in parallel by the DQ2 write data BL_C [2n-1: 0].

11 is a second example of a block diagram of a memory device including the symbol lock pattern detecting unit of FIG. The memory device 120a of FIG. 11 is different from the memory device 120 of FIG. 3 in that it detects a plurality of symbol lock patterns in the preamble interval T _PREAMBLE , And generates a signal WR_EN. Also, the memory device 120a differs in that it generates the data latch signal PDSD based on the write enable signal WR_EN. Memory device 120 of Figure 3 is the enable signal (WR_EN) written from the write command (WR) is generated, and the symbol lock interval (T _{SYMBOL _ LOCK)} detecting a symbol lock pattern, and based on the detected symbol lock pattern from Thereby generating a data latch signal PDSD.

Referring to FIG. 11, the memory device 120a may include a clock generating unit 310a, a first clock operating unit 1100, and a second clock operating unit 1200. FIG. The clock generating unit 310a generates a first clock signal CLK_E generated according to an even clock edge based on the clock signal CLK or the data strobe signal DQS in the same manner as the clock generating unit 310 of FIG. And the second clock signal CLK_O generated according to the odd clock edge.

The first clock operating part 1100 is a write data path operated according to the first clock signal CLK_E and the second clock operating part 1200 is a write data path operated according to the second clock signal CLK_O. . The first clock operating unit 1100 and the second clock operating unit 1200 may be configured substantially the same. The description of the first clock operating portion 1100 and the operation description of the first clock operating portion 1100 may be applied to the second clock operating portion 1200 in order to avoid duplication of explanation.

The first clock operation unit 1100 may include a sampler and a write FIFO 340a, a data alignment unit 920a, and a symbol lock pattern detection unit 124a. The sampler and write FIFO 340a includes a sampler 410a and a write FIFO 430a and may be configured similar to the sampler 410 and write FIFO 430 described in FIG. The sampler and write FIFO 340a receives the DQ data in response to the first clock signal CLK_E and outputs the sampler outputs SA and SB and outputs the sampler outputs SA , SB) and output the write FIFO outputs (FC, FD).

The symbol lock pattern detection unit 124a may include a write enable signal generation unit 1120 and a data latch signal generation unit 1140. [ The write enable signal generator 1120 includes first to third pattern detectors 1122, 1124 and 1126 and outputs the outputs of the first to third pattern detectors 1122, 1124 and 1126, And generate the enable signal WR_EN.

The second pattern detector 1124 detects a C or D symbol lock pattern, and the third pattern detector 1126 detects an E or F symbol lock pattern. The first pattern detector 1122 detects an A or B symbol lock pattern, the second pattern detector 1124 detects a C or D symbol lock pattern, As shown in FIG. The data latch signal generator 1140 may generate a data latch signal PDSD that controls the operation of the data aligner 920a based on the write enable signal WR_EN.

The data sorting unit 920a may be configured to be substantially similar to the second sorting unit 920 described in FIG. The data arranging unit 920a may parallel output the write FIFO outputs FC and FD to the data arranging outputs AE and AF in response to the data latch signal PDSD.

12 is a timing diagram illustrating a symbol locking method performed in the memory device of FIG.

Referring to FIG. 12, a first clock signal CLK_E is generated according to the even clock edge of the clock signal CLK, and a second clock signal CLK_O is generated according to the odd clock edge. In response to the first clock signal CLK_E, the output A of the sampler 410a is x-B-D-F-BL1-BL3- ... -BL9-BL11-BL13 and the output B of the sampler 410a is x-A-C-E-BL0-BL2- ... -BL8-BL10-BL12.

The symbol lock pattern detector 124a can detect the symbol lock pattern in the preamble period T _PREAMBLE of the clock signal CLK. In the symbol lock pattern detection section 124a, the first pattern detection section 1122 detects the B symbol lock pattern, the second pattern detection section 1124 detects the D symbol lock pattern, and the third pattern detection section 1126 detects F Thereby detecting a symbol lock pattern. The symbol lock pattern detector 124a generates a write enable signal WR_EN corresponding to the detected B, D, and F symbol lock pattern intervals. The symbol lock pattern detector 124a generates a data latch signal PDSD based on the write enable signal WR_EN and provides the data latch signal PDSD to the data aligner 920a.

The write FIFO 430a sequentially latches the outputs SA and SB of the sampler 410a based on the write enable signal WR_EN and outputs the write FIFO outputs FC and FD. The data arranging unit 920a outputs the write FIFO outputs FC and FD in parallel to the data arranging outputs AE and AF in response to the data latch signal PDSD.

13 is a second example of a memory system including a memory device for performing a symbol lock method according to embodiments of the present invention.

Referring to FIG. 13, the memory system 100a is connected to the memory controller 110 and the memory device 1300 via a multi-signaling IO interface. The multi-signaling IO interface is an interface for transmitting a symbol lock pattern using a voltage level applied to one of a plurality of DQ data lines constituting the DQ bus 130. The memory device 1300 differs from the memory device 120 of FIG. 1 in that it includes an analog-to-digital converter 1312 in the symbol lock pattern detector 1310.

Figs. 14 and 15 are views for explaining the memory device of Fig. 14 is a block diagram constituting the memory device 1300, and Fig. 15 is a diagram for explaining the operation of the symbol lock pattern detecting section 1312 in the memory device 1300. Fig.

14, the memory device 1300 includes a clock generator 310, a command / address sampler 320, a command decoder 330, a sampler, and a write A FIFO 340, a data alignment unit 350, and a symbol lock pattern detection unit 1300. The remaining components except for the symbol lock pattern detection unit 1310 may be operated in the same manner as the component having the same reference numeral in FIG.

The symbol lock pattern detector 1310 may include an analog-to-digital converter 1312 connected to one DQ line. The analog-to-digital converter 1312 can divide the voltage level range of the DQ line into predetermined groups, as shown in Fig. 15, and convert it into a digital output corresponding to the divided voltage level range.

The symbol lock pattern detector 1310 can determine the symbol lock pattern A when the digital output of the analog-to-digital converter 1312 is 0-0-1. The symbol lock pattern detector 1310 determines a symbol lock pattern B when the digital output of the analog-to-digital converter 1312 is 0-1-0, a symbol lock pattern C when the digital output of the analog-to-digital converter 1312 is 0-1-1, 0-0, the symbol lock pattern D is determined. In case of 1-0-1, the symbol lock pattern E is determined. In case of 1-1-0, the symbol lock pattern F is determined.

The symbol lock pattern detector 1310 may store the A-F symbol lock patterns. The symbol lock pattern detector 1310 may detect the symbol lock pattern by comparing the digital output of the analog-to-digital converter 1312 with the stored A-F symbol lock pattern.

16 and 17 are diagrams illustrating a memory system including a memory controller that performs a symbol lock method according to embodiments of the present invention. 16 is a block diagram of the memory system 1600, and FIG. 17 is a timing diagram illustrating a symbol lock operation performed in the memory controller of FIG.

16, a memory system 1600 includes a memory controller 1610 and a memory device 1620 that perform symbol lock operations and a memory controller 1610 and a memory device 1620 include a bus 1630 Lt; / RTI > The memory controller 1610 may issue a read command RAED and transfer it to the memory device 1620 via CA line 1630. [ The memory device 1620 may send the requested read data in response to the read command RAED to the memory controller 1610 via the DQ bus 1630. [

The memory controller 1610 may include a symbol lock pattern detector 1612 to find the starting point of the read data burst RD_DATA provided from the memory device 1620. [ The symbol lock pattern detector 1612 can detect the symbol lock pattern in the preamble section (T _PREAMBLE ) of the clock signal (CLK). The symbol lock pattern detector 1612 can find the first UI of the read data burst (Rd-DATA) according to the detected symbol lock pattern.

17, the memory controller 1610 issues a read command RD synchronized with the clock signal CLK and sets the read data burst RD_DATA to be received after the read latency RL from the read command RD . The read data burst RD_DATA may be received as a plurality of DQ data through the DQ bus 1630. For example, DQ data (BL0-BL13) corresponding to the burst length BL = 14 may be received as the read data burst RD_DATA.

The memory controller 1610 sets a part of the plurality of DQ data DQ0, DQ1, and DQ2 as one group, and uses patterns of grouped DQ data as symbol lock patterns. The data BL0 to BL13 corresponding to the read data burst RD_DATA can be received by the LANE_A, LANE_B, and LANE_C lanes through which the data DQ0, DQ1, and DQ2 are respectively transmitted.

The symbol lock pattern detector 1612 of the memory controller 1610 can detect the symbol lock pattern transmitted in the multi lane (LANE_A, LANE_B, LANE_C) during the read latency RL. The symbol lock pattern may be composed of various combinations of data bits transmitted in a multi-lane (LANE_A, LANE_B, LANE_C).

For example, if the data bits transmitted in the multi lanes (LANE_A, LANE_B, and LANE_C) are 0-0-1, the symbol lock pattern A can be defined. When the data bits transmitted in the multi lanes (LANE_A, LANE_B, LANE_C) are 0-1-0, it is determined as a B pattern, 0-1-1 is set as a C pattern, 1-0-0 is set as a D pattern , 1-0-1, and an F pattern for 1-1-0, respectively.

When a symbol lock pattern transmitted in a multi-lane (LANE_A, LANE_B, LANE_C) is detected as a pattern by the symbol lock pattern detection section 1612, a multi-lane (LANE_A) synchronized with the sixth clock signal (CLK) , LANE_B, and LANE_C may be determined to be the first UI (BL0) that is the start of the read data burst RD_DATA. When the B symbol lock pattern is detected by the symbol lock pattern detection unit 1612, the data synchronized with the fifth clock signal (CLK) edge from the detection time is determined as the first UI (BL0) of the read data burst (RD_DATA) When the symbol lock pattern is detected, the data synchronized with the fourth clock signal (CLK) edge from the detection point can be determined as the first UI (BL0) of the read data burst RD_DATA.

When the D symbol lock pattern is detected by the symbol lock pattern detection unit 1612, the data synchronized with the third clock signal (CLK) edge from the detection point is detected as the second clock signal (CLK ) And an F symbol lock pattern are detected, the data synchronized with the first clock signal (CLK) edge from the detection point can be determined as the first UI (BL0) of the read data burst RD_DATA.

In this embodiment, the symbol lock pattern detector 1612 of the memory controller 1610 determines a first UI (BL0) of a read data burst RD_DATA according to A-F symbol lock patterns. According to the embodiment, the first UI (BL0) of the read data burst RD_DATA can be determined using symbol lock patterns other than the A-F symbol lock patterns.

18 is a view for explaining a memory device performing a symbol lock method according to embodiments of the present invention.

18, memory device 1800 includes control logic 1810, a refresh address generator 1815, an address buffer 1820, a bank control logic 1830, a row address multiplexer 1840, a column address latch 1850, a row decoder, a memory cell array, a sense amplifier section, an input / output gating circuit 1890, and a data input / output buffer 1895.

The memory cell region may include first through fourth bank arrays 1880a, 1880b, 1880c, and 1880d. Each of the first to fourth bank arrays 1880a, 1880b, 1880c, and 1880d includes a plurality of memory cell rows (or pages), and sense amplifiers 1885a, 1885b, 1885c, 1885d).

The row decoder may include first through fourth bank row decoders 1860a, 1860b, 1860c, and 1860d connected to the first through fourth bank arrays 1880a, 1880b, 1880c, and 1880d, respectively. The column decoder may include first to fourth bank column decoders 1870a, 1870b, 1870c, and 1870d connected to the first to fourth bank arrays 1880a, 1880b, 1880c, and 1880d, respectively.

The first through fourth bank arrays 1880a 1880b 1880c and 1880d and the first through fourth bank row decoders 1860a 1860b 1860c and 1860d and the first through fourth bank column decoders 1870a and 1870b , 1870c, and 1870d may constitute the first to fourth memory banks, respectively. Although FIG. 11 shows an example of a memory device 1800 that includes four memory banks, according to an embodiment, the memory device 1800 may include any number of memory banks.

In addition, according to an embodiment, the memory device 1800 may be implemented as a DDR SDRAM, a LPDDR SDRAM, a Graphics Double Data Rate (SDRAM) SDRAM, a Rambus Dynamic RAM (RDRAM) And a dynamic random access memory (DRAM) such as an access memory (DRAM).

The control logic 1810 may control the operation of the memory device 1800. For example, control logic 1810 may generate control signals such that memory device 1800 performs a write or read operation. The control logic 1810 may include a command decoder 1811 that decodes the command CMD received from the memory controller and a mode register 1813 for setting the operating mode of the memory device 1800.

The command decoder 1811 decodes the write enable signal / WE, the row address strobe signal / RAS, the column address strobe signal / CAS, the chip selection signal / CS, Lt; / RTI > The command CMD may include an active command, a read command, a write command, a free charge command, and the like.

The mode register 1813 provides a plurality of operating options of the memory device 1800 and is capable of programming various functions, characteristics, and modes of the memory device 1800.

Control logic 1810 may further receive differential clocks (CLK_t / CLK_c) and a clock enable signal (CKE) for driving memory device 1800 in a synchronous manner. The data in memory device 1800 may operate at a double data rate. The clock enable signal CKE may be captured at the rising edge of the clock CLK_t.

The control logic 1810 controls the refresh address generator 1815 to perform the auto refresh operation in response to the refresh command or controls the refresh address generator 1815 to perform the self refresh operation in response to the self refresh enter command can do.

The refresh address generator 1815 can generate the refresh address REF_ADDR corresponding to the memory cell row in which the refresh operation is to be performed. The refresh address generator 1815 may generate the refresh address REF_ADDR from the refresh cycle defined in the standard of the volatile memory device.

The address buffer 1820 may receive an address ADDR including the bank address BANK_ADDR, the row address ROW_ADDR and the column address COL_ADDR from the memory controller. The address buffer 1820 also provides the received bank address BANK_ADDR to the bank control logic 1830 and provides the received row address ROW_ADDR to the row address multiplexer 1840 and the received column address COL_ADDR May be provided to the column address latch 1850.

The bank control logic 1830 may generate bank control signals in response to the bank address BANK_ADDR. In response to the bank control signals, a bank row decoder corresponding to the bank address (BANK_ADDR) of the first to fourth bank row decoders 1860a, 1860b, 1860c, and 1860d is activated and the first to fourth bank column decoders The bank column decoder corresponding to the bank address BANK_ADDR among the banks 1870a, 1870b, 1870c and 1870d may be activated.

The bank control logic 1830 may generate bank group control signals in response to a bank address (BANK_ADDR) that determines a bank group. In response to the bank group control signals, the row decoders of the bank group corresponding to the bank address (BANK_ADDR) of the first to fourth bank row decoders 1860a, 1860b, 1860c and 1860d are activated, The column decoders of the bank group corresponding to the bank address BANK_ADDR among the bank column decoders 1870a, 1870b, 1870c, and 1870d may be activated.

The row address multiplexer 1840 may receive the row address ROW_ADDR from the address buffer 1820 and receive the refresh row address REF_ADDR from the refresh address generator 1815. [ The row address multiplex 1840 can selectively output the row address ROW_ADDR or the refresh row address REF_ADDR. The row address output from the row address multiplexer 1840 may be applied to the first to fourth bank row decoders 1860a, 1860b, 1860c, and 1860d, respectively.

The bank row decoder activated by the bank control logic 1830 of the first to fourth bank row decoders 1860a, 1860b, 1860c and 1860d decodes the row address output from the row address multiplexer 1840, Lt; RTI ID = 0.0 > wordline < / RTI > For example, an activated bank row decoder may apply a word line drive voltage to a word line corresponding to a row address.

The column address latch 1850 may receive the column address COL_ADDR from the address buffer 1820 and temporarily store the received column address COL_ADDR. The column address latch 1850 may incrementally increase the column address (COL_ADDR) received in burst mode. The column address latch 1850 may apply the temporarily stored or gradually increased column address COL_ADDR to the first to fourth bank column decoders 1870a, 1870b, 1870c, and 1870d, respectively.

The bank column decoder activated by the bank control logic 1830 of the first to fourth bank column decoders 1870a, 1870b, 1870c and 1870d outputs the bank address BANK_ADDR and the column address COL_ADDR) can be activated.

The input / output gating circuit 1890, together with the circuits for gating the input / output data, includes input data mask logic, a read data latch for storing data output from the first to fourth bank arrays 1880a, 1880b, 1880c, And a write driver for writing data to the first to fourth bank arrays 1880a, 1880b, 1880c, and 1880d.

The write data to be written to the memory cell array of one bank array of the first to fourth bank arrays 1880a, 1880b, 1880c, and 1880d may be provided from the memory controller to the data input / output buffer 1895 through the memory buffer . Data provided to the data input / output buffer 1895 may be written to one bank array through the write driver.

The data input / output buffer 1895 may include a symbol lock pattern detector 1896 to find the start point of the write data burst. The symbol lock pattern detector 1896 stores a plurality of symbol lock patterns, compares received DQ data with stored symbol lock patterns, and detects a symbol lock pattern corresponding to the comparison result. The symbol lock pattern detector 1896 can find the first data of the write data burst according to the detected symbol lock pattern.

19 is a block diagram illustrating an example of application of a memory device performing a symbol lock method according to embodiments of the present invention to a mobile system.

19, the mobile system 1900 includes an application processor 1910, a communication unit 1920, a first memory device 1930, a second memory device 1940 ), A user interface 1950, and a power supply 1960. The first memory device 1930 may be set to a volatile memory device and the second memory device 1940 may be set to a non-volatile memory device. According to an embodiment, the mobile system 1900 may be a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera Camera, a music player, a portable game console, a navigation system, and the like.

The application processor 1910 may execute applications that provide Internet browsers, games, animations, and the like. According to an embodiment, the application processor 1910 may include a single processor core or a plurality of processor cores (Multi-Core). For example, the application processor 1910 may include a dual-core, a quad-core, and a hexa-core. In addition, according to the embodiment, the application processor 1910 may further include a cache memory located inside or outside.

The communication unit 1920 can perform wireless communication or wired communication with an external device. For example, the communication unit 1920 may be an Ethernet communication, a Near Field Communication (NFC), a Radio Frequency Identification (RFID) communication, a Mobile Telecommunication, a memory card communication, A universal serial bus (USB) communication, and the like. For example, the communication unit 1920 may include a baseband chipset, and may support communication such as GSM, GRPS, WCDMA, and HSxPA.

The first memory device 1930, which is a volatile memory device, may store data processed by the application processor 1910 as write data, or may operate as a working memory. The first memory device 1930 may include a symbol lock pattern detector 1931 to find the start point of the write data burst received at the first memory device 1930. The symbol lock pattern detector 1931 stores a plurality of symbol lock patterns, compares received data with stored symbol lock patterns, and detects a symbol lock pattern corresponding to the comparison result. The symbol lock pattern detector 1931 can find the first data of the write data burst according to the detected symbol lock pattern.

A second memory device 1940, which is a non-volatile memory device, may store a boot image for booting the mobile system 1900. For example, the nonvolatile memory device 1940 may be an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistance random access memory (RRAM) A Floating Gate Memory, a Polymer Random Access Memory (PoRAM), a Magnetic Random Access Memory (MRAM), a Ferroelectric Random Access Memory (FRAM), or the like.

The user interface 1950 may include one or more input devices, such as a keypad, a touch screen, and / or a speaker, a display device, and one or more output devices. It is possible to supply the operating voltage of the power supply 1960. In addition, according to an embodiment, the mobile system 1900 may include a camera image processor (CIP), a memory card, a solid state drive (SSD), a hard disk drive A hard disk drive (HDD), a CD-ROM, and the like.

20 is a block diagram illustrating an example of application of a memory device performing a symbol lock method according to embodiments of the present invention to a computing system.

20, a computer system 2000 includes a processor 2010, an input / output hub 2020, an input / output controller hub 2030, a memory device 2040, and a graphics card 2050. According to an embodiment, the computer system 2000 may be a personal computer (PC), a server computer, a workstation, a laptop, a mobile phone, a smart phone, A personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a digital television, a set-top box, A music player, a portable game console, a navigation system, and the like.

Processor 2010 may execute various computing functions, such as certain calculations or tasks. For example, the processor 2010 may be a microprocessor or a central processing unit (CPU). According to an embodiment, the processor 2010 may include one processor core (Core) or a plurality of processor cores (Multi-Core). For example, the processor 2010 may include a dual-core, a quad-core, a hexa-core, and the like. Also shown in FIG. 13 is a computing system 2000 that includes one processor 2010, but according to an embodiment, the computing system 2000 may include a plurality of processors. Also, according to the embodiment, the processor 2010 may further include a cache memory located inside or outside.

Processor 2010 may include a memory controller 2011 that controls the operation of memory device 2040. [ The memory controller 2011 included in the processor 2010 may be referred to as an integrated memory controller (IMC). According to an embodiment, the memory controller 2011 may be located in the input / output hub 2020. [ The input / output hub 2020 including the memory controller 2011 may be referred to as a memory controller hub (MCH).

The memory controller 2011 may include a symbol lock pattern detector 2012 to find the start point of a read data burst read from the memory device 2040. [ The symbol lock pattern detector 2012 stores a plurality of symbol lock patterns, compares data received by the memory controller 2011 with stored symbol lock patterns, and detects a symbol lock pattern corresponding to a comparison result. The symbol lock pattern detector 2012 can find the first data of the read data burst according to the detected symbol lock pattern.

The memory device 2040 may include a symbol lock pattern detector 2041 to find the start point of the write data burst provided by the memory controller 2012. [ The symbol lock pattern detector 2041 may store a plurality of symbol lock patterns, compare data received with the memory device 2040 with stored symbol lock patterns, and detect a symbol lock pattern corresponding to the comparison result. The symbol lock pattern detector 2041 can find the first data of the write data burst according to the detected symbol lock pattern.

The input / output hub 2020 can manage data transfer between the processor 2010 and devices such as the graphics card 2050. [ The input / output hub 2020 can be connected to the processor 2010 through various types of interfaces. For example, the input / output hub 2020 and the processor 2010 may include a front side bus (FSB), a system bus, a hypertransport, a lighting data transport 20 can be connected to various standard interfaces such as an LDT, a QuickPath Interconnect (QPI), a common system interface, and a Peripheral Component Interface-Express (CSI) 2020, although the computing system 2000 may include a plurality of input / output hubs, according to an embodiment.

The input / output hub 2020 may provide various interfaces with the devices. For example, the input / output hub 2020 may include an Accelerated Graphics Port (AGP) interface, a Peripheral Component Interface-Express (PCIe) interface, a Communications Streaming Architecture (CSA) Can be provided.

The graphics card 2050 may be connected to the input / output hub 2020 via AGP or PCIe. The graphics card 2050 may control a display device (not shown) for displaying an image. Graphics card 2050 may include an internal processor and internal processor and internal semiconductor memory device for image data processing. Output hub 2020 may include a graphics device in the interior of the input / output hub 2020, with or instead of the graphics card 2050 located outside of the input / output hub 2020 . The graphics device included in the input / output hub 2020 may be referred to as Integrated Graphics. In addition, the input / output hub 2020 including the memory controller and the graphics device may be referred to as a graphics and memory controller hub (GMCH).

The input / output controller hub 2030 can perform data buffering and interface arbitration so that various system interfaces operate efficiently. The input / output controller hub 2030 may be connected to the input / output hub 2020 through an internal bus. For example, the input / output hub 2020 and the input / output controller hub 2030 may be connected through a direct media interface (DMI), a hub interface, an enterprise southbridge interface (ESI), a PCIe .

The I / O controller hub 2030 may provide various interfaces with peripheral devices. For example, the input / output controller hub 2030 may include a universal serial bus (USB) port, a serial Advanced Technology Attachment (SATA) port, a general purpose input / output (GPIO) (LPC) bus, Serial Peripheral Interface (SPI), PCI, PCIe, and the like.

Depending on the embodiment, two or more components of the processor 2010, the input / output hub 2020, or the input / output controller hub 2030 may be implemented as one chipset.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (20)

A transmitter for transmitting at least one symbol lock pattern and a data burst through an input / output interface; And
And a receiving unit for detecting the symbol lock pattern received through the input / output interface and searching for the first data of the data burst according to the detected symbol lock pattern. The method according to claim 1,
Wherein the receiver stores a plurality of symbol lock patterns and detects at least one symbol lock pattern by comparing data received as a data input / output (DQ) signal with stored symbol lock patterns through the input / output interface. 3. The method of claim 2,
Wherein the transfer unit is a memory controller that issues a write command,
Wherein the reception unit is a memory device that generates a write enable signal in response to the write command and finds the first data of the data burst based on the write enable signal. 4. The apparatus of claim 3, wherein the memory device
A clock generator for receiving a clock signal, generating a first clock signal in accordance with even edges of the clock signal, and generating a second clock signal in accordance with the odd edges of the clock signal;
A sampler for sequentially inputting and serially outputting the symbol lock pattern and the data burst transferred through the plurality of data input / output (DQ) signals in response to the first and second clock signals and the write enable signal, Write FIFO;
A symbol lock pattern detector for detecting the symbol lock pattern at an output of the sampler and the write FIFO in response to the write enable signal and generating a data latch signal in accordance with the detected symbol lock pattern; And
And a data arrangement for outputting the data bursts in parallel in an output of the sampler and a write FIFO in response to the data latch signal. The method according to claim 1,
The receiver stores a plurality of symbol lock patterns, detects a plurality of symbol lock patterns by comparing data received as a data input / output (DQ) signal received through the input / output interface with stored symbol lock patterns, And generates a write enable signal in accordance with the lock patterns and finds the first data of the data burst based on the write enable signal. 6. The apparatus of claim 5, wherein the memory device
A clock generator for receiving a clock signal, generating a first clock signal in accordance with even edges of the clock signal, and generating a second clock signal in accordance with the odd edges of the clock signal;
A sampler and a write FIFO for sequentially inputting and serially outputting the symbol lock patterns and the data bursts transmitted through a plurality of data input / output (DQ) signals in response to the first and second clock signals;
A symbol lock for generating the data latch signal based on the write enable signal, and for generating a data latch signal based on the write enable signal, the method comprising: detecting the symbol lock patterns at the output of the sampler and write FIFO; generating the write enable signal in accordance with the detected symbol lock patterns; A pattern detector; And
And a data arrangement for outputting the data bursts in parallel in an output of the sampler and a write FIFO in response to the data latch signal. The method according to claim 1,
Wherein the transfer unit is a memory device that outputs read data to the data burst in response to a read command,
Wherein the receiver is a memory controller that issues the read command and searches for the first data of the read data. The input / output interface as claimed in claim 7, wherein the memory controller stores a plurality of symbol lock patterns, and detects symbol lock patterns by comparing data received via the input / output interface with stored symbol lock patterns. The method according to claim 1,
The input / output interface sets a part of a plurality of data input / output (DQ) signals connected between the transmitting unit and the receiving unit as a group, and uses a pattern of grouped DQ signals as the symbol lock pattern. The method according to claim 1,
Wherein the input / output interface uses a voltage level applied to a data input / output (DQ) signal connected between the transmitting unit and the receiving unit as the symbol lock pattern. 11. The method of claim 10,
The receiver stores a plurality of symbol lock patterns, converts a voltage level of the DQ signal received through the input / output interface into a digital signal, compares the converted digital signal with stored symbol lock patterns, I / O interface to detect. A command decoder for generating a write enable signal in response to a write command;
A sampler and a write FIFO for sequentially inputting and outputting at least one first symbol lock pattern and a write data burst transferred as a plurality of data input / output (DQ) signals according to a clock signal; And
And a symbol lock pattern detector for finding the first data of the write data burst at the output of the sampler and write FIFO based on the write enable signal. 13. The memory device of claim 12, wherein the memory device
Further comprising a clock generator for receiving the clock signal, generating a first clock signal in accordance with even edges of the clock signal, and generating a second clock signal in accordance with the odd edges of the clock signal,
Wherein the sampler and the write FIFO serially output the output of the sampler and the write FIFO in accordance with the first and second clock signals. 14. The apparatus of claim 13, wherein the symbol lock pattern detector
Storing a plurality of second symbol lock patterns, detecting the first symbol lock pattern by comparing the output of the sampler and the write FIFO with the second symbol lock patterns in response to the write enable signal, And generates a data latch signal that causes the write data burst to be output in a parallel fashion at an output of the sampler and write FIFO according to a symbol lock pattern. A sampler and a write FIFO for sequentially inputting and outputting first symbol lock patterns and write data bursts transmitted as a plurality of data input / output (DQ) signals according to a clock signal; And
Detecting a portion of the first symbol lock patterns by comparing a plurality of second symbol lock patterns with an output of the sampler and write FIFO and the second symbol lock patterns, And a symbol lock pattern detector for detecting a first data of the write data burst according to the write enable signal. A sampler and a write FIFO for sequentially inputting and outputting a first symbol lock pattern and a write data burst applied at a voltage level of a data input / output (DQ) signal; And
A plurality of second symbol lock patterns are stored, a voltage level of the DQ signal is converted into a digital signal through an analog-to-digital conversion unit, and the converted digital signal is compared with the second symbol lock patterns, And detects a first data of the write data burst according to the detected first symbol lock pattern. Transmitting at least one first symbol lock pattern and a data burst in a transmitter;
Storing second symbol lock patterns in a receiver; And
Comparing the first symbol lock pattern with the second symbol lock pattern in the receiver, detecting a symbol lock pattern matching the comparison result, and searching for the first data of the data burst according to the detected symbol lock pattern Symbol lock method. 18. The method of claim 17,
And a plurality of data input / output (DQ) signals connected between the transmitting unit and the receiving unit are set as a group, and a pattern of grouped DQ signals is used as the first symbol lock pattern. 18. The method of claim 17,
And a voltage level applied to a data input / output (DQ) signal connected between the transmitting unit and the receiving unit is used as the first symbol lock pattern. 20. The method of claim 19,
Wherein the receiver converts the voltage level of the DQ signal into a digital signal and compares the converted digital signal with the second symbol lock pattern to detect the symbol lock pattern.

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