KR20160051543A - Memory device with selective power mode - Google Patents

Abstract

A memory device that is selectively operated in accordance with a power mode is disclosed. The memory device includes a memory cell array, a page size changing circuit, and an encoding and decoding changing circuit. The page size changing circuit changes the data to be prefetched in the memory cell array in accordance with the power mode. The encoding and decoding change circuit performs a decoding operation to convert the data bits to be written to the memory cell array based on data applied to the data pins in accordance with the power mode and outputs the data bits read from the memory cell array to the data pins And performs an encoding operation for outputting.

Description

[0001] The present invention relates to a memory device,

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor memory device, and more particularly, to a memory device capable of selectively operating according to a high-performance mode and a low-power mode, thereby reducing power consumption.

High-speed memory devices are being used to improve system performance in mobile devices. High-speed memory devices are designed with high performance to optimize the operating range with maximum bandwidth. However, users of actual mobile devices frequently use mobile devices in a state requiring low performance such as home-screen viewing, internet page reading, music listening, or watching a moving image. Accordingly, there is a need for a method of reducing power consumption in a situation where only low performance is required in order to reduce battery consumption of a mobile device.

It is an object of the present invention to provide a memory device that is selectively operated according to a power mode.

According to an aspect of the present invention, there is provided a memory device including a memory cell array, a plurality of lanes connected to a memory cell array and constituting at least one channel, and a plurality of lanes, Data pins, data pins to be written into the memory cell array based on data applied to the data pins in accordance with the power mode, and an encoding operation for outputting data bits read from the memory cell array to data pins And an encoding and decoding circuit for performing an operation.

In order to achieve the above object, a memory device according to another aspect of the present invention includes a memory cell array and a page size changing circuit for changing data to be prefetched in a memory cell array according to a power mode.

The memory device according to the embodiments of the present invention can reduce the power consumption because it does not perform the demapping and mapping operation by the encoding and decoding changing circuit when in the low power mode.

In the memory device according to the embodiments of the present invention, in the low power mode, the page size changing circuit changes the number of core cycle operations for pre-fetching data in the memory cell array, The power consumption can be reduced by reducing the burst length and reducing the number of data input / output pins to be activated.

1 is a diagram illustrating a mobile device including a memory device selectively operated according to a power mode according to embodiments of the present invention.
2 is a schematic diagram illustrating a memory device selectively operated according to a power mode according to embodiments of the present invention.
3A and 3B are diagrams for explaining the input / output level changing circuit of FIG.
Figs. 4A to 4F are diagrams for explaining the encoding / decoding changing circuit of Fig.
5A and 5B are views of a first example for explaining the operation of the page size changing circuit of FIG.
6A and 6B are views of a second example for explaining the operation of the page size changing circuit of FIG.
Figs. 7A and 7B are views of a third example for explaining the operation of the page size changing circuit of Fig. 2. Fig.
8 is a diagram for explaining the clock path changing circuit of Fig.
Figs. 9A and 9B are views of a first example for explaining the operation of the timing changing circuit of Fig.
10 is a second example of the operation of the timing changing circuit of Fig.
Figure 11 is a block diagram of a memory device that is selectively operated according to a power mode according to embodiments of the present invention.
12 is a block diagram illustrating an example of application of a memory device selectively operated according to the power mode according to the embodiments of the present invention to a mobile system.
13 is a block diagram illustrating an example of application of a memory device selectively operated according to a power mode according to embodiments of the present invention to a computing system.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. The present invention is capable of various modifications and various forms, and specific embodiments are illustrated and described in detail in the drawings. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for similar elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are enlarged or reduced from the actual dimensions for the sake of clarity of the present invention.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a part or a combination thereof is described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

1 is a diagram illustrating a mobile device including a memory device selectively operated according to a power mode according to embodiments of the present invention.

Referring to FIG. 1, the mobile device 100 may be a portable terminal such as a Galaxy S, an iPhone, or the like. The mobile device 100 includes a communication unit 110, a control unit 120, a memory unit 130, a display unit 140, and an input unit 150.

The communication unit 110 transmits / receives a wireless signal of data input / output through an antenna or transmits / receives data of a computer system connected via a USB (Universal Serial Bus) port.

The control unit 120 controls and processes the overall operation of the mobile device 100. The control unit 120 may control the operation of the memory unit 130 according to the power mode of the mobile device 100. [ The power mode of the mobile device 100 includes a high performance mode (HP_MODE) and a low power mode (LP_MODE). The high performance mode (HP_MODE) is a mode in which the memory unit 130 is operated in high performance, and can be called a high power mode because of high power consumption. The low power mode LP_MODE is a mode in which the memory unit 130 is operated with low performance and low power consumption.

The memory unit 130 stores various programs and data for the overall operation of the mobile device 100. The memory unit 130 may include at least one DRAM 131, at least one NAND memory 132, and at least one MO memory NAND memory 133.

The DRAM 131 temporarily stores data processed in the mobile device 100 under the control of the controller 120. [ Each of the NAND memory 132 and the MOBY NAND memory 133 may include at least one NAND flash memory device.

The NAND memory 132 performs a function of downloading the boot loader and OS of the mobile device 100 and the MOBILE NAND memory 133 performs a mass storage function of the mobile device 100 . The Moving NAND memory 133 refers to an embedded memory card using an SD / MMC (Secure Digital / Multi-Media Card) interface protocol. The MOVIE NAND memory 133 receives and stores the data stored in the DRAM 131 via the SD / MMC interface.

Display unit 140 displays status information, numbers, and characters that occur during operation of mobile device 100. The display unit 140 may display a list of contents and version information stored in the mobile NAND memory 133 under the control of the controller 120. [

The input unit 150 includes various keys for inputting numeric or character information and outputs functions corresponding to the keys input by the user to the control unit 120. [

2 is a diagram illustrating a memory device selectively operated according to a power mode according to embodiments of the present invention.

Referring to FIG. 2, the memory device 200 includes a memory cell array 210 and power mode changeover circuitry portions 220. The memory device 200 may be the DRAM 131 of FIG. The memory cell array 210 may include a plurality of memory cells arranged in rows and columns. The memory cell may consist of one access transistor and one storage capacitor. The memory cells are arranged in an inter-sectored arrangement, one at each intersection of the matrix consisting of word lines and bit lines. The memory device 200 can write write data into the memory cells of the memory cell array 210 during the write operation and output read data from the memory cells of the memory cell array 210 during the read operation.

According to an embodiment, the memory cell array 210 may be implemented as a three-dimensional (3D) memory array. The 3D memory array is monolithically formed on at least one physical level of memory cell arrays having an active area disposed on a silicon substrate and circuits associated with operation of the memory cells on the substrate or in the substrate. The term " low " means that layers of each level constituting the array are stacked directly on top of the layers of each lower level of the array.

U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and U.S. Patent Application Publication No. 2011/0233648 disclose that a 3D memory array is constructed at multiple levels and word lines and / Which are incorporated herein by reference in their entirety as those that describe suitable configurations for a 3D memory array in which bit lines are shared between levels.

The power mode changing circuits 220 include an input / output level changing circuit 300, an encoding / decoding changing circuit 400, a page size changing circuit 500, and an input / output level changing circuit 400 which operate in response to a low power mode LP_MODE or a high performance mode HP_MODE. A clock path changing circuit 600, and a timing changing circuit 700.

The input / output level changing circuit 300 controls the internal nodes of the input / output level changing circuit 300 to have multi-levels according to data applied to the data pins of the memory device 200 in the high performance mode (HP_MODE) The internal node of the input / output level changing circuit 300 may have two levels according to data applied to the data pins of the memory device 200. [

In the high performance mode, the encoding / decoding changing circuit 400 generates symbols based on data applied to the data pins of the memory device 200 and encodes the generated symbols to generate data bits And transmit the outputs of the comparators that compare the data applied to the data pins of the memory device 200 to the first reference voltage in serial or parallel to the memory cell array 210 in the low power mode.

The page size changing circuit 500 prefetches data from the memory cell array 210 into core cycle operation # 1 in which data is prefetched from the memory cell array 210 in the high performance mode, and at least two Data can be prefetched from the memory cell array 210 by a core cycle operation. The page size changing circuit 500 pre-fetches data corresponding to the first burst length from the memory cell array 210 in the core cycle operation # 1 in the high performance mode and outputs the data through the first and second groups of data input / In the low power mode, data of the second burst length less than the data corresponding to the first burst length is prefetched from the memory cell array 210 to the core cycle operation # 1 and output to the first group of data input / output pins have.

The clock path changing circuit 600 transmits the internal clock signal generated based on the clock signal received through the clock buffer in the high performance mode to the high performance tree circuits using the current mode logic (CML) Mode, the internal clock signal can be transmitted to a low power tree circuit driven at the CMOS level.

The timing changing circuit 700 sets the tRCD timing between the row active command and the read command applied to the memory device 200 in the high performance mode to the first time and sets the tRCD timing between the low active command and the read command to the sensing operation for sensing the data read out from the memory cell array 210 The operation may be driven by a first current, the tRCD timing may be set to a second time longer than the first time when in the low power mode, and the sensing operation may be driven by a second current less than the first current.

The operations of the input / output level changing circuit 300, the encoding / decoding changing circuit 400, the page size changing circuit 500, the clock path changing circuit 600, and the timing changing circuit 700 are shown in FIGS. .

3A and 3B are diagrams for explaining the input / output level changing circuit of FIG. FIG. 3A shows an input / output level changing circuit 300a in a high performance mode (HP_MODE), and FIG. 3B shows an input / output level changing circuit 300b in a low power mode (LP_MODE).

3A, the input / output level changing circuit 300a in the high performance mode (HP_MODE) includes a transmitting unit 310, a termination unit 320, and a first receiving unit 330a.

The transmission unit 310 includes a plurality of output buffers 311, 312, and 313. The first output buffer 311 may be composed of an inverter connected between the power supply voltage VDDQ and the ground voltage VSSQ and receiving the first input A. [ The output of the first output buffer 311 is output to the first line 341. The second output buffer 312 is composed of an inverter connected between the power supply voltage VDDQ and the ground voltage VSSQ and receiving the second input B and the output of the second output buffer 312 is connected to the second line (342). The third output buffer 313 is constituted by an inverter connected between the power supply voltage VDDQ and the ground voltage VSSQ and inputting the third input C and the output of the third output buffer 313 is connected to the third line (342). According to an embodiment, the transmitter 310 may include a variety of output buffers in addition to the three output buffers 311, 312, and 313.

The termination unit 320 functions to terminate the first to third lines 341 to 343 so as to have a multi-level. The termination unit 320 includes a first resistor 321 connected between the first line 341 and the node NA, a second resistor 322 connected between the second line 342 and the node NA, And a third resistor 323 connected between the third line 343 and the node NA. The node NA is an internal node to which the first to third resistors 321 to 323 are connected in common, and the voltage levels of the first to third lines 341 to 343 are the power supply voltage VDDQ and the ground voltage (VSSQ) so as to have a multilevel without full-swing. Thus, the first to third lines 341 to 343 have input / output levels of multi-level signaling.

The first receiver 330a may include a plurality of input buffers 331a-333a connected to the first through third lines 341-343. The first input buffer 331a is a differential amplifier in which a terminated first line 341 is connected to a first input terminal (+) and a terminated second line 342 is connected to a second input terminal (-) Lt; / RTI > The first input buffer 331a outputs the first output A-B based on the voltage levels of the terminated first line 341 and the second line 342. [

The second input buffer 332a is a differential amplifier in which the terminated second line 342 is connected to the first input terminal (+) and the terminated third line 343 is connected to the second input terminal (-) Lt; / RTI > The second input buffer 332a outputs a second output (B-C) based on the voltage levels of the terminated second line 342 and the third line 343. The third input buffer 333a is a differential amplifier in which a terminated third line 343 is connected to a first input terminal (+) and a terminated first line 341 is connected to a second input terminal (-) Lt; / RTI > The third input buffer 333a outputs the third output C-A based on the voltage levels of the terminated third line 343 and the first line 341. [

The first through third outputs AB, BC and CA when in the high performance mode HP_MODE are used in the high performance mode encoding / decoding changing circuit 400a described in FIGS. 4A through 4E, 2, or may be used for a mapping operation that is transformed from data bits read from the memory cell array 210. [

Referring to FIG. 3B, the input / output level changing circuit 300b in the low power mode (LP_MODE) includes a transmitting unit 310 and a second receiving unit 330b. The input / output level changing circuit 300b does not include a termination section as compared with the input / output level changing circuit 300b of FIG. 3A.

The transmission unit 310 is the same as the transmission unit 310 in the input / output level changing circuit 300b of FIG. The transmitting unit 310 includes first through third output buffers 311, 312, and 313 connected between a power supply voltage VDDQ and a ground voltage VSSQ. Each of the first to third output buffers 311, 312, and 313 may be configured as an inverter for inputting the first to third inputs A, B, and C, respectively. The output of the first output buffer 311 is output to the first line 341 and the output of the second output buffer 312 is output to the second line 342 and the output of the third output buffer 313 And output to the third line 342.

Since the first to third lines 341, 342 and 343 are not terminated, the power supply voltage VDDQ and the ground voltage VSSQ are changed according to the outputs of the first to third output buffers 311, Has a full-swing voltage level. That is, the first to third lines 341, 342, and 343 have input / output levels of two-level signaling having a logic high level of the power supply voltage VDDQ or a logic low level of the ground voltage VSSQ.

The second receiving unit 300b includes first through third input buffers 331b, 332b, and 333c that compare the first reference voltage VREFDQ with the voltage levels of the first through third lines 341, 342, . The first input buffer 331b compares the voltage level of the first line 341 with the first reference voltage VREFDQ and outputs a first output A-B. The second input buffer 332b compares the voltage level of the second line 342 with the first reference voltage VREFDQ to output the second output BC and the third input buffer 332c outputs the third output 343 and the first reference voltage VREFDQ to output a third output CA.

Since the input / output level changing circuit 300b of the low power mode LP_MODE does not perform the multilevel signaling operation of the input / output level changing circuit 300b of the high performance mode (HP_MODE), the power consumption can be reduced.

Figs. 4A to 4F are diagrams for explaining the encoding / decoding changing circuit of Fig. 4A to 4E illustrate the encoding / decoding changing circuit 400a in the high performance mode (HP_MODE), and FIG. 4F illustrates the encoding / decoding changing circuit 400b in the low power mode (LP_MODE) .

4A, the encoding / decoding change circuit 400a may provide an interface function between the memory device 200 (FIG. 2) and the memory device 200. FIG. The memory device 200 may be composed of a plurality of independent interfaces called channels. Each channel contains independent memory banks, independently clocked, and can configure independent commands and data interfaces.

The encoding / decoding changing circuit 400a is described as corresponding to one channel (CH) for the sake of simplicity of explanation. The description of the encoding / decoding changing circuit 400a for one channel CH may be equally applied to the remaining plurality of channels in the memory device 200 (FIG. 2).

The encoding / decoding changing circuit 400a provides an interface for transmitting, for example, 512 bits of data per channel (CH) to the memory cell array 210 (FIG. 2). 512 data bits may be divided into 64 bits and the divided 64 bits may be designed to be transmitted through the eight lanes 411, 412, ..., 417, and 418. 427 and 428 to which three data pins A, B and C are connected and the map blocks 431 and 432, respectively, are connected to the lanes 411, 412, ..., 417 and 418, ..., 437, 438).

In this embodiment, three data pins A, B and C are allocated to one lane and eight lanes are included in one channel CH, and 24 data pins constitute one channel CH .

The demapping blocks 421, 422, ..., 427 and 428 of each lane 411, 412, ..., 417 and 418 combine the data provided by the three data pins A, B and C into 28 symbols , So that 28 symbols are converted to 64-bit data. Such a de-mapping operation can be referred to as a decoding operation.

The map blocks 431, 432, ..., 437 and 438 of each lane 411, 412, ..., 417 and 418 are arranged so that 64-bit data read out from the memory cell array 210 (Fig. 2) You can map. This mapping operation can be referred to as an encoding operation.

Referring to FIG. 4B, the first lane 411 among the plurality of lanes 411, 412, ..., 417, and 418 is described. The description of the first lane 411 may be applied to the remaining lanes 412, ..., 417 and 418 as well. In the first lane 411, there are shown 28 symbols based on the burst data (BL0-BL27) applied to the three data pins (A, B, C). The first burst data BL0 to be applied to the data pins A, B and C is defined as a unit interval (UI) Let's define it as one symbol.

The 28 symbols of the first lane 411 are converted into 64-bit data through the de-map block 421. The converted 64-bit data may be written to the memory cell array 210 (FIG. 2) in the memory device 200 (FIG. 2). The 64-bit data read out from the memory cell array 210 can be converted into 28 symbols through the map block 431. The converted 28 symbols can be output through three data pins (A, B, C).

Referring to FIG. 4C, an example in which one symbol is configured based on data applied to three data pins A, B, and C is shown. Each of the data pins A, B, and C is connected to the first input A, the second input A, and the second input A in order to be associated with the multi-level signaling described in the input / output level changing circuit 300a in the high performance mode (HP_MODE) A second input B, and a third input C, respectively. The input / output level changing circuit 300a outputs the first to third outputs A-B, B-C and C-A in response to the first to third inputs A, B and C. The first to third outputs A-B, B-C, and C-A may constitute one symbol.

One symbol composed of the first to third outputs A-B, B-C and C-A of the input / output level changing circuit 300a may be composed of 3-bit data. The symbols of 3-bit data can be combined into six codes except 001, 010, 011, 100, 101, and 110, except 000 and 111. That is, one symbol may be composed of 6 codes.

The consecutive two symbols, e.g., the Nth symbol Sn and the N + 1th symbol Sn + 1, are 6x6 = 36, i.e., 36 code combinations are possible. Illustratively, the 36 codes are combinable as shown in Figure 4D. In the table of FIG. 4D, 36 codes can be divided into data codes (0 to 31) and data masks (DM1 and DM2). This means that data information and data mask information can be extracted from 36 codes combined into two consecutive symbols.

32 data codes (0 to 31) may be converted into 5-bit binary data. The mapping / demapping between two consecutive symbols (S1-S2, S3-S4, ..., S25-S26, S27-S28) and 5 bit data among the 28 symbols (S1- Can be represented by the table of FIG. 4E. In the table of FIG. 4E, 28 symbols (S1-S28) can be converted to 64-bit data (1-64). Conversely, 64-bit data can be converted into 28 symbols (S1-S28).

Referring to FIG. 4F, the low-power mode (LP_MODE) encoding / decoding changing circuit 400b includes 16 data pins DQ and 2 data mask pins DM_CH, . The encoding / decoding changing circuit 400b of the low power mode LP_MODE reduces the number of pins to be activated per channel CH from 24 to 18 as compared with the encoding / decoding changing circuit 400a of the high performance mode (HP_MODE) Due to the six pins can be reduced.

The encoding / decoding changing circuit 400b can transmit the input signals A, B and C applied to the data pins DQ and the mask pins DM in a single-ended manner for comparing the first reference voltage VREFDQ have. The encoding / decoding changing circuit 400b includes comparators 461, 462 and 463 for comparing the voltage levels of the input signals A, B and C with a first reference voltage VREFDQ, and comparators 461 and 462 And 463, which transmit serial or parallel outputs. The deserializers 471, 472,

Since the encoding / decoding changing circuit 400b of the low power mode (LP_MODE) does not perform the demapping and mapping operation described in Figs. 4B to 4D, power consumption can be reduced.

5A and 5B are views of a first example for explaining the operation of the page size changing circuit of FIG.

In FIG. 5A, page size changing circuit 500 (FIG. 2) may perform a core cycle operation to prefetch data from a memory core area including memory cell array 210 (FIG. 2). The page size changing circuit 500 (FIG. 2) can prefetch data (BL0-BL15) corresponding to the burst length, for example, BL = 16, through one core cycle operation in the high performance mode (HP_MODE). The prefetched burst data BL0 to BL15 can be output from the read command READ to the data input / output pads DQ after the read latency RL.

5B, the page size changing circuit 500 (FIG. 2) may prefetch data (BL0-BL15) corresponding to the burst length BL = 16 through two core cycle operations when in the low power mode (LP_MODE) . The first group of burst data BL0 to BL7 is pre-patched by the first core cycle operation, and the second group of burst data BL8 to BL15 is pre-fetched by the second core cycle operation. The burst data BL0-BL7 of the first group and the burst data BL8-BL15 of the second group are output from the read command READ to the data input / output pads DQ after the read latency RL .

According to the embodiment, the page size changing circuit 500 (FIG. 2) may prefetch data corresponding to the burst length through several core cycle operations in addition to the two core cycle operations when in the low power mode (LP_MODE). This means that power consumption can be reduced by reducing prefetch data read at a time in the memory core area in low power mode (LP_MODE).

6A and 6B are views of a second example for explaining the operation of the page size changing circuit of FIG. The page size changing circuit 500 (FIG. 2) can vary the burst data according to the amount of data to be accessed according to the power mode (HP_MODE, LP_MODE)

6A, the page size changing circuit 500 (FIG. 2) reads the data (BL0-BL15) corresponding to the first burst length, for example, BL = 16 through one core cycle operation in the high performance mode (HP_MODE) . 6B, the page size changing circuit 500 (FIG. 2) reads the data (BL0-BL7) corresponding to the second burst length, for example, BL = 8 through one core cycle operation in the low power mode (LP_MODE) . That is, the page size changing circuit 500 (FIG. 2) of the low power mode LP_MODE can read data corresponding to the second burst length less than the data corresponding to the first burst length in the high performance mode (HP_MODE).

Figs. 7A and 7B are views of a third example for explaining the operation of the page size changing circuit of Fig. 2. Fig. The page size changing circuit 500 (FIG. 2) can change the number of data input / output pins to be activated in accordance with the amount of data to be accessed according to the power mode (HP_MODE, LP_MODE).

Referring to FIG. 7A in conjunction with the high performance mode (HP_MODE) described in FIG. 6A, data (BL0-BL15) corresponding to the first burst length BL = 16 read from the memory core region 710 is transferred to the sixteen data input / (DQ0-DQ15). The memory core region 710 includes a plurality of memory banks A-H and each of the memory banks A-H is divided into subbanks A0, A1 - (H0, H1). The first sub-banks A0-H0 are electrically connected to the first group of data input / output pins DQ0-DQ7 via the first data lines 721 and the second sub-banks A1-H1 are electrically connected to the first group of data input / And are electrically connected to the second group of data input / output pins DQ8-DQ15 via the second data lines 722. [

The page size changing circuit 500 (FIG. 2) in the high performance mode (HP_MODE) is connected to the memory cells connected to the word lines 711 and 712 activated in the sub-banks A0 and A1 of the first bank A BL15 corresponding to the first burst length BL = 16 read out from the first and second data lines 721 and 722 are outputted to the sixteen data input / output pins DQ0 to DQ15 through the first and second data lines 721 and 722, respectively. That is, in the high performance mode (HP_MODE), 16 data input / output pins (DQ0 to DQ15) are activated.

In FIG. 7B, the page size changing circuit 500 (FIG. 2) is a circuit for changing the page size from the memory cells connected to the word line 711 activated in the first sub-banks A0 of the first bank A in the low power mode LP_MODE Data BL0 to BL15 corresponding to the read first burst length BL = 16 are output to the first group of data input / output pins DQ0 to DQ7 through the first data lines 721. [ The first data lines 721 and the second data lines 722 are selectively connected to the first group of data input / output pins DQ0-DQ7 through a selector 730. [ That is, in the low power mode (LP_MODE), eight data input / output pins DQ0-DQ7 are activated.

8 is a diagram for explaining the clock path changing circuit 600 of FIG.

Referring to FIG. 8, the clock path changing circuit 600 may selectively change the clock path according to the power mode (HP_MODE, LP_MODE). The clock path change circuit 600 includes a clock buffer 810, first and second selectors 820a and 820b, first and second high performance tree circuits 830a and 830b, and first and second low power tree circuits 830a and 830b. (840a, 840b). The first and second high performance tree circuits 830a and 830b can transmit the internal clock signal ICLK at a high speed using CML (Current Mode Logic). The first and second low power tree circuits 840a and 840b can transmit at a low speed by driving the internal clock signal ICLK to the CMOS level.

The clock buffer 810 may receive the first clock signal CK_T and the second clock signal CK_C and output the internal clock signal ICLK. The first clock signal CK_T and the second clock signal CK_C are complementary clock signals. The first and second selectors 820a and 820b transmit the internal clock signal ICLK to the first and second high performance tree circuits 830a and 830b in response to the high performance mode HP_MODE and the low power mode LP_MODE And transmits the internal clock signal ICLK to the first and second low power tree circuits 840a and 840b in response to the internal clock signal ICLK.

Figs. 9A and 9B are views of a first example for explaining the operation of the timing changing circuit of Fig. The timing changing circuit 700 (Fig. 2) may vary the AC timing of the memory device 200 (Fig. 2) in accordance with the power mode (HP_MODE, LP_MODE). The timing changing circuit 700 (Fig. 2) may cause the DC parameter to change in accordance with the changed AC timing.

9A, by the operation of the timing changing circuit 700 (Fig. 2) in the high performance mode (HP_MODE), the tRCD time which is the timing between the row active command and the read command applied to the memory device 200 You can take it short. In this case, the timing changing circuit 700 can cause the bit line sensing operation for sensing the memory cell data to operate in the high current mode according to the read command.

In Fig. 9B, by the operation of the timing changing circuit 700 in the low power mode (LP_MODE), the tRCD time can be long. In this case, the timing changing circuit 700 may cause the bit line sensing operation to operate in the low current mode.

10 is a second example of the operation of the timing changing circuit of Fig. The timing change circuit 700 (FIG. 2) may change the read latency on the internal read path of the memory device 200 (FIG. 2) or change the data toggling on the internal read path in accordance with the power mode (HP_MODE, LP_MODE) .

10, the burst data (BL0 to BL15) read out from the memory cell array 210 (FIG. 2) of the memory device 200 (FIG. 2) is read through the internal readout paths RDOI_08, RDOI_19, ..., RDOI_715 Can be read. Each of the internal read paths RDOI_08, ..., and RDOI_715 may be connected to the read data buses RDO_08, ..., RDO_715 through the sampler 1010 and the data inversion discrimination unit 1020. [ The sampler 1010 may sample the data on the internal readout paths RDOI_08, ..., RDOI_715. The data inversion discrimination unit 1020 includes a shift register 1030 connected in series to the read data buses RDO_08 ... RDO_715 and a comparator 1040 and a data inversion comparator 1050, And perform a data toggling operation to invert or invert the output of the sampler 1010. [

The operation speed of the comparator 1040 and the data inversion comparator 1050 can be made slow by the operation of the timing changing circuit 700 (Fig. 2) in the low power mode (LP_MODE), and the read latency can be increased. According to the embodiment, the timing change circuit 700 (Fig. 2) in the low power mode (LP_MODE) can minimize the data inversion toggling operation by the data inversion discrimination section 1020. [

Figure 11 is a block diagram of a memory device that is selectively operated according to a power mode according to embodiments of the present invention.

11, memory device 1800 includes control logic 1810, a refresh address generator 1815, an address buffer 1820, a bank control logic 1830, a row address multiplexer 1840, a column address latch 1850, a row decoder, a memory cell array, a sense amplifier section, an input / output gating circuit 1890, and a data input / output buffer 1895.

The memory cell region may include first through fourth bank arrays 1880a, 1880b, 1880c, and 1880d. Each of the first to fourth bank arrays 1880a, 1880b, 1880c, and 1880d includes a plurality of memory cell rows (or pages), and sense amplifiers 1885a, 1885b, 1885c, 1885d).

The row decoder may include first through fourth bank row decoders 1860a, 1860b, 1860c, and 1860d connected to the first through fourth bank arrays 1880a, 1880b, 1880c, and 1880d, respectively. The column decoder may include first to fourth bank column decoders 1870a, 1870b, 1870c, and 1870d connected to the first to fourth bank arrays 1880a, 1880b, 1880c, and 1880d, respectively.

The first through fourth bank arrays 1880a 1880b 1880c and 1880d and the first through fourth bank row decoders 1860a 1860b 1860c and 1860d and the first through fourth bank column decoders 1870a and 1870b , 1870c, and 1870d may constitute the first to fourth memory banks, respectively. Although FIG. 11 shows an example of a memory device 1800 that includes four memory banks, according to an embodiment, the memory device 1800 may include any number of memory banks.

In addition, according to an embodiment, the memory device 1800 may be a DDR SDRAM (SDRAM), a Low Power Double Data Rate (LPDDR) SDRAM, a Graphics Double Data Rate (SDRAM) SDRAM, a Rambus Dynamic Random Such as a dynamic random access memory (DRAM), such as an access memory.

The control logic 1810 may control the operation of the memory device 1800. For example, control logic 1810 may generate control signals such that memory device 1800 performs a write or read operation. The control logic 1810 may include a command decoder 1811 that decodes the command CMD received from the memory controller and power mode change circuits 1813 that are selectively operated according to the power mode of the memory device 1800 have.

The command decoder 1811 decodes the write enable signal / WE, the row address strobe signal / RAS, the column address strobe signal / CAS, the chip selection signal / CS, Lt; / RTI > The command CMD may include an active command, a read command, a write command, a free charge command, and the like.

The power mode changing circuits 1813 include the input / output level changing circuit 300, the encoding / decoding changing circuit 400, and the input / output level changing circuit 300 described in FIGS. 3 to 10, which operate in response to the low power mode LP_MODE or the high performance mode HP_MODE. A page size changing circuit 500, a clock path changing circuit 600, and a timing changing circuit 700. The number of core cycle operations for pre-fetching data in the memory cell array can be varied by the power mode changing circuits 1813 without performing the demapping and mapping operation by the encoding and decoding changing circuit in the low power mode (LP_MODE) The burst length can be reduced according to the data prefetched by the core cycle operation, and the number of data input / output pins activated can be reduced.

Control logic 1810 may further receive differential clocks (CLK_t / CLK_c) and a clock enable signal (CKE) for driving memory device 1800 in a synchronous manner. The data in memory device 1800 may operate at a double data rate. The clock enable signal CKE may be captured at the rising edge of the clock CLK_t.

The control logic 1810 controls the refresh address generator 1815 to perform the auto refresh operation in response to the refresh command or controls the refresh address generator 1815 to perform the self refresh operation in response to the self refresh enter command can do.

The refresh address generator 1815 can generate the refresh address REF_ADDR corresponding to the memory cell row in which the refresh operation is to be performed. The refresh address generator 1815 may generate the refresh address REF_ADDR from the refresh cycle defined in the standard of the volatile memory device.

The address buffer 1820 may receive an address ADDR including the bank address BANK_ADDR, the row address ROW_ADDR and the column address COL_ADDR from the memory controller. The address buffer 1820 also provides the received bank address BANK_ADDR to the bank control logic 1830 and provides the received row address ROW_ADDR to the row address multiplexer 1840 and the received column address COL_ADDR May be provided to the column address latch 1850.

The bank control logic 1830 may generate bank control signals in response to the bank address BANK_ADDR. In response to the bank control signals, a bank row decoder corresponding to the bank address (BANK_ADDR) of the first to fourth bank row decoders 1860a, 1860b, 1860c, and 1860d is activated and the first to fourth bank column decoders The bank column decoder corresponding to the bank address BANK_ADDR among the banks 1870a, 1870b, 1870c and 1870d may be activated.

The bank control logic 1830 may generate bank group control signals in response to a bank address (BANK_ADDR) that determines a bank group. In response to the bank group control signals, the row decoders of the bank group corresponding to the bank address (BANK_ADDR) of the first to fourth bank row decoders 1860a, 1860b, 1860c and 1860d are activated, The column decoders of the bank group corresponding to the bank address BANK_ADDR among the bank column decoders 1870a, 1870b, 1870c, and 1870d may be activated.

The row address multiplexer 1840 may receive the row address ROW_ADDR from the address buffer 1820 and receive the refresh row address REF_ADDR from the refresh address generator 1815. [ The row address multiplex 1840 can selectively output the row address ROW_ADDR or the refresh row address REF_ADDR. The row address output from the row address multiplexer 1840 may be applied to the first to fourth bank row decoders 1860a, 1860b, 1860c, and 1860d, respectively.

The bank row decoder activated by the bank control logic 1830 of the first to fourth bank row decoders 1860a, 1860b, 1860c and 1860d decodes the row address output from the row address multiplexer 1840, Lt; RTI ID = 0.0 > wordline < / RTI > For example, an activated bank row decoder may apply a word line drive voltage to a word line corresponding to a row address.

The column address latch 1850 may receive the column address COL_ADDR from the address buffer 1820 and temporarily store the received column address COL_ADDR. The column address latch 1850 may incrementally increase the column address (COL_ADDR) received in burst mode. The column address latch 1850 may apply the temporarily stored or gradually increased column address COL_ADDR to the first to fourth bank column decoders 1870a, 1870b, 1870c, and 1870d, respectively.

The bank column decoder activated by the bank control logic 1830 of the first to fourth bank column decoders 1870a, 1870b, 1870c and 1870d outputs the bank address BANK_ADDR and the column address COL_ADDR) can be activated.

The input / output gating circuit 1890, together with the circuits for gating the input / output data, includes input data mask logic, a read data latch for storing data output from the first to fourth bank arrays 1880a, 1880b, 1880c, And a write driver for writing data to the first to fourth bank arrays 1880a, 1880b, 1880c, and 1880d.

The write data to be written to the memory cell array of one bank array of the first to fourth bank arrays 1880a, 1880b, 1880c, and 1880d may be provided from the memory controller to the data input / output buffer 1895 through the memory buffer . Data provided to the data input / output buffer 1895 may be written to one bank array through the write driver.

12 is a block diagram illustrating an example of application of a memory device selectively operated according to the power mode according to the embodiments of the present invention to a mobile system.

12, the mobile system 1900 includes an application processor 1910, a communication unit 1920, a first memory device 1930, a second memory device 1940 ), A user interface 1950, and a power supply 1960. The first memory device 1930 may be set to a volatile memory device and the second memory device 1940 may be set to a non-volatile memory device. According to an embodiment, the mobile system 1900 may be a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera Camera, a music player, a portable game console, a navigation system, and the like.

The application processor 1910 may execute applications that provide Internet browsers, games, animations, and the like. According to an embodiment, the application processor 1910 may include a single processor core or a plurality of processor cores (Multi-Core). For example, the application processor 1910 may include a dual-core, a quad-core, and a hexa-core. In addition, according to the embodiment, the application processor 1910 may further include a cache memory located inside or outside.

The communication unit 1920 can perform wireless communication or wired communication with an external device. For example, the communication unit 1920 may be an Ethernet communication, a Near Field Communication (NFC), a Radio Frequency Identification (RFID) communication, a Mobile Telecommunication, a memory card communication, A universal serial bus (USB) communication, and the like. For example, the communication unit 1920 may include a baseband chipset, and may support communication such as GSM, GRPS, WCDMA, and HSxPA.

The first memory device 1930, which is a volatile memory device, may store data processed by the application processor 1910 as write data, or may operate as a working memory. The first memory device 1930 may include power mode change circuits 1931 that are selectively operated according to the power mode of the first memory device 1930. The power mode changing circuits 1931 include the input / output level changing circuit 300, the encoding / decoding changing circuit 400, and the input / output level changing circuit 300 described in Figs. 3 to 10, which operate in response to the low power mode LP_MODE or the high performance mode HP_MODE. A page size changing circuit 500, a clock path changing circuit 600, and a timing changing circuit 700. The first memory device 1930 varies the number of core cycle operations for prefetching data in the memory cell array without performing the demapping and mapping operation by the encoding and decoding changing circuit when in the low power mode LP_MODE, The burst length can be reduced in accordance with the data to be prefetched in the cycle operation, and the number of data input / output pins to be activated can be reduced.

A second memory device 1940, which is a non-volatile memory device, may store a boot image for booting the mobile system 1900. For example, the nonvolatile memory device 1940 may be an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistance random access memory (RRAM) A Floating Gate Memory, a Polymer Random Access Memory (PoRAM), a Magnetic Random Access Memory (MRAM), a Ferroelectric Random Access Memory (FRAM), or the like.

The user interface 1950 may include one or more input devices, such as a keypad, a touch screen, and / or a speaker, a display device, and one or more output devices. It is possible to supply the operating voltage of the power supply 1960. In addition, according to an embodiment, the mobile system 1900 may include a camera image processor (CIP), a memory card, a solid state drive (SSD), a hard disk drive A hard disk drive (HDD), a CD-ROM, and the like.

13 is a block diagram illustrating an example of application of a memory device selectively operated according to a power mode according to embodiments of the present invention to a computing system.

13, the computer system 2000 includes a processor 2010, an input / output hub 2020, an input / output controller hub 2030, a memory device 2040, and a graphics card 2050. According to an embodiment, the computer system 2000 may be a personal computer (PC), a server computer, a workstation, a laptop, a mobile phone, a smart phone, A personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a digital television, a set-top box, A music player, a portable game console, a navigation system, and the like.

Processor 2010 may execute various computing functions, such as certain calculations or tasks. For example, the processor 2010 may be a microprocessor or a central processing unit (CPU). According to an embodiment, the processor 2010 may include one processor core (Core) or a plurality of processor cores (Multi-Core). For example, the processor 2010 may include a dual-core, a quad-core, a hexa-core, and the like. Also shown in FIG. 13 is a computing system 2000 that includes one processor 2010, but according to an embodiment, the computing system 2000 may include a plurality of processors. Also, according to the embodiment, the processor 2010 may further include a cache memory located inside or outside.

Processor 2010 may include a memory controller 2011 that controls the operation of memory device 2040. [ The memory controller 2011 included in the processor 2010 may be referred to as an integrated memory controller (IMC). According to an embodiment, the memory controller 2011 may be located in the input / output hub 2020. [ The input / output hub 2020 including the memory controller 2011 may be referred to as a memory controller hub (MCH).

Memory device 2040 may include power mode change circuits 2041 that are selectively operated according to the power mode of memory device 2040. [ The power mode changing circuits 2041 include the input / output level changing circuit 300, the encoding / decoding changing circuit 400, and the input / output changing circuit 2050 described in FIGS. 3 to 10, which operate in response to the low power mode LP_MODE or the high performance mode HP_MODE. A page size changing circuit 500, a clock path changing circuit 600, and a timing changing circuit 700. The memory device 2040 varies the number of core cycle operations to prefetch data in the memory cell array without performing the demapping and mapping operations by the encoding and decoding changing circuit when in the low power mode (LP_MODE) The burst length can be reduced in accordance with the data to be pre-patched, and the number of data input / output pins to be activated can be reduced.

The input / output hub 2020 can manage data transfer between the processor 2010 and devices such as the graphics card 2050. [ The input / output hub 2020 can be connected to the processor 2010 through various types of interfaces. For example, the input / output hub 2020 and the processor 2010 may include a front side bus (FSB), a system bus, a hypertransport, a lighting data transport (I / O) interface (LDI), a QuickPath Interconnect (QPI), a common system interface, and a Peripheral Component Interface-Express 2020, although the computing system 2000 may include a plurality of input / output hubs, according to an embodiment.

The input / output hub 2020 may provide various interfaces with the devices. For example, the input / output hub 2020 may include an Accelerated Graphics Port (AGP) interface, a Peripheral Component Interface-Express (PCIe) interface, a Communications Streaming Architecture (CSA) Can be provided.

The graphics card 2050 may be connected to the input / output hub 2020 via AGP or PCIe. The graphics card 2050 may control a display device (not shown) for displaying an image. Graphics card 2050 may include an internal processor and internal processor and internal semiconductor memory device for image data processing. Output hub 2020 may include a graphics device in the interior of the input / output hub 2020, with or instead of the graphics card 2050 located outside of the input / output hub 2020 . The graphics device included in the input / output hub 2020 may be referred to as Integrated Graphics. In addition, the input / output hub 2020 including the memory controller and the graphics device may be referred to as a graphics and memory controller hub (GMCH).

The input / output controller hub 2030 can perform data buffering and interface arbitration so that various system interfaces operate efficiently. The input / output controller hub 2030 may be connected to the input / output hub 2020 through an internal bus. For example, the input / output hub 2020 and the input / output controller hub 2030 may be connected through a direct media interface (DMI), a hub interface, an enterprise southbridge interface (ESI), a PCIe .

The I / O controller hub 2030 may provide various interfaces with peripheral devices. For example, the input / output controller hub 2030 may include a universal serial bus (USB) port, a serial Advanced Technology Attachment (SATA) port, a general purpose input / output (GPIO) (LPC) bus, Serial Peripheral Interface (SPI), PCI, PCIe, and the like.

Depending on the embodiment, two or more components of the processor 2010, the input / output hub 2020, or the input / output controller hub 2030 may be implemented as one chipset.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (10)

A memory cell array;
A plurality of lanes connected to the memory cell array and constituting at least one channel;
Data pins coupled to one of the plurality of lanes; And
Performing a decoding operation to convert data bits to be written into the memory cell array based on data applied to the data pins according to a power mode and outputting data bits read from the memory cell array to the data pins Wherein the encoding and decoding circuitry performs an encoding operation to cause the memory device to perform the encoding operation. 2. The apparatus of claim 1, wherein the encoding and decoding circuit
A demap block for decoding symbols applied to the data pins in a high performance mode and converting the decoded symbols into data bits to be written into the memory cell array; And
And a deserializer for serially or parallelly transmitting an output of the comparators comparing the data applied to the data pins to a first reference voltage when in the low power mode. 3. The apparatus of claim 2, wherein the memory device
And a map block for decoding the data bits read from the memory cell array and converting the data bits into the symbols when the memory cell array is in the high performance mode. 3. The apparatus of claim 2, wherein the memory device
And an input / output changing circuit for setting a multi-level according to data applied to the data pins in the high performance mode,
The input / output changing circuit
Output buffers for transmitting data applied to the data pins;
A termination unit for terminating each of the outputs of the output buffers into the multilevel; And
And input buffers for outputting the symbols in response to the outputs of the terminated output buffers. 3. The method of claim 2,
Wherein in the low power mode, data applied to at least one data mask pin together with the data pins is compared to a second reference voltage, and the result of the comparison is transferred through the deserializer. 3. The apparatus of claim 2, wherein the memory device
And an input / output changing circuit for setting two levels according to data applied to the data pins in the low power mode,
The input / output changing circuit
Output buffers for transmitting the two-level output according to data applied to the data pins; And
And input buffers for comparing each of the outputs of the output buffers with the first reference voltage. A memory cell array; And
And a page size changing circuit for changing data to be prefetched in the memory cell array in accordance with the power mode. The apparatus of claim 7, wherein the page size changing circuit
In a high performance mode, prepatching data from the memory cell array to core cycle operation # 1 prefetching data from the memory cell array,
And in a low power mode, prefetches data from the memory cell array in at least two of the core cycle operations. The apparatus of claim 7, wherein the page size changing circuit
In a high performance mode, pre-fetches data corresponding to a first burst length from the memory cell array into core cycle operation # 1 in which data is prefetched from the memory cell array,
When in the low power mode, pre-fetches data of a second burst length less than the data corresponding to the first burst length from the memory cell array in the core cycle operation # 1. 8. The method of claim 7,
Wherein the memory device includes first and second data lines coupled to the memory cell array,
The page size changing circuit
In the high performance mode, data prefetched from the memory cell array is read through the first data line and the second data line
And in the low power mode, selectively activates and reads the first data line or the second data line.

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