KR20160035443A - 3d nonvolatile semiconductor memory device, data storage device and user device using variable incremental step pulse programming - Google Patents

Abstract

Disclosed is a three-dimensional nonvolatile semiconductor memory device. The three-dimensional nonvolatile semiconductor memory device variably generates an intensity of a program voltage according to a position of a selection word line in a nonvolatile memory device having a three-dimensional vertical channel layer structure to perform a program operation to increase program performance.

Description

TECHNICAL FIELD [0001] The present invention relates to a three-dimensional nonvolatile semiconductor memory device, a data storage device, and a user device for performing a program using a variable ISPP method,

The present invention relates to a three-dimensional nonvolatile semiconductor memory device, and more particularly, to a three-dimensional nonvolatile semiconductor memory device that variably generates a magnitude of a program voltage according to a position of a selected word line, a data storage device, will be.

Semiconductor memory devices are storage devices that store data and can be read when needed. Such a semiconductor memory device is roughly classified into a random access memory (RAM) and a read only memory (ROM).

Data stored in the RAM is lost when the power supply is interrupted. This type of memory is called volatile memory. Such a volatile semiconductor memory device has a drawback in that the stored contents disappear if the external power supply is cut off although the reading and writing speed is fast. On the other hand, the data stored in the ROM is not destroyed even if the power supply is interrupted. This type of memory is called nonvolatile memory. Therefore, a nonvolatile memory device is used to store contents that should be stored regardless of whether power is supplied or not.

Non-volatile memory devices include, but are not limited to, mask read-only memory (MROM), programmable read only memory (PROM), erasable programmable read-only memory (EPROM) And electrically erasable programmable read-only memory (EEPROM). Among them, MROM, PROM and EPROM are not free to erase and write on the system itself, and it is not easy for general users to update the memory contents. On the other hand, since the above EEPROM can be electrically erased and written, application to system programming or an auxiliary memory device which is continuously updated is expanding. In particular, flash memory has a higher integration density than conventional EEPROMs, which is very advantageous for application as a large capacity auxiliary memory device. Among NAND-type flash memories, NAND-type flash memories have a high degree of integration.

A flash memory device which is a nonvolatile memory device has a feature in which writing and erasing of data are electrically performed. The memory cells of the flash memory device are composed of a plurality of blocks, and each block is composed of a plurality of pages. In particular, a block is a minimum unit for erasing data stored in a memory cell.

The flash memory device utilizes a hot carrier effect in which a hot carrier having a tunneling effect and a high kinetic energy pass through a high energy barrier during a program operation or an erase operation.

When programming such a flash memory device, a pass voltage (Vpass) is applied to the program inhibit word line while a program voltage (Vpgm) is applied to the word line to be programmed. More specifically, the program voltage Vpgm and the pass voltage Vpass generated in the voltage supply unit are applied to the global word line, and the voltage applied to the global word line through the block switch driven by the block selection signal becomes the local word Line.

On the other hand, recently, as the degree of integration of a non-volatile semiconductor memory device having a two-dimensional structure for forming memory cells in a single layer on a semiconductor substrate has reached a limit, a plurality of memory cells are formed along a channel layer projecting vertically from the semiconductor substrate A nonvolatile memory device having a three-dimensional structure has been proposed.

Such a three-dimensional nonvolatile semiconductor memory device is classified into a structure having a straight channel layer and a structure having a U-type channel layer. A structure having a straight channel layer has bit lines and source lines disposed at the top and bottom of the stacked memory cells, respectively. The structure having the U-type channel layer is a structure in which both the bit line and the source line are disposed on the stacked memory cell. Such a structure having a U-type channel layer is advantageous in terms of integration because only one select gate is required.

However, in the case of a nonvolatile semiconductor memory device having such a three-dimensional structure, there is a difference in program speed between the upper word line and the lower word line, and the overall program speed is slowed by the difference in speed.

For example, when forming the channel layer by etching the conductive layers for the word lines to form the channel layer, the diameter of the channel hole is not formed uniformly but is formed differently according to the height. That is, the diameter of the channel hole gradually decreases as it goes downward. Accordingly, the threshold voltages Vth of the corresponding cells are different from each other depending on the position (vertical position) of the stacked word lines, resulting in a difference in program speed.

An embodiment of the present invention seeks to provide a three-dimensional nonvolatile semiconductor memory device capable of increasing program performance by improving the programming speed of a nonvolatile memory device having a vertical channel layer structure.

A three-dimensional nonvolatile semiconductor memory device according to an embodiment of the present invention includes: a cell array including memory cells formed in a region where a word line and a vertical channel layer are stacked; A row decoder for applying a program voltage to selected word lines of the word lines during a program operation; A voltage generator for variably generating a magnitude of the program voltage according to a start voltage control signal and a step control signal and providing the generated program voltage to the row decoder; And a control unit for generating the start voltage control signal and the step control signal according to the position of the selected word line and outputting the generated start voltage control signal and the step control signal to the voltage generator.

A data storage device according to an embodiment of the present invention includes a cell array in which memory cells are formed in a region where a word line and a vertical channel layer are stacked, A memory device for generating a program voltage of a different magnitude for each position of a selected word line to perform the program operation; And a controller for decoding the command applied from the host and controlling the program operation of the memory device according to the decoded result, and generating the start voltage control signal in accordance with the position of the selected word line during the program operation and transmitting the start voltage control signal to the memory device Memory controller.

A user apparatus according to an embodiment of the present invention includes a data storage device including at least one memory chip in which memory cells are formed in a region where a word line and a vertical channel layer are crossed; And a host for controlling operation of the data storage device, wherein the data storage device provides location information for a selected word line to the host during a program operation for the memory chip, A program voltage can be generated by generating a program voltage having a different magnitude according to the start voltage control signal.

Embodiments of the present invention can increase program performance by improving the program speed of a non-volatile memory device having a vertical channel layer.

1 is a configuration diagram showing a configuration of a three-dimensional nonvolatile semiconductor memory device according to an embodiment of the present invention;
FIG. 2A is a sectional view schematically showing a structure in which the memory cell array of FIG. 1 according to the present embodiment has a U-shaped channel layer; FIG.
FIG. 2B is a cross-sectional view schematically showing a structure in which the memory cell array of FIG. 1 has a straight channel layer according to the present embodiment; FIG.
FIG. 3 is a view showing a program voltage variable according to a variable ISPP method according to an embodiment of the present invention; FIG.
FIG. 4A is a diagrammatic representation of a threshold voltage distribution of memory cells according to the location of the word lines in the cell array structure of FIG. 2A; FIG.
4B is a diagrammatic representation of a threshold voltage distribution of memory cells according to the location of the word lines in the cell array structure of Fig. 2B. Fig.
FIG. 5 is a view showing a program voltage variable according to a variable ISPP method according to another embodiment of the present invention; FIG.
FIG. 6 is a view showing a program voltage variable according to a variable ISPP method according to another embodiment of the present invention; FIG.
FIG. 7 is a block diagram schematically showing a configuration of a data storage device according to an embodiment of the present invention; FIG.
8 is a configuration diagram briefly showing a configuration of a user apparatus according to an embodiment of the present invention;

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a configuration diagram showing a configuration of a three-dimensional nonvolatile semiconductor memory device according to an embodiment of the present invention.

The three dimensional nonvolatile memory device 100 according to the present embodiment includes a memory cell array 110, a row decoder 120, a page buffer 130, a voltage generator 140, controller 150.

The memory cell array 110 includes a plurality of pages PG0 to PGn including memory cells MC0 to MCn connected to word lines WL0 to WLn and bit lines BL0 to BLn. At this time, the memory cell array 110 is formed in a three-dimensional structure in which memory cells are formed in a region where vertically stacked word lines WL0 to WLn and a vertical channel layer are crossed. For example, the memory cell array 110 may be formed in a three-dimensional structure having a U-shaped channel layer in which the bit line BL and the source line CSL are located on top of the memory cell, as shown in FIG. 2A. Alternatively, the memory cell array 110 may be formed in a three-dimensional structure having a bit line BL located on the upper portion of the memory cell and a source line CSL located on the lower portion of the memory cell, as shown in FIG. 2B. Drain select transistors DST0 to DSTn are formed between the cell strings connected in series with the memory cells MC0 to MCn and the bit lines BL0 to BLn and source select transistors SST0 to SSTn are formed between the cell strings and the common source line CSL .

The row decoder 120 decodes a row address X-ADDR during a program operation for the memory cell array 110 and outputs the word line X-ADDR received from the voltage generator 110 according to the decoded row address, (E.g., a program voltage Vpgm, a pass voltage Vpass) to the word lines WL0 to WLn of the memory cell array 110. [

The page buffer 130 is connected to the bit lines BL0 to BLn of the memory cell array 110 and stores data read from the memory cell array 110. [ In addition, the page buffer 130 stores data to be written to the memory cell array 110 through the bit lines BL0 to BLn.

The voltage generator 140 generates word line voltages (a program voltage, a pass voltage, and a read voltage) under the control of the controller 150 and provides them to the row decoder 120. For example, the voltage generator 140 generates the program voltage Vpgm and the pass voltage Vpass according to the step control signal STEP and the start voltage control signal SVC received from the controller 150 and provides the program voltage Vpgm and the pass voltage Vpass to the row decoder 120. At this time, the program voltage Vpgm is generated according to an incremental step pulse programming (ISPP) method. For example, the voltage generator 140 first generates a start bias corresponding to the selected word line and provides it to the row decoder 120, and gradually raises the program voltage by a predetermined step voltage? Vispp in accordance with the program loop To the row decoder (120). At this time, the voltage generator 140 according to the present embodiment variably generates the program start voltage according to the start voltage control signal SVC provided from the controller 150, and provides the variable voltage to the row decoder 120. Alternatively, the voltage generator 140 variably generates both the magnitude of the program start voltage and the magnitude of the step voltage? Vispp according to the start voltage control signal SVC. The program voltage generating method according to the variable ISSP scheme according to this embodiment will be described in detail later.

The control unit 150 controls the overall operation of the memory device 100, such as program, erase and read operations. For example, the control unit 140 controls the page buffer 130 and the voltage generator 140 so that the program voltage Vpgm is applied to the selected word line and the pass voltage Vpass is applied to the unselected word lines do. In particular, the control unit 150 generates a start voltage control signal SVC for controlling the magnitude of the program start voltage according to the ISSP scheme and a step control signal STEP for controlling the number of times of generation of the program voltage, and outputs the generated step control signal STEP to the voltage generator 140 . At this time, the start voltage control signal SVC is a signal indicating the magnitude of the program start voltage to be applied to the corresponding word line according to the position (stacked height) of the selected word line. For example, the control unit 150 may decode the row address X-ADDR to determine the position (height) of the selected word line, and then generate the start voltage control signal SVC corresponding to the position.

FIG. 3 is a view showing a program voltage variable according to a variable ISPP method according to an embodiment of the present invention. Referring to FIG.

The program operation according to the variable ISPP scheme in the three-dimensional nonvolatile semiconductor memory device having the structure of FIG. 1 and FIG. 2 will be described with reference to FIG.

In a three-dimensional semiconductor memory device having a vertical channel layer, threshold voltages Vth of memory cells are formed differently according to the positions (heights) of the memory cells.

For example, the threshold voltages of the memory cells corresponding to the top word line WL0 are the largest, and the threshold voltages of the memory cells corresponding to the bottom word line WLk are the smallest. This is because, when forming a channel hole in which a vertical channel layer is to be formed by etching a large number of conductive layers for word lines and an insulating layer sequentially stacked in a vertical direction, the diameter of the channel hole can not be formed uniformly.

Accordingly, in the three-dimensional memory cell array having the U-type channel layer as shown in FIG. 2A and the three-dimensional memory cell array having the linear channel layer as shown in FIG. 2B, the threshold voltage of the memory cells constituting one string 4A and 4B, respectively, when the size is continuously represented according to the position (height) of the memory cell. At this time, the slope value may vary according to the structure of the memory cell array 110 (for example, the number of stacked word lines) and can be known through a test process for the semiconductor memory device 100.

Therefore, in order to match the programming speed of the vertically stacked memory cells along the vertical channel layer, the programming voltage applied to the corresponding word line in accordance with the position (height) of the word line, reflecting the slope value in FIG. 4A or 4B The size needs to be applied differently. For example, as the word line is closer to the uppermost word line, a relatively higher program voltage is applied to the word lines, and a lower program voltage is applied to a lower word line.

For this, in the present embodiment, when the row address X-ADDR is applied, the controller 150 decodes the row address to determine the position (height) of the selected word line.

When the position of the selected word line is determined, the controller 150 generates a start voltage control signal STEP indicating the magnitude of the program start voltage corresponding to the word line, together with a step control signal STEP for controlling the number of times of generation of the program voltage according to the ISPP scheme, And outputs the SVC to the voltage generator 140. For example, the control unit 150 generates the start voltage control signal SVC corresponding to the selected word line by reflecting the slope of FIG. 4A or FIG. 4B.

The voltage generator 140 receiving the step control signal STEP and the start voltage control signal SVC generates a program start voltage having a magnitude corresponding to the received start voltage control signal SVC and outputs it to the row decoder 120. That is, the voltage generator 140 generates a program start voltage having a different magnitude corresponding to the position (height) of the selected word line according to the start voltage control signal SVC and provides it to the row decoder 120.

For example, the voltage generator 140 generates Vpgm_s0 as a program start voltage if the start voltage control signal SVC is a signal corresponding to the most significant word lines WL0, WLn. The voltage generator 140 generates Vpgm_sk as a program start voltage if the start voltage control signal SVC is a signal corresponding to the lowermost word line WLk WLk + 1. If the start voltage control signal SVC is a signal corresponding to the word lines WLi and WLm between the most significant word line and the least significant word line, the voltage generator 140 may reflect the inclination of FIG. 4A or 4B and correspond to the corresponding position And generates a program start voltage Vpgm_si. At this time, the magnitudes of the program start voltages Vpgm_s0, Vpgm_si, and Vpgm_sk have the following relationship.

Vpgm_s0>Vpgm_si> Vpgm_sk

Also, the voltage generator 140 generates a pass voltage Vpass for the unselected word lines and provides it to the row decoder 120.

Next, each time the step control signal STEP is received from the control unit 150, the voltage generator 140 sequentially generates a program voltage having a magnitude increased by the step voltage? Vispp as compared with the previous program voltage, and supplies the generated program voltage to the row decoder 120 do.

For example, the magnitudes of the program voltages Vpgm_01 and Vpgm_02 applied to the most significant word lines WL0 and WLn after the program start voltage Vpgm_s0 can be expressed by the following equations.

Vpgm_01 = Vpgm_s0 +? Vispp

Vpgm_02 = Vpgm_01 +? Vispp

Similarly, the program voltages Vpgm_i1 and Vpgm_i2 applied to the word lines WLi and WLm after the program start voltage Vpgm_si and the program voltages Vpgm_k1 and Vpgm_k2 applied to the word lines WLk and WLk + 1 after the program start voltage Vpgm_sk are also set to the program start voltage Vpgm_si , Vpgm_sk has a value obtained by sequentially increasing the step voltage? Vispp.

At this time, the step voltage? Vispp has a constant size regardless of the position of the selected word line as shown in FIG. However, the magnitude of the step voltage? Vispp can also be varied depending on the position of the selected word line.

FIG. 5 is a view illustrating a program voltage variable according to a variable ISPP method according to another embodiment of the present invention. Referring to FIG.

The step voltages? Vispp0,? Visppi, and? Visppk in FIG. 5 have a larger value as the program starting voltage is reflected in the slope of FIG. 4A or 4B and closer to the most significant word line. (? Vispp0>? Visppi>? Visppk). That is, the voltage generator 140 can vary the step voltage? Vispp according to the start voltage control signal SVC.

FIG. 6 is a view showing a program voltage variable according to a variable ISPP method according to another embodiment of the present invention. Referring to FIG.

In Fig. 5, step voltages? Vispp0,? Visppi, and? Visppk vary depending on the positions of the selected word lines, but the same applies to the same selected word lines. However, the step voltage? Vispp may also be varied for the same selected word line as in FIG. For example, the voltage generating unit 140 may gradually increase or decrease the step voltage? Vispp according to the number of times the step control signal STEP is generated.

In FIG. 1, the voltage generator 140 and the controller 150 are shown as separate components. However, the voltage generator 140 and the controller 150 may have the same configuration.

7 is a configuration diagram briefly showing a configuration of a data storage device according to an embodiment of the present invention.

The data storage device of FIG. 7 may include a memory device 1100 and a memory controller 1200.

The memory device 1100 includes at least one memory chips 100_1 to 100_4 including memory cells of a vertically stacked three-dimensional structure as shown in FIG. 2A or 2B, and in response to a request of the memory controller 1200 (Program) data from the memory controller 1200 to the memory cell or reads the recorded data and provides the read data to the memory controller 1200. At this time, the memory chips 100_1 to 100_4 may have a three-dimensional structure having a U-type channel layer as shown in FIG. 2 or a three-dimensional structure having a straight channel layer. In particular, the memory device 1100 performs a program operation according to the above-described variable ISSP scheme under the control of the memory controller 1200 during a program operation. For example, the memory device 1100 generates program start voltages of different sizes corresponding to the position of the selected word line according to the start voltage control signal SVC from the memory controller 1200, and applies the generated program start voltages to the corresponding word line. Then, the memory device 1100 sequentially applies the program voltage increased by the step voltage? Vispp to the selected word line, which is earlier than the previous program voltage. The program operation in the memory device 1100 can be performed in the same manner as the above-described variable ISSP method.

The memory controller 1200 decodes the command applied from the external device (host device) and controls the program operation and the read operation for the memory device 1100 according to the decoded result. In particular, the memory controller 1200 generates a start voltage control signal SVC indicating the magnitude of the program start voltage corresponding to the position of the selected word line during program operation, and transmits the start voltage control signal SVC to the memory device 1100.

In the embodiment of FIG. 1, the memory device (memory chip) 100 itself generates the start voltage control signal SVC. However, in the embodiment of FIG. 6, the memory controller 1200 generates the start voltage control signal SVC, To the device 1100. At this time, a step control signal STEP for controlling the number of times of generation of the program voltage may be generated in the memory device 1100 as shown in FIG.

Such a data storage device may be a solid state disk (SSD), a USB memory (Universal Serial Bus Memory), a secure digital (SD) card, a mini Secure Digital card (mSD) Card, micro SD, Secure Digital High Capacity (SDHC), Memory Stick Card, Smart Media Card (SM), Multi Media Card (MMC) An embedded multimedia card (eMMC), a compact flash (CF) card, and the like.

8 is a configuration diagram briefly showing a configuration of a user apparatus according to an embodiment of the present invention.

The user device of FIG. 8 includes a data storage device 1000 and a host 2000.

The data storage device 1000 stores data from the host 2000 in response to a request from the host 2000, reads the stored data, and provides the data to the host 2000. The data storage device 1000 includes a memory device 1100 and a host 2000 including at least one memory chips 100_1 through 100_4 formed with vertically stacked three-dimensional memory cells as shown in FIG. 2A or 2B. And a memory controller 1300 that controls the program operation and the read operation for the memory device 1100 in response to a request from the memory controller 1100. Particularly, the data storage device 1000 performs a program operation according to the variable ISSP method described above under the control of the host 2000 in the program operation. For example, the memory controller 1300 of the data storage apparatus 1000 may transmit positional information on the position of the selected word line to the host 200 during a program operation, and may receive a start voltage control signal SVC, and performs the program operation according to the variable ISSP method described above. At this time, a step control signal STEP for controlling the number of times of generation of the program voltage may be generated in the memory device 1100 as shown in FIG.

The host 2000 controls the operation of the data storage device 1000. In particular, when the host 2000 receives the positional information from the data storage device 1000, it generates the start voltage control signal SVC corresponding to the positional information by reflecting the inclination in FIG. 4A or 4B, .

Such a user device may be a mobile phone, a smart phone, a tablet computer, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, such as a portable multimedia player (PDN), a personal navigation device or portable navigation device (PDN), a handheld game console, or an e-book, Device (handheld device). Further, the user device may be embodied as an embedded system for performing a specific function in an automobile, a ship, or the like.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It should be regarded as belonging to the claims.

100: 3D nonvolatile memory device 110: Memory cell array
120: row decoder 130: page buffer
140: voltage generator 150:
1000: data storage device 1100: memory device
1200, 1300: memory controller 2000: host

Claims (26)

A cell array including memory cells formed in a region where the stacked word lines and the vertical channel layer intersect;
A row decoder for applying a program voltage to selected word lines of the word lines during a program operation;
A voltage generator for variably generating a magnitude of the program voltage according to a start voltage control signal and a step control signal and providing the generated program voltage to the row decoder; And
And a control unit for generating the start voltage control signal and the step control signal according to the position of the selected word line and outputting the generated start voltage control signal and the step control signal to the voltage generator. 2. The cell array according to claim 1,
A three-dimensional structure having a bit line and a U-type channel layer in which a source line is located above the memory cells, or a three-dimensional structure in which bit lines and source lines each have a linear channel layer located above and below the memory cells, Dimensional nonvolatile semiconductor memory device. 2. The apparatus of claim 1, wherein the voltage generator
Wherein the programmable voltage generation unit variably generates a program start voltage of the program voltage according to the start voltage control signal. 4. The apparatus of claim 3, wherein the control unit
And controlling the program start voltage to be gradually increased as the selected word line is closer to the top word line so that the program start voltage gradually decreases as the selected word line approaches the lowest word line Dimensional non-volatile semiconductor memory device according to claim 1, 4. The apparatus of claim 3, wherein the voltage generator
And sequentially generates a voltage in which the program start voltage is stepped up by a step voltage in accordance with the step control signal, and provides the voltage to the row decoder. 6. The apparatus of claim 5, wherein the voltage generator
Dimensional nonvolatile semiconductor memory device according to claim 1, wherein the step voltage generating circuit generates the step voltage of the same size for all selected word lines. 6. The apparatus of claim 5, wherein the voltage generator
Dimensional nonvolatile semiconductor memory device according to claim 1, wherein the step voltage generating circuit generates the step voltage of different magnitudes according to the position of the selected word line by using the start voltage control signal. 8. The apparatus of claim 7, wherein the voltage generator
The step voltage is gradually increased as the selected word line is closer to the top word line and the step voltage is gradually made smaller as the selected word line is closer to the lowest word line. Dimensional nonvolatile semiconductor memory device. 9. The apparatus of claim 8, wherein the voltage generator
And the step voltage is gradually increased or decreased in accordance with the number of times the step control signal is generated. The apparatus of claim 1, wherein the control unit
And decodes the row address to determine the position of the selected word line. And a memory cell array in which memory cells are formed in a region where the word lines and the vertical channel layers intersect with each other, wherein a program voltage of a different magnitude for each position of the selected word line in accordance with a start voltage control signal during a program operation for the memory cells To perform the program operation; And
A memory for decoding a command applied from a host and controlling a program operation of the memory device according to a decoded result and generating the start voltage control signal according to a position of the selected word line in the program operation, A data storage device comprising a controller. 12. The memory device of claim 11, wherein the memory device
Wherein the control unit variably generates the program start voltage of the program voltage according to the start voltage control signal. 13. The apparatus of claim 12, wherein the memory controller
And controlling the program start voltage to be gradually increased as the selected word line is closer to the top word line so that the program start voltage gradually decreases as the selected word line approaches the lowest word line And generates said start voltage control signal for controlling said start voltage control signal. 12. The apparatus of claim 11, wherein the memory device
And sequentially generates a program voltage in which the program start voltage is stepped up stepwise by a step voltage according to a step control signal to perform the program operation. 15. The memory device of claim 14, wherein the memory device
And generates a step voltage of the same magnitude for all selected word lines. 15. The memory device of claim 14, wherein the memory device
And generates a step voltage of a different magnitude according to a position of the selected word line by using the start voltage control signal. 17. The memory device of claim 16, wherein the memory device
The step voltage is gradually increased as the selected word line is closer to the top word line and the step voltage is gradually made smaller as the selected word line is closer to the lowest word line. Lt; / RTI > 18. The memory device of claim 17, wherein the memory device
And the step voltage is gradually increased or decreased in accordance with the number of times the step control signal is generated. A data storage device including at least one memory chip in which memory cells are formed in an area where the stacked word lines and the vertical channel layer intersect; And
And a host for controlling operation of the data storage device,
The data storage device
Wherein the controller is configured to provide the host with positional information about a selected word line during a program operation of the memory chip to receive a start voltage control signal corresponding to the positional information from the host, And generating a voltage to perform the program operation. 20. The apparatus of claim 19, wherein the data storage device
And generates a program start voltage of the program voltage variable according to the start voltage control signal. 21. The system of claim 20, wherein the host
And controlling the program start voltage to be gradually increased as the selected word line is closer to the top word line so that the program start voltage gradually decreases as the selected word line approaches the lowest word line And generates the start voltage control signal to control the start voltage control signal. 21. The system of claim 20, wherein the data storage device
And sequentially generates a program voltage in which the program start voltage is stepped up stepwise by a step voltage according to a step control signal to perform the program operation. 23. The apparatus of claim 22, wherein the data storage device
And generates a step voltage of the same magnitude for all selected word lines. 23. The apparatus of claim 22, wherein the data storage device
And generates a step voltage of a different magnitude according to a position of the selected word line by using the start voltage control signal. 25. The system of claim 24, wherein the data storage device
The step voltage is gradually increased as the selected word line is closer to the top word line and the step voltage is gradually made smaller as the selected word line is closer to the lowest word line. Lt; / RTI > 26. The system of claim 25, wherein the data storage device
And the step voltage is gradually increased or decreased in accordance with the number of times the step control signal is generated.

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