KR20160034459A - Organic Light Emitting Display Capable Of Reducing Image Sticking - Google Patents

Abstract

The present invention relates to an organic light emitting display device capable of preventing an asymmetry phenomenon of a displayed image when an image shift technology for reducing image sticking is performed. According to the present invention, the organic light emitting display device comprises a display panel (10) and an image sticking reduction circuit (20). The image sticking reduction circuit (20) shifts an image displayed on the display panel (10) in a first direction up to a pre-determined pixel unit according to an image shift enable (ISE) signal. In addition, the image sticking reduction circuit (20) substitutes a first boundary unit of the displayed image corresponding to the first direction, and a second boundary unit of the displayed image corresponding to a second direction opposite to the first direction, with black image data up to the pre-determined pixel unit.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic light-

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly to an organic light emitting display device capable of reducing a residual image.

Flat panel displays (FPDs) are used in various types of electronic products including mobile phones, tablet PCs, and notebook computers.

Among the flat panel display devices, the organic light emitting display device is a self-luminous device that emits an organic light emitting layer by recombination of electrons and holes, and is expected to be a next generation display device because it has a high luminance, a low driving voltage and an ultra thin film. Each of the plurality of pixels constituting the organic light emitting diode display device includes an organic light emitting diode (OLED), which is a light emitting device composed of an anode electrode, a cathode electrode, and an organic light emitting layer formed therebetween, And a pixel circuit for driving the pixel circuit. The pixel circuit mainly includes a switching thin film transistor (hereinafter referred to as TFT), a storage capacitor, and a driving element (driving TFT). The switching TFT charges a data voltage in a capacitor in response to a scan signal, and the driving TFT controls a magnitude of a current supplied to the OLED according to the magnitude of a voltage charged in the capacitor, thereby adjusting an amount of light emitted from the OLED. The amount of light emission of the OLED is proportional to the current supplied from the driving TFT.

Such an organic light emitting display device may display a fixed pattern for a long time or a persistent afterimage due to deterioration of an OLED element in a portion where an average brightness is higher than other regions of an image such as a portion where a logo of a broadcasting station is displayed. In order to solve this problem, there is known a technique of shifting a display image every time a scene change occurs or at a preset time interval.

FIG. 1 illustrates a conventional image shift technique. Referring to FIG. 1, the conventional image shift technique shifts a display image according to a predetermined shift direction, and processes a black image of a portion where input image data is not displayed due to a shift, that is, an image boundary portion in a shift direction. Therefore, according to the conventional image shifting technique, image asymmetry occurs in the left / right or upper / lower display portions of the display image. If asymmetry occurs in the displayed image when implementing the image shift for reducing the afterimage, the image shifting is easily visible to the user.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an organic light emitting display device capable of preventing an asymmetric phenomenon of a display image when implementing a video shift technique for reducing afterimage.

In order to achieve the above object, the present invention includes a display panel 10 and a residual image reduction circuit 20. The residual image reduction circuit 20 generates a residual image reduction circuit 20 based on the image shift enable signal ISE, Wherein the display image is shifted by a predetermined pixel interval in a first direction, and the display image is shifted in a first direction corresponding to a first boundary of the display image corresponding to the first direction and a second direction opposite to the first direction, 2 boundary portions are replaced with black image data by the predetermined pixel interval.

The residual image reduction circuit 20 includes a display start point generator 22 for generating a display start point in consideration of a preset horizontal movement amount HS and a vertical movement amount VS when the image shift enable signal ISE is inputted, A display image shifting unit 24 for delaying the input image data RGB in accordance with the display start point and outputting shifted image data R'G'B 'shifted in the first direction by the predetermined pixel interval, And outputs the horizontal selection signal by comparing the pixel count value PC counted with the pixel number and the horizontal shift amount HS and compares the vertical shift amount VS with the line count value LC that counts the number of lines (R'G'B ') on the basis of the horizontal selection signal and the vertical selection signal to output a vertical selection signal to the first boundary portion of the display image And a second boundary portion And a cutting edge portion 28 to displace.

The window setting unit 26 sets the horizontal selection signal to a low logic level when the pixel count value PC is equal to or less than the horizontal movement amount HS or is equal to or larger than a value obtained by subtracting the horizontal movement amount HS from the horizontal resolution When the line count value LC is equal to or less than the vertical movement amount VS or is equal to or larger than a value obtained by subtracting the vertical movement amount VS from the vertical resolution, And outputs the selection signal as a low logic level and otherwise outputs the vertical selection signal as a high logic level. The edge cutting unit 28 outputs the selection signal only when the horizontal selection signal and the vertical selection signal are both at a high logic level Shift image data R'G'B 'as modulated image data RmGmBm, and when at least one of the horizontal selection signal and the vertical selection signal is at a low logic level And it outputs the black image data to the modulated video data (RmGmBm).

The residual image reduction circuit 20 includes a display start point generator 122 for generating a display start point in consideration of a preset horizontal movement amount HS and a vertical movement amount VS when the image shift enable signal ISE is input, And outputs the horizontal selection signal by comparing the pixel count value PC counted by the number of pixels and the horizontal shift amount HS and outputs the horizontal count value LC and the vertical movement amount VS, And a second selector for selecting one of the first and second video signals based on the horizontal selection signal and the vertical selection signal, An edge cutting unit 126 for outputting the selected image data RcGcBc substituted with the selected image data RcGcBc by modulating the synchronization signals in accordance with the display start point and shifting the selected image data RcGcBc in the first direction And Kim and as well as a display image shift unit 128 to the substitution with the black image data for the second boundary of the display image.

The window setting unit 124 outputs the horizontal selection signal as a low logic level when the pixel count PC is equal to or larger than a horizontal resolution minus the horizontal shift amount HS * And outputs the vertical selection signal as a low logic level when the line count value LC is equal to or greater than a value obtained by subtracting the vertical movement amount VS from the vertical resolution, The edge cutting unit 126 outputs the input image data RGB as the selected image data RcGcBc only when the horizontal selection signal and the vertical selection signal are both at a high logic level, And outputs the black image data as the selected image data (RcGcBc) when at least one of the horizontal selection signal and the vertical selection signal is at a low logic level, The first display image shifting unit 128 shifts the selected image data RcGcBc in the first direction by the predetermined pixel interval so that the first and second boundaries of the display image are shifted to the black image data And outputs the substituted modulated image data (RmGmBm).

The present invention replaces not only the direction opposite to the shift but also the boundary of the display area corresponding to the shift direction with a black image. Accordingly, when the image shift technique for reducing afterimage is implemented, asymmetric phenomenon of the display image can be prevented, and the display quality can be remarkably increased.

1 is a view showing a conventional image shift technique.
2 is a block diagram showing an organic light emitting diode display of the present invention.
3 is a view illustrating a video shift result screen according to the present invention in comparison with a conventional one.
4 is a flowchart illustrating a video shift concept according to an embodiment of the present invention;
FIG. 5 is a view showing a display image corresponding to each step of FIG. 4;
Fig. 6 schematically shows a configuration of a residual image reduction circuit embodying Fig. 4; Fig.
7 is a view showing a detailed configuration of Fig.
FIGS. 8 and 9 are diagrams for explaining the pixel counter operation of FIG. 7; FIG.
FIGS. 10 to 15 are diagrams for explaining the operation of the line counter of FIG. 7;
16 is a flowchart showing a video shift concept according to another embodiment of the present invention;
Fig. 17 is a view showing a display image corresponding to each step of Fig. 16; Fig.
FIG. 18 is a view schematically showing the configuration of a residual image reduction circuit embodying FIG. 16. FIG.
19 is a view showing a detailed configuration of FIG. 18;

Hereinafter, a preferred embodiment of the present invention will be described with reference to FIG. 2 to FIG.

2 is a block diagram showing an organic light emitting diode display of the present invention. 3 is a diagram illustrating a video shift result screen according to the present invention in comparison with a conventional one.

Referring to FIG. 2, the OLED display includes a display panel 10, a timing controller 11, a data driving circuit 12, a gate driving circuit 13, and a residual image reducing circuit 20 according to the present invention.

In the display panel 10, a plurality of data lines 15 and a plurality of gate lines 16 are intersected, and pixels are arranged in a matrix form in each of the intersection areas. Each pixel has an OLED and a pixel circuit. The pixel circuit includes a driver TFT (DT) for controlling the amount of current flowing through the OLED and a switching portion (SC) for programming the gate-source voltage of the driver TFT (DT). The switching unit SC may include at least one switch TFT and a storage capacitor. The switch TFT is turned on in response to a scan signal from the gate line 16, thereby charging the data voltage from the data line 15 to one electrode of the storage capacitor. The driving TFT controls the amount of current supplied to the OLED according to the magnitude of the voltage charged in the storage capacitor to control the amount of light emitted from the OLED. The amount of light emission of the OLED is proportional to the current supplied from the driving TFT. These pixels are supplied with a high potential power source (EVDD) and a low potential power source (EVSS) from a power source not shown. The TFTs constituting the pixel may be implemented as a p-type or an n-type. In addition, the semiconductor layer of the TFTs constituting the pixel may include amorphous silicon, polysilicon, or an oxide.

The timing controller 11 receives digital video data RGB of an input image from the host system 14 through an interface circuit (not shown) and outputs the digital video data RGB of the input image to a residual image reduction circuit 20, And supplies the modulated image data (RmGmBm) from the residual image reduction circuit 20 to the data mapping circuit 12 through a mini-LVDS interface method or the like.

The timing controller 11 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a dot clock CLK from the host system 14, And generates control signals for controlling the operation timing of the drive circuit 12 and the gate drive circuit 13. [ The control signals include a gate timing control signal GDC for controlling the operation timing of the gate drive circuit 13 and a source timing control signal DDC for controlling the operation timing of the data drive circuit 12. [ In some cases, the gate timing control signal GDC and the source timing control signal DDC may be modulated in the afterimage reducing circuit 20. [

The data driving circuit 12 converts the modulated image data RmGmBm into a data voltage in accordance with the data control signal DDC from the timing controller 11 and supplies the data voltage to the data lines 15. [

The gate drive circuit 13 generates a scan signal in accordance with the gate control signal GDC from the timing controller 11 and supplies the scan signal to the gate lines 16 in a line sequential manner.

The residual image reduction circuit 20 can be incorporated in the timing controller 11 and receives the image shift enable signal ISE from the host system 14. [ The video shift enable signal ISE is a control signal for activating the display image shift operation, and can be input at every preset scene change or at a predetermined time interval, where the amount of change of the inter-frame video is equal to or greater than a preset threshold value. The residual image reduction circuit 20 shifts the display image displayed on the display panel 10 in the first direction by a predetermined pixel interval as shown in FIG. 3 (B) (Right and lower boundary portions) of the display image corresponding to the first boundary portion (left and upper boundary portion) of the display image and the second direction opposite to the first direction are replaced with the black image data by the predetermined pixel interval . Although the first and second directions are shown only in a diagonal direction opposite to each other, the technical idea of the present invention is not limited to this, and may be applied to a case where the first direction and the second direction are horizontally opposite to each other, Vertical direction.

In the conventional image shift technique shown in FIG. 3A, the display image is viewed asymmetrically by black image processing of only the image boundary portion in the direction opposite the shift. 55 inches FHD (Full HD) Maximum 6 pixels / 1920 pixels = 3.8 mm when the display image is set to shift by a maximum of ± 6 pixels with respect to the display panel. However, in recent borderless and narrow bezel designs, 3.8mm is a non-negligible width. For example, in the case of FIG. 3A, a deviation of about 4 mm between the left border area of the screen including the bezel BZ and the right border area of the screen may be generated. May be offensive to the user.

Therefore, as shown in FIG. 3 (B), the present invention replaces not only the direction opposite to the shift but also the boundary of the display area corresponding to the shift direction with a black image at the time of image shifting, Resolves image asymmetry.

FIG. 4 is a flowchart illustrating an image shift concept according to an embodiment of the present invention, and FIG. 5 shows a display image corresponding to each step of FIG.

4 and 5, a video shift method according to an embodiment of the present invention is implemented through delay control of a video signal without changing a sync signal, and includes a step of inputting a display image S1, (S2) of shifting the display image in accordance with the enable signal (ISE), an edge cutting step (S3) of replacing the boundary of the display image with black image data so that the symmetry of the shifted display image is maintained, And outputting data (S4).

In the step S2 of shifting the display image, the display image is shifted in consideration of the horizontal movement amount HS and the vertical movement amount VS set in advance.

In the edge cut step S3, the second border portion (hatched portion) of the display image corresponding to the second direction opposite to the shift direction is determined as the black image data replacement area. Then, the first border portions (2HS, 2VS) of the display image corresponding to the first direction, which is the shift direction, are cut out, and a part of the cut-out region is determined as the black image data replacement region. Subsequently, in the edge cut step S3, the first and second boundaries of the display image determined as the black image data replacement area are replaced with black image data.

Fig. 6 schematically shows the configuration of the afterimage reduction circuit 20 implementing Fig. 4, and Fig. 7 shows the detailed configuration of Fig. FIGS. 8 and 9 are diagrams for explaining the operation of the pixel counter 26A of FIG. FIGS. 10 to 15 are diagrams for explaining the operation of the line counter 26B of FIG.

6 and 7, a residual image reduction circuit 20 according to an embodiment of the present invention includes a display start point generating unit 22, a display image shifting unit 24, a window setting unit 26, (28).

The display start point generating unit 22 generates a display start point in consideration of a preset horizontal movement amount HS and a vertical movement amount VS when the video shift enable signal ISE is input from the host system 14. [

The display image shifting unit 24 delays the input image data RGB according to the display start point and outputs the shifted image data R'G'B 'shifted in the first direction by a predetermined pixel interval. To this end, the display image shifting unit 24 may include a data delay unit 24A. The data delay unit 24A delays the input image data RGB horizontally by the horizontal movement amount HS from the display start point generating unit 22 and refers to the separate line memory 24B to generate the display start point generating unit The input image data RGB can be delayed in the vertical direction by the vertical movement amount VS from the vertical movement amount detecting unit 22.

The window setting unit 26 outputs a horizontal select signal (Horizontal Enable) by comparing the pixel count value PC counted from the pixel count with the horizontal shift amount HS and outputs a line count value LC, And the vertical movement amount VS to output a vertical select signal (Vertical Enable). To this end, the window setting unit 26 includes a pixel counter 26A, a first determination unit 26C, a line counter 26B, and a second determination unit 26D.

The pixel counter 26A counts the high logic period of the data enable signal DE by the rising edge or the falling edge of the dot clock CLK and outputs the pixel count value PC as " 1 " And resets the pixel count value PC to '0' when the data enable signal DE is inverted to the low logic. The pixel count value PC is a reference for judging the horizontal display position of the image data.

The first determination unit 26C determines whether or not the pixel count value PC is equal to or smaller than the horizontal shift amount HS (PC? HS) or greater than or equal to a value obtained by subtracting the horizontal shift amount HS from the horizontal resolution ), The horizontal selection signal is outputted as a low logic level ('0') and the horizontal selection signal is outputted as a high logic level ('1') in other cases (HS <PC < do.

The line counter 26B generates a line count value LC based on internally generated line pulses and frame pulses as shown in Figs. Here, the frame pulse (c) is a difference between the inverted signal (Bar Vsync) (a) of the vertical synchronizing signal Vsync obtained through the inverter as shown in Figs. 12 and 13 and the vertical synchronizing signal Vsync Can be obtained as a result of the logical product operation between the delayed signal (b). 14 and 15, the line pulse c 'is a logical product of the data enable signal DE and the delay of the data enable signal DE obtained through the inverter and the delay and the inverted signal b' Can be obtained as an operation result. The line counter 26B counts the line pulse by the rising edge or the falling edge of the dot clock CLK to increase the line count value LC by 1 and outputs the line count value LC when the frame pulse is detected Reset to '0'. The line count value LC serves as a reference for judging the vertical display position of the image data.

The second determination unit 26D determines whether the line count value LC is equal to or smaller than the vertical movement amount VS (LC? VS) or greater than or equal to a value obtained by subtracting the vertical movement amount VS from the vertical resolution (LC? ), The vertical select signal is outputted as a low logic level ('0') while the other (VS <LC <vertical resolution -VS) is outputted as a high logic level do.

The edge cutting unit 28 includes a horizontal selection signal input from the window setting unit 26 and an AND gate for performing an AND operation of the vertical selection and generates and outputs a window enable signal as a result of the AND operation. The AND gate outputs the window enable signal to the high logic level ('1') only when both the horizontal selection signal and the vertical selection signal are at the high logic level, and otherwise outputs the window enable signal to the low logic level (' . The edge cutting unit 28 outputs the shift image data R '/ G' / B 'as the modulated image data RmGmBm only when the window enable signal is at the high logic level (' 1 '), And outputs the black image data 0/0/0 as the modulated image data RmGmBm when the enable signal is at the low logic level ('0').

FIG. 16 is a flowchart showing a video shift concept according to another embodiment of the present invention, and FIG. 17 shows a display image corresponding to each step of FIG.

16 and 17, a video shift method according to another embodiment of the present invention is realized through a delay control of a sync signal, and includes a step of inputting a display image (S10), a video shift enable signal (ISE) (S20) for selecting a portion to be processed in the display image in accordance with the display image, an edge cut step (S20) for corresponding to the shift direction (first direction) of the display image and replacing the first boundary of the display image selected in S20 with black image data S30), a display image shifting step (S40) of shifting the display image in the shift direction and replacing the second boundary portion of the display image corresponding to the direction opposite to the shifting direction (second direction) with black image data, And outputting the modulated image data (S50).

In the step S20 of selecting a part to be processed in the display image, a part to be processed in the display image (2HS, 2VS located in the first direction) is selected in consideration of the preset horizontal movement amount HS and the vertical movement amount VS do.

In the edge cutting step S30, the first boundary part 2HS, 2VS of the selected display image is cut out and the cut-out area is replaced with the black image data.

In the display image shifting step S40, the display signals are shifted in the shift direction by modulating the synchronizing signals in accordance with the display start point, and the symmetry of the shifted display image is maintained so as to correspond to the second direction opposite to the shifting direction The second boundary portion of the display image is replaced with the black image data.

Fig. 18 is a view schematically showing a configuration of a residual image reduction circuit implementing Fig. 16. Fig. 19 is a view showing a detailed configuration of Fig.

18 and 19, the afterimage reducing circuit 20 according to another embodiment of the present invention includes a display start point generating unit 122, a window setting unit 124, an edge cutting unit 126, (128).

The display start point generating unit 122 generates a display start point in consideration of a preset horizontal movement amount HS and a vertical movement amount VS when the video shift enable signal ISE is input from the host system 14. [

The window setting unit 124 outputs a horizontal select signal (Horizontal Enable) by comparing the pixel count value PC counted from the pixel count with the horizontal shift amount HS and outputs a line count value LC, And the vertical movement amount VS to output a vertical select signal (Vertical Enable). To this end, the window setting unit 124 includes a pixel counter 124A, a first determination unit 124C, a line counter 124B, and a second determination unit 124D.

The pixel counter 124A counts the high logic period of the data enable signal DE by the rising edge or the falling edge of the dot clock CLK and outputs the pixel count value PC as &quot; 1 &quot; And resets the pixel count value PC to '0' when the data enable signal DE is inverted to the low logic. The pixel count value PC is a reference for judging the horizontal display position of the image data.

The first determination unit 124C may set the horizontal selection signal to a low logic level when the pixel count value PC is equal to or larger than a value obtained by subtracting the horizontal shift amount HS * ('0'), and outputs the horizontal selection signal as a high logic level ('1') to others (PC <horizontal resolution -2 * HS).

The line counter 124B generates the line count value LC based on internally generated line pulses and frame pulses as shown in Figs. Here, the frame pulse (c) is a difference between the inverted signal (Bar Vsync) (a) of the vertical synchronizing signal Vsync obtained through the inverter as shown in Figs. 12 and 13 and the vertical synchronizing signal Vsync Can be obtained as a result of the logical product operation between the delayed signal (b). 14 and 15, the line pulse c 'is a logical product of the data enable signal DE and the delay of the data enable signal DE obtained through the inverter and the delay and the inverted signal b' Can be obtained as an operation result. The line counter 26B counts the line pulse by the rising edge or the falling edge of the dot clock CLK to increase the line count value LC by 1 and outputs the line count value LC when the frame pulse is detected Reset to '0'. The line count value LC serves as a reference for judging the vertical display position of the image data.

The second determination unit 124D determines that the vertical select signal Vertical Enable is equal to or greater than a value obtained by subtracting the vertical movement amount VS * 2 from the vertical resolution by the line count value LC And outputs the vertical selection signal as a high logic level ('1') at the low logic level ('0') and others (LC <vertical resolution -2 * VS).

The edge cutting unit 126 processes the input image data RGB based on the horizontal selection signal and the vertical selection signal input from the window setting unit 124 so that the first boundary of the display image is the black image data 0 / 0/0), and outputs the selected image data Rc / Gc / Bc. The edge cutting unit 126 outputs the input image data RGB as the selected image data Rc / Gc / Bc only when the horizontal selection signal and the vertical selection signal are all at the high logic level ('1'), (0/0) to the selected video data (Rc / Gc / Bc) when at least one of the selection signal and the vertical selection signal is a low logic level ('0').

The display image shifting unit 128 modulates (delays) the synchronizing signals according to the display start point and aligns the image data in accordance with the delay so that the selected image data Rc / Gc / Bc is shifted in the first direction And the second boundary portion of the display image is replaced with the black image data (0/0/0). The display image shifting unit 128 shifts the selected image data Rc / Gc / Bc in the first direction by the predetermined pixel interval so that the first and second boundaries of the display image are shifted to the black And outputs the modulated image data RmGmBm substituted with the image data 0/0/0.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Timing controller
12: data driving circuit 13: gate driving circuit
20: afterimage reduction circuit

Claims (5)

A display panel (10); And
The display image displayed on the display panel (10) is shifted in a first direction by a predetermined pixel interval according to a video shift enable signal (ISE), the first boundary of the display image corresponding to the first direction, And a residual image reduction circuit (20) for replacing each of the second boundaries of the display image corresponding to the second direction opposite to the one direction with black image data by the predetermined pixel interval. The method according to claim 1,
The residual image reduction circuit 20 includes:
A display start point generating unit 22 for generating a display start point in consideration of a preset horizontal movement amount HS and a vertical movement amount VS when the image shift enable signal ISE is inputted;
A display image shifting unit (24) for delaying input image data (RGB) in accordance with the display start point and outputting shifted image data (R'G'B ') shifted in the first direction by the predetermined pixel interval;
The horizontal count value LC is compared with the vertical count value VS by comparing the pixel count value PC counted with the pixel count value PC and the horizontal shift amount HS to output a horizontal selection signal, A window setting unit 26 for outputting a selection signal; And
An edge cutting part for processing the shift image data (R'G'B ') based on the horizontal selection signal and the vertical selection signal and replacing the first boundary and the second boundary of the display image with the black image data, (28). &Lt; / RTI &gt; 3. The method of claim 2,
The window setting unit 26,
And outputs the horizontal selection signal as a low logic level when the pixel count value PC is equal to or less than the horizontal movement amount HS or a value obtained by subtracting the horizontal movement amount HS from the horizontal resolution, And outputs the vertical selection signal as a low logic level when the line count value LC is equal to or less than the vertical movement amount VS or equal to or greater than a value obtained by subtracting the vertical movement amount VS from the vertical resolution Otherwise outputs the vertical selection signal at a high logic level,
The edge cutting portion (28)
And outputs the shifted image data (R'G'B ') as the modulated image data (RmGmBm) only when the horizontal selection signal and the vertical selection signal are both at a high logic level, And outputs the black image data as the modulated image data (RmGmBm) when at least one of them is at a low logic level. The method according to claim 1,
The residual image reduction circuit 20 includes:
A display start point generating unit 122 for generating a display start point in consideration of a preset horizontal movement amount HS and a vertical movement amount VS when the image shift enable signal ISE is inputted;
The horizontal count value LC is compared with the vertical count value VS by comparing the pixel count value PC counted with the pixel count value PC and the horizontal shift amount HS to output a horizontal selection signal, A window setting unit 124 for outputting a selection signal;
And an edge cutting unit for processing the input image data RGB based on the horizontal selection signal and the vertical selection signal and outputting the selected image data RcGcBc in which the first boundary of the display image is replaced with the black image data 126); And
A display image shift unit for shifting the selected image data (RcGcBc) in the first direction by the predetermined pixel interval and modifying a second boundary of the display image by the black image data by modulating the synchronization signals according to the display start point, (128). &Lt; / RTI &gt; 5. The method of claim 4,
The window setting unit (124)
And outputs the horizontal selection signal as a low logic level when the pixel count value PC is equal to or greater than a value obtained by subtracting the horizontal movement amount HS * 2 from the horizontal resolution, and outputs the horizontal selection signal as a high logic level, Outputs the vertical selection signal as a low logic level when the line count value LC is equal to or greater than a value obtained by subtracting the vertical shift amount VS * 2 from the vertical resolution, and outputs the vertical selection signal as a high logic level,
The edge cutting portion 126,
And outputs the selected image data (RcGcBc) as the input image data (RGB) only when the horizontal selection signal and the vertical selection signal are at a high logic level, and at least one of the horizontal selection signal and the vertical selection signal And outputs the black image data as the selected image data (RcGcBc) at a low logic level,
The display image shifting unit (128)
(RmGmBm) obtained by shifting the selected image data (RcGcBc) in the first direction by the predetermined pixel interval so that the first and second boundaries of the display image are replaced with the black image data by the predetermined pixel interval And outputs the output signal.

Images