KR102203768B1 - Organic Light Emitting Display Capable Of Reducing Image Sticking - Google Patents

Abstract

The present invention relates to an organic light emitting display device capable of preventing asymmetry of a displayed image when implementing an image shift technology for reducing afterimages.
The present invention includes a display panel 10 and an afterimage reduction circuit 20, wherein the afterimage reduction circuit 20 generates a display image displayed on the display panel 10 according to an image shift enable signal ISE. By shifting in a first direction by a predetermined pixel interval, each of a first boundary portion of the display image corresponding to the first direction and a second boundary portion of the display image corresponding to a second direction opposite to the first direction is determined by the predetermined Black image data is replaced by pixel intervals.

Description

Organic Light Emitting Display Capable Of Reducing Image Sticking {Organic Light Emitting Display Capable Of Reducing Image Sticking}

The present invention relates to a display device, and more particularly, to an organic light emitting display device capable of reducing afterimages.

Flat panel displays (FPDs) are used in various types of electronic products, including mobile phones, tablet PCs, and notebook computers.

Among flat panel displays, an organic light emitting display device is a self-luminous device that emits an organic light emitting layer through recombination of electrons and holes, and is expected to be a next-generation display device because of its high luminance, low driving voltage, and ultra thin film. Each of the plurality of pixels constituting the organic light emitting display device independently drives the OLED and an organic light emitting diode (OLED), which is a light-emitting element composed of an anode electrode and a cathode electrode, and an organic emission layer formed therebetween. A pixel circuit to be used. The pixel circuit mainly includes a switching thin film transistor (TFT), a storage capacitor, and a driving element (driving TFT). The switching TFT charges the data voltage to the capacitor in response to the scan signal, and the driving TFT controls the amount of light emitted by the OLED by controlling the amount of current supplied to the OLED according to the amount of the voltage charged in the capacitor. The amount of light emitted by the OLED is proportional to the current supplied from the driving TFT.

In such an organic light-emitting display device, a permanent afterimage occurs due to deterioration of an OLED element in a portion having a higher average luminance than other areas of an image, such as a portion where a fixed pattern is displayed for a long time or a broadcaster logo is displayed. In order to solve this problem, a technique of shifting a display image at each scene change or at a preset time interval is known.

1 shows a conventional image shifting technique. Referring to FIG. 1, in the conventional image shifting technique, a display image is shifted according to a predetermined shift direction, and a portion in which input image data is not displayed due to the shift, that is, an image boundary portion in a direction opposite to the shift is processed as a black image. Accordingly, in the case of the conventional image shifting technique, image asymmetry occurs in left/right or upper/lower display portions of a display image. When asymmetry occurs in the displayed image when implementing image shift for reducing afterimages, the image shifting is easily recognized by the user, which is not good.

Accordingly, an object of the present invention is to provide an organic light emitting display device capable of preventing asymmetry of a display image when implementing an image shifting technique for reducing afterimages.

In order to achieve the above object, the present invention includes a display panel 10 and an afterimage reduction circuit 20, wherein the afterimage reduction circuit 20 includes the display panel 10 according to an image shift enable signal ISE. The display image displayed in is shifted in a first direction by a predetermined pixel interval, and a first boundary of the display image corresponding to the first direction and a first boundary of the display image corresponding to a second direction opposite to the first direction. 2 Each of the borders is replaced with black image data by the predetermined pixel interval.

When the image shift enable signal ISE is input, the afterimage reduction circuit 20 generates a display starting point in consideration of a preset horizontal movement amount HS and a vertical movement amount VS. ) And a display image shift unit 24 for outputting shifted image data R'G'B' shifted in the first direction by the predetermined pixel interval by delaying the input image data RGB to match the display starting point. And, a horizontal selection signal is output by comparing the pixel count value (PC) counting the number of pixels and the horizontal movement amount (HS), and comparing the line count value (LC) counting the number of lines and the vertical movement amount (VS). A window setting unit 26 that outputs a vertical selection signal and the shifted image data R'G'B' based on the horizontal selection signal and the vertical selection signal to process the first boundary of the display image And an edge cutting unit 28 for replacing the second boundary with the black image data.

The window setting unit 26 sets the horizontal selection signal to a low logic level when the pixel count value PC is less than or equal to the horizontal movement amount HS or greater than or equal to a value obtained by subtracting the horizontal movement amount HS from the horizontal resolution. The horizontal selection signal is output at a high logic level, and when the line count value (LC) is equal to or less than the vertical movement amount (VS) or greater than the value obtained by subtracting the vertical movement amount (VS) from the vertical resolution, the vertical The selection signal is output at a low logic level and the vertical selection signal is output at a high logic level, and the edge cutting unit 28, the horizontal selection signal and the vertical selection signal are both high logic levels. The shifted image data R'G'B' is output as modulated image data RmGmBm, and when at least one of the horizontal selection signal and the vertical selection signal is at a low logic level, the black image data is converted into modulated image data ( RmGmBm).

When the image shift enable signal ISE is input, the afterimage reduction circuit 20 generates a display starting point in consideration of a preset horizontal movement amount HS and a vertical movement amount VS. ), the pixel count value (PC) counting the number of pixels and the horizontal movement amount (HS) are compared to output a horizontal selection signal, and the line count value (LC) counting the number of lines and the vertical movement amount (VS) are calculated. A window setting unit 124 that compares and outputs a vertical selection signal, and processing input image data (RGB) based on the horizontal selection signal and the vertical selection signal, so that the first boundary of the display image is the black image data. An edge cutting unit 126 that outputs the selected image data RcGcBc replaced by and, by modulating synchronization signals according to the display starting point, shifts the selected image data RcGcBc in the first direction by the predetermined pixel interval. In addition, a display image shift unit 128 for replacing the second boundary of the display image with the black image data is provided.

The window setting unit 124 outputs the horizontal selection signal at a low logic level when the pixel count value PC is greater than or equal to a value obtained by subtracting the horizontal movement amount HS*2 from the horizontal resolution, and otherwise, the horizontal selection signal Is output at a high logic level, and when the line count value LC is greater than or equal to a value obtained by subtracting the vertical movement amount VS*2 from the vertical resolution, the vertical selection signal is output at a low logic level. Outputs at a high logic level, and the edge cutting unit 126 outputs the input image data RGB as the selected image data RcGcBc only when both the horizontal selection signal and the vertical selection signal are high logic levels. And, when at least one of the horizontal selection signal and the vertical selection signal is at a low logic level, the black image data is output as the selection image data (RcGcBc), and the display image shift unit 128 is the selected image data By shifting (RcGcBc) in the first direction by the predetermined pixel interval, the modulated image data RmGmBm in which the first and second boundary portions of the display image are replaced with the black image data by the predetermined pixel interval is output.

In the present invention, when the image is shifted, not only the opposite direction of the shift but also the boundary of the display area corresponding to the shift direction is replaced with a black image. Through this, the present invention can significantly improve display quality by preventing asymmetry of a display image when implementing an image shifting technique for reducing afterimages.

1 is a diagram showing a conventional image shifting technique.
2 is a block diagram showing an organic light emitting display device of the present invention.
3 is a view showing an image shift result screen according to the present invention in comparison with the prior art.
4 is a flowchart showing an image shift concept according to an embodiment of the present invention.
5 is a view showing a display image corresponding to each step of FIG. 4.
6 is a diagram schematically showing the configuration of an afterimage reduction circuit implementing FIG. 4.
7 is a diagram showing a detailed configuration of FIG. 6.
8 and 9 are diagrams for explaining a pixel counter operation of FIG. 7;
10 to 15 are diagrams for explaining the line counter operation of FIG. 7.
16 is a flow chart showing an image shift concept according to another embodiment of the present invention.
17 is a view showing a display image corresponding to each step of FIG. 16;
18 is a diagram schematically showing the configuration of an afterimage reduction circuit implementing FIG. 16;
19 is a diagram showing a detailed configuration of FIG. 18;

Hereinafter, a preferred embodiment of the present invention will be described with reference to FIGS. 2 to 19.

2 is a block diagram showing an organic light emitting display device of the present invention. And, FIG. 3 is a view showing an image shift result screen according to the present invention compared with the conventional one.

Referring to FIG. 2, an organic light emitting display device according to the present invention includes a display panel 10, a timing controller 11, a data driving circuit 12, a gate driving circuit 13, and an afterimage reduction circuit 20.

A plurality of data lines 15 and a plurality of gate lines 16 intersect on the display panel 10, and pixels are arranged in a matrix form in each of the intersection regions. Each of the pixels has an OLED and a pixel circuit. The pixel circuit includes a driving TFT (DT) for controlling the amount of current flowing through the OLED, and a switching unit (SC) for programming a gate-source voltage of the driving TFT (DT). The switching unit SC may include at least one switch TFT and a storage capacitor. The switch TFT is turned on in response to the scan signal from the gate line 16, thereby charging the data voltage from the data line 15 to one electrode of the storage capacitor. The driving TFT controls the amount of light emitted by the OLED by controlling the amount of current supplied to the OLED according to the amount of voltage charged in the storage capacitor. The amount of light emitted by the OLED is proportional to the current supplied from the driving TFT. These pixels receive high-potential power (EVDD) and low-potential power (EVSS) from a power generator (not shown). The TFTs constituting the pixel may be implemented as a p type or may be implemented as an n type. Further, the semiconductor layer of the TFTs constituting the pixel may include amorphous silicon, polysilicon, or oxide.

The timing controller 11 receives digital video data (RGB) of an input image from the host system 14 through an interface circuit (not shown), and converts the digital video data (RGB) of the input image into an afterimage reduction circuit (20). The modulated image data RmGmBm from the afterimage reduction circuit 20 is supplied to the data driving circuit 12 through a mini-LVDS interface method or the like.

The timing controller 11 receives timing signals such as a vertical synchronization signal (Vsync), a horizontal synchronization signal (Hsync), a data enable signal (Data Enable, DE), and a dot clock (CLK) from the host system 14 to provide data. Control signals for controlling operation timings of the driving circuit 12 and the gate driving circuit 13 are generated. The control signals include a gate timing control signal GDC for controlling an operation timing of the gate driving circuit 13 and a source timing control signal DDC for controlling an operation timing of the data driving circuit 12. In some cases, the gate timing control signal GDC and the source timing control signal DDC may be modulated within the afterimage reduction circuit 20.

The data driving circuit 12 converts the modulated image data RmGmBm into a data voltage according to the data control signal DDC from the timing controller 11 and supplies the data voltage to the data lines 15.

The gate driving circuit 13 generates a scan signal according to the gate control signal GDC from the timing controller 11 and then supplies the scan signal to the gate lines 16 according to a line sequential method.

The afterimage reduction circuit 20 may be embedded in the timing controller 11 and receives an image shift enable signal ISE from the host system 14. The image shift enable signal ISE is a control signal for activating a display image shifting operation, and may be input whenever a scene change amount of an image between frames is equal to or greater than a preset threshold or at a preset time interval. As shown in FIG. 3B, the afterimage reduction circuit 20 shifts the display image displayed on the display panel 10 in a first direction by a predetermined pixel interval, and the display image corresponding to the first direction Each of the first boundary (left and upper boundary) of and the second boundary (right and lower boundary) of the display image corresponding to a second direction opposite to the first direction is replaced with black image data by the predetermined pixel interval. . Here, in the drawings, the first and second directions are shown only in diagonal directions opposite to each other, but the technical idea of the present invention is not limited thereto, and the first and second directions are horizontal directions opposite to each other or opposite to each other. It can also be vertical.

In the conventional image shifting technique shown in FIG. 3A, the displayed image is viewed asymmetrically by processing only the image boundary in the opposite direction of the shift as a black image. When the display image is set to be shifted by a maximum of ±6 pixel intervals based on a 55-inch FHD (Full HD) display panel, the maximum is 6 pixels/1920 pixels = 3.8 mm. By the way, in recent borderless or narrow bezel designs, 3.8mm becomes an insignificant width. For example, in the case of (A) of FIG. 3, a deviation of about 4 mm may occur between the left border area of the screen including the bezel (BZ) and the border area on the right side of the screen. May be offensive to users.

Accordingly, the present invention replaces not only the opposite direction of the shift but also the boundary of the display area corresponding to the shift direction with a black image when the image is shifted, as shown in FIG. 3B. Resolve image asymmetry.

4 is a flowchart illustrating an image shift concept according to an embodiment of the present invention, and FIG. 5 is a view illustrating a display image corresponding to each step of FIG. 4.

4 and 5, an image shift method according to an embodiment of the present invention is implemented through delay control of an image signal without changing a synchronization signal, and inputting a display image (S1), an image shift-in. Shifting the display image according to the enable signal (ISE) (S2), the edge cut step (S3) of replacing the boundary of the display image with black image data to maintain the symmetry of the shifted display image (S3), and the modulated image by edge cut And outputting data (S4).

In the step of shifting the display image (S2), the display image is shifted in consideration of a preset horizontal movement amount HS and a vertical movement amount VS.

In the edge cutting step S3, the second boundary (hatched portion) of the display image corresponding to the second direction opposite to the shift direction is determined as a black image data replacement region. Then, the first boundary portions 2HS and 2VS of the display image corresponding to the first direction, which is the shift direction, are cut out, and a part of the cut-out area is determined as a black image data replacement area. Subsequently, in the edge cutting step S3, the first and second boundaries of the display image determined as the black image data replacement region are replaced with black image data.

6 schematically shows the configuration of the afterimage reduction circuit 20 implementing FIG. 4, and FIG. 7 shows the detailed configuration of FIG. 6. 8 and 9 are diagrams for explaining the operation of the pixel counter 26A of FIG. 7. In addition, FIGS. 10 to 15 are diagrams for explaining the operation of the line counter 26B of FIG. 7.

6 and 7, the afterimage reduction circuit 20 according to an embodiment of the present invention includes a display starting point generation unit 22, a display image shift unit 24, a window setting unit 26, and edge cutting. It has a part 28.

When the image shift enable signal ISE is input from the host system 14, the display start point generator 22 generates a display start point in consideration of a preset horizontal movement amount HS and a vertical movement amount VS.

The display image shift unit 24 outputs shifted image data R'G'B' shifted in the first direction by a predetermined pixel interval by delaying the input image data RGB to match the display starting point. To this end, the display image shift unit 24 may include a data delay unit 24A. The data delay unit 24A delays the input image data RGB in the horizontal direction by the amount of horizontal movement HS from the display start point generation unit 22, and refers to a separate line memory 24B to a display start point generation unit ( The input image data RGB may be delayed in the vertical direction by the amount of vertical movement VS from 22).

The window setting unit 26 outputs a horizontal selection signal (Horizontal Enable) by comparing the pixel count value (PC) counting the number of pixels with the horizontal movement amount (HS), and counts the number of lines. The vertical movement amount VS is compared with each other to output a vertical selection signal (Vertical Enable). To this end, the window setting unit 26 includes a pixel counter 26A, a first determination unit 26C, a line counter 26B, and a second determination unit 26D.

The pixel counter 26A counts the high logic section of the data enable signal DE as a rising edge or a falling edge of the dot clock CLK as shown in FIGS. 8 and 9, and sets the pixel count value PC by '1'. When the data enable signal DE is inverted to a low logic, the pixel count value PC is reset to '0'. The pixel count value PC is a reference for determining the horizontal display position of image data.

The first determination unit 26C determines that the pixel count value PC is equal to or less than the horizontal movement amount HS (PC≦HS), or a value obtained by subtracting the horizontal movement amount HS from the horizontal resolution (PC≥horizontal resolution-HS). ), the horizontal selection signal (Horizontal Enable) is output as a low logic level ('0') and the horizontal selection signal is output as a high logic level ('1') to other (HS<PC<Horizontal Resolution-HS). do.

The line counter 26B generates a line count value LC based on the line pulse and frame pulse generated internally as shown in FIGS. 10 and 11. Here, the frame pulse (ⓒ) is the inversion signal (Bar Vsync) (ⓐ) of the vertical synchronization signal (Vsync) obtained through the inverter as shown in FIGS. 12 and 13, and the vertical synchronization signal (Vsync) obtained through the delay device. It can be obtained as a result of a logical multiplication operation between the delay signals ⓑ. And, the line pulse (ⓒ') is a logical product between the data enable signal DE and the delay and inversion signal ⓑ'of the data enable signal DE obtained through the inverter and the delay as shown in Figs. 14 and 15. It can be obtained as an operation result. The line counter 26B increases the line count value LC by '1' by counting the line pulse as a rising edge or a falling edge of the dot clock CLK, and increases the line count value LC when a frame pulse is detected. Reset to '0'. The line count value LC serves as a reference for determining the vertical display position of image data.

The second determination unit 26D determines that the line count value LC is equal to or less than the vertical movement amount VS (LC ≤ VS), or equal to or greater than the value obtained by subtracting the vertical movement amount VS from the vertical resolution (LC≥ vertical resolution-VS). ), the vertical selection signal (Vertical Enable) is output at a low logic level ('0') and the vertical selection signal is output at a high logic level ('1') to other (VS<LC<vertical resolution-VS)'' do.

The edge cutting unit 28 includes an AND gate for logical multiplication operation between a horizontal selection signal and a vertical selection input from the window setting unit 26, and generates and outputs a window enable signal as a result of the logical multiplication operation. The AND gate outputs the window enable signal at a high logic level ('1') only when both the horizontal and vertical selection signals are at a high logic level, and otherwise, the window enable signal is at a low logic level ('0'). Output as The edge cutting unit 28 outputs the shifted image data (R'/G'/B') as modulated image data (RmGmBm) only when the window enable signal is at a high logic level ('1'), and When the enable signal is at the low logic level ('0'), black image data (0/0/0) is output as modulated image data (RmGmBm).

16 is a flowchart showing an image shift concept according to another embodiment of the present invention, and FIG. 17 is a view illustrating a display image corresponding to each step of FIG. 16.

16 and 17, an image shift method according to another embodiment of the present invention is implemented through delay control of a synchronization signal, and inputs a display image (S10), an image shift enable signal (ISE). According to the step of selecting a portion to be processed in the display image (S20), an edge cut step of replacing the first boundary of the display image selected in S20 with black image data corresponding to the shift direction (first direction) of the display image ( S30), a display image shift step (S40) of shifting the display image in the shift direction and replacing the second boundary of the display image corresponding to the direction opposite to the shift direction (second direction) with black image data (S40), shift And outputting the modulated image data by (S50).

In the step of selecting a portion to be processed in the display image (S20), a portion to be processed (2HS, 2VS located in the first direction) in the display image is selected in consideration of a preset horizontal movement amount (HS) and vertical movement amount (VS). do.

In the edge cutting step S30, the first boundary portions 2HS and 2VS of the selected display image are cut out corresponding to the first direction, which is the shift direction, and the cut-out area is replaced with black image data.

In the display image shifting step (S40), synchronization signals are modulated to fit the display starting point to shift the display image in the shift direction, and to maintain symmetry of the shifted display image, corresponding to the second direction opposite to the shift direction. The second boundary of the display image is replaced with black image data.

18 is a diagram schematically illustrating a configuration of an afterimage reduction circuit implementing FIG. 16. And, FIG. 19 is a diagram showing a detailed configuration of FIG. 18.

18 and 19, the afterimage reduction circuit 20 according to another embodiment of the present invention includes a display starting point generation unit 122, a window setting unit 124, an edge cutting unit 126, and a display image shift. It has a section 128.

When the image shift enable signal ISE is input from the host system 14, the display start point generation unit 122 generates a display start point in consideration of a preset horizontal movement amount HS and a vertical movement amount VS.

The window setting unit 124 outputs a horizontal selection signal (Horizontal Enable) by comparing the pixel count value (PC) counting the number of pixels with the horizontal movement amount (HS), and counts the number of lines. The vertical movement amount VS is compared with each other to output a vertical selection signal (Vertical Enable). To this end, the window setting unit 124 includes a pixel counter 124A, a first determination unit 124C, a line counter 124B and a second determination unit 124D.

The pixel counter 124A counts the high logic section of the data enable signal DE as a rising edge or a falling edge of the dot clock CLK as shown in FIGS. 8 and 9, and sets the pixel count value PC by '1'. When the data enable signal DE is inverted to a low logic, the pixel count value PC is reset to '0'. The pixel count value PC is a reference for determining the horizontal display position of image data.

The first determination unit 124C sets the horizontal selection signal to a low logic level when the pixel count value PC is equal to or greater than a value obtained by subtracting the horizontal movement amount HS*2 from the horizontal resolution (PC≥horizontal resolution-2*HS). ('0') and other (PC<horizontal resolution-2*HS), the horizontal selection signal is output as a high logic level ('1').

The line counter 124B generates a line count value LC based on the line pulse and frame pulse generated internally as shown in FIGS. 10 and 11. Here, the frame pulse (ⓒ) is the inversion signal (Bar Vsync) (ⓐ) of the vertical synchronization signal (Vsync) obtained through the inverter as shown in FIGS. 12 and 13, and the vertical synchronization signal (Vsync) obtained through the delay device. It can be obtained as a result of a logical product operation between the delay signals ⓑ. And, the line pulse (ⓒ') is a logical product between the data enable signal DE and the delay and inversion signal ⓑ'of the data enable signal DE obtained through the inverter and the delay as shown in Figs. 14 and 15. It can be obtained as an operation result. The line counter 26B increases the line count value LC by '1' by counting the line pulse as a rising edge or a falling edge of the dot clock CLK, and increases the line count value LC when a frame pulse is detected. Reset to '0'. The line count value LC serves as a reference for determining the vertical display position of image data.

The second determination unit 124D generates a vertical selection signal (Vertical Enable) when the line count value LC is equal to or greater than the value obtained by subtracting the vertical movement amount VS*2 from the vertical resolution (LC≥vertical resolution-2*VS). The vertical selection signal is output at a low logic level ('0'), and the vertical selection signal is output at a high logic level ('1') for other (LC<vertical resolution-2*VS).

The edge cutting unit 126 processes the input image data RGB based on the horizontal selection signal and the vertical selection signal input from the window setting unit 124, so that the first boundary of the display image is the black image data (0). /0/0) and outputs the selected video data (Rc/Gc/Bc). The edge cutting unit 126 outputs the input image data RGB as the selected image data Rc/Gc/Bc only when both the horizontal selection signal and the vertical selection signal are at a high logic level ('1'). When at least one of the selection signal and the vertical selection signal is at the low logic level ('0'), black image data (0/0/0) is output as the selection image data (Rc/Gc/Bc).

The display image shift unit 128 modulates (delays) the synchronization signals according to the display starting point and aligns the image data accordingly, thereby moving the selected image data Rc/Gc/Bc in the first direction by the predetermined pixel interval. In addition to shifting, the second boundary of the display image is replaced with the black image data (0/0/0). The display image shift unit 128 shifts the selected image data Rc/Gc/Bc in the first direction by the predetermined pixel interval, so that the first and second boundary portions of the display image are black by the predetermined pixel interval. The modulated image data (RmGmBm) replaced with the image data (0/0/0) is output.

It will be appreciated by those skilled in the art through the above description that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

10: display panel 11: timing controller
12: data driving circuit 13: gate driving circuit
20: afterimage reduction circuit

Claims (5)

Display panel; And
The display image displayed on the display panel is shifted in a first direction by a predetermined pixel interval according to an image shift enable signal ISE, and the display image is shifted in a first direction and a first boundary of the display image corresponding to the first direction. And an afterimage reduction circuit for replacing each second boundary portion of the display image corresponding to an opposite second direction with black image data by the predetermined pixel interval,
The afterimage reduction circuit,
A display start point generator configured to generate a display start point in consideration of a preset horizontal movement amount HS and a vertical movement amount VS when the image shift enable signal ISE is input; And
Generate a horizontal selection signal and a vertical selection signal required to replace the first boundary and the second boundary with the black image data, and compare the pixel count value (PC) obtained by counting the number of pixels with the horizontal movement amount (HS). And a window setting unit configured to output the vertical selection signal by outputting the horizontal selection signal, comparing a line count value (LC) counting the number of lines with the vertical movement amount (VS). The method of claim 1,
The afterimage reduction circuit,
A display image shift unit for outputting shifted image data R'G'B' shifted in the first direction by the predetermined pixel interval by delaying the input image data RGB in accordance with the display starting point; And
An edge cutting unit for processing the shifted image data R'G'B' based on the horizontal selection signal and the vertical selection signal and replacing the first boundary and the second boundary of the display image with the black image data The display device further comprising. The method of claim 2,
The window setting unit,
When the pixel count value (PC) is equal to or less than the horizontal movement amount (HS) or greater than or equal to a value obtained by subtracting the horizontal movement amount (HS) from the horizontal resolution, the horizontal selection signal is output at a low logic level, and the horizontal selection signal is otherwise Outputs at a high logic level, and outputs the vertical selection signal at a low logic level when the line count value LC is less than or equal to the vertical movement amount VS or greater than or equal to a value obtained by subtracting the vertical movement amount VS from the vertical resolution. Otherwise, the vertical selection signal is output at a high logic level,
The edge cutting part,
Only when the horizontal selection signal and the vertical selection signal are at a high logic level, the shifted image data R'G'B' is output as modulated image data RmGmBm, and one of the horizontal selection signal and the vertical selection signal And outputting the black image data as modulated image data (RmGmBm) when at least one of them is at a low logic level. The method of claim 1,
The afterimage reduction circuit,
An edge cutting unit processing input image data RGB based on the horizontal selection signal and the vertical selection signal, and outputting selection image data RcGcBc in which a first boundary portion of the display image is replaced with the black image data; And
Display image shift in which synchronization signals are modulated according to the display starting point, and the selected image data RcGcBc is shifted in the first direction by the predetermined pixel interval, and a second boundary of the display image is replaced with the black image data. The display device, further comprising a unit. The method of claim 4,
The window setting unit,
When the pixel count value (PC) is greater than or equal to the horizontal resolution minus the horizontal movement amount (HS) *2, the horizontal selection signal is output at a low logic level, and other than that, the horizontal selection signal is output at a high logic level, and the line When the count value (LC) is greater than or equal to the vertical resolution minus the vertical movement amount (VS) *2, the vertical selection signal is output at a low logic level, and otherwise, the vertical selection signal is output at a high logic level,
The edge cutting part,
Only when both the horizontal selection signal and the vertical selection signal are at a high logic level, the input image data RGB is output as the selection image data RcGcBc, and at least one of the horizontal selection signal and the vertical selection signal is At a low logic level, the black image data is output as the selected image data RcGcBc,
The display image shift unit,
Modulated image data RmGmBm in which the first and second boundary portions of the display image are replaced with the black image data by the predetermined pixel interval by shifting the selected image data RcGcBc in the first direction by the predetermined pixel interval. Display device, characterized in that to output.

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