KR20160032592A - Method for generating prototype of power delivery network of integrated circuit - Google Patents

Abstract

Disclosed is a method for generating a prototype of a power transmission network of an integrated circuit. According to an exemplary embodiment of the present invention, the method may include the following steps: extracting a current profile of operation current consumed by the integrated circuit; calculating target impedance of the power transmission network based on the current profile; and determining arrangement and a value of a passive element based on the target impedance. According to the present invention, an unnecessary margin which may be included in the power transmission network can be reduced.

Description

[0001] METHOD FOR GENERATING PROTOTYPE OF POWER DELIVERY [0002] NETWORK OF INTEGRATED CIRCUIT [0003]

The technical idea of the present invention relates to a method of generating a prototype of a power transmission network of an integrated circuit, and more particularly to a method of generating a prototype of a power transmission network at an initial stage of an integrated circuit design.

As the performance of electronic devices such as smart phones, tablets, and laptop computers becomes more sophisticated, the data processing speed of integrated circuits included in electronic devices is increasing. Along with the development of semiconductor manufacturing process technology, integrated circuits that perform various functions in one semiconductor package such as system-on-chip (SOC) are being implemented. Accordingly, the power consumed by the integrated circuit not only requires a large amount of current, but also includes a high frequency component.

A Power Delivery Network (PDN) provides power to an integrated circuit from a power supply such as a voltage regulator module (VRM). In order to stably supply power to the integrated circuit, the power transmission network needs to have sufficient decoupling capacitance with low inductance, and there is a need to be designed in consideration of spatial constraints and cost constraints.

The technical idea of the present invention relates to a method of prototyping a power transmission network, and a method of designing a prototype of a power transmission network or a power transmission network at an initial stage of an integrated circuit design and a plurality of instructions for implementing the method A non-volatile storage medium readable by a computer, and a processor for performing a plurality of instructions.

In order to achieve the above object, a computer-implemented method for generating a prototype of a power transmission network of an integrated circuit according to an aspect of the technical idea of the present invention is characterized in that, from a simulation result of the integrated circuit, Calculating a target impedance of the power transmission network based on the current profile, a supply voltage of the integrated circuit, and a tolerance of the supply voltage, calculating a target impedance of the power transmission network based on the target impedance, Determining the placement of at least one passive element in one of the die of the integrated circuit, the package interior and the board to which the package is attached, and determining a value of the passive element, Data that can be used to computerize a power transmission network prototype As shown in FIG.

According to an exemplary embodiment of the present invention, the current profile and the target impedance may each be a function of frequency.

According to an exemplary embodiment of the present invention, a method of generating a prototype of the power transmission network may further include receiving specification information of the integrated circuit through a computer system, the specification information including input / Port, supply voltage, and tolerance of the supply voltage.

According to an exemplary embodiment of the present invention, the step of extracting the current profile includes the steps of simulating the operating current while the signals at the input / output port transit according to a predetermined data pattern, and outputting the simulation result as a function of frequency And a step of converting the data.

According to an exemplary embodiment of the present invention, extracting the current profile further comprises extracting the current profile from the functions of frequency based on the plurality of data patterns to include a maximum value in all frequency ranges can do.

According to an exemplary embodiment of the present invention, the step of calculating the target impedance may comprise generating the target impedance by dividing the product of the supply voltage and the tolerance of the supply voltage as the current profile.

According to an exemplary embodiment of the present invention, extracting the current profile includes extracting a power profile by simulating a chip power model of the integrated circuit for a power transfer network for the core circuit of the integrated circuit .

According to an exemplary embodiment of the present invention, the step of determining the placement and value of the passive element comprises calculating a target decoupling capacitance from the target impedance, determining a target decoupling capacitance of the at least one decoupling capacitor based on the target decoupling capacitance and the capacitor library And determining an allowable parasitic inductance of the conductors of the power transmission network between the components in the integrated circuit, the package, and the board, wherein the capacitor library includes a plurality of capacitors And may include information about each capacitance, size, and resonance frequency.

According to an exemplary embodiment of the present invention, the target decoupling capacitance is calculated based on the target impedance and the resonant frequency.

According to an exemplary embodiment of the present invention, the step of determining the arrangement and the capacitance of the decoupling capacitor comprises the step of disposing a decoupling capacitor whose placement is determined on the board from one of the areas spaced by predetermined distances from the package, Based on the result of the determination.

According to an exemplary embodiment of the present invention, the step of determining the placement and value of the passive element is based on the capacitance and the operating frequency of the decoupling capacitor, And calculating an allowable parasitic inductance of the lead wire.

According to an exemplary embodiment of the present invention, the step of calculating the permissible parasitic inductance of the conductors between the components in the power transmission network may include a high-to-low frequency method .

According to an exemplary embodiment of the present invention, the method may further include determining whether a prototype of the power transmission network according to the determined passive element is feasible.

According to an exemplary embodiment of the present invention, the step of determining the arrangement and capacitance of the decoupling capacitor may comprise setting a plurality of groups based on the target decoupling capacitance and the position at which the decoupling capacitor is disposed.

According to an exemplary embodiment of the present invention, the plurality of groups may include a first group corresponding to the interior of the die of the integrated circuit, a second group corresponding to the interior of the package of the integrated circuit, A fourth group corresponding to a region spaced a first distance from the package on the board, a third group corresponding to a region opposite to the first distance from the package on the board, A corresponding fifth group, and a sixth group corresponding to a region adjacent to the voltage regulator module.

According to an exemplary embodiment of the present invention, the capacitor library may include information on the capacitance, size and resonant frequency of each of the plurality of capacitors, and the step of determining the arrangement and capacitance of the decoupling capacitor comprises: And selecting a capacitor from the capacitor library to have a capacitance greater than the target decoupling capacitance in each of the plurality of groups based on the frequency.

According to an aspect of the technical idea of the present invention, a computer system is a computer-readable medium storing a computer-readable program for executing a method of prototyping a power transmission network of a processor and an integrated circuit, The method comprising: extracting a current profile of an operating current consumed by the integrated circuit from a simulation result of the integrated circuit; Calculating a target impedance of the power transmission network based on a supply voltage and a tolerance of the supply voltage, calculating a target impedance of the power transmission network based on the target impedance, The placement of at least one passive element is determined Determining a value of the passive element, and generating a prototype of the power transmission network including the at least one passive element as computer processable data.

According to an exemplary embodiment of the present invention, a method of generating a prototype of the power transmission network may further include receiving specification information of the integrated circuit through a computer system, the specification information including input / Port, supply voltage, and tolerance of the supply voltage.

According to an exemplary embodiment of the present invention, extracting the current profile includes simulating the operating current while the signals at the output port transit according to a predetermined data pattern, and comparing the simulation result with a function of frequency And a step of converting the data.

According to an exemplary embodiment of the present invention, the step of determining the placement and value of the passive element includes calculating a target decoupling capacitance from the target impedance, and determining a placement and decoupling of the decoupling capacitor based on the target decoupling capacitance and the capacitor library. Determining a capacitance, and the capacitor library may include information on a capacitance and a resonance frequency of each of the plurality of capacitors.

According to the technical idea of the present invention, by deriving the prototype of the power transmission network relatively accurately at the initial stage of the integrated circuit design, it is possible to reduce unnecessary margins that can be included in the power transmission network.

In addition, an efficient power transmission network can be designed in consideration of all the levels including the die of the integrated circuit, the package and the board to which the package is attached, and the design time of the system including the integrated circuit and the power transmission network can be shortened have.

1 is a diagram illustrating a method for generating a prototype of a power transmission network in accordance with an exemplary embodiment of the present invention.
2 is a diagram illustrating a system including a power transmission network.
3 is a diagram illustrating a method for creating a prototype of a power transmission network in accordance with an exemplary embodiment of the present invention.
4 is a diagram of a model of an integrated circuit for deriving the operating current of FIG. 2 in accordance with an exemplary embodiment of the present invention.
5A and 5B are diagrams illustrating methods of extracting a current profile in accordance with exemplary embodiments of the present invention.
Figure 6 is a diagram of an integrated circuit model for deriving the operating current of Figure 2 in accordance with an exemplary embodiment of the present invention.
Figure 7 is a graph showing the extracted operating current in the frequency domain, in accordance with an exemplary embodiment of the present invention.
8 is a diagram illustrating a method for determining the placement and value of passive elements in accordance with an exemplary embodiment of the present invention.
9 is a diagram showing an example of a capacitor library.
10 is a diagram illustrating a method for determining the placement and capacitance of a decoupling capacitor in accordance with an exemplary embodiment of the present invention.
11 is a diagram illustrating a plurality of groups of decoupling capacitors according to locations where a decoupling capacitor is disposed in accordance with an exemplary embodiment of the present invention.
12 is a diagram illustrating the operation of setting a plurality of groups of decoupling capacitors in accordance with an exemplary embodiment of the present invention.
Figure 13 is a diagram illustrating the results of determining the placement and capacitance of decoupling capacitors in a power transmission network in accordance with an exemplary embodiment of the present invention.
14 is a diagram illustrating a method for calculating an allowable parasitic inductance in a conductor of a power transmission network in which an operating current flows in accordance with an exemplary embodiment of the present invention.
15 is a diagram illustrating a method for generating a prototype of a power transmission network in accordance with an exemplary embodiment of the present invention.
16 is a block diagram illustrating another computer-readable storage medium in accordance with an exemplary embodiment of the present invention.
17 is a block diagram illustrating a computer system in accordance with an exemplary embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. The present invention is capable of various modifications and various forms, and specific embodiments are illustrated and described in detail in the drawings. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for similar elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are enlarged or reduced from the actual dimensions for the sake of clarity of the present invention.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a part or a combination thereof is described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be construed to have meanings consistent with the contextual meanings of the related art and are not to be construed as ideal or overly formal meanings as are expressly defined in the present application .

1 is a diagram illustrating a method for generating a prototype of a power transmission network in accordance with an exemplary embodiment of the present invention. FIG. 2 is a diagram illustrating a system 1000 including a power transmission network 100, and FIG. 2 is referred to throughout this specification. The method of prototyping the power transmission network 100 according to the exemplary embodiment of the present invention may create a prototype of the power transmission network 100 at an early stage of designing the system 1000. [ In accordance with an exemplary embodiment of the present invention, a prototype of the power transmission network 100 enables a more efficient system 1000 by eliminating unnecessary margins. In addition, it is possible to reduce the time and cost spent on the design of the system 1000 by eliminating the iterative loop for the redesign of the power transmission network 100 in the process of designing the system 1000.

Referring first to FIG. 2, a system 1000 may include a power transmission network 100, an integrated circuit 200, and a power supply 300. The power supply 300 may provide power and may include, for example, a Power Management Integrated Circuit (PMIC) or a Voltage Regulator Module (VRM). The power supply 300 may be connected to the power transmission network 100 through a wire, and may be physically spaced apart from the integrated circuit 200. Although FIG. 2 illustrates one power transmission network 100 and integrated circuit 200 coupled to the power supply 300, the power supply 300 may be connected to a plurality of power transmission networks and integrated circuits And can supply power to each of them.

The integrated circuit 200 is a component that performs a specific function by consuming power, and may include transistors, conductors, and / or passive components. For example, the integrated circuit 200 may include a microprocessor, an application processor, or a semiconductor memory device. The integrated circuit 200 may be powered by one or more power terminals. For example, as shown in FIG. 2, the integrated circuit 200 may receive the operation current i_pdn and the operation voltage v_pdn from the power transmission network 100.

The operation voltage v_pdn transmitted to the integrated circuit 200 may be a direct current voltage and the amount of the operation current i_pdn consumed by the integrated circuit 200 varies based on the operation of the integrated circuit 200, (v_pdn) may fluctuate. The variation range of the operating voltage v_pdn that allows the integrated circuit 200 to operate normally can be referred to as a tolerance of the supply voltage. Due to the increase in the data processing speed in the integrated circuit 200 such as an application processor, the operation current i_pdn may include a high frequency component. Despite the high frequency component of the operating current i_pdn, the operating voltage v_pdn must remain within the tolerance of the supply voltage so that the integrated circuit 200 can operate normally.

As shown in FIG. 2, the power transmission network 100 may be disposed between the integrated circuit 200 and the power supply 300. The power transmission network 100 may be designed to communicate the operating current i_pdn and the operating voltage v_pdn to the integrated circuit 200 to allow the integrated circuit 200 to operate normally. The power transmission network 100 may include passive elements connected through the conductors of the power transmission network 100 and the placement and value of the passive elements may be determined based on the integrated circuit 200. Passive devices are devices that can consume, scale or emit the supplied power and can refer to devices that do not have active functions such as amplification or rectification. For example, the power transmission network 100 may include at least one decoupling capacitor, and the arrangement and capacitance of the decoupling capacitor may be determined to compensate for the high frequency components of the operating current i_pdn consumed by the integrated circuit 200 . As shown in FIG. 2, the power transmission network 100 may have an impedance (Z_PDN) as viewed from the side of the integrated circuit 200 based on the passive elements and conductors involved.

In an early stage of the system 1000 design, the integrated circuit 200 is in an incomplete state, so that the power transmission network 100 may be schematically designed. The schematically designed power transmission network 100 may be designed according to some predetermined types and may have an unnecessary margin for the integrated circuit 200. [ For example, as the value of the passive element increases, the number and the physical size of passive elements increase, so that the schematically designed power transmission network 100 may result in inefficiency of the system 1000. In addition, after the design of the integrated circuit 200 and other components of the system 1000 is completed, the roughly designed power transmission network 100 is redesigned based on the characteristics of the finished integrated circuit 200 and components It can be very limited. Accordingly, in order to prevent the failure of the power transmission network 100, the power transmission network 100 schematically designed at the initial stage may have a large unnecessary margin.

The method of prototyping a power transmission network 100 in accordance with an exemplary embodiment of the present invention enables the design of the power transmission network 100 based on the characteristics of the integrated circuit 200 at an early stage of system 1000 design . For example, the power transmission network 100 may design a prototype of the power transmission network 100 or the power transmission network 100 based on the operating current i_pdn that the integrated circuit 200 consumes. In accordance with an exemplary embodiment of the present invention, the power transmission network 100 or its prototype may have reduced unnecessary margins and thus an efficient system 1000 may be designed.

1, a method of generating a prototype of a power transmission network 100 according to an exemplary embodiment of the present invention includes generating a profile (or current profile) of the operating current i_pdn consumed by the integrated circuit 200 (S20). The extracted current profile can be defined in the frequency domain as a function of frequency. For example, the operating current i_pdn may be obtained by simulating the current supplied to the drivers that drive the output signals while the output signals of the output ports included in the integrated circuit 200 transit according to a predetermined data pattern have. Alternatively, the operating current i_pdn may be derived from the power model (or chip power model) of the core portion included in the integrated circuit 200.

The current profile may be generated from one or more operating currents i_pdn. For example, the current profile can be extracted by converting the waveform of the derived operation current i_pdn into a function of frequency through FFT (Fast Fourier Transform). Alternatively, the waveforms of two or more operating currents (i_pdn) may be converted to functions of frequency through an FFT and may be calculated from the converted frequency functions to correspond to the worst case (i.e., to include the maximum value of the frequency functions in all frequency ranges) ) Current profile can be extracted.

A method of generating a prototype of the power transmission network 100 according to an exemplary embodiment of the present invention may calculate a target impedance of the power transmission network 100 based on the current profile (S40). For example, the target impedance may be defined in the frequency domain as a function of frequency and may correspond to the maximum impedance that the power transmission network 100 may have. That is, the impedance Z_PDN of the power transmission network 100 may be smaller in the entire frequency range than the target impedance.

As shown in Figure 1, a method of generating a prototype of the power transmission network 100 may determine the placement and value of at least one passive element included in the power transmission network 100 based on the target impedance ( S60). For example, the passive element may be selected based on the space in which the passive element is to be placed and the characteristics of the passive element such that the impedance Z_PDN of the power transmission network 100 is smaller than the target impedance.

The method of generating the prototype of the power transmission network 100 may generate computer processable data (S80). That is, prototypes of a power transmission network including at least one passive element whose placement and value are determined can be generated as computer-processable data. For example, a netlist defining an electronic circuit may be generated, the generated netlist may include attribute information including values of passive elements, information about the connection relationship between passive elements . ≪ / RTI > The generated data may be output to the outside through a peripheral device of the computer system or stored in a storage device of the computer system.

3 is a diagram illustrating a method for generating a prototype of a power transmission network 100 in accordance with an exemplary embodiment of the present invention. Referring to FIG. 3, a method of generating a prototype of the power transmission network 100 may receive specification information of the integrated circuit 200 through a computer system (S10a). The specification information of the integrated circuit 200 may be information that can be collected at an initial stage of the design of the system 1000. For example, the specification information of the integrated circuit 200 may include information on the output ports of the integrated circuit 200, the operating voltage, and the tolerance of the operating voltage. The method of generating the prototype of the power transmission network 100 can then extract the current profile of the operating current i_pdn consumed by the integrated circuit 200 through simulation or power model (S20a). For example, the current profile may be extracted based on information about the output ports of the integrated circuit 200 included in the specification information of the integrated circuit 200. [ Details of extracting the current profile will be described in detail in Figs. 4-7.

As shown in FIG. 3, a method of generating a prototype of the power transmission network 100 may calculate a target impedance of the power transmission network 100 (S40a).

As shown in Equation 1, the target impedance Z_TAR is calculated by multiplying the current profile I_PRO and the supply voltage v_dc of the integrated circuit 200 included in the specification information of the integrated circuit 200 and the tolerance? Can be calculated on the basis of the information on the information. As shown in Equation (1), the current profile I_PRO and the target impedance Z_TAR can be defined as a function of frequency, respectively. The supply voltage v_dc is a voltage output from the power supply 300 and may be a DC voltage. The tolerance delta of the supply voltage may be defined as the ratio of the difference of the supply voltage v_dc to the supply voltage v_dc and the difference of the operating voltage v_pdn and may be, for example, 5%. The target impedance Z_TAR calculated according to Equation (1) may correspond to the maximum impedance that the power transmission network 100 can have. That is, the power transmission network 100 may be designed to have an impedance (Z_PDN) having a value lower than the target impedance Z_TAR at all frequencies.

As shown in FIG. 3, a method of generating a prototype of the power transmission network 100 may then determine the placement and value of at least one passive element based on the target impedance Z_TAR (S60a). Specifically, the arrangement and value of at least one passive element can be determined such that the impedance Z_PDN of the power transmission network 100 is lower than the target impedance Z_TAR. Determination of the placement and value of passive elements will be described in detail in Figures 8-12.

4 is a diagram illustrating a model 200 'of an integrated circuit 200 for deriving the operating current i_pdn of FIG. 2 in accordance with an exemplary embodiment of the present invention. The operating current i_pdn consumed by the integrated circuit 200 may include two types of currents, namely, the currents consumed in each of the input / output circuit and the core circuit. The input / output circuit may be connected to the input / output ports of the integrated circuit 200, respectively, for a signal transmitted to the outside of the integrated circuit 200 or a signal received from the outside. The circuit for the input signal may comprise an input buffer and the circuit for the output signal may comprise an output buffer, i. E. A signal driver. A signal driver coupled to a conductor outside the integrated circuit 200, as compared to an input buffer that outputs a signal to a conductor inside the integrated circuit 200 in accordance with an input signal, A positive current can be consumed.

As shown in FIG. 4, the integrated circuit model 200 'may include a plurality of signal drivers 211-214. According to an exemplary embodiment of the present invention, by simulating the current supplied to the signal drivers 211 to 214 included in the integrated circuit model 200 ', the operating current i_pdn' of the integrated circuit model 200 ' Can be derived.

Referring to FIG. 4, information about the input / output ports of the integrated circuit 200 may be available at an early stage of system 1000 design. For example, when the integrated circuit 200 includes four output ports, the integrated circuit model 200 'may include four signal drivers 211 through 214, as shown in FIG. The signal drivers 211 to 214 may be respectively connected to the interconnect models 401 to 404 and the output signals may be respectively transmitted to the interconnect models 401 to 404. The interconnect models 401-404 may include resistors, capacitors, and / or inductors to model the resistance, capacitance, and / or inductance of the conductors.

According to an exemplary embodiment of the present invention, while an output signal that transits according to a predetermined data pattern is generated at the output port of the integrated circuit model 200 ', the operating current (current) consumed by the signal drivers 211 to 214 i_pdn ') may be simulated. As shown in FIG. 4, signals D 1 to D 4 of a predetermined data pattern may be applied to the signal drivers 211 to 214. While the signal drivers 211 to 214 generate the output signal in response to the signals D1 to D4, the operating current i_pdn 'can be simulated.

According to an exemplary embodiment of the present invention, the predetermined data pattern may include a simultaneous transition of the signals D1 to D4 such that a large operating current i_pdn 'can be simulated. In addition, the supply voltage v_dc, which is an ideal DC voltage, can be applied to the signal drivers 211 to 214 to derive the operating current i_pdn '. The interconnect model 401, 402, 403, or 404 may be, for example, an LC model.

5A and 5B are diagrams illustrating methods of extracting a current profile in accordance with exemplary embodiments of the present invention. The steps S10b and S10c of receiving the specification information of the integrated circuit 200 in Figs. 5A and 5B and the steps S40b and S40c of calculating the target impedance are similar to the steps S10a and S40a of Fig.

5A is a diagram illustrating a method of extracting a current profile based on one data pattern in accordance with an exemplary embodiment of the present invention. Referring to FIG. 5A in conjunction with FIG. 4, step S20b of extracting a current profile according to an exemplary embodiment of the present invention includes step S21 of simulating an operating current i_pdn 'based on a predetermined data pattern, . ≪ / RTI > For example, in order to derive the operation current i_pdn 'corresponding to the worst case, the operation current i_pdn supplied to the signal drivers 411 through 414 in accordance with the data pattern that the signals D1 through D4 transit simultaneously Can be simulated.

According to an exemplary embodiment of the present invention, the current profile extraction step S20b may then convert the simulation result, i. E., The waveform of the operating current i_pdn ', to a frequency function (S22). The current profile can be extracted by converting the waveform of the operating current i_pdn 'derived through the simulation step S21 into a function of frequency using FFT.

5B is a diagram illustrating a method of extracting a current profile based on a plurality of data patterns. Referring to FIG. 5B in conjunction with FIG. 4, step S20c of extracting the current profile of the operating current i_pdn 'of the integrated circuit model 200', according to an exemplary embodiment of the present invention, (Step S23) of simulating the operating current i_pdn 'based on the operating current i_pdn'. For example, the plurality of data patterns may comprise a plurality of predetermined data patterns, or may comprise randomly generated data patterns. A plurality of simulation results, that is, waveforms of a plurality of operating currents i_pdn ', can be generated by simulating the operating current i_pdn' based on a plurality of data patterns.

In accordance with an exemplary embodiment of the present invention, a method of extracting a current profile S20c may then comprise the steps of generating a plurality of simulation results (i. E., Waveforms of a plurality of operating currents i_pdn ' (S24). The waveforms of the operating current i_pdn 'according to the plurality of simulation results generated through the simulation step S23 can be converted into functions of frequency using FFT. Since the operating current i_pdn 'consumed by the signal drivers 211 to 214 varies according to the data pattern, the waveforms of the simulated operating current i_pdn' based on the plurality of data patterns may be different from each other.

According to an exemplary embodiment of the present invention, the method of extracting the current profile may extract maximum values in the overlapping envelope of the converted frequency functions (S25c). Referring to FIG. 7, the frequency functions converted from the waveforms of different operating currents (i_pdn ') may overlap in one graph. Accordingly, an envelope defined by a minimum value and a maximum value of a plurality of frequency functions in all frequency ranges can be defined. According to an exemplary embodiment of the present invention, a current profile may be extracted to include high values of the envelope. In other words, the current profile can be extracted by extracting points located at the highest position in the vertical axis direction in the overlapping graphs in FIG.

By extracting the maximum value at all frequencies from the plurality of frequency functions, the current profile can correspond to the operating current i_pdn 'consumed by the integrated circuit model 200' in the worst case. Since the power transmission network 100 must have the operating voltage v_pdn within the tolerance of the supply voltage even in the worst case, the prototyping method of the power transmission network 100 according to the exemplary embodiment of the present invention is not limited to the worst case The corresponding current profile can be extracted.

Figure 6 is a diagram illustrating an integrated circuit model 200 " for deriving the operating current i_pdn of Figure 2 in accordance with an exemplary embodiment of the present invention. According to an exemplary embodiment of the present invention, the operating current i_pdn '' can be extracted by using the power model 220 of the core circuit included in the integrated circuit 200. For example, the core circuit may be defined by an RTL (Register Transfer Level) and the power model generation tool may generate the power model 220 from the RTL corresponding to the core circuit. The operation current i_pdn '' can be extracted based on the generated power model 220. [

Similar to the embodiment of FIG. 5A, the current profile can be extracted by converting the extracted operating current i_pdn '' based on power model 220 'into a function of frequency using FFT. Also, similar to the embodiment of FIG. 5B, waveforms of a plurality of operating currents i_pdn '' may be extracted based on the power model 220 'and converted to functions of frequency through an FFT. The current profile can then be extracted from the functions of frequency to include the maximum in all frequency domains.

7 is a graph showing the extracted operating current i_pdn in the frequency domain, in accordance with an exemplary embodiment of the present invention. Referring to FIG. 7, a plurality of frequency functions may be transformed from waveforms of a plurality of operation currents i_pdn according to an exemplary embodiment of the present invention, and a plurality of frequency functions may overlap in one graph. Thus, an envelope can be formed and the current profile can be extracted to include high values of the envelope. That is, a current profile can be extracted from a plurality of frequency functions to include a maximum value in all frequency domains. Accordingly, the current profile can correspond to the operation current i_pdn consumed by the integrated circuit 200 in the worst case.

FIG. 8 is a diagram illustrating a method for determining the placement and value of passive elements in accordance with an exemplary embodiment of the present invention, and FIG. 9 is an illustration of an example of a capacitor library 50. The step S40d of calculating the target impedance in Fig. 8 is similar to the step S40a in Fig. 8, step S60d of determining the placement and value of the passive elements includes calculating S61 the decoupling capacitance, determining the placement and value of the decoupling capacitor S62, 100 may include determining (S63) the permissible parasitic inductance of the conductors connecting the components in the semiconductor device. The conductors connecting the components in the power transmission network 100 having a decoupling capacitor and a parasitic inductance lower than the permissible parasitic inductance provide the charged charge to the integrated circuit 200 thereby reducing the operating voltage v_pdn to a tolerance of the supply voltage And the like. The number of decoupling capacitors, the physical size, and the operating frequency can be determined depending on the value of the decoupling capacitor, i.e., the capacitance.

According to an exemplary embodiment of the present invention, the target decoupling capacitance may be calculated from the target impedance (S61).

As shown in Equation 2, the target decoupling capacitance C_TAR can be calculated from the target impedance Z_TAR. As shown in Equation 2, the target decoupling capacitance C_TAR may be defined as a function of frequency and may be inversely proportional to the target impedance Z_TAR. The impedance Z_PDN of the power transmission network 100 may be designed to be lower than the target impedance Z_TAR and the decoupling capacitance of the power transmission network 100 may be designed to be higher than the target decoupling capacitance C_TAR.

Referring to FIG. 9, the capacitor library 50 may include a part number, a capacitance, a size information, and a resonance frequency of a capacitor for a plurality of capacitors. Except for the capacitors disposed on the die of the integrated circuit 200, the capacitors disposed on the board to which the package of the integrated circuit 200 and the package are attached are connected to predetermined capacitances, for example, capacitors included in the capacitor library 50 And the capacitor library 50 may include information on the characteristics of the capacitor in accordance with these predetermined capacitances. As shown in FIG. 9, the capacitor may have a resonance frequency, and the capacitor at the resonance frequency may operate similarly to the short circuit, and the resonance frequency may decrease as the capacitance of the capacitor increases. The capacitor may function as a capacitor in a frequency region lower than the resonance frequency, and such a frequency region may be referred to as an operating frequency. The capacitor library 50 may be extracted from the circuit models of the capacitors provided by the manufacturer of the capacitor.

As shown in FIG. 8, the arrangement and value of the decoupling capacitor can be determined based on the target decoupling capacitance and the capacitor library 50 (S62). The arrangement and capacitance of the decoupling capacitors included in the power transmission network 100 are determined such that the decoupling capacitance of the power transmission network 100 is higher than the target decoupling capacitance and is the smallest of the capacitances provided by the capacitor library 50 . Details of determining the placement and capacitance of the decoupling capacitors will be described in detail in Figures 10-13.

FIGS. 10 to 13 are diagrams for explaining a method of determining the arrangement and capacitance of a decoupling capacitor. FIG. 10 is a diagram illustrating a method for determining the placement and capacitance of a decoupling capacitor in accordance with an exemplary embodiment of the present invention. 11 is a diagram illustrating a plurality of groups of decoupling capacitors according to locations where a decoupling capacitor is disposed in accordance with an exemplary embodiment of the present invention. 12 is a diagram illustrating an operation for setting a plurality of groups according to an exemplary embodiment of the present invention. 13 is a diagram illustrating the results of determining the placement and capacitance of the decoupling capacitors of the power transmission network 100 in accordance with an exemplary embodiment of the present invention. In the following description, FIGS. 10 to 13 are referred to collectively.

Referring to Fig. 10, step S61e of calculating the decoupling capacitance is similar to step S61 of Fig. The step S62e of determining the arrangement and capacitance of the decoupling capacitor may comprise the step of setting a plurality of groups (S62_1). Specifically, a plurality of groups may be set based on the target decoupling capacitance and the location where the decoupling capacitor is placed. The step S62_1 will be described in detail with reference to Figs. 11 and 13. Fig.

Referring to FIG. 11, a system 2000 may include a board 500 to which a package 500 and a VRM 600 are attached. The package 500 may include two integrated circuits 200a and 200b and each of the integrated circuits 200a and 200b may be located in the package internal boards 501 and 502 respectively. The board 700 may be a printed circuit board (PCB) and the power, i.e., current and voltage, provided by the VRM 600 through the leads formed on the board 700 may be integrated To circuits 200a and 200b. The power transmission network 100 may be comprised of the conductors and decoupling capacitors C1 to C6 disposed between the VRM 600 and the integrated circuits 200a and 200b.

11, the power transmission network 100 includes a decoupling capacitor C1 disposed within the die of the integrated circuit 200b, a decoupling capacitor C1 disposed within the package 500 of the integrated circuits 200a, 200b, A decoupling capacitor C3 arranged in the area opposite to the package 500 in the board 700, a decoupling capacitor C4 arranged in the area separated by the first distance L1 from the package 500, A decoupling capacitor C5 disposed in a region spaced from the package 500 by a second distance L2 that is longer than the first distance L1 and a decoupling capacitor C6 disposed in an area adjacent to the VRM 600 . According to the exemplary embodiment of the present invention, the first to sixth groups G1 to G6 corresponding to the regions in which the respective decoupling capacitors C1 to C6 are arranged can be set. Each of the first through sixth groups Gl to G6 may have a size and number of deployable decoupling capacitors due to spatial constraints. The first distance L1 and the second distance L2 may be determined according to spatial constraints of the system 2000. According to the embodiment, the fourth group G4 and the fifth group G5 may be treated as one group.

Referring to FIG. 12, when the target decoupling capacitance is given as shown in FIG. 12, the first to sixth groups G1 to G6 are set so that the power transmission network 100 has a higher decoupling capacitance than the target decoupling capacitance . Specifically, the resonant frequency (or maximum operating frequency) of the decoupling capacitor that can be placed in the third group G3 can be determined from the capacitor library 50. [ As shown in Fig. 12, when the resonance frequency of the third group G3 is determined to be 50 MHz, the value of the target decoupling capacitance crossing 50 MHz may be approximately 2 nF. The decoupling capacitance of the first group G1 can be set to 2 nF when it is possible to arrange a 2nF decoupling capacitor in the first group G1 corresponding to the inside of the die of the integrated circuit 200b. Unlike FIG. 12, when it is impossible to arrange the decoupling capacitors of 2nF in the first group G1, the second group G2 and the first group G1 can be consecutively considered. In the same manner, the capacitances and resonance frequencies of the third to sixth groups G3 to G6 can be set.

10, the step S62e of determining the arrangement and capacitance of the decoupling capacitor may then include the step of selecting a capacitor from the capacitor library 50 in each of the plurality of groups (S62_2) have. Specifically, the capacitor can be selected from the capacitor library 50 to satisfy the resonance frequency and capacitance set for the plurality of groups.

12 and 13, the decoupling capacitors in the first group G1 corresponding to the inside of the die of the integrated circuit 200b may be determined to be 2 nF and the decoupling capacitors in the second group G2 may not be mapped have. Since the decoupling capacitance of the third group G3 is set to 30 nF, a capacitor having a capacitance of 33 nF and a resonance frequency of 40 MHz from the capacitor library 50 can be considered. However, since the resonance frequency does not reach the resonance frequency of the third group G3, the decoupling capacitor in the third group G3 may be composed of two capacitors having a capacitance of 15 nF and a resonance frequency of 50 MHz. In the same manner, the decoupling capacitors can be determined in the fourth to sixth groups G4 to G6.

14 is a diagram illustrating a method for calculating an allowable parasitic inductance in a conductor connecting components in a power transmission network in which an operating current i_pdn flows in accordance with an exemplary embodiment of the present invention. The permissible parasitic inductance can be used as a design guide in the physical layout and board design of the integrated circuit 200. The actual parasitic inductance of the conductors connecting the components in the power transmission network 100 need to be lower than the allowable values in the integrated circuit 200, package and board. After step S62e of Fig. 10 is finished, the permissible parasitic inductance of the conductor through which the operating current i_pdn flows as shown in Fig. 14 can be calculated. 14, the decoupling capacitors C1, C3 to C6 correspond to the decoupling capacitors of FIG. 11, and the decoupling capacitors C2 of the second group G2, as in the embodiment shown in FIG. 13, Are not disposed.

Referring to Fig. 14 in conjunction with Figs. 8 and 11, the permissible parasitic inductance of the line between the decoupling capacitors can be calculated. The actual parasitic inductance of a conductor can depend on the length and structure of the conductor. The parasitic inductance between the decoupling capacitor C2 and the decoupling capacitor C3 connected to each other through the pad of the package 500 is determined by the decoupling capacitor C3 and the decoupling capacitor C4 connected to the lead of the board 700, The parasitic inductance may be different. By considering the calculated permissible parasitic inductance, it is possible to appropriately determine the structure, length, and width of the leads connecting the decoupling capacitors when designing the system 2000, and the necessity for the actual parasitic inductance to be lower than the permissible parasitic inductance have.

In accordance with an exemplary embodiment of the present invention, the permissible parasitic inductances can be sequentially determined in the direction from the integrated circuit 200a or 200b to the VRM 600. [ 14 (a) to 14 (d) show the manner in which the parasitic inductance is calculated in order. 14 (d), which corresponds to the entire model of the power transmission network 100, the power transmission network 100 includes a power transmission network (not shown) disposed between the decoupling capacitors C1, C3 to C6 L34, L45, and L56, which represent the parasitic inductance of the conductors in the first and second regions 100 and 100, respectively. 14, in order to reflect the actual operation of the decoupling capacitor C1 disposed inside the die of the integrated circuit 200a or 200b to take charge of a high frequency component, A resistor R1 may be connected in series with the decoupling capacitor C1 to indicate the resistance of the die connection.

According to an exemplary embodiment of the present invention, the permissible parasitic inductance of the inductor L13 between the decoupling capacitor C1 of the first group G1 and the decoupling capacitor C3 of the third group G3 can be calculated first have. Referring to Figure 14 (d) in conjunction with Figure 13, the inductances of inductors L34, L45 and L56 at 50 MHz are so high that inductors L34, L45 and L56 are approximately considered open circuits . Thus, the inductance of the inductor L13 between the decoupling capacitor C1 that is responsible for a high frequency component of 50 MHz or more and the decoupling capacitor C3 that is adjacent to the decoupling capacitor C1 is the same as the inductance of the inductor L13 It can be calculated through a simple circuit. The inductance of the inductor L13 can be determined so that the resonance frequency of the circuit becomes 50 MHz.

The permissible parasitic inductances of the inductors L34, L45 and L56 can be calculated in the same manner as the method of calculating the inductance of the inductor L13. For example, referring to FIG. 14 (d), the permissible parasitic inductances of the inductors L45 and L56 at 10 MHz are very high, so the inductors L45 and L56 can be regarded as approximate open circuits. Accordingly, the inductance of the inductor L34 between the decoupling capacitor C3 that is responsible for a frequency component of 10 MHz or more and the decoupling capacitor C4 that is adjacent to the decoupling capacitor c3 is the same as that shown in FIG. 14 (b) Can be calculated through a circuit. The permissible parasitic inductance of the inductor L34 can be determined so that the resonance frequency of the circuit becomes 10 MHz. The manner of calculating the inductances of the inductors L45 and L56 is similar to that described above, and thus is omitted. The method of calculating the respective permissible parasitic inductances is referred to herein as a high-to-low frequency method.

15 is a diagram illustrating a method for creating a prototype of a power transmission network 100 in accordance with an exemplary embodiment of the present invention. The steps S10f, S20f, S40f, and S60f shown in FIG. 15 are similar to the steps S10a, S20a, S40a, and S60a shown in FIG. In accordance with an exemplary embodiment of the present invention, a method of generating a prototype of a power transmission network 100 includes the steps of determining (S60f) the placement and value of the passive elements, (Step S70f). If it is determined that the power transmission network is not feasible, step S60f of determining the placement and value of the passive element may be performed again.

For example, referring to FIG. 15 in conjunction with FIGS. 11 and 13, two capacitors are selected as decoupling capacitors in the third group G3 corresponding to the area opposite to the package 500 in the board 700, It can be determined that two capacitors can not be arranged in the area corresponding to the third group G3 by the package 500 and other components attached on the board 700. [ Thus, step S60f of determining the arrangement and value of the passive elements can again be performed, for example, so that a capacitor can be selected from the capacitor library in the second group G2. 15, it can be seen that the permissible parasitic inductance of the conductors in the power transmission network 100 between specific decoupling capacitors is calculated to have a low value and the actual parasitic inductance calculated according to the placement of the decoupling capacitors If the inductance can not be satisfied, step S60f of determining the placement and value of the passive element can be performed again.

16 is a block diagram illustrating another computer-readable storage medium 5000 in accordance with an exemplary embodiment of the present invention. The computer-readable storage medium 5000 may include any storage medium that can be read by a computer while being used to provide instructions and / or data to the computer. For example, the computer-readable storage medium 5000 may be a magnetic or optical medium such as a disk, a tape, a CD-ROM, a DVD-ROM, a CD-R, a CD-RW, a DVD- Volatile or nonvolatile memory such as ROM, flash memory, etc., nonvolatile memory accessible through a USB interface, and microelectromechanical systems (MEMS). The computer-readable storage medium 5000 may be embedded in a computer, integrated into a computer, or coupled to a computer via a communication medium such as a network and / or a wireless link.

16, a computer-readable storage medium 5000 is coupled to the power transfer network 100, such as a power transfer network design program 5200, integrated circuit information 5400, a capacitor library 5600, Type and may include a data structure 5800 for managing the data generated in the process of creating the prototype of the power transmission network 100. [

The power transmission network design program 5200 may include a plurality of instructions to perform a method of generating a prototype of the power transmission network 100. [ For example, computer readable storage medium 5000 may store a powertransmission network design program 5200 that includes any instructions that implement some or all of the flowcharts shown in one or more of the preceding figures. have.

The integrated circuit information 5400 may include information about the specifications of the integrated circuit 200 and may include information about the tolerance of the output port, the supply voltage, and the supply voltage of the integrated circuit, for example. The capacitor library 5600 may include information on the capacitance and the resonance frequency of each of the plurality of capacitors. The data structure 5800 may include storage space for managing data generated in the prototyping process of the power transmission network 100 performed in accordance with the power transmission network design program 5200, such as target impedance, and the like .

17 is a block diagram illustrating a computer system 6000 in accordance with an exemplary embodiment of the present invention. As shown in FIG. 17, the computer system 6000 may include a processor 6200, a memory 6400, and various peripherals 6600. Processor 6200 may be coupled to memory 6400 and peripheral devices 6600. [

The processor 6200 may be configured to execute instructions that perform at least one of the methods according to the exemplary embodiments of the invention described above. In accordance with an exemplary embodiment of the present invention, processor 6200 may be implemented as any instruction set (e.g., IA-32 (Intel Architecture-32), 64-bit extension IA-32, x86-64, PowerPC, Sparc, , IA-64, etc.). Computer system 6000 may also include one or more processors.

Processor 6200 may be coupled with memory 6400 and peripherals 6600 in any manner. For example, processor 6200 may be coupled to memory 6400 and / or peripheral devices 6600 through various interconnects. In addition, one or more bridge chips may be used to connect these components while creating multiple connections between processor 6200, memory 6400, and peripherals 6600.

Memory 6400 may comprise any type of memory system. For example, memory 6400 may include DRMA, DDR SDRAM, RDRAM, and the like. A memory controller may be included to interface to memory 6400, and / or processor 6200 may include the memory controller. The memory 6400 may store instructions to perform the method of generating the layout of the integrated circuit described above and data processed by the processor 6200. [

Peripherals 6600 may include any type of hardware devices, such as storage devices or input / output devices (such as video hardware, audio hardware, user interface devices, networking hardware, etc.), which may be included in or coupled to computer system 6000 . ≪ / RTI >

As described above, exemplary embodiments have been disclosed in the drawings and specification. While the embodiments have been described herein with reference to specific terms, it should be understood that they have been used only for purposes of describing the technical idea of the invention and not for limiting the scope of the invention as defined in the claims . Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (10)

A computer-implemented method of generating a prototype of a power transmission network of an integrated circuit,
Extracting a current profile of an operating current consumed by the integrated circuit from a simulation result of the integrated circuit;
Calculating a target impedance of the power transmission network based on the current profile, a supply voltage of the integrated circuit, and a tolerance of the supply voltage;
Determining placement of at least one passive element in the die of the integrated circuit, in the package, and in one of the boards to which the package is attached, based on the target impedance, and determining a value of the passive element; And
Generating a prototype of the power transmission network including the at least one passive element as computer processable data. The method according to claim 1,
Wherein the current profile and the target impedance are functions of frequency, respectively. The method according to claim 1,
Wherein the method of prototyping the power transmission network further comprises receiving specification information of the integrated circuit through a computer system,
Wherein the specification information includes information on an input / output port of the integrated circuit, a supply voltage, and a tolerance of the supply voltage. The method of claim 3,
The step of extracting the current profile comprises:
Simulating the operating current while the signals at the input / output port transit according to a predetermined data pattern; And
And converting the simulation result into a function of frequency. 5. The method of claim 4,
Wherein extracting the current profile further comprises extracting the current profile from the functions of frequency based on the plurality of data patterns to include a maximum value in all frequency domains. How to create a type. The method of claim 3,
Wherein the step of calculating the target impedance comprises generating the target impedance by dividing the product of the supply voltage and the tolerance of the supply voltage as the current profile. The method according to claim 1,
Wherein extracting the current profile comprises extracting a power profile by simulating a chip power model of the integrated circuit for a power transmission network for the core circuit of the integrated circuit. How to create a type. The method according to claim 1,
Wherein the step of determining the placement and value of the passive element comprises:
Calculating a target decoupling capacitance from the target impedance;
Determining placement and capacitance of at least one decoupling capacitor based on the target decoupling capacitance and the capacitor library; And
Calculating the permissible parasitic inductance of the conductors of the power transmission network between the components in the integrated circuit, the package, and the board,
Wherein the capacitor library includes information on a capacitance, a size, and a resonance frequency of each of the plurality of capacitors. 9. The method of claim 8,
Wherein the target decoupling capacitance is calculated based on the target impedance and the resonant frequency. 9. The method of claim 8,
Wherein the step of determining the arrangement and capacitance of the decoupling capacitor comprises:
And determining a placement of the decoupling capacitor in one of the areas spaced from the package by a predetermined distance. ≪ Desc / Clms Page number 21 >

Images