KR20160026653A - Substrate design for semiconductor packages and method of forming same - Google Patents

Substrate design for semiconductor packages and method of forming same Download PDF

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Publication number
KR20160026653A
KR20160026653A KR1020150075186A KR20150075186A KR20160026653A KR 20160026653 A KR20160026653 A KR 20160026653A KR 1020150075186 A KR1020150075186 A KR 1020150075186A KR 20150075186 A KR20150075186 A KR 20150075186A KR 20160026653 A KR20160026653 A KR 20160026653A
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South Korea
Prior art keywords
die
package
connector
rdl
rdls
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Application number
KR1020150075186A
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Korean (ko)
Inventor
첸후아 유
미릉-지 리이
치엔-선 리
청-딩 왕
정 웨이 쳉
밍-체 리우
하오-쳉 호우
훙젠 린
Original Assignee
타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드
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Priority claimed from US14/473,236 external-priority patent/US10026671B2/en
Application filed by 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 filed Critical 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드
Publication of KR20160026653A publication Critical patent/KR20160026653A/en

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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The present invention relates to a substrate design for a semiconductor package and a method for forming the same. According to an embodiment of the present invention, a device package includes first die and one or more redistribution layers (RDLs) electrically connected to the first die. The one or more RDLs extend laterally past edge parts of the first die. The device package further includes one or more second dies bonded to a first surface of the RDLs and a connector element on the first surface of the RDLs. The connector element has a vertical dimension greater than the second dies. A package substrate is bonded to the RDLs using the connector element, wherein the second dies are disposed between the first die and the package substrate.

Description

[0001] DESCRIPTION [0002] SUBSTRATE DESIGN FOR SEMICONDUCTOR PACKAGES AND METHOD OF FORMING SAME [0003]

<Priority claim and cross reference>

The present application is a continuation-in-part of U.S. Patent Application Serial No. 14 / 181,305, filed February 14, 2014, which is incorporated herein by reference in its entirety.

<Background>

In one aspect of the integrated circuit packaging technique, separate semiconductor dies are formed and initially separated. These semiconductor dies are then joined together and the die stack thus formed can be connected to other package components such as a package substrate (e.g., interposer, printed circuit board, etc.) using a connector on the bottom die of the die stack Lt; / RTI &gt;

The final package is known as Three-Dimensional Integrated Circuits (3DIC). The top die of the die stack may be electrically connected to other package components via an interconnect structure (e.g., through-substrate via, TSV) in the bottom die of the die stack. However, existing 3DIC packages may include a number of limitations. For example, a bonded die stack and other package components may result in large form factors and may require complex heat dissipation features. Conventional interconnection structures (e.g., TSV) of the bottom die are expensive to fabricate and the conduction path (e.g., signal / power path) to the normal die of the die stack may be long. Moreover, packages with conventional 3D ICs, specifically high density solder balls (e.g., package-on-package (PoP) configurations), thin package structures, etc., may have solder bridges, warpage, and / or other disruptions.

BRIEF DESCRIPTION OF THE DRAWINGS The aspects of the present disclosure are best understood from the following detailed description with reference to the accompanying drawings. Depending on the industry standard practice, the various features are not shown in full scale. In fact, the dimensions of the various features may be scaled up or down arbitrarily for convenience of explanation.
1A-1N are cross-sectional views of various intermediate stages for fabricating a semiconductor device package in accordance with some embodiments.
2 is a cross-sectional view of a semiconductor device package according to some alternative embodiments.
Figures 3A-3E are cross-sectional views of various intermediate stages for fabricating a semiconductor device package in accordance with some alternative embodiments.
4A-4L are perspective views of various intermediate stages for fabricating a package substrate in accordance with some embodiments.
5A and 5B are cross-sectional views of a semiconductor device package according to some alternative embodiments.
6A and 6B are cross-sectional views of a semiconductor device package according to some alternative embodiments.
7 is a cross-sectional view of a semiconductor device package according to some alternative embodiments.
8A-8H are different cross-sectional views of various intermediate stages for fabricating a semiconductor device package in accordance with some alternative embodiments.
9A-9C are cross-sectional and top views of a semiconductor device package including an interposer in accordance with some embodiments.
10A-10D are cross-sectional views of a semiconductor device package including an interposer in accordance with some alternative embodiments.
11A-11C are cross-sectional views of a semiconductor device package including an interposer in accordance with some alternative embodiments.
12 is a process flow diagram for forming a package in accordance with some alternative embodiments.

The following description provides a number of different embodiments or examples for implementing different features of the claimed subject matter. Specific embodiments of components and configurations are described below to simplify the present disclosure. Of course, these are merely examples, and are not intended to be limiting. For example, in the following description, the formation of the first feature on the second feature over or on may include an embodiment in which the first and second features are formed in direct contact, And an additional feature may be formed between the first and second features such that the second feature is not in direct contact. In addition, the present disclosure may repeat the reference numerals and / or characters in various embodiments. This repetition is for simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations described.

Also, terms related to space such as "beneath", "below", "lower", "above", "upper" May be used herein for ease of description in describing the relationship between a feature and other element (s) or feature (s). Spatial terms are intended to include different orientations of the device during use or operation, as well as the orientations shown in the figures. The device may be oriented differently (rotated to 90 degrees or other orientation) and the spatial descriptor used herein may be similarly interpreted accordingly.

Various embodiments include a plurality of first die (e.g., memory die) electrically connected to one or more second die (e.g., logic die) through a first input / output (I / O) And a redistribution layer (RDL). The final die stack may be bonded to another package component, such as an interposer, a package substrate, a printed circuit board, etc., via the RDL of the second I / O pad and the second die. The package substrate may include a cavity, and the first die may be disposed within the cavity. Thus, a three-dimensional integrated circuit (3DIC), such as a chip on a fan-out package, can be configured with a relatively inexpensive relatively small form factor and can have a relatively short conduction path (e.g., signal / power path) have. Furthermore, one or more heat dissipating features may be independently formed on the opposte surface of the first and / or second die.

1A-1N illustrate cross-sectional views of various intermediate stages for fabricating an integrated circuit (IC) package 100 (see FIG. 1n) in accordance with various embodiments. 1A shows a plurality of dies 10. The die 10 may include a substrate, an active device, and an interconnect layer (not shown). The substrate may be a bulk silicon substrate, but other semiconductor materials including Group III, Group IV, and Group V elements may be used. Alternatively, the substrate may comprise a semiconductor-on-insulator (SOI) structure. An active device such as a transistor can be formed on the top surface of the substrate. The interconnect layer may be formed over the active device and the substrate.

The interconnect layer may comprise an inter-layer dielectric (ILD) and an inter-metal dielectric layer (IMD) formed over the substrate. The ILD and IMD may be formed of a low k dielectric material with a k value of, for example, less than about 4.0 or even less than about 2.8. In some embodiments, the ILD and IMD include silicon oxide, SiCOH, and others.

A contact layer 12 comprising one or more contact pads may be formed over the interconnect structure and electrically connected to the active device through the various metal lines and vias in the interconnect layer. The contact pad in the contact layer 12 may be made of a metal material such as aluminum, but other metal materials may be used. A passivation layer (not shown) may be formed over the contact layer 12 from an inorganic material such as silicon oxide, undoped silicate glass, silicon oxynitride, or the like. The passivation layer may extend over and cover the edges of the contact pads in the contact layer 12. An opening is formed in the portion of the passivation layer covering the contact pad to expose at least a portion of the contact pad in the contact layer 12. The various features of the die 10 may be formed in any suitable manner, but will not be described in further detail herein. Also, the die 10 may be formed in a wafer (not shown) and singulated. A functional test can be performed on the die 10. Thus, the die 10 of FIG. 1A may only include what is known to be good passing one or more functional quality tests.

Next, referring to FIG. 1B, a die 10 may be disposed on the carrier 14. In FIG. The carrier 14 can be made of a suitable material, such as glass or carrier tape. The die 10 may be attached to the carrier 14 via one or more adhesive layers (not shown). The adhesive layer may be formed of any temporary adhesive material such as ultraviolet (UV) tape, wax, glue and the like. In some embodiments, the adhesive layer further comprises a die attach film (DAF), which may optionally be formed below the die 10 prior to placing the die 10 on the carrier 14 .

1C, a molding compound 16 may be used to fill the gap between the dies 10 and cover the top surface of the die 10. [ Molding compound 16 may comprise any suitable material such as epoxy resin, molded underfill, and the like. Suitable methods for forming the molding compound 16 may include compression molding, transfer molding, encapsulant molding, and the like. For example, molding compound 16 may be dispensed between dies 10 in liquid form. A curing process may then be performed to solidify the molding compound 16.

1D, a planarization process such as a grinding process (e.g., chemical mechanical polishing (CMP) or mechanical grinding) or etching back to expose the contact layer 12 (and any contact pads therein) A process may be performed on the molding compound 16. In a top view (not shown) of the die 10, the molding compound 16 may surround the die 10.

 1E illustrates forming a redistribution layer (RDL) 18 over the die 10 and the molding compound 16. 1E, the RDL 18 may extend laterally beyond the edge of the die 10 above the molding compound 16. The RDL 18 may comprise an interconnect structure 20 formed in one or more polymer layers 22. The polymer layer 22 can be formed from any suitable material (e.g., polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy, Silicon, acrylate, nano-filled phenol resin, siloxane, fluorinated polymer, polynorbornene, and the like).

Interconnect structures 20 (e.g., conductive lines and / or vias) may be formed in the polymer layer 22 and electrically connected to the contact layer 12 of the die 10. The formation of the interconnect structure 20 may include patterning the polymer layer 22 (e.g., using a combination of photolithography and etching processes), and patterning the patterned polymer layer 22 (Using a mask layer that defines the shape of the contact structure 20). The interconnect structure 20 may be formed of copper or a copper alloy, but other metals such as aluminum and gold may be used. The interconnect structure 20 may be electrically connected to the contact pads of the contact layer 12 (and consequently the active device) in the die 10.

1F and 1G illustrate forming the connector 24 over the RDL 18. In particular, connectors 24 and 26 are formed on the same side of die 10 (i.e., on the same side of RDL 18). The connectors 24, 26 may be formed of any suitable material (e.g., copper, solder, etc.) using any suitable method. In some embodiments, the formation of the connectors 24 and 26 is accomplished by first forming under bump metallurgies (UBM) 24 '/ 26' electrically connected to the active devices in the die 10 via the RDL 18 . &Lt; / RTI &gt; The connectors 24 and 26 may extend laterally beyond the edge of the die 10 to form a fanout interconnect structure. By including the RDL 18, the number of connectors 24 and 26 (e.g., input / output pads) connected to the die 10 can be increased. As the number of connectors 24, 26 increases, the bandwidth may increase and the processing speed may increase (e.g., as the signaling path becomes shorter) in a subsequently formed IC package (e.g., package 100 of Figure 1n) , The power consumption can be reduced (e.g., as the power induction path becomes shorter).

Further, the connectors 24 and 26 may have different sizes. For example, the connector 24 may be a micro bump having a pitch of about 40 microns or greater, and the connector 26 may be a controlled collapse chip connection (C4) bump having a pitch between about 140 microns and about 150 microns. In an alternative embodiment, the connectors 24, 26 may include different dimensions. Thus, as shown in Figs. 1F and Ig, the connector 24 can be formed before the connector 26 in consideration of the size difference.

By varying the size of the connectors 24 and 26, different electrical devices (e.g., connectors having different sizes) can be bonded to the die 10. For example, the connector 24 may be used to electrically connect the die 10 to one or more other device dies 28 (see FIG. 1H), and the connector 26 may connect the die 10 to the package substrate 30) (e.g., printed circuit board, interposer, etc., see Figure 1K). In addition, since the connectors 24, 26 are formed on the same side of the die 10, different electrical devices can also be bonded to the same side of the die 10. (10) and RDL (18), alternative embodiments may employ alternate configurations (e.g., different configurations of RDL 18 and / or connectors 24/26) .

In FIG. 1h, a plurality of die 32 may be bonded to die 10 to form die stack 10/32 through connector 24 (e.g., by reflowing connector 24). The die 32 may be electrically connected to the active device in the die 10 via the RDL 18. [ In some embodiments, the die stack 10/32 may include a memory die 32 (e.g., a dynamic random access memory (DRAM) die) that is bonded to the die 10, Or may be a logic die that provides control functionality to the die 32. In an alternative embodiment, other types of die may be included in the die stack 10/32. Next, the underfill 34 can be distributed around the connector 24 between the die 32 and the RDL 18, as shown in FIG. The underfill 34 can support the connector 24.

1J illustrates removing carrier 14 from die stack 10/32 using any suitable method. For example, in one embodiment where the adhesion between the die 10 and the carrier 14 is a UV tape, the die 10 can be removed by exposing the adhesive layer to UV light. Subsequently, the die stack 10/34 is unified and packaged into an IC package. Unification of the die stack 10/34 may involve the use of appropriate pick-and-place tools.

Next, each die stack 10/32 can be bonded to the package substrate 30 through the connector 26, as shown in Fig. 1K. Reflow may be performed on the connector 26 to bond the die stack 10/32 to the package substrate 30. Subsequently, the underfill 46 can be distributed around the connector 26 between the die stack 10/32 and the package substrate 30, as shown in FIG. The underfill 46 may be substantially the same as the underfill 34.

The package substrate 30 may be an interposer, a printed circuit board (PCB), or the like. For example, the package substrate 30 may comprise a core 37 and one or more buildup layers 39 (designated 39A and 39B) disposed on both sides of the core 37. Interconnect structures 38 (e.g., conductive lines, vias, and / or through vias) may be included within the package substrate 30 to provide functional electrical use of power, ground, and / or signal layers. Other configurations of the package structure 30 may also be used.

In addition, the package substrate 30 may include a cavity 36. The cavity 36 can not extend through the package substrate 30. Instead, some or all of buildup layer 39A (e.g., buildup layer 39 disposed on the same side of die stack 10/32 and core 37) may be patterned to form cavity 36 have. As shown in FIG. 11, the cavity 36 includes a core 37 and / or a buildup layer 39B (a buildup layer disposed on the opposite side of the core 37 from the die stack 10/32) 39). &Lt; / RTI &gt; The configuration of the package substrate 30 may be designed such that the active interconnection structure 38 (e.g., power, ground, and / or signal layers within the buildup layer 39A) Therefore, the cavity 36 will not substantially interfere with the functionality of the package substrate 30.

The package substrate 30 may be formed using any suitable method. For example, FIGS. 4A-4L illustrate perspective views of various intermediate stages for fabricating the package substrate 30 in accordance with various embodiments. In Figure 4a, a core 37 is provided. The core 37 may be a metal-clad insulated substrate such as a copper-clad epoxy-impregnated glass-cloth laminate or a copper-clad polyimide-impregnated glass-cloth laminate. 4B, the cavity 36 and / or the through hole 52 may be formed in the core 37 using, for example, a mechanical drilling or milling process. The mechanical drilling / milling process may extend the through hole 52 through the core 37. However, the mechanical drilling / milling process can not extend the cavity 36 through the core 37.

Next, in Fig. 4C, the surfaces of the through holes 52 and the cavity 36 can be plated with the metallic material 54, for example, using an electrochemical plating process. In some embodiments, the metallic material 54 may comprise copper. Plating of the through hole 52 may form a through via that provides electrical connection from one side of the core 37 to the other side. Moreover, the metallic material 54 'on the surface of the cavity 36 can function as a laser stopping layer in subsequent processing steps (see FIG. 4k). 4D, the cavity 36 and the through hole 52 can be filled with a suitable material 56 (e.g., ink). The material 56 may fill the cavity 36 / through hole 52 to provide a substantially level surface to form one or more buildup layers on the core 37. Grinding or other planarization techniques may be performed on the core 37. [

One or more layers 39 having interconnect structures 38 may be formed on either side of the core 37, as shown in Figures 4E-4I. Formation of the buildup layer 39 may include plating the core 37 with a conductive layer 58 comprising copper, for example, as shown in Figure 4E. Next, as shown in FIGS. 4F and 4G, the conductive layer 58 may be patterned to form a conductive line 38 '. Patterning of the conductive layer 58 may include laminating a dry film 60 (e.g., photoresist) over the conductive layer 58, patterning the dry film 60 (e.g., using an appropriate exposure technique) , And etching the conductive layer 58 using the patterned dry film 60 as a mask. Then, the dried film 60 can be removed.

In FIG. 4h, a buildup layer 39 'may be laminated over the conductive line 38' (shown faintly). The laminate of the buildup layer 39 'may comprise a curing process (e.g., heat treatment or pressure treatment). The opening 62 may be patterned within the buildup layer 39 '(e.g., via laser piercing), and the opening 62 may be aligned with the conductive line 38'. As shown in Figure 4i, additional conductive lines 38 "are formed using processes (e.g., conductive layer plating and patterning) that are substantially the same as those shown in Figures 4E-4H for forming conductive lines 38 ' The conductive layer plating process used to form the conductive lines 38 &quot; may be formed by plating the openings 62 (not shown in Figure 4h) to form a buildup layer &lt; RTI ID = 0.0 & (Not shown) for interconnecting the conductive lines 38 ', 38 "through the openings 62. The conductive lines 38" As shown in FIG. The process steps shown in FIGS. 4E-4I may be repeated as desired to form any build-up layer (e.g., power, ground, and / or signal layer) in the package substrate 30. 4e-4i illustrate forming the interconnect structure 38 / buildup layer 39 only on one side of the core 37, the same process may be performed on the opposite side of the core 37, Structure 38 / build-up layer 39 as shown in FIG.

4J, a solder resist 64 may be formed on the buildup layer 39 (e.g., on both sides of the core 37). Next, as shown in Fig. 4K, the cavity 36 can be patterned in the package substrate 30. Fig. The formation of the cavity 36 can be accomplished by patterning the solder resist 63 (e.g., using an exposure technique) and laser etching the buildup layer 39 using the material 54 'as a laser stop layer . Thus, the cavity 36 can not extend through the package substrate 30. Furthermore, the patterning of the solder resist 64 may pattern an opening (not shown) around the cavity 36 to expose the interconnect structure 38 in the buildup layer 39. These openings may be plated with a suitable material (e.g., nickel, aluminum, etc.) to form a contact pad 66 on the package substrate 30. [ The contact pad 66 may be electrically connected to the interconnect structure 38 in the buildup layer 39. Subsequently, a connector 68 (e.g., a solder ball) may be formed on the contact pad 66 for bonding with the die stack 10/32, as shown in FIG.

Referring again to FIG. 11, when the die stack 10/34 is bonded to the package substrate 30, the die 32 may be disposed at least partially within the cavity 36. In a top view (not shown) of the package 100, the cavity 36 may surround the die 32. Thus, the bonded structure can preferably have a relatively small form factor and high bandwidth. The die 32 may also be electrically connected to the package substrate 30 via the RDL 18 and connectors 24/26. In some embodiments, the die 10 may include less or no substrate through vias TSV for electrically connecting the die 32 to the package substrate 30. The cost of manufacturing the die 10 can be further reduced by reducing the number of TSVs.

Next, referring to FIG. 1M, a heat dissipating feature 40 is disposed on the die 10. The heat dissipation feature 40 may be disposed on the surface of the die 10 opposite the RDL 18, the connector 24, and the die 32. The heat dissipating feature 40 may be a high thermal conductivity, such as a contour lid having a wattage per meter kelvin of about 200 W / mK or more and a contour lid of about 400 W / Or the like. For example, the heat dissipating features 40 may include metals and / or metal alloys such as Al, Cu, Ni, Co, combinations thereof, and the like. The heat dissipation feature 40 may also be formed of a composite material such as silicon carbide, aluminum nitride, graphite, or the like. In some embodiments, the heat dissipating features 40 may also extend above the surface of the molding compound 16.

The package 100 is not used to be electrically connected to the die 32 or the package substrate 30 as compared to a conventional 3D IC in which the package substrate 30 and the die 32 are disposed on both sides of the die 10 (10 ') to the die (10). Thus, the heat dissipating pitch 40 can be placed directly on the surface 10 'of the die 10 for improved heat dissipation.

An interfacing material 42 may be disposed between the heat dissipating features 40 and the die 10 / molding compound 16. The interfacial material 42 may comprise a thermal interface material (TIM), such as a polymer having a good thermal conductivity of at least about 5 W / m 占 내지, such as about 3 W / m 占 K (watts per meter kelvin) . Because the TIM can have good thermal conductivity, the TIM can be placed (e.g., in contact) directly between the die 10 and the heat dissipating features 40. The interface material 42 may also include an adhesive (e.g., epoxy, silicone resin, etc.) for attaching the heat spreading lid 40 to the die 10 / molding compound 16. The adhesive used may be more adhesive and thermally conductive than TIM. For example, the adhesive used may have a thermal adhesion of less than about 0.5 W / m · K. Thus, the bonding portion of the interface material 42 can be disposed on a region where the heat radiation requirement is low (for example, on the surface of the molding compound 16).

After attachment of the heat dissipating feature 40, a marking process (e.g., laser marking) may be performed for display on the package 100. 1N, a connector 44 (e.g., a ball-and-array (BGA) ball) is mounted on the surface of the package substrate 30 opposite the connector 26 and the die stack 10/32 . The connector 44 may be used to electrically connect the package 100 to a motherboard (not shown) or another device component of the electrical system.

FIG. 1n shows the completed package 100. Because the die 32 is disposed within the cavity 36 of the package substrate 30, the package 100 can have a relatively small form factor and high bandwidth. By including the RDL 18, it is possible to further increase the number of I / O pads relative to the die stack 10/32, thereby achieving various performance advantages such as increased speed and reduced power consumption. In addition, the package substrate 30 and the die 32 may be disposed on the same side of the die 10 so that the heat dissipating features 40 may be placed directly on one side of the die 10 for improved heat dissipation.

FIG. 2 shows a cross-sectional view of a package 200 according to various alternative embodiments. Package 200 is substantially similar to package 100 and like reference numerals designate like elements. The contoured ring portion 40 'that may be included in the heat dissipation feature 40 may extend through the die 10 and the RDL 18 to the top surface of the package substrate 30. In a top view (not shown) of the package 200, a contoured ring portion 40 'may surround the die 10. The contoured ring portion 40 'is formed of substantially the same material as the remaining portion of the heat-radiating lid 40 (e.g., high Tk material) and can provide additional heat dissipation for the package 200. [ The contoured ring portion 40'can be attached to the package substrate 30 using any suitable material such as an adhesive layer 42 'disposed between the contoured ring portion 40' and the package substrate 30. [

3A-3E illustrate various intermediate steps for fabricating the package 300 in accordance with an alternative embodiment. Figure 3A shows a plurality of dies 10 having an RDL 18 and a connector 26 formed on the die 10. The various features shown in Fig. 2A can be formed using steps substantially similar to those formed in Figs. 1A-IJ, wherein like numerals denote like elements and are substantially similar to those features. Thus, the details of the features and their formation are omitted for the sake of brevity. 2A, however, the die 10 (including the RDL 18 and the connector 24) is separated from the carrier (e.g., the carrier 14) without being bonded onto the die 32 . Also, the connector 24 may not be formed on the RDL 18. Instead, the structure shown in FIG. 2A includes a connector 26 that belongs to substantially the same size on the RDL 18. FIG. For example, the connector 26 may be a C4 bump.

Figure 3b illustrates unification of the die 10 (e.g., along a scribe line with any pick and place tool) and attachment of the die 10 to the package substrate 30 via the connector 26 . In particular, the die 10 may be bonded to the package substrate 30 before the die 32 is attached to the package 300.

The configuration of the package substrate 30 in the package 300 may be changed from the configuration in the package 100. [ For example, the cavity 36 may be disposed on the opposite surface (not the same surface) of the package substrate 30. [ Within the package 300, the die 10 may be bonded to the surface 30A of the package substrate 30. The surface 30A may be substantially horizontal. The package substrate 30 may further include a surface 30B (e.g., in the cavity 36) and a surface 30C opposite the die 10. By including the cavity 36, the surfaces 30B and 30C may not be substantially horizontal. For example, in the orientation shown in FIG. 3B, the surface 30B may be higher than the surface 30C.

The formation of the package substrate 30 with the cavity 36 can be achieved by forming the core 37, the buildup layer 39B (e.g., placed on the opposing face of the die 10 and the core 37) and / (E.g., placed on the same side of die 10 and core 37). In various embodiments, the cavity 36 can not extend through the package substrate 30.

FIG. 3C illustrates the formation of various other features of the package 300. For example, reflow can be done on the connector 26 and the underfill 46 can be distributed around the connector 26. The connector 44 may be attached to the surface 30C of the package substrate 30 in opposition to the die 10. In addition, heat dissipating features 40 may be disposed on the die 10 / molding compound 16. An interfacial material 42 (including a TIM and / or an adhesive material) may be disposed between the heat dissipating features 40 and the die 10 / molding compound 16.

Functional testing may then be performed on the package 300 prior to attachment of the die 32. For example, the electrical connection between the die 10 and the package substrate 30 can be tested. If the package 300 passes the test, the die 32 may be attached to the package 30 using a connector 24 formed, for example, as shown in FIG. 3D. The connector 24 may be formed on the die 32 using any suitable method prior to attaching the die 32 to the package 300. By performing a functional test on the package 300 prior to attachment of the die 32, the die 32 can be attached only to a known good package. A package that fails the functional test is not attached to the die 32. Thus, cost savings can be achieved by avoiding the attachment of the die 32 to the defective package.

The connector 24 (e.g., micro-bumps) may be formed on the die 32 using any suitable method. The connector 24 may be of a different size than the connector 26 and the connector 24 may be attached to a contact pad on the package substrate 30. [ The connector 24 is mounted on the die 10 via the interconnection structure 38 (e.g., interconnect structure 38 '), the connector 26, and the RDL 18 in the package substrate 30, Can be electrically connected.

The die 32 may be disposed within the cavity 36 of the package substrate. Within the package 300, the die 32 and the die 10 may be disposed on opposite sides of the package substrate 30. Attaching the die 32 may include stepping the package 300 upside down (e.g., orienting the connector 24 upward) and aligning the die 32 within the cavity 36. (E.g., to electrically connect the die 32 to the die 10 / package substrate 30), and the underfill 34 may be dispensed around the connector 24 .

With the configuration of the package 300, a heat dissipation pitch (e.g., heat dissipation pitch 70) may be disposed on the surface die 32. [ The interface material 72 may be disposed between the heat dissipating pitch 70 and the die 32 so that the interface material 72 may be in physical contact with the die 32. [ The heat dissipation feature 70 and the interface material 72 may be substantially the same as the heat dissipation feature 40 and the interface material 42, respectively. Alternative manufacturing processes can then be used to form the package 300.

Figures 5A and 5B show cross-sectional views of semiconductor packages 400 and 500, respectively. Package 400, 500 is substantially similar to package 100, and like reference numerals denote like elements. On the other hand, the packages 400 and 500 may further include a plurality of dies 10 (denoted by 10A and 10B). Dies 10A and 10B may be part of the same fan-out package. For example, the dies 10A and 10B may be surrounded by the molding compound 16 and the RDL 18 may be formed on the surfaces of the dies 10A and 10B. The RDL 18 can electrically connect the dies 10A, 10B to the die 32. [ Also, the dies 10A, 10B may be substantially horizontal. The formation of the dies 10A, 10B may be substantially the same as the process shown in Figs. 1A-IJ, but the unification can be done at different locations (e.g., the scribe lines for the pick and place tool are configured at different locations . In some embodiments, the die 32 may be disposed in a cavity formed in the substrate 30 (as shown in Fig. 5A). In another embodiment, the die 32 may be disposed in the through hole 74 in the substrate 30 (as shown in Fig. 5B). The through hole 74 may be formed in the substrate 30 using, for example, a laser drilling process.

In an alternative embodiment, the package substrate 30 may be substantially free of any cavities or through holes. In such an embodiment, a connector element (e.g., connector 26 or interposer) may be used to bond the package substrate to the die 10 / RDL 18. Such a connector element may have a suitable configuration and sufficient standoff height to accommodate the die 32 between the die 10 / RDL 18 and the package substrate 30. In such an embodiment, the connector element may be further reinforced to provide structural support and reduce the risk of manufacturing defects (e.g., solder bridging). For example, in some embodiments, the connector element includes a connector 26 having an elongated bump portion (e.g., conductive post), a molded underfill (MUF) that extends at least partially along the side wall of the solder region, ), Interposers with conductive through vias and / or through holes, combinations thereof, and the like. 6A-C illustrate various semiconductor device packages according to this alternative embodiment.

Figures 6A and 6B illustrate cross-sectional views of semiconductor device packages 600 and 650, respectively. The packages 600 and 650 are substantially similar to the package 100 and the same reference numerals denote the same elements. The package substrate 30 of the packages 600 and 650 may not include any cavities or through holes therein. Instead, both the top and bottom surfaces of the package substrate 30 can be substantially horizontal.

In packages 600 and 650, die 32 and package substrate 30 are bonded to the same side of RDL 18 that electrically connects die 32, package substrate 30 and die 10 . In the above embodiment, the die 32 may be disposed between the RLD 18 and the package substrate 30. [ The connector 26 (e.g., joining the RDL 18 to the package substrate 30) may be elongated and long enough to provide a standoff height sufficient to accommodate the vertical dimension of the die 32. For example, the connector 26 may have a vertical dimension that is greater than the associated vertical dimension of the die 32 and connector 24 (used to bond the die 32 to the RDL 18).

Each connector 26 may include one or more conductive posts 27, including, for example, copper, nickel, gold, aluminum, combinations thereof, and the like. In some embodiments (e.g., as shown in FIG. 6A), each connector 26 may include a single conductive post 27 extending from the bottom surface of the RDL 18. A solder region 26 "(e.g., a solder ball) may be disposed on the conductive pillar 27 and a solder region 26 " may contact and electrically connect to the contact pad on the package substrate 30. [ In other embodiments, each connector 26 may include a first conductive post 27 'and a second conductive post 27 ". The first conductive post 27' and the second conductive post 27 " The conductive pillar portion 27 'extends from the bottom surface of the RDL 18. The second conductive pillar portion 27' 'extends from the top surface of the package substrate 30. In the above embodiment, the solder balls 26 "are disposed between the two conductive pillars 27 'and 27" to make them contact each other. Within the package 600, 650, the conductive posts 27, 27 ', 27 "are elongate and relatively large compared to the solder region 26 ". For example, in FIG. 6A, each conductive post 27 (of package 600) may occupy most of the vertical dimension of each connector 26 (e.g., greater than about 50%). In this embodiment, the conductive pillar 27 can have a vertical dimension that is larger than the solder region 26 &quot;. In addition, in Fig. 6 (b), the first and second conductive pillar portions Each of the connectors 27 ', 27 "may occupy at least about 20% to about 50% of the vertical dimension of each connector 26. In some embodiments, conductive pillar 27 (FIG. 6A) and conductive pillar 27 '(FIG. 6B) each may have a vertical dimension of about 100 μm or greater. By providing the portion 27, the size of the corresponding solder region 26 "can be reduced while still providing a sufficient standoff height to accommodate the die 32. The configuration of such a connector 26 can reduce the risk of manufacturing defects such as solder bridging.

 FIG. 7 shows a cross-sectional view of a semiconductor device package 700. FIG. Package 700 is substantially similar to package 600 or 650, and like reference numerals designate like elements. However, the connector 26 may have an alternative configuration within the package 700. For example, the connector 26 in the package 700 may include solder areas 702 and 704, and the connector 26 may bond the bottom surface of the RDL 18 to the top surface of the package substrate 30 . The RDL 18 may provide electrical connection between the die 10 (e.g., a logic die), the die 32, and the package substrate 30.

As with packages 600 and 650, connector 26 may have a vertical dimension large enough to accommodate die 32 between RDL 18 and package substrate 30. In some embodiments, the solder regions 702 and 704 may be two or more solder balls that are vertically stacked and reflowed to form the connector 26. [ A molded underfill (MUF) 706 may be disposed (at least partially) around the solder region 702 to provide structural support during subsequent reflow processes and to reduce the risk of solder bridging. In some embodiments, the MUF 706 may also be disposed about the connector 24 and extend at least partially along the sidewalls of the die 32.

8A-8H illustrate cross-sectional views of an intermediate step of forming a portion of a package 700 (e.g., a connector 26 having solder regions 702 and 704) according to some embodiments. First, referring to FIG. 8A, a cross-sectional view of a die 10 with a fan-out RDL 18 formed thereon is provided. The die 10 may be a semiconductor die having a contact pad 12 and a first passivation layer 11 covering the edge portion of the contact pad 12, as described above. 8A-8H, the die 10 includes a conductive pillar portion 13 (e.g., copper or the like) extending through an opening in the passivation layer 11 for electrical connection to the contact pad 12. In the embodiment shown in Figs. And the like). A second passivation layer 15 (e.g., including a polymer) may be formed on the passivation layer 11 and around the conductive pillar portion 13. The conductive features in the RDL 18 may be electrically connected to the conductive posts 13 and extend laterally beyond the edge of the die 10. In another embodiment, the conductive pillar portion 13 / passivation layer 15 may be omitted and the conductive features in the RDL 18 may be directly connected to the contact pad 12. Although FIG. 8A shows two dies 10, other embodiments may include any number of dies 10, depending on the package design. The die 10 may be attached to the carrier 14 (e.g., using an adhesive layer 17), and a molding compound 16 may be formed around the die 10.

A seed layer 708 may be formed on the RDL 18 using any suitable technique, such as sputtering, as further shown in Figure 8A. The seed layer 708 may comprise a conductive material (e.g., copper) and may be electrically connected to a conductive feature in the RDL 18. [ A photoresist 710 is formed on the seed layer 708 and is patterned to include an opening 712 that can expose a portion of the seed layer 708.

8B, a connector 24 (which is used to substantially bond the RDL 18 to the die 32, not shown in Fig. 8B) is at least partially formed within the opening 712. In Fig. For example, the connector 24 may be a micro-bump formed within the opening 712 using an electrochemical plating process. The connector 24 may include a plurality of conductive layers. For example, in FIG. 8B, the connector 24 includes a copper portion 24A and a nickel portion 24B on the copper portion. In this embodiment, first, a bottom conductive portion (e.g., copper portion 24A) may be formed, a second seed layer may be deposited on the bottom conductive portion thereof, (E.g., the nickel portion 24B) may be formed. Subsequently, a solder region (not shown) including, for example, tin and silver solder may be formed on the nickel portion 24B. On the other hand, the connector 24 may include any number of conductive layers and / or other conductive materials may be used. Subsequently, as also shown in FIG. 8B, the photoresist 710 can be removed.

FIGS. 8C and 8D illustrate the formation of the UBM 26 'for the connector 26. FIG. 8C, a second photoresist 714 is formed over the seed layer 708 and the connector 24. [ The photoresist 714 may mask over the connector 24 and the photoresist 714 may have openings that expose portions of the seed layer 708 previously masked by the photoresist 710 (see FIG. 8A) 716. &lt; / RTI &gt; Next, as shown in Fig. 8D, the UBM 26 'is formed in the opening 716 by using, for example, an electrochemical plating process. The photoresist 714 can then be removed.

8E, after formation of the connector 24 and the UBM 26 ', the seed layer 708 may be patterned using, for example, a combination of photolithography and / or etching processes. Patterning of the seed layer 708 may remove portions of the seed layer 708 that are not covered by the connector 24 or UBM 26 '. As further shown in FIG. 8E, a first solder region 702 (e.g., a solder ball) is disposed on the UBM 26 '.

8F, one or more dies 32 are attached to the connector 24, for example, using a reflow process. Connector 24 may electrically connect die 32 to RDL 18 (and die 10). Subsequently, a MUF 706 may be formed over the seed layer 708 and the RDL 18 (as also shown in FIG. 8F). The MUF 706 may extend further along the sidewalls of the die 32 and the solder region 702. In the illustrated embodiment, a solder region 702 may extend above the top surface of the MUF 706. [ The formation of the MUF 706 can be accomplished by any suitable process such as compression molding, transfer molding, encapsulant molding, and the like. The configuration of the illustrated MUF 706 can be achieved, for example, by controlling the amount of MUF material used.

8G shows planarization of the top of the solder region 702. FIG. After planarization, the top surfaces of the MUF 706 and the solder region 702 may be substantially horizontal. The solder region 702 may be planarized by any suitable process. For example, a coin head 718 operates to urge the rigid board 720 downward, so that the rigid substrate 720 will compress and flatten the top surface of the solder region 702 . The action of pressing and flattening the top surface of the solder region 702 is referred to as "coining" the solder region 702. [ In some embodiments, the coin head 718 heats the rigid substrate 720 to further heat the solder region 702 during the time that the rigid substrate 720 is pressed. As a result, the temperature of the solder region 702 is higher than room temperature (e.g., about 21 캜 to about 25 캜) and lower than the melting temperature of the solder region 702. In some embodiments, the temperature of the solder region 702 is between about 50 캜 and about 150 캜 during the coining process. In an alternative embodiment, the heating of the solder region 702 is done by heating the package 700 at the bottom.

With the heating of the solder region 702, the power required to coin the solder region 702 is reduced. Pressing of the coin head 718 causes the height of the solder region 702 to decrease and the rigid substrate 720 until the rigid substrate 720 touches the MUF 706, . The MUF 706 serves as a coining stopper. In addition, the thickness of the MUF 706 defines the final height of the solder region 702. The rigid substrate 720 may not contact the MUF 706 and the coined plane of the solder region 702 may be higher than the top surface of the MUF 706. In an alternative embodiment, Thereafter, rigid substrate 720 and coin head 718 can be removed. With the use of a coining process, a relatively flat top surface for subsequent formation of additional solder features on the solder region 702 can be formed. Alternatively, this coining process may be omitted.

Next, a solder region 704 (e.g., a second solder ball) is disposed on the planarized solder region 702, as shown in Fig. 8H. Accordingly, the connector 26 is formed in the package 700. [ In a subsequent process step, a connector 26 may be used to bond the RDL 18 to the package substrate 30 (e.g., see FIG. 7). Each connector 26 includes a UBM 26 ', a first solder region 702 (e.g., a coined solder ball), and a second solder region 704 over the solder region 702 Solder balls). The MUF 706 may be used to provide structural support during a subsequent reflow process (e.g., upon bonding of the package substrate 30) and to reduce the risk of manufacturing defects such as solder bridging.

9A-9C are different cross-sectional views of an intermediate stage forming a semiconductor package 800 in accordance with some alternative embodiments. Package 800 is substantially similar to package 700 and like reference numerals designate like elements. 9C, the interposer 802 is used to connect the bottom surface of the RDL 18 to the top surface of the package substrate 30 in place of the connector 26 in the package 800. However, Can be used.

Referring to FIG. 9A, the interposer 802 includes a substrate 804 having conductive vias 814 extending through the substrate. The substrate 804 may comprise silicon and may or may not further comprise a filler material (e.g., silica filler, glass filler, aluminum oxide, silicon oxide, etc.). The conductive vias 814 may include copper, nickel, gold, aluminum, combinations thereof, and the like, and the conductive vias 814 may extend from the top surface to the bottom surface of the substrate 804. Contact vias 806 (including conductive material) may be formed on the top and bottom surfaces of the substrate 804 over the conductive vias 801. [ In the embodiment shown, the interposer 802 may be laminated to the bottom surface of the RDL 18 (as indicated by arrow 810) and the contact pad 806 may be laminated to the conductive features (Not shown separately). Such a conductive feature may further provide an electrical connection between the interposer 802 and the die 10/32.

The interposer 802 may have a suitable configuration and vertical dimensions to accommodate the die 32 between the RDL 18 and the package substrate 30. [ For example, the interposer 802 may include a through hole extending through the interposer, as shown in the top view of the interposer 802 provided in FIG. 9B. When the interposer 802 is bonded to the RDL 18, the die 32 may be disposed (at least partially) in the through hole 808. Subsequently, the package substrate 30 may be bonded to the bottom surface of the interposer 802 using a connector 812 (e.g., a solder ball) and aligned with the conductive via 814. Interposer 802 and RDL 18 may provide electrical connection between die 10 (e.g., logic die), die 32 and package substrate 30. At this point, additional features (e.g., heat dissipation features 40) may be attached to the package 80. The final package structure is shown in Figure 9c.

10A and 10B illustrate cross-sectional views of forming a semiconductor device package 850 in accordance with an alternative embodiment. Package 850 is substantially similar to package 800 and like reference numerals designate like elements. Within package 850, interposer 802 may be bonded to RDL 18 by connector 26, rather than being laminated onto RDL 18. In some embodiments, the interposer 802 may be bonded to the RDL 30 prior to attachment of the package substrate 30 (e. G., As shown in FIG. 10A). In an alternative embodiment (e.g., as shown in FIG. 10B), an interposer 802 may first be bonded to the package substrate 30 (e.g., using connector 812 and / or a lamination process) , Followed by the die 10 / RDL 18. 10C shows a die 10, RDL 18, interposer 802, a die 32 disposed in the through hole 808 of the interposer 802, and a bonded package 850 &lt; / RTI &gt; 10D shows a completed package 850 after formation of additional features such as heat dissipation feature 40 and connector 44. As shown in FIG.

11A-C illustrate cross-sectional views of forming a semiconductor device package 900 in accordance with an alternative embodiment. Package 900 is substantially similar to package 800 and like reference numerals denote like elements. In package 900, interposer 802 may not include conductive vias 814 (see FIG. 9A). Instead, at least a portion of the connector 26 may extend through the opening 802 in the interposer 802 to bond the RDL 18 to the package substrate 30.

For example, referring to FIG. 11A, an interposer 802 having a through hole 902 extending through a substrate 804 is provided. Also provided is a connector 26 disposed on the bottom surface of the RDL 18. The connector 26 may include a UBM 26 'and a solder region 26' '. In some embodiments, the solder region 26' 'may extend through the opening 902 in the interposer 802 Lt; RTI ID = 0.0 &gt; and / or &lt; / RTI &gt; 11B, the interposer 802 is bonded to a connector 26 having a solder region 26 "extending through the substrate 804. The interposer 802 may be formed, for example, using a reflow process, Quot; can be attached to the &lt; / RTI &gt; The contact feature 806 may be electrically connected to the connector 26. In some embodiments, the solder region 26 "may extend further beyond the bottom surface of the interposer 802. In addition, The interposer 26 may bond the interposer 802 to the RDL 18 and the die 32 may be disposed in the through hole 808 of the interposer 802. Subsequently, The connector 26 is used to bond the RDL 18 to the package substrate 30. Figure 11C also shows the completed package 900 after formation of additional features such as the heat dissipation features 40 and the connector 44 Respectively.

Figure 12 illustrates a process flow 1000 of a method of forming a semiconductor device package in accordance with some embodiments. At step 1002, one or more RDLs (e.g., RDL 18) are formed on the surface of the first die (e.g., die 10). This RDL can also be referred to as a fanout RDL, since one or more RDLs can extend laterally beyond the edge of the first die (e.g., on a molding compound). Next, at step 1004, one or more second die (e.g., die 32) is bonded to the surface of one or more RDLs against the first die.

At step 1006, a connector element is formed on the surface of one or more RDLs. In some embodiments, the connector element may be, for example, a connector 26 (e.g., as shown in Figs. 6A and 6B) having one or more conductive posts and a solder region disposed on the conductive posts have. In another embodiment, the solder region may be disposed on the UBM and the forming underfill may extend at least partially along the side wall of the solder region (e.g., as shown in FIG. 7). In yet another embodiment, the connector element may include an interposer (e.g., interposer 802) that may include a through hole (e.g., through hole 808). In this embodiment, one or more second die may be disposed at least partially within the through-vias. At step 1008, a package substrate (e.g., package substrate 30) is bonded to the surface of one or more RDLs using a connector element. In some embodiments, the package substrate and the at least one second die may be bonded to the same side of the at least one RDL, and the at least one second die may be disposed between the package substrate and the at least one RDL. To accommodate this configuration, in the above embodiments, the connector element may have a vertical dimension that is greater than one or more second die.

Thus, as described above, the package substrate may include a cavity. A first die may be bonded to the package substrate, the cavity being on the same side of the first die and the package substrate, or on the opposite side of the package substrate with the first die. One or more second die may be bonded to the package substrate and the first die, and the second die may be disposed within the cavity. The second die may be directly bonded to the first die, or the second die may be bonded directly to the package substrate. In another embodiment, the package substrate may be substantially free of any cavities, and the second die may be disposed between the first die and the package substrate. The connector element joining the first die to the package substrate may be elongate and long enough to provide a sufficient standoff height to accommodate the second die. Thus, with this package substrate configuration, it is possible to package with a relatively thin form factor. Also, with this configuration of the die in the package, a relatively simple heat dissipation element can be attached to at least the first die.

According to one embodiment, the device package comprises a first die and one or more redistribution layers (RDL) electrically connected to the first die. One or more RDLs extend laterally past the edge of the first die. The device package further includes one or more second die bonded to a first side of the one or more RDLs and a connector element on the first side of the one or more RDLs. The connector element has a vertical dimension that is greater than one or more second die. A connector substrate is used to bond the package substrate to one or more RDLs, and one or more second die is disposed between the first die and the package substrate.

According to another embodiment, the device package comprises a first die, a molding compound extending along a sidewall of the first die, and one or more redistribution layers (RDL) on the first die and molding compound. The device package further comprises a plurality of second dies bonded to the surface of the one or more RDLs against the first die and the molding compound. A connector element is disposed on a surface of the one or more RDLs. The connector element bonds the package substrate to one or more RDLs and the plurality of second dies are disposed between the one or more RDLs and the package substrate. The device package further comprises one or more RDLs and a heat dissipation feature on the opposite side of the first die.

According to yet another embodiment, a method of forming a device package includes forming at least one redistribution layer (RDL) on a first die, and attaching one or more second die to the one or more RDLs To the surface of the substrate. One or more RDLs extend laterally past the edge of the first die. The method further includes forming a connector element on the surface of the one or more RDLs and bonding the package substrate to the surface of the one or more RDLs using the connector element. The connector element has a first vertical dimension that is greater than the second vertical dimension of the at least one second die and the at least one second die is disposed between the at least one RDL and the package substrate.

The foregoing is a summary of features of the various embodiments to enable those skilled in the art to more fully understand aspects of the disclosure. Those skilled in the art will readily appreciate that the present disclosure can readily be used as a basis for designing or modifying other processes and structures to accomplish the same purpose and / or achieving the same effects of the embodiments presented herein. It will also be appreciated by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of this disclosure and that various changes, substitutions and alterations can be made therein without departing from the spirit and scope of the disclosure.

Claims (10)

In a device package,
A first die,
At least one redistribution layer (RDL) electrically connected to the first die and extending laterally beyond the edge of the first die,
At least one second die bonded to a first side of the at least one RDL,
A connector element on a first side of the one or more RDLs, the connector element having a vertical dimension greater than the one or more second die;
And a package substrate bonded to the one or more RDLs using the connector element.
/ RTI &gt;
Wherein the at least one second die is disposed between the first die and the package substrate. The connector according to claim 1,
A first conductive pillar on a first side of the at least one RDL,
A solder region disposed on the first conductive pillar portion;
Gt; device package. &Lt; / RTI &gt; 3. The package of claim 2, wherein the connector element further comprises a second conductive post on a second side of the package substrate, wherein the solder region is disposed between the first conductive post and the second conductive post Device package. 3. The device package of claim 2, wherein the first conductive post has a vertical dimension greater than the solder region. The connector according to claim 1,
A solder region,
A molded underfill surrounding the solder region,
The solder balls on the solder region
Gt; device package. &Lt; / RTI &gt; 6. The device package of claim 5, wherein the forming underfill extends at least partially along a side wall of the at least one second die. The device package of claim 1, wherein the connector element is an interposer including a through hole, and wherein the at least one second die is at least partially disposed within the through hole. 8. The apparatus of claim 7, wherein the interposer comprises:
A substrate;
At least one of a copper via or a solder region extending through the substrate
Lt; / RTI &gt; package. In a device package,
A first die,
A molding compound extending along a side wall of the first die,
One or more redistribution layers (RDL) on the first die and the molding compound,
A plurality of second die bonded to a surface of the one or more RDLs against the first die and the molding compound,
A connector element on the surface of the one or more RDLs, the connector element joining the package substrate to the one or more RDLs, and the plurality of second die being disposed between the one or more RDLs and the package substrate. Wow,
Wherein the one or more RDLs comprise a heat dissipation feature on an opposing face of the first die,
/ RTI &gt; A method of forming a device package,
Forming on the first die at least one redistribution layer (RDL) extending laterally beyond the edge of the first die;
Bonding one or more second die to the surface of the one or more RDLs against the first die;
Forming a connector element on the surface of the at least one RDL, wherein the connector element has a first vertical dimension that is greater than a second vertical dimension of the at least one second die;
Joining the package substrate to the surface of the one or more RDLs using the connector element
Lt; / RTI &gt;
Wherein the at least one second die is disposed between the at least one RDL and the package substrate.
KR1020150075186A 2014-08-29 2015-05-28 Substrate design for semiconductor packages and method of forming same KR20160026653A (en)

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USD918860S1 (en) * 2019-10-11 2021-05-11 Vizio, Inc. Low profile speaker
CN112864123A (en) * 2019-11-27 2021-05-28 联发科技股份有限公司 Semiconductor packaging structure
US11532584B2 (en) * 2016-12-30 2022-12-20 Intel Corporation Package substrate with high-density interconnect layer having pillar and via connections for fan out scaling

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KR20210093612A (en) 2020-01-20 2021-07-28 삼성전자주식회사 Semiconductor package with barrier layer
KR20210105255A (en) 2020-02-18 2021-08-26 삼성전자주식회사 Semiconductor package-and-package on package having the same

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US11532584B2 (en) * 2016-12-30 2022-12-20 Intel Corporation Package substrate with high-density interconnect layer having pillar and via connections for fan out scaling
USD918860S1 (en) * 2019-10-11 2021-05-11 Vizio, Inc. Low profile speaker
CN112864123A (en) * 2019-11-27 2021-05-28 联发科技股份有限公司 Semiconductor packaging structure

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