KR102473590B1 - Semiconductor device and method - Google Patents

Abstract

An embodiment is a package structure, the package structure including a first integrated circuit die, and a redistribution structure bonded to the first integrated circuit die, the redistribution structure comprising: a first metallization pattern in a first dielectric layer—a first The metallization pattern includes a plurality of first conductive features, each of the first conductive features being over and electrically coupled to a first conductive via in the first dielectric layer and to the respective first conductive via; a first conductive line, each of the first conductive lines including a curved line in plan view, a second dielectric layer over the first dielectric layer and the first metallization pattern, and a second metallization in the second dielectric layer; a pattern, wherein the second metallization pattern includes a plurality of second conductive vias in the second dielectric layer, each of the second conductive vias over and electrically connected to each first conductive line; are coupled

Description

Semiconductor device and method {SEMICONDUCTOR DEVICE AND METHOD}

Priority claims and cross-references

This application claims priority from US Provisional Application Serial No. 63/15,775, filed on April 27, 2020, which is hereby incorporated herein by reference.

The semiconductor industry has grown rapidly due to continuous improvements in integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.). In most cases, improvements in integration density are due to iterative reductions in minimum feature size, allowing more components to be integrated within a given area. As the demand for shrinking electronic devices increases, smaller and more inventive packaging techniques of semiconductor dies are needed. An example of such packaging systems is Package-on-Package (PoP) technology. In PoP devices, a top semiconductor package is stacked on top of a bottom semiconductor package, providing a high level of integration and component density. Generally, PoP technology enables the production of semiconductor devices with improved functionalities and small footprints on a printed circuit board (PCB).

Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.
1 illustrates a cross-sectional view of an integrated circuit, in accordance with some embodiments.
2-7 and 10-18 illustrate cross-sectional views of intermediate steps during a process for forming a package component, in accordance with some embodiments.
8 is a top view of conductive features, in accordance with some embodiments.
9A and 9B are detailed top views of the conductive features illustrated in FIG. 8, in accordance with some embodiments.
19 illustrates a cross-sectional view of formation and implementation of device stacks, in accordance with some embodiments.

The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, formation of a first feature on or onto a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and the first and second features are formed in direct contact. Embodiments may also be included in which additional features may be formed between the first and second features such that they may not come into direct contact. In addition, the disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Additionally, spatially relative terms such as “below,” “below,” “lower,” “above,” “upper,” etc. refer to one element or feature and other element(s), as illustrated in the figures. or may be used herein for convenience of description to explain the relationship of the feature(s). Spatially relative terms are intended to include different orientations of the device in use or operation other than the orientation shown in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be similarly interpreted accordingly.

Redistribution structures including metallization patterns and methods of forming the same are provided, according to some embodiments. In particular, redistribution structures include metallization patterns with shapes that provide more flexibility to the metallization pattern to handle warping and other deformations without breaking. For example, the metallization patterns may have a curved, “C”-shaped, or “U”-shaped shape in plan view. Metallization patterns in redistribution structures may warp or deform due to coefficient of thermal expansion (CTE) mismatches of materials in a semiconductor package. This CTE mismatch allows the metallization patterns to withstand high stresses due to bending and deformation. However, the disclosed shapes of metallization patterns with increased flexibility increase the reliability of the redistribution structure. These flexible-shaped metallization patterns are surrounded by conforming dielectric layers such as polymer layers. The combination of flexible-shaped metallization patterns and surrounding conformal dielectric layers provides a buffer to release stress in the redistribution structure and package structure.

1 illustrates a cross-sectional view of an integrated circuit die 50, in accordance with some embodiments. The integrated circuit die 50 will be packaged in subsequent processing to form an integrated circuit package. The integrated circuit die 50 may include a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system-on-chip (SoC), an application processor (AP), a microcontroller, etc.), a memory die (e.g., , dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), power management die (e.g., power management integrated circuit (PMIC) die), radio frequency (RF) die, sensor die, MEMS (micro -electro-mechanical-system) die, signal processing die (e.g., digital signal processing (DSP) die), front-end die (e.g., analog front-end (AFE) die), etc., or combinations thereof .

Integrated circuit die 50 may be formed in a wafer that may include different device regions that are singulated in subsequent steps to form a plurality of integrated circuit dies. Integrated circuit die 50 may be processed according to applicable manufacturing processes to form integrated circuits. For example, the integrated circuit die 50 includes an active layer of a doped or undoped semiconductor substrate 52, such as silicon, or a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 52 may be made of other semiconductor materials, such as germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates may also be used, such as multilayer or gradient substrates. The semiconductor substrate 52 has an active surface (e.g., the upward facing surface in FIG. 1) (sometimes referred to as the front face), and an inactive surface (e.g., the downward facing surface in FIG. 1) (sometimes referred to as the back face). have

Devices (represented by transistors 54 ) may be formed on the front surface of the semiconductor substrate 52 . Devices 54 may be active devices (eg, transistors, diodes, etc.), capacitors, resistors, and the like. An interlayer dielectric (ILD) 56 is over the front surface of the semiconductor substrate 52 . ILD 56 may surround and cover devices 54 . The ILD 56 is composed of Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), and Boron-Doped Phospho-Silicate Glass. , BPSG), undoped silicate glass (USG), and the like.

Conductive plugs 58 extend through ILD 56 to electrically and physically couple devices 54 . For example, when devices 54 are transistors, conductive plugs 58 may couple the gate and source/drain regions of the transistors. Conductive plugs 58 may be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, etc., or combinations thereof. Interconnect structure 60 overlies ILD 56 and conductive plugs 58 . Interconnect structure 60 interconnects devices 54 to form an integrated circuit. Interconnect structure 60 may be formed by, for example, metallization patterns in dielectric layers on ILD 56 . The metallization patterns include metal lines and vias formed in one or more low-k dielectric layers. The metallization patterns of interconnect structure 60 are electrically coupled to devices 54 by conductive plugs 58 .

The integrated circuit die 50 further includes pads 62, such as aluminum pads, to which external connections are made. Pads 62 are on the active side of integrated circuit die 50 , such as in and/or on interconnect structure 60 . One or more passivation films 64 are on the integrated circuit die 50 , such as on the pads 62 and portions of the interconnect structure 60 . Openings extend through passivation films 64 to pads 62 . Die connectors 66, such as conductive pillars (eg, formed of a metal such as copper), extend through openings in passivation films 64 and are physically and electrically coupled to pads 62, respectively. do. Die connectors 66 may be formed, for example, by plating or the like. Die connectors 66 electrically couple the respective integrated circuits of integrated circuit die 50 .

Optionally, solder regions (eg, solder balls or solder bumps) may be disposed on the pads 62 . Solder balls may be used to perform chip probe (CP) testing on the integrated circuit die 50 . The CP test may be performed on the integrated circuit die 50 to verify that the integrated circuit die 50 is a known good die (KGD). Accordingly, only integrated circuit dies 50 that are KGDs are packaged through subsequent processing, and dies that fail the CP test are not packaged. After testing, the solder regions can be removed in subsequent processing steps.

Dielectric layer 68 may (or may not) be on the active side of integrated circuit die 50, such as may (or may not) be on passivation films 64 and die connectors 66. ). Dielectric layer 68 laterally encapsulates die connectors 66 and dielectric layer 68 is laterally co-end with integrated circuit die 50 . Initially, dielectric layer 68 may bury die connectors 66 such that a top surface of dielectric layer 68 is above top surfaces of die connectors 66 . In some embodiments where solder regions are disposed on die connectors 66, dielectric layer 68 may also bury the solder regions. Alternatively, the solder regions may be removed prior to forming dielectric layer 68.

Dielectric layer 68 may be a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like; nitrides such as silicon nitride and the like; oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), and the like; etc., or combinations thereof. Dielectric layer 68 may be formed by, for example, spin coating, lamination, chemical vapor deposition (CVD), or the like. In some embodiments, die connectors 66 are exposed through dielectric layer 68 during formation of integrated circuit die 50 . In some embodiments, die connectors 66 remain buried and exposed during a subsequent process for packaging the integrated circuit die 50 . Exposing the die connectors 66 may remove any solder areas that may be on the die connectors 66 .

In some embodiments, integrated circuit die 50 is a stacked device that includes multiple semiconductor substrates 52 . For example, the integrated circuit die 50 may be a memory device comprising multiple memory dies, such as a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, or the like. In these embodiments, the integrated circuit die 50 includes multiple semiconductor substrates 52 interconnected by through-substrate vias (TSVs). Each of the semiconductor substrates 52 may (or may not) have an interconnection structure 60 .

2-18 illustrate cross-sectional views of intermediate steps during the process for forming the first package component 100, in accordance with some embodiments. A first package section 100A and a second package section 100B are illustrated, and one or more of the integrated circuit dies 50 are packaged to form an integrated circuit package in each of the package sections 100A and 100B. Integrated circuit packages may also be referred to as integrated fan-out (InFO) packages.

In FIG. 2 , a carrier substrate 102 is provided and a release layer 104 is formed on the carrier substrate 102 . The carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 102 may be a wafer so that multiple packages may be formed on the carrier substrate 102 simultaneously.

The release layer 104 may be formed of a polymer-based material that may be removed along with the carrier substrate 102 from superstructures to be formed in subsequent steps. In some embodiments, the release layer 104 is an epoxy-based heat-release material, such as a light-to-heat-conversion (LTHC) release coating, that loses adhesive properties when heated. In other embodiments, the release layer 104 can be an ultraviolet (UV) glue that loses adhesive properties when exposed to UV lights. The release layer 104 may be discharged as a liquid and cured, or may be a laminate film laminated on the carrier substrate 102 , and the like. The top surface of the release layer 104 may be leveled and may have a high degree of flatness.

3-7, a redistribution structure 120 (see FIG. 7) is formed over the release layer 104. The redistribution structure 120 includes dielectric layers 124, 128, 132, 136, and 140; and metallization patterns 126, 130, 134, and 138. Metallization patterns may also be referred to as redistribution layers or redistribution lines. The redistribution structure 120 is shown as an example having four layers of metallization patterns. More or fewer dielectric layers and metallization patterns may be formed in the redistribution structure 120 . If fewer dielectric layers and metallization patterns are to be formed, the steps and process discussed below can be omitted. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed below can be repeated.

In FIG. 3 , a dielectric layer 124 is deposited over the release layer 104 . In some embodiments, dielectric layer 124 is formed of a photosensitive material that can be patterned using a lithography mask, such as PBO, polyimide, BCB, or the like. Dielectric layer 124 may be formed by spin coating, lamination, CVD, the like, or a combination thereof. Dielectric layer 124 is then patterned. Patterning forms openings that expose portions of the release layer 104 . Patterning may be accomplished by any acceptable process, such as by exposing and developing dielectric layer 124 to light when dielectric layer 124 is a photosensitive material, or etching using, for example, anisotropic etching. can be made by

A metallization pattern 126 is then formed. Metallization pattern 126 extends along a major surface of dielectric layer 124 and includes conductive elements that extend through dielectric layer 124 . As an example for forming metallization pattern 126 , a seed layer is formed over dielectric layer 124 and in openings extending through dielectric layer 124 . In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, physical vapor deposition (PVD) or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like, and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 126 . Patterning forms openings through the photoresist to expose the seed layer. A conductive material is then formed over the openings in the photoresist and the exposed portions of the seed layer. The conductive material may be formed by plating such as electroplating or electroless plating. Conductive materials may include metals such as copper, titanium, tungsten, aluminum, and the like. The combination of the conductive material and the lower portions of the seed layer form metallization pattern 126 . Portions of the seed layer that do not have photoresist and conductive material formed thereon are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as by using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching.

In FIG. 4 , dielectric layer 128 is deposited over metallization pattern 126 and dielectric layer 124 . Dielectric layer 128 may be formed in a manner similar to dielectric layer 124 and may be formed of a material similar to dielectric layer 124 .

A metallization pattern 130 is then formed. Metallization pattern 130 is on a major surface of dielectric layer 128 and includes portions extending along a major surface of dielectric layer 128 . Metallization pattern 130 further includes portions extending through dielectric layer 128 to physically and electrically couple metallization pattern 126 . Metallization pattern 130 may be formed in a similar manner and from a similar material to metallization pattern 126 . In some embodiments, metallization pattern 130 has a different size than metallization pattern 126 . For example, the conductive lines and/or vias of metallization pattern 130 may be wider or thicker than the conductive lines and/or vias of metallization pattern 126 . Additionally, metallization patterns 130 may be formed with a larger pitch than metallization patterns 126 .

In FIG. 5 , dielectric layer 132 is deposited over metallization pattern 130 and dielectric layer 128 . Dielectric layer 132 may be formed in a manner similar to dielectric layer 124 and may be formed of a material similar to dielectric layer 124 .

A metallization pattern 134 is then formed. Metallization pattern 134 is on a major surface of dielectric layer 132 and includes portions extending along a major surface of dielectric layer 128 . Metallization pattern 134 further includes portions extending through dielectric layer 132 to physically and electrically couple metallization pattern 130 . Metallization pattern 134 may be formed in a similar manner and from a similar material to metallization pattern 126 . In some embodiments, metallization pattern 134 has a different size than metallization patterns 126 and 130 . For example, the conductive lines and/or vias of metallization pattern 134 may be wider or thicker than the conductive lines and/or vias of metallization patterns 126 and 130 . Additionally, metallization patterns 134 may be formed with a larger pitch than metallization patterns 130 .

In FIG. 6 , dielectric layer 136 is deposited over metallization pattern 134 and dielectric layer 132 . Dielectric layer 136 may be formed in a manner similar to dielectric layer 124 and may be formed of a material similar to dielectric layer 124 .

A metallization pattern 138 is then formed. The metallization pattern 138 is on a major surface of the dielectric layer 132 and extends along the major surface of the dielectric layer 132 at portions 138a (portions as discussed below in FIGS. 9A and 9B ). (including 138a1, 138a2, and 138a3)). Metallization pattern 138 further includes portions 138b extending through dielectric layer 136 to physically and electrically couple metallization pattern 134 . Metallization pattern 138 may be formed in a similar manner and from a similar material to metallization pattern 126 . The metallization pattern 138 is the topmost metallization pattern of the redistribution structure 120 . In some embodiments, metallization pattern 138 has a different shape than metallization patterns 126 , 130 , and 134 . For example, portions 138a of metallization patterns 138 may be formed into curved, "C"-shaped, or "U"-shaped shapes that, in plan view, can be bent and deformed without breaking. (see FIGS. 8, 9A, and 9B as discussed below). Additionally, metallization patterns 134 , 130 , and 126 may be formed with a larger pitch than metallization pattern 138 .

In FIG. 7 , dielectric layer 140 is deposited over metallization pattern 138 and dielectric layer 136 . Dielectric layer 140 may be formed in a manner similar to dielectric layer 124 and may be formed of a material similar to dielectric layer 124 . Dielectric layer 140 is then patterned. Patterning forms openings that expose portions of metallization pattern 138 . Patterning may be accomplished by any acceptable process, such as by exposing and developing dielectric layer 140 to light when dielectric layer 140 is a photosensitive material, or etching using, for example, anisotropic etching. can be made by

Dielectric layer 140 has a thickness T ₁ , and the conductive features of metallization pattern 138 have a thickness T ₂ . In some embodiments, the thickness T ₁ of dielectric layer 140 is greater than the thickness T ₂ of metallization pattern 138 . In some embodiments, the thickness T ₁ ranges from 5 μm to 20 μm. In some embodiments, the thickness T ₁ ranges from 5 μm to 8 μm. In some embodiments, the thickness T ₂ ranges from 2 μm to 15 μm. In some embodiments, the thickness T ₂ ranges from 2 μm to 5 μm.

In some embodiments, metallization pattern 138 has a different size than metallization patterns 126 , 130 , and 134 . For example, in some embodiments, the conductive lines and/or vias of metallization pattern 138 are wider or wider than the conductive lines and/or vias of metallization patterns 126, 130, and 134. can be thick In some embodiments, the conductive lines and/or vias of metallization pattern 138 are of the same width and/or thickness as the conductive lines and/or vias of metallization patterns 126, 130, and 134. It can be done.

In some embodiments, dielectric layer 140 has a different thickness than dielectric layers 124 , 128 , 132 , and 136 . For example, in some embodiments, dielectric layer 140 may be thicker than dielectric layers 124 , 128 , 132 , and 136 . In some embodiments, dielectric layer 140 may be of the same thickness as dielectric layers 124 , 128 , 132 , and 136 .

Conductive vias 142 are then formed in the openings in dielectric layer 140 to physically and electrically couple metallization pattern 138 . As an example for forming the conductive vias 142 , a seed layer is formed in the openings extending through the dielectric layer 140 . In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A conductive material is then formed on the seed layer in the openings. The conductive material may be formed by plating such as electroplating or electroless plating. Conductive materials may include metals such as copper, titanium, tungsten, aluminum, and the like. The combination of the conductive material and the lower portions of the seed layer form conductive vias 142 . To form a substantially planar top surface of conductive vias 142 and dielectric layer 140, a planarization process may be performed. The planarization process may include, for example, a chemical mechanical polish (CMP) process.

8 is a top view of conductive features of redistribution structure 120 , including metallization pattern 138 (ie, portions 138a and 138b ) and conductive vias 142 . As illustrated in FIG. 8 , portions 138a of metallization pattern 138 have a curved, “C”-shaped, or “U”-shaped shape in plan view, where portions 138b are Located at the first end of the curved shape, the conductive vias 142 are located at the second end of the curved shape. A curved, “C”-shaped, or “U”-shaped shape can act like a coil of a spring and can be bent and deformed without breaking. Metallization patterns in redistribution structures may warp or deform due to coefficient of thermal expansion (CTE) mismatches of materials in a semiconductor package. This CTE mismatch allows the metallization patterns to withstand high stresses due to bending and deformation. However, the disclosed shapes of metallization patterns with increased flexibility increase the reliability of the redistribution structure. Flexible-shaped metallization pattern 138 and flexible dielectric layer 140 may be referred to as stress buffer films because they provide a buffer to safely release stress in the redistribution structure and package structure.

FIG. 9A illustrates a detailed view of the “C”-shaped conductive features of metallization pattern 138 from FIG. 8 . The portion 138a includes a first portion 138a1 immediately above the via portion 138b, a second portion 138a2 extending from the first portion 138a1, and a third portion directly below the conductive via 142 ( 138a3). The first and third portions 138a1 and 138a3 are pad portions coupled to the upper and lower vias 138 and 142, the second portion 138a2 has a curved or bypass pattern, and Connect the three parts 138a1 and 138a3. The bypass pattern of second portion 138a2 helps the conductive features of metallization pattern 138 safely release stress in the redistribution structure and/or package structure.

In some embodiments, pad portions 138a1 and 138a3 are wider than curved portion 138a2 in plan view. This allows the pad portions 138a1 and 138a3 to better connect to the upper and lower vias, and improves the reliability of the redistribution structure.

As illustrated in FIG. 9A , line A extends through the center of conductive via 142 and through the center of portion 138B of a single conductive feature of metallization pattern 138, wherein portion 138B is made of metal. Electrically coupled to conductive via 142 by portion 138a of the same conductive feature of flower pattern 138 . Line B extends from the center of the same conductive via 142 and along the center of the first line segment of portion 138a2 of the same conductive feature of the metallization pattern extending from the conductive via 142 . Line C is a first line segment of portion 138a2 of same conductive feature of metallization pattern 138 extending from via portion 138b, from the center of same portion 138a of same conductive feature of metallization pattern 138. extends along the center of

In some embodiments, lines A, B, and C are parallel to a major surface of dielectric layer 140 . Angle θ1 is made between line A and line B. In some embodiments, angle θ1 ranges from 30° to 150°. In some embodiments, angle θ1 ranges from 30° to 90°. In some embodiments, angle θ1 ranges from 40° to 50°. Angle θ2 is made between line A and line C. In some embodiments, angle θ2 ranges from 30° to 150°. In some embodiments, angle θ2 ranges from 30° to 90°. In some embodiments, angle θ2 ranges from 40° to 50°. In some embodiments, angles θ1 and θ2 are equal. In some other embodiments, the angles θ1 and θ2 are different. In some embodiments, conductive line portions 138a2 of metallization pattern 138 are curved and do not include any sharp corners or abrupt changes in direction. For example, in top view, conductive line portions 138a2 utilize arcs to slowly change directions, but do not have corners with sharp changes in directions, such as 90° corners. In some embodiments, the disclosed stress relieving metallization patterns 138 and dielectric layer 140 reduce stress on underlying metallization patterns (eg, metallization pattern 134) in the range of 15% to 35%; For example, it can be reduced by 30%.

9B illustrates a detailed view of the “U”-shaped conductive features of metallization pattern 138 from FIG. 8 . The main components (eg, portions 138a1 , 138a2 , 138a3 , θ1 , and θ2 ) of the “U”-shaped conductive feature have been previously described in FIG. 9A , and the description is not repeated here.

In some embodiments, each of the conductive features of the metallization pattern 138 on the first package component 100 have the same shape, each of their lines (A) are parallel, and their lines (B) Each is parallel, and each of its lines (C) is oriented in the same direction so that each is parallel (eg, see the metallization patterns in FIG. 8 ). In some embodiments, the conductive features of metallization pattern 138 have different shapes, their lines (A) are not parallel, their lines (B) are not parallel, and/or their The lines C are oriented differently so that they are not parallel. In some embodiments, the conductive features of metallization pattern 138 are all “C”-shaped, all “U”-shaped, or a mixture of “C”-shaped and “U”-shaped shapes. .

Although angles θ1 and θ2 have been described using lines A, B, and C, lines A, B, and C may be replaced by planes A, B, and C; , where planes A, B, and C are perpendicular to the major surface of dielectric layer 140 .

In FIG. 10 , under-bump metallurgy (UBM) 144 are formed for external connection to conductive vias 142 . UMBs 144 may be referred to as pads 144 . The UBMs 144 are on a major surface of the dielectric layer 140 and have bump portions extending along the major surface of the dielectric layer 140 and physically and electrically coupling the conductive vias 142 . UBMs 144 may be formed of the same material as conductive vias 142 . In some embodiments, UBMs 144 have a different size than metallization patterns 126 , 130 , 134 , and 138 .

As an example, UBMs 144 may be formed by first forming a seed layer over dielectric layer 140 and conductive vias 142 . In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer comprising a plurality of sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, PVD or the like. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like, and may be exposed to light for patterning. The pattern of photoresist corresponds to UBMs 144 . Patterning forms openings through the photoresist to expose the seed layer. A conductive material is then formed over the openings in the photoresist and the exposed portions of the seed layer. The conductive material may be formed by plating such as electroplating or electroless plating. Conductive materials may include metals such as copper, titanium, tungsten, aluminum, and the like. In some embodiments, UBMs 144 may include alloys such as electroless nickel, electroless palladium, immersion gold (ENEPIG), electroless nickel, immersion gold (ENIG), and the like. The combination of the conductive material and the lower portions of the seed layer form UBMs 144 . Portions of the seed layer that do not have photoresist and conductive material formed thereon are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as by using an oxygen plasma or the like. Once the photoresist is removed, exposed portions of the seed layer are removed using an acceptable etching process, such as by wet or dry etching.

In FIG. 11 , conductive connectors 146 are formed on UBMs 144 . Conductive connectors 146 may include ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG ) forming bumps and the like. Conductive connectors 146 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or combinations thereof. In some embodiments, conductive connectors 146 are formed by initially forming a solder layer via evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once the solder layer has been formed on the structure, a reflow may be performed to mold the material into the desired bump shapes. In another embodiment, the conductive connectors 146 include metal pillars (eg, copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars may be solder free and may have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillars. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or combinations thereof, and may be formed by a plating process.

In FIG. 12 , integrated circuit dies 50 (eg, first integrated circuit dies 50A and second integrated circuit dies 50B) are attached to the structure of FIG. 11 . A desired type and amount of integrated circuit dies 50 are adhered to each of the package regions 100A and 100B. Integrated circuit dies 50 may be referred to as package modules 50 . In the illustrated embodiment, multiple integrated circuit dies, including first integrated circuit die 50A and second integrated circuit die 50B in first package section 100A and second package section 100B, respectively. Fields 50 are glued adjacent to each other. The first integrated circuit die 50A may be a logic device, such as a central processing unit (CPU), a graphics processing unit (GPU), a system-on-chip (SoC), a microcontroller, or the like. The second integrated circuit die 50B may be a memory device, such as a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a hybrid memory cube (HMC) module, a high bandwidth memory (HBM), or the like. In some embodiments, integrated circuit dies 50A and 50B may be the same type of dies, such as SoC dies. The first integrated circuit die 50A and the second integrated circuit die 50B may be formed with processes of the same technology node, or may be formed with processes of different technology nodes. For example, first integrated circuit die 50A may be made of a more advanced process node than second integrated circuit die 50B. Integrated circuit dies 50A and 50B may have different sizes (eg, different heights and/or surface areas) or may have the same size (eg, same heights and/or surface areas).

Integrated circuit dies 50 are attached to conductive connectors 146 . That is, die connectors 66 of integrated circuit dies 50A and 50B are connected to conductive connectors 146 on opposite sides of UBMs 144 .

In some embodiments, conductive connectors 146 are reflowed to attach integrated circuit dies 50 to UBMs 144 . Conductive connectors 146 electrically and/or physically couple redistribution structure 120 , including metallization patterns in redistribution structure 120 , to integrated circuit dies 50 . In some embodiments, a solder resist (not shown) is formed on the redistribution structure 120 . Conductive connectors 146 may be disposed in openings in the solder resist to electrically and mechanically couple to UBMs 144 . A solder resist may be used to protect regions of the redistribution structure 120 from external damage.

Conductive connectors 146 may have epoxy flux (not shown) before they are reflowed, and at least some of the epoxy portion of the epoxy flux after integrated circuit dies 50 are attached to redistribution structure 120. is maintained This residual piece of epoxy may act as an underfill to reduce stress and protect the joints resulting from reflowing the conductive connectors 146 .

In FIG. 13 , underfill 150 is applied to dielectric layer 140 and regions 100A and 100B, including between and around UBMs 144 , conductive connectors 146 , and die connectors 66 . It is formed between integrated circuit dies 50A and 50B in each. The underfill 150 may be formed by a capillary flow process after the integrated circuit dies 50 are attached, or may be formed by a suitable deposition method before the integrated circuit dies 50 are attached. Although not shown in FIG. 13 and subsequent figures, in some embodiments, underfill 150 is also between integrated circuit dies 50 in adjacent regions 100A and 100B.

In FIG. 14 , encapsulant 152 is formed around integrated circuit dies 50 , conductive connectors 146 , and underfill 150 . After formation, encapsulant 152 encapsulates conductive connectors 146 and integrated circuit dies 50 . The encapsulant 152 may be a molding compound, epoxy, or the like. The encapsulant 152 may be applied by compression molding, transfer molding, or the like. The encapsulant 152 may be applied in liquid or semi-liquid form and then cured. In some embodiments, a planarization step may be performed to remove and planarize the upper surface of the encapsulant 152 . In some embodiments, the surfaces of underfill 150 , encapsulant 152 , and integrated circuit dies 50 are coplanar (within a process variation).

In FIG. 15 , carrier substrate de-bonding is performed to separate (or “de-bond”) carrier substrate 102 from redistribution structure 120 , such as dielectric layer 124 . According to some embodiments, de-bonding includes projecting light, such as laser light or UV light, onto the release layer 104 such that the release layer 104 is decomposed under the heat of the light and the carrier substrate (102) can be eliminated. The structure is then inverted and placed on a tape (not shown).

In FIG. 16 , UBMs 160 are formed for external connection to the redistribution structure 120 , for example the metallization pattern 126 . UBMs 130 are on a major surface of dielectric layer 124 and have bump portions extending along a major surface of dielectric layer 124 . UBMs 160 may be formed of the same material as metallization pattern 126 .

In FIG. 17 , conductive connectors 162 are formed on UBMs 160 . Conductive connectors 162 may include ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG ) forming bumps and the like. Conductive connectors 162 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or combinations thereof. In some embodiments, conductive connectors 162 are formed by initially forming a layer of solder via evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the structure, reflow may be performed to mold the material into the desired bump shapes. In another embodiment, the conductive connectors 162 include metal pillars (eg, copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars may be solder free and may have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillars. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or combinations thereof, and may be formed by a plating process.

As illustrated in FIG. 18 , the singulation process is performed by sawing along the scribe line regions, eg, between the first package region 100A and the second package region 100B. Sawing singulates the first package area 100A from the second package area 100B. The resulting singulated device stack is produced from either the first package section 100A or the second package section 100B. Subsequently, each of the singulated structures is turned over and mounted on the package substrate 200 (see FIG. 19).

In FIG. 19 , the first package component 100 may be mounted to the package substrate 200 using conductive connectors 162 . The package substrate 200 includes a substrate core 202 and bond pads 204 over the substrate core 202 . Substrate core 202 may be made of a semiconductor material, such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations thereof, and the like may also be used. Additionally, the substrate core 202 may be a semiconductor-on-insulator (SOI) substrate. Generally, an SOI substrate includes a layer of semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. In one alternative embodiment, the substrate core 202 is based on an insulative core such as a glass fiber reinforced resin core. One exemplary core material is a fiberglass resin such as FR4. Alternatives to the core material include bismaleimide-triazine (BT), or alternatively, other PCB materials or films. Build up films, such as ABF or other laminates, may be used for the substrate core 202 .

Substrate core 202 may include active and passive devices (not shown). A variety of devices, such as transistors, capacitors, resistors, combinations thereof, and the like, may be used to create the structural and functional requirements of the design for the device stack. Devices may be formed using any suitable methods.

The substrate core 202 may also include metallization layers and vias (not shown), to which bond pads 204 are physically and/or electrically coupled. Metallization layers can be formed over active and passive devices and are designed to connect the various devices to form functional circuitry. The metallization layers may be formed from alternating layers of dielectric material (eg, low-k dielectric material) and conductive material (eg, copper) (vias interconnecting layers of conductive material), by any suitable process (such as , tabernacle, damascene, dual damascene, etc.). In some embodiments, substrate core 202 is substantially free of active and passive devices.

In some embodiments, conductive connectors 162 are reflowed to attach first package component 100 to bond pads 204 . The conductive connectors 162 electrically and/or physically couple the package substrate 200 , including the metallization layers in the substrate core 202 , to the first package component 100 . In some embodiments, solder resist 206 is formed on substrate core 202 . Conductive connectors 162 may be disposed in openings in solder resist 206 to electrically and mechanically couple to bond pads 204 . Solder resist 206 may be used to protect regions of substrate 202 from external damage.

The conductive connectors 162 may have epoxy flux (not shown) formed thereon before they are reflowed, and after the first package component 100 is attached to the package substrate 200, the epoxy portion of the epoxy flux At least some are retained. This residual epoxy portion may act as an underfill to reduce stress and protect joints from reflowing conductive connectors 162 . In some embodiments, an underfill 208 may be formed between the first package component 100 and the package substrate 200 and around the conductive connectors 162 . The underfill 208 may be formed by a capillary flow process after the second package component 200 is attached, or may be formed by a suitable deposition method before the second package component 200 is attached.

Other features and processes may also be included. For example, test structures may be included to aid in 3D packaging or verification testing of 3DIC devices. The test structure may include, for example, test pads formed on a redistribution layer or on a substrate, which enables testing of 3D packaging or 3DIC, use of probes and/or probe cards, and the like. Verification tests may be performed on the final structure as well as intermediate structures. Additionally, the structures and methods disclosed herein can be used in conjunction with test methods that include interim verification of known good dies to increase yield and reduce costs.

Embodiments may obtain advantages. Redistribution structures including metallization patterns and methods of forming the same are provided, according to some embodiments. In particular, redistribution structures include metallization patterns with shapes that provide more flexibility to the metallization pattern to handle warping and other deformations without breaking. For example, the metallization patterns may have a curved, “C”-shaped, or “U”-shaped shape. Metallization patterns in redistribution structures may warp or deform due to coefficient of thermal expansion (CTE) mismatches of materials in a semiconductor package. This CTE mismatch allows the metallization patterns to withstand high stresses due to bending and deformation. However, the disclosed shapes of metallization patterns with increased flexibility increase the reliability of the redistribution structure. These flexible-shaped metallization patterns are surrounded by conforming dielectric layers such as polymer layers. The combination of flexible-shaped metallization patterns and surrounding conformal dielectric layers provides a buffer to release stress in the redistribution structure and package structure.

One embodiment includes a first integrated circuit die. The package structure also includes a redistribution structure bonded to the first integrated circuit die, and the redistribution structure includes a first dielectric layer. The structure also includes a first metallization pattern in the first dielectric layer, the first metallization pattern includes a plurality of first conductive features, each of the first conductive features comprising a first conductive via and a first conductive line. wherein the first conductive via is in the first dielectric layer, the first conductive line is over the first dielectric layer and electrically coupled to each first conductive via, each of the first conductive lines is curved in plan view. includes The structure also includes a first dielectric layer and a second dielectric layer over the first metallization pattern. The structure also includes a second metallization pattern in the second dielectric layer, the second metallization pattern including a plurality of second conductive features, each of the second conductive features comprising a second conductive via in the second dielectric layer. wherein each of the second conductive vias is over and electrically coupled to each first conductive line.

Embodiments may include one or more of the following features. A package structure wherein the second metallization pattern is closer to the first integrated circuit die than the first metallization pattern. The package structure further includes a package substrate bonded to the first side of the redistribution structure, the first integrated circuit die bonded to the second side of the redistribution structure, the first metallization pattern being higher than the second metallization pattern. Closer to the first side of the line structure. The package substrate is bonded to the first side of the redistribution structure by a first set of conductive connectors and the first integrated circuit die is bonded to the second side of the redistribution structure by a second set of conductive connectors. The package structure includes an underfill between the first integrated circuit die and the second side of the redistribution structure, the underfill surrounding the second set of conductive connectors, and the underfill and the sidewalls of the first integrated circuit die and the second side of the redistribution structure. A cotton encapsulant is further included. A first angle is formed between the first plane and the second plane, the first plane and the second plane intersect a first one of the plurality of first conductive features, the first plane and the second plane are of the second dielectric layer. a second conductive via perpendicular to the major surface, the first plane being over and coupled to the first one of the plurality of first conductive features, from the center of the first conductive vias of the first one of the plurality of first conductive features; extends to the center of the first plurality of conductive features, the second plane extending from the center of the second conductive via over and coupled to the first one of the plurality of first conductive features, the first conductive line of the first one of the plurality of first conductive features extends along a first portion of the first angle, and the first angle is between 30° and 150°. Each of the first conductive lines of the plurality of first conductive features has no corners in plan view. Each of the first conductive lines includes copper, and the second dielectric layer includes a polymer. The second dielectric layer includes polybenzoxazole (PBO), polyimide, or benzocyclobutene (BCB).

An embodiment includes a first package component including a first module and a second module, the first module including a logic chip and the second module including a memory chip. The package structure also includes a first redistribution structure, the first redistribution structure including metallization patterns in the dielectric layers, a first side of the first redistribution structure to the first module and the second module to provide physical and electrical electrical properties. , wherein a first one of the metallization patterns is in a first one of the dielectric layers, the first metallization pattern includes first conductive features, each of the first conductive features having a first conductive a via and a first conductive line, the first conductive via is in the first dielectric layer, the first conductive line is over the first dielectric layer and electrically coupled to each first conductive via, the first conductive line Each of the s is curved in plan view and has no corners. The structure also includes a second package component, the second package component including a package substrate bonded to a second side of the first redistribution structure, the second side being opposite the first side.

Embodiments may include one or more of the following features. The first redistribution structure further includes a second dielectric layer over the first dielectric layer and the first metallization pattern, and a second metallization pattern in the second dielectric layer, the second metallization pattern defining the second conductive features. wherein each of the second conductive features includes a second conductive via in the second dielectric layer, each of the second conductive vias is over a respective first conductive line and electrically coupled to the respective first conductive line. package structure. The first conductive line directly connects the first conductive via to the second conductive via. The second metallization pattern is closer to the first module and the second module than the first metallization pattern. Each of the first conductive lines includes copper, and the second dielectric layer includes a polymer. The first package component includes an underfill between the first module, the second module, and the first face of the first redistribution structure, the underfill extending along the first sidewalls of the first module and the second module, and the first sidewalls of the second module face each other; and the second sidewalls of the first module and the second module, and an encapsulant on the first side of the first redistribution structure, The second side walls of the 2 modules do not face each other. The top surfaces of the first module, the second module, the underfill, and the encapsulant are coplanar.

One embodiment includes forming a first dielectric layer over a substrate. The method also includes patterning the first dielectric layer. The method also includes forming a first metallization pattern in the patterned first dielectric layer and along an upper surface of the patterned first dielectric layer, the first metallization pattern including first conductive features; Each of the first conductive features includes a first conductive via and a first conductive line, the first conductive via is in a first dielectric layer, the first conductive line is along a top surface of the first dielectric layer and each first conductive via is in a first dielectric layer. Electrically coupled to the conductive via, each of the first conductive lines is curved in plan view and has no corners. The method also includes forming a second dielectric layer over the patterned first dielectric layer and the first metallization pattern. The method also includes patterning the second dielectric layer. The method also includes forming a second metallization pattern in the patterned second dielectric layer, the second metallization pattern including second conductive vias in the second dielectric layer, each of the second conductive vias comprising: Electrically coupled to each first conductive line of the first conductive features.

Embodiments may include one or more of the following features. The method includes forming bond pads over a second dielectric layer and a second metallization pattern, the bond pads coupled to second conductive vias, bonding a first module and a second module to the bond pads; The first module includes a logic chip and the second module includes a memory chip - encapsulating the first module and the second module in an encapsulant, removing the substrate, and encapsulating the encapsulant, first metallization. Further comprising singulating the pattern and the second metallization pattern and the first dielectric layer and the second dielectric layer. The method further includes, after the singulating step, bonding the singulated structure to a package substrate comprising: a first metallization pattern and a second metallization pattern and a first dielectric layer and a second dielectric layer; , on the side opposite to the side with the first module and the second module. Each of the first conductive lines includes copper, and the second dielectric layer includes a polymer.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. . Those skilled in the art should also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. do.

Examples

Example 1. In the package structure,

a first integrated circuit die; and

A redistribution structure bonded to the first integrated circuit die

Including,

The redistribution structure is:

a first dielectric layer;

A first metallization pattern in the first dielectric layer, the first metallization pattern comprising a plurality of first conductive features, each of the first conductive features comprising a first conductive via and a first conductive line; wherein the first conductive via is in the first dielectric layer, the first conductive line is over the first dielectric layer and electrically coupled to each first conductive via, each of the first conductive lines contains curves in plan view;

a second dielectric layer over the first dielectric layer and the first metallization pattern; and

a second metallization pattern in the second dielectric layer, the second metallization pattern comprising a plurality of second conductive features, each of the second conductive features comprising a second conductive via in the second dielectric layer; , each of the second conductive vias is over and electrically coupled to a respective first conductive line -

To include, the package structure.

Example 2. In Example 1,

wherein the second metallization pattern is closer to the first integrated circuit die than the first metallization pattern.

Example 3. In Example 1,

Further comprising a package substrate bonded to the first surface of the redistribution structure,

wherein the first integrated circuit die is bonded to the second side of the redistribution structure, and wherein the first metallization pattern is closer to the first side of the redistribution structure than the second metallization pattern. .

Example 4. In Example 3,

The package substrate is bonded to the first side of the redistribution structure by a first set of conductive connectors, and the first integrated circuit die is bonded to the second side of the redistribution structure by a second set of conductive connectors. A package structure that is bonded.

Example 5. In Example 4,

an underfill between the first integrated circuit die and the second side of the redistribution structure, the underfill surrounding the second set of conductive connectors; and

an encapsulant on the underfill and sidewalls of the first integrated circuit die, and the second side of the redistribution structure;

Further comprising a package structure.

Example 6. In Example 1,

A first angle is formed between the first plane and the second plane, the first plane and the second plane intersect a first one of the plurality of first conductive features, the first plane and the second plane are perpendicular to a major surface of the second dielectric layer, wherein the first plane is above the first one of the plurality of first conductive features and from a center of the first conductive vias of the first one of the plurality of first conductive features; extending to a center of the second conductive via coupled to the first one, the second plane extending from the center of the second conductive via coupled to the first one over and coupled to the first one of the plurality of first conductive features; , wherein the first angle extends along a first portion of a first conductive line of a first one of the plurality of first conductive features, wherein the first angle is between 30° and 150°.

Example 7. In Example 1,

wherein each of the first conductive lines of the plurality of first conductive features is free of corners in the plan view.

Example 8. In Example 1,

wherein each of the first conductive lines comprises copper and the second dielectric layer comprises a polymer.

Example 9. In Example 8,

The second dielectric layer is a package structure comprising polybenzoxazole (PBO, polybenzoxazole), polyimide, or benzocyclobutene (BCB, benzocyclobutene).

Example 10. In the package structure,

a first package component; and

Second Package Component

Including,

The first package component is:

a first module and a second module, wherein the first module includes a logic chip and the second module includes a memory chip; and

A first redistribution structure comprising metallization patterns in dielectric layers, a first side of the first redistribution structure physically and electrically coupled to the first module and the second module, wherein one of the metallization patterns A first metallization pattern is in a first one of the dielectric layers, the first metallization pattern includes first conductive features, each of the first conductive features defining a first conductive via and a first conductive line. wherein the first conductive via is in the first dielectric layer, the first conductive line is over the first dielectric layer and electrically coupled to each first conductive via, each of the first conductive lines is curved in plan view and has no corners —

including,

The second package component is:

A package substrate bonded to the second surface of the first redistribution structure.

wherein the second side is opposite to the first side, the package structure.

Example 11. According to Example 10,

The first redistribution structure is:

a second dielectric layer over the first dielectric layer and the first metallization pattern; and

a second metallization pattern in the second dielectric layer, the second metallization pattern including second conductive features, each of the second conductive features including a second conductive via in the second dielectric layer; each of the second conductive vias is over and electrically coupled to a respective first conductive line;

To include, the package structure.

Example 12. According to Example 11,

Wherein the first conductive line directly connects the first conductive via to the second conductive via.

Example 13. According to Example 11,

wherein the second metallization pattern is closer to the first module and the second module than the first metallization pattern.

Example 14. According to Example 11,

wherein each of the first conductive lines comprises copper and the second dielectric layer comprises a polymer.

Example 15. According to Example 10,

The first package component is:

an underfill between the first module, the second module, and a first surface of the first redistribution structure, wherein the underfill extends along first sidewalls of the first module and the second module; and the first sidewalls of the second module face each other; and

second sidewalls of the first module and the second module, and an encapsulant on the first side of the first redistribution structure, wherein the second sidewalls of the first module and the second module do not face each other;

To further include, the package structure.

Example 16. According to Example 15,

The package structure, wherein the top surfaces of the first module, the second module, the underfill, and the encapsulant are coplanar.

Example 17. In the method,

forming a first dielectric layer over the substrate;

patterning the first dielectric layer;

forming a first metallization pattern in the patterned first dielectric layer and along an upper surface of the patterned first dielectric layer, the first metallization pattern including first conductive features, the first conductive features each of which includes a first conductive via and a first conductive line, the first conductive via is in the first dielectric layer, the first conductive line is along an upper surface of the first dielectric layer and each first conductive via is in the first dielectric layer; electrically coupled to a conductive via, wherein each of the first conductive lines is curved in plan view and has no corners;

forming a second dielectric layer over the patterned first dielectric layer and the first metallization pattern;

patterning the second dielectric layer; and

forming a second metallization pattern in the patterned second dielectric layer, the second metallization pattern comprising second conductive vias in the second dielectric layer, each of the second conductive vias comprising the first conductive vias; electrically coupled to each first conductive line of the features—

Including, method.

Example 18. According to Example 17,

forming bond pads over the second dielectric layer and the second metallization pattern, the bond pads coupled to the second conductive vias;

bonding a first module and a second module to the bond pads, the first module including a logic chip and the second module including a memory chip;

encapsulating the first module and the second module in an encapsulant;

removing the substrate; and

Singulating the encapsulant, the first metallization pattern and the second metallization pattern, and the first dielectric layer and the second dielectric layer.

Further comprising a method.

Example 19. According to Example 18,

After the singulating step, further comprising bonding the singulated structure to a package substrate;

wherein the package substrate is on a side of the first metallization pattern and the second metallization pattern and the first dielectric layer and the second dielectric layer opposite to the side where the first module and the second module are located. in, how.

Example 20. As in Example 17,

wherein each of the first conductive lines comprises copper and the second dielectric layer comprises a polymer.

Claims (10)

In the package structure,
a first integrated circuit die; and
A redistribution structure bonded to the first integrated circuit die
Including,
The redistribution structure is:
a first dielectric layer;
A first metallization pattern in the first dielectric layer, the first metallization pattern comprising a plurality of first conductive features, each of the first conductive features comprising a first conductive via and a first conductive line; wherein the first conductive via is in the first dielectric layer, the first conductive line is over the first dielectric layer and is electrically coupled to each first conductive via, each of the first conductive lines contains curves in plan view;
a second dielectric layer over the first dielectric layer and the first metallization pattern; and
a second metallization pattern in the second dielectric layer, the second metallization pattern comprising a plurality of second conductive features, each of the second conductive features comprising a second conductive via in the second dielectric layer; , each of the second conductive vias is over and electrically coupled to a respective first conductive line -
To include, the package structure. According to claim 1,
wherein the second metallization pattern is closer to the first integrated circuit die than the first metallization pattern. According to claim 1,
Further comprising a package substrate bonded to the first surface of the redistribution structure,
wherein the first integrated circuit die is bonded to the second side of the redistribution structure, and wherein the first metallization pattern is closer to the first side of the redistribution structure than the second metallization pattern. . According to claim 3,
The package substrate is bonded to the first side of the redistribution structure by a first set of conductive connectors, and the first integrated circuit die is bonded to the second side of the redistribution structure by a second set of conductive connectors. A package structure that is bonded. According to claim 4,
an underfill between the first integrated circuit die and the second side of the redistribution structure, the underfill surrounding the second set of conductive connectors; and
an encapsulant on the underfill and sidewalls of the first integrated circuit die, and the second side of the redistribution structure;
Further comprising a package structure. According to claim 1,
A first angle is formed between the first plane and the second plane, the first plane and the second plane intersect a first one of the plurality of first conductive features, the first plane and the second plane are perpendicular to a major surface of the second dielectric layer, wherein the first plane is above the first one of the plurality of first conductive features and from a center of the first conductive vias of the first one of the plurality of first conductive features; extending to a center of the second conductive via coupled to the first one, the second plane extending from the center of the second conductive via coupled to the first one over and coupled to the first one of the plurality of first conductive features; , wherein the first angle extends along a first portion of a first conductive line of a first one of the plurality of first conductive features, wherein the first angle is between 30° and 150°. According to claim 1,
wherein each of the first conductive lines of the plurality of first conductive features is free of corners in the plan view. According to claim 1,
wherein each of the first conductive lines comprises copper and the second dielectric layer comprises a polymer. In the package structure,
a first package component; and
Second Package Component
Including,
The first package component is:
a first module and a second module, wherein the first module includes a logic chip and the second module includes a memory chip; and
A first redistribution structure comprising metallization patterns in dielectric layers, a first side of the first redistribution structure being physically and electrically coupled to the first module and the second module, wherein one of the metallization patterns A first metallization pattern is in a first one of the dielectric layers, the first metallization pattern includes first conductive features, each of the first conductive features defining a first conductive via and a first conductive line. wherein the first conductive via is in the first dielectric layer, the first conductive line is over the first dielectric layer and is electrically coupled to each first conductive via, each of the first conductive lines is curved in plan view and has no corners —
including,
The second package component is:
A package substrate bonded to the second surface of the first redistribution structure.
wherein the second side is opposite to the first side, the package structure. in the method,
forming a first dielectric layer over the substrate;
patterning the first dielectric layer;
forming a first metallization pattern in the patterned first dielectric layer and along an upper surface of the patterned first dielectric layer, the first metallization pattern including first conductive features, the first conductive features each of which includes a first conductive via and a first conductive line, the first conductive via is in the first dielectric layer, the first conductive line is along an upper surface of the first dielectric layer and each first conductive via is in the first dielectric layer; electrically coupled to a conductive via, wherein each of the first conductive lines is curved in plan view and has no corners;
forming a second dielectric layer over the patterned first dielectric layer and the first metallization pattern;
patterning the second dielectric layer; and
forming a second metallization pattern in the patterned second dielectric layer, the second metallization pattern comprising second conductive vias in the second dielectric layer, each of the second conductive vias comprising the first conductive vias; electrically coupled to each first conductive line of the features—
Including, method.

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