KR20160018145A - Switching device and driving method thereof - Google Patents

Abstract

Provides are a switching device and a driving method thereof. The switching device includes a switch which controls a current flowing along an inductive element, a monitoring node connected to the switch, and a signal control circuit which is connected to the monitoring node and a reference voltage and turns on/off the switch. The signal control circuit includes an integrator which generates a comparison voltage by using the reference voltage and the monitoring voltage of the monitoring node, a comparator which compares the comparison voltage and the reference voltage and generates a reset signal, and an offset elimination part which prevents a first offset voltage by the integrator and a second offset voltage by the comparator from affecting the comparison voltage.

Description

[0001] Switching device and driving method [0002]

The present invention relates to a switching device and a driving method thereof.

Conventional current programmed control mainly uses the peak current of the switching transistor. While this peak current control scheme has fast transient response and stability, the switching ripple current in the inductor can degrade the accuracy of the current control loop. Therefore, in order to sense the correct average current, the peak current control is limited and all of the current flowing through the inductor must be sensed.

US 8,659, 278 (registered April 2014)

SUMMARY OF THE INVENTION It is an object of the present invention to provide a switching device for eliminating an offset voltage generated in a switching device to increase the accuracy of current program control.

Another object of the present invention is to provide a method of driving a switching device for eliminating an offset voltage generated in a switching device to increase the accuracy of current program control.

The problems to be solved by the present invention are not limited to the above-mentioned problems, and other matters not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a switching device including a switch for controlling current flowing in an inductive element, a monitoring node connected to the switch, Wherein the signal control circuit includes an integrator for generating a comparison voltage by using the monitoring voltage of the monitoring node and the reference voltage, A comparator for comparing the reference voltage to generate a reset signal and an offset canceling circuit for preventing a first offset voltage by the integrator and a second offset voltage by the comparator from affecting the reset signal.

Wherein the offset elimination is located between the integrator and the comparator, wherein the offset elimination is provided with a sum of the comparison voltage and the first offset voltage, and wherein the offset elimination is performed by comparing the reference voltage, The sum of the first offset voltage and the second offset voltage may be provided to the comparator by using the sum of the first offset voltage and the second offset voltage.

The offset canceling may be connected to one end of the comparator to which the comparison voltage is applied and the other end of the comparator.

The offset canceling means includes a first capacitor connected to one end of the comparator and the other end of the comparator by first and second switches and a second capacitor connected in parallel with the first capacitor by third and fourth switches, And a buffer connected between one end of the second capacitor and the other end of the comparing unit, and the reference voltage may be applied to the other end of the second capacitor.

The second capacitor may charge a sum of the first offset voltage, the negative voltage of the second offset voltage, and the negative voltage of the third offset voltage of the buffer.

The first and second switches may be turned on / off together, and the third and fourth switches may be turned on / off.

And a fifth switch connected in parallel with the capacitor of the integrator.

The turn-on of the fifth switch partially overlaps the turn-on of the first and second switches, and the third and fourth switches may be turned on within a time at which the reset signal is generated.

According to an aspect of the present invention, there is provided a method of driving a switching device including a switch for controlling current flowing in an inductive element, a monitoring node connected to the switch, A signal control circuit coupled to a reference voltage and configured to turn on / off the switch, wherein the signal control circuit generates a comparison voltage using the monitoring voltage of the monitoring node and the reference voltage, A comparator for comparing the comparison voltage with the reference voltage to generate a reset signal; and a comparator for comparing the first offset voltage of the integrator and the second offset voltage of the comparator And an offset cancellation for preventing an influence, said offset cancellation being applied to the first and second switches A second capacitor connected in parallel with the first capacitor by third and fourth switches, and a second capacitor connected between one end of the second capacitor and the other end of the comparison unit, And turns on the first and second switches to partially overlap the turn-on of the fifth switch to charge the first capacitor, and the first and second switches are turned on to partially overlap the turn-on of the fifth switch to charge the first capacitor, The fifth switch is turned off while the second switch is turned on, the first and second switches are turned off, and the third and fourth switches are turned on to charge the second capacitor.

Turning off the first and second switches may comprise turning off the first and second switches at the same time the reset signal is generated.

Turning on the third and fourth switches may include turning on the third and fourth switches only while the reset signal is being generated.

Turning on the third and fourth switches may include turning on the third and fourth switches to distribute a voltage charged to the first capacitor to each of the first and second capacitors.

Further comprising turning off the third and fourth switches after turning on the third and fourth switches, and applying a negative voltage between the first offset voltage and the second offset voltage to the second capacitor, , The first to fifth switches may be repeatedly turned on / off until the sum of the negative voltages of the third offset voltage of the buffer is charged.

According to another aspect of the present invention, there is provided a switching device including a switch for controlling a current flowing in an inductive element, a monitoring node connected to the switch, And a signal control circuit for turning on / off the switch, wherein the signal control circuit generates a first voltage based on the monitoring voltage of the monitoring node, and based on at least one of the sampling voltage and the reference voltage A comparator for turning off the switch when the first voltage and the second voltage become equal to each other; and an offset canceling circuit for removing an offset voltage generated in the comparator.

The offset canceling circuit includes a first capacitor connected to the other end of the comparator by one of the first and second switches and one end of the comparator, and a second capacitor connected in parallel with the first capacitor by third and fourth switches, A second capacitor coupled to one end of the comparator, and a buffer coupled to the other end of the second capacitor.

The offset canceling may further include a sixth switch connected in parallel with the second capacitor and initializing the second capacitor.

The first and second switches may be turned on / off together, and the third and fourth switches may be turned on / off.

The third and fourth switches can be turned on only while the switch is turned off.

The second capacitor may charge the sum of the negative voltage of the offset voltage of the comparator and the negative voltage of the offset voltage of the buffer.

Other specific details of the invention are included in the detailed description and drawings.

1 is a block diagram illustrating a switching device according to some embodiments of the present invention.
2 is an exemplary block diagram of the signal control circuit of FIG.
3 is a block diagram according to an exemplary embodiment of the reset signal generator of FIG.
4 is a circuit diagram of the reset signal generator of FIG.
5 is a timing diagram corresponding to the circuit diagram of Fig.
FIG. 6 is a flowchart for explaining a method of operating offset canceling.
7 is a timing chart for explaining an operation method of offset canceling.
Figs. 8 to 12 are circuit diagrams for explaining Fig. 6 at an intermediate stage.
13 is a block diagram according to another example of the reset signal generator of FIG.
14 is an example of a circuit diagram of the reset signal generator of Fig.
15 is an example of a circuit diagram of the offset canceling of Fig.
16 is a timing diagram corresponding to the circuit diagram of Fig.
Figs. 17 to 19 each show examples of the application circuit portion of Fig.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

One element is referred to as being "connected to " or " coupled to " another element, either directly connected to or coupled to another element, . On the other hand, when one element is referred to as "directly connected to" or "directly coupled to" another element, it does not intervene another element in the middle. Like reference numerals refer to like elements throughout the specification. "And / or" include each and every combination of one or more of the mentioned items.

Although the first, second, etc. are used to describe various elements, components and / or sections, it is needless to say that these elements, components and / or sections are not limited by these terms. These terms are only used to distinguish one element, element or section from another element, element or section. Therefore, it goes without saying that the first element, the first element or the first section mentioned below may be the second element, the second element or the second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

1 is a block diagram illustrating a switching device according to some embodiments of the present invention. FIG. 2 is an exemplary block diagram of the signal control circuit of FIG. 1, and FIG. 3 is a block diagram in accordance with an embodiment of the reset signal generator of FIG. 2. FIG.

Referring first to FIG. 1, a switching device 1 according to some embodiments of the present invention includes a switch 20, a signal control circuit 100 that turns on / off the switch 20, and the like. The switching device 1 may further include a monitoring element 30 electrically connected to the switch 20 and a monitoring node MN1 between the monitoring node 30 and the switch 20. [

The switching device (1) is electrically connected to the application circuit part (10). The switching device 1 can control the current flowing in the inductive element 15 located in the application circuit part 10. [ Here, the application circuit portion 10 can be any circuit capable of including the inductive element 15, for example, a buck converter, a light device, a power transformer, have. The application circuit portion 10 may include, for example, an output load 13 connected to the input power source 11, an inductive element 15 connected to the output load 13, and the like. The output load 13 may be, for example, a resistor or an LED. One terminal of the inductive element 15 may be connected to the output load 13 and the other terminal may be connected to the switch 20, but is not limited thereto.

One terminal of the catch diode 19 may be connected to the switch 20 and the other terminal may be connected between the input power source 11 and the output rod 13. The catch diode 19 is also referred to as a flyback diode, a freewheeling diode, a snubber diode, a suppressor diode, a clamp diode, and the like. That is, the catch diode 19 generates a continuous loop so that the current flowing in the inductive element 15 can be extinguished even when the switch 20 is turned off. That is, after the switch 20 is turned off, the current is consumed while continuing to flow through the catch diode 19, the output load 13, and the inductive element 15.

The monitoring node MNl may be located between the switch 20 and the monitoring element 30. [ The monitoring element 30 may be, but is not limited to, a resistor placed between the ground voltage and the switch 20.

The signal control circuit 100 is connected to the monitoring node MNl and the reference voltage REF to turn on and off the switch 20. [ 2, the signal control circuit 100 may include a reset signal generator 110 and an SR latch 120. [ The SR latch 120 receives the set signal S from the oscillator 40 and receives the reset signal RST from the reset signal generator 110.

The SR latch 120 periodically receives the set signal S in the form of a periodic pulse at a predetermined frequency from the oscillator 40 and turns on the switch 20 periodically.

Also, the reset signal generator 110 generates the reset signal RST using the monitoring voltage CS and the reference voltage REF. The SR latch 120 receives the reset signal RST and turns off the switch 20.

Here, the monitoring voltage CS means the voltage of the monitoring node MN1. The monitoring voltage CS may, but is not limited to, gradually change (e.g., increase) over time when the switch is turned on.

The reference voltage REF is greater than the level of the monitoring voltage CS when the switch 20 is turned on (hereinafter referred to as the "start level ") and the monitoring voltage CS when the switch 20 is turned off, (Hereinafter referred to as "final level"). For example, the reference voltage REF may be the average of the start level VL and the final level VH of the monitoring voltage CS (see FIG. 5).

The comparison voltage CVS refers to the voltage generated by the integrator 111 when the switch 20 is turned on. The comparison voltage CVS may be generated using the reference voltage REF and the monitoring voltage CS.

Specifically, when the switch 20 is turned on, the current supplied from the input power source 11 passes through the output load 13, the inductive element 15, and the monitoring element 30 to the ground voltage. The switch 20 is periodically turned on / off at a constant frequency to control the current flowing in the inductive element 15 such that the inductive voltage has a high or low value around the reference voltage. . In this way, the switch 20 regulates the average current flowing through the output load 13 and the inductive element 15. [

3, the reset signal generator 110 may include an integrator 111, a comparator 113, and an offset cancellation 115.

The integrator 111 may generate the comparison voltage CVS by receiving the monitoring voltage CS and the reference voltage REF.

The comparator 113 compares the comparison voltage CVS with the reference voltage REF to generate a reset signal RST. The comparator 113 generates the reset signal RST when the comparison voltage CVS and the reference voltage REF are the same.

The offset canceling unit 115 removes an offset voltage generated in the reset signal generator 110. Specifically, the integrator 111 and the comparator 113 include an active element, and an offset voltage can be generated by the active element. It is necessary to remove the offset voltage because it may cause an error in the switching device 1 which requires precise operation. Therefore, the offset cancellation 115 generates the first offset voltage (i.e., the first offset voltage by the integrator 111) (Vo1 in FIG. 4) generated in the integrator 111 and the second offset voltage The offset voltage (i.e., the second offset voltage by the comparator 113) (Vo2 in Fig. 4) can be eliminated. The reset signal RST generated in the comparator 113 is not affected by the first and second offset voltages Vo1 and Vo2 in FIG. 4, and the first and second offset voltages Vo1 and Vo2 in FIG. May not be included.

FIG. 4 is an example of a circuit diagram of the reset signal generator 110 of FIG. 5 is a timing diagram corresponding to the circuit diagram of Fig.

4, the integrator 111 integrates the monitoring voltage CS and the reference voltage REF when the switch 20 is turned on to generate the comparison voltage CVS. The integrator 111 includes a resistor R, a capacitor C, and a first amplifier OP1. One end of the first amplifier OP1 is provided with a reference voltage REF and the monitoring voltage CS is connected through the resistor R to the other end of the first amplifier OP1. Since the arrangement of the resistor R, the capacitor C, and the first amplifier OP1 is the same as that of the conventional integrator, detailed description thereof will be omitted.

On the other hand, the integrator 111 may include a fifth switch S1 arranged in parallel with the capacitor C. The operation of the fifth switch S1 will be described later.

The first offset voltage Vo1 may be generated by the first amplifier OP1 so that the first offset voltage Vo1 may be included in the comparison voltage CVS output from the integrator 111. [

The comparator 113 compares the comparison voltage CVS output from the output terminal of the first amplifier OP1 with the reference voltage REF and outputs a reset signal RST when the comparison voltage CVS and the reference voltage REF become equal to each other. ). The second offset voltage Vo2 can be generated by the comparator 113 and therefore the second offset voltage Vo2 can be included in the reset signal RST.

The offset canceling unit 115 may be connected to one end N1 of the comparator 113 to which the comparison voltage CVS is applied and the other end N2 of the comparator 113 to which the reference voltage REF is applied. The offset canceling unit 115 includes a first capacitor Co1, a second capacitor Co2, first and second switches S21 and S22, third and fourth switches S31 and S32, and a buffer OP2. .

The first switch S21 and the second switch S22 are connected to each other with the first capacitor Co1 therebetween. The first switch S21 is connected to the first end N1 of the comparing unit 113, S22) are connected to the other end (N2) of the comparing unit (113). The second capacitor Co2 is connected in parallel with the first capacitor Co1. And the third switch S31 and the fourth switch S32 are connected with the second capacitor Co2 in between. The buffer OP2 is disposed between one end of the second capacitor Co2 and the other end N2 of the comparator 113. [ A reference voltage REF may be applied to the other end of the second capacitor Co2.

The first and second switches S21 and S22 are also turned on / off. Accordingly, when the first switch S21 is turned on, the second switch S22 is also turned on, and when the first switch S21 is turned off, the second switch S22 is also turned off.

The third and fourth switches S31 and S32 are also turned on / off. Therefore, when the third switch S31 is turned on, the fourth switch S32 is also turned on, and when the third switch S31 is turned off, the fourth switch S32 is turned off.

Here, referring to FIGS. 1, 4 and 5, at time t1, a set signal S in the form of a pulse is generated. The switch 20 is turned on based on the set signal S. At time t1, the monitoring voltage CS has a start level VL. At time t2 when the monitoring switch 20 is turned off, the monitoring voltage CS increases to the final level VH. The monitoring voltage CS gradually increases from the start level VL to the final level VH.

The integrator 111 generates the comparison voltage CVS from the time t1. The comparison voltage CVS is generated by integrating the monitoring voltage CS and the reference voltage REF.

The comparison voltage CVS may have a value according to the following equation (1).

Since the comparison voltage CVS is generated by integrating the reference voltage REF and the monitoring voltage CS as shown in the equation (1), the comparison voltage CVS starts from the reference voltage REF. For example, the comparison voltage CVS gradually increases, and when the monitoring voltage CS becomes equal to the reference voltage REF, it has the peak voltage Vpeak and gradually decreases to the reference voltage REF at the time t2, (CVS).

The magnitude and waveform of the peak voltage Vpeak can be determined by the RC value of Equation (1), that is, the magnitude of the resistor R and the magnitude of the capacitor C.

The comparator 113 receives the reference voltage REF at one end and the comparison voltage CVS at the other end. And outputs the reset signal RST when the comparison voltage CVS becomes equal to the reference voltage REF. The reset signal RST is not influenced by the first offset voltage Vo1 and the second offset voltage Vo2 by the offset canceling unit 115. [

The operation method of the offset canceling unit 115 will be described with reference to FIGS. 6 to 12. FIG. 6 is a flow chart for explaining a method of operating the offset canceling unit 115. FIG. 7 is a timing chart for explaining an operation method of the offset canceling unit 115. In FIG. Figs. 8 to 11 are circuit diagrams for explaining Fig. 6 at an intermediate stage.

First, as shown in FIGS. 7 and 8, the fifth switch S1 is turned on (S10). In the first section (1) in which the fifth switch S1 is closed, the capacitor C of the integrator 111 is not charged. The comparison voltage CVS may be the sum of the reference voltage REF and the first offset voltage Vo1.

In Fig. 7, T means one cycle.

Next, as shown in FIGS. 7 and 9, the first and second switches S21 and S22 are turned on to partially overlap the turn-on of the fifth switch S1 (S20). In the second section (2), REF + Vo1 is applied to one end N1 of the comparator 113. Since the third and fourth switches S31 and S32 are turned off and the reference voltage REF is applied to the other end of the second capacitor Co2, REF + Vo3 is added to the other end N2 of the comparator 113 . The third offset voltage Vo3 of the buffer OP2 may be added to the reference voltage REF.

As a result, the voltage Vo1 - Vo3 between one end N1 and the other end N2 of the comparator 113 is charged to the first capacitor Co1.

Next, as shown in FIGS. 7 and 10, the fifth switch S1 is turned off and the first and second switches S21 and S22 are turned on (S30). In the third period (3), the fifth switch S1 is turned off, so that the integrator 111 operates normally and the comparison voltage CVS has the waveform shown in FIG. Therefore, the voltage applied to one end N1 of the comparator 113 is REF + Vo1 + alpha. Here,? Represents a change in the comparison voltage CVS in FIG.

The third and fourth switches S31 and S32 are turned off so that REF + Vo3 is still applied to the other end N2 of the comparator 113 in the third section (3) Vo1 - Vo3 + alpha, which is the difference between the one end N1 and the other end N2 of the capacitor 113, is charged.

7 and 11, the comparator 113 generates the reset signal RST and turns off the first and second switches S21 and S22 (S40). In the fourth period (4), when the reset signal RST is generated, the reference voltage REF and the comparison voltage CVS become equal (see Fig. 5). The magnitude of the comparison voltage CVS applied to one end N1 of the comparator 113 by the first offset voltage Vo1 of the integrator 111 is REF + Vo1.

Since the comparator 113 includes the second offset voltage Vo2, REF + Vo2 + Vo3 is applied to the other end N2 of the comparator 113.

At this time, since the first and second switches S21 and S22 are turned off, Vo1 - Vo2 - Vo3 is charged in the first capacitor Co1.

Next, referring to FIGS. 7 and 12, the third and fourth switches S31 and S32 are turned on (S50). The third and fourth switches S31 and S32 are turned on while the comparator 113 generates the reset signal RST and the comparator 113 stops generating the reset signal RST in the fifth section The third and fourth switches S31 and S32 are turned off before they are turned on.

The third and fourth switches S31 and S32 are turned on to charge the voltage charged in the first capacitor Co1 to the second capacitor Co2. Since the first capacitor Co1 and the second capacitor Co2 are connected in parallel when the first capacitor Co1 and the second capacitor Co2 are the same size and the third and fourth switches S31 and S32 are turned on, The voltage charged in each of the first and second capacitors Co1 and Co2 is (Vo1 - Vo2 - Vo3) / 2.

On the other hand, if the sizes of the first capacitor Co1 and the second capacitor Co2 are different from each other, Vo1-Vo2-Vo3 charged in the first capacitor Co1 is connected to the first capacitor Co1 and the second capacitor Co2 The values to be distributed may be different.

Then, the third and fourth switches S31 and S32 are turned off as shown in Fig. 7 (S60).

(Vo1 - Vo2 - Vo3) / 4 is applied to the second capacitor Co2 after one more period in the same manner as described above, and after one more cycle, 7 (Vo1 - Vo2 - Vo3) / 8 is applied to the second capacitor Co2, and 15 (Vo1 - Vo2 - Vo3) / 16 is applied to the second capacitor Co2 after one more period. In this way, Vo1 - Vo2 - Vo3 can be finally applied to the second capacitor Co2 after several cycles.

That is, Vo1 - Vo2 - Vo3 is charged in the second capacitor Co2 when the above process is repeated several times. That is, the second capacitor Co2 is charged with the sum of the first offset voltage Vo1, the negative voltage of the second offset voltage Vo2, and the negative voltage of the third offset voltage Vo3. When Vo1 - Vo2 - Vo3 is charged in the second capacitor Co2, the voltage applied to the other end N2 of the comparator 113 when the comparator 113 generates the reset signal RST may be REF + Vo1 . -Vo2 and -Vo3 are removed by the second offset voltage Vo3 of the comparator 113 and the third offset voltage Vo3 of the buffer OP2, respectively. At this time, since the voltage applied to one end N1 of the comparator 113 is REF + Vo1, voltages applied to one end N1 and the other end N2 of the comparator 113 become equal. The reset signal generator 110 can generate the reset signal RST without being influenced by the first offset voltage Vo1 of the integrator 111 and the second offset voltage 113 of the comparator 113. [

Another example of the reset signal generator 110 of the present invention will be described with reference to FIG. 1, FIG. 2, and FIG. 13 to FIG. 13 is a block diagram according to another example of the reset signal generator 110 of FIG. FIG. 14 is an example of a circuit diagram of the reset signal generator 110 of FIG. 15 is an example of a circuit diagram of the offset canceling unit 115 in FIG. 16 is a timing diagram corresponding to the circuit diagram of Fig.

1, 2, and 13, the reset signal generator 110 includes a first voltage V1 generated based on the monitoring voltage CS, at least one of a sampling voltage CSS and a reference voltage REF And generates the reset signal RST when the second voltage V2 generated based on one becomes equal to each other. The SR latch 120 receives the reset signal RST and turns off the switch 20.

13, the reset signal generator 110 may include a hold circuit 117, an arithmetic circuit 119, a comparator 113, and an offset canceling unit 115. [ The hold circuit 117 may be a sample and hold circuit or a track and hold circuit. For example, the hold circuit 117 may be provided with a monitoring voltage CS and a reference voltage REF, and may sample the monitoring voltage CS when the switch is turned on (see CSS reference in Figures 13-16) ). On the other hand, the difference between the monitoring voltage CS and the reference voltage REF when the switch is turned on may be sampled (see Va in FIGS. 14 and 16).

The operation circuit 119 generates the first voltage V1 and the second voltage V2 using the monitoring voltage CS, the sampling voltage CSS and the reference voltage REF. For example, the first voltage V1 is generated using a selected one of the monitoring voltage CS, the sampling voltage CSS and the reference voltage REF, and the monitoring voltage CS, the sampling voltage CSS, And the second voltage V2 may be generated using the rest of the voltage REF.

The comparator 113 generates the reset signal RST when the first voltage V1 and the second voltage V2 generated in this manner become equal to each other.

The offset canceling circuit 115 prevents the reset signal RST from being affected by the second offset voltage Vo2 of the comparator 113. [ The comparator 113 may comprise an active element and may generate an offset voltage.

Referring to Fig. 14, the hold circuit 117 of Fig. 13 samples the monitoring voltage CS when the switch 20 is turned on to generate the sampling voltage CSS.

The arithmetic operation circuit 119 includes first and second arithmetic operation units 131 and 132. The first calculator 131 subtracts the sampling voltage CSS from the reference voltage REF to generate the Va voltage (Va = REF-CSS). The second calculator 132 adds the Va voltage and the reference voltage REF to generate the second voltage V2. That is, the second voltage V2 may be REF + Va. On the other hand, the first voltage V1 is the monitoring voltage CS.

The comparator 113 generates the reset signal RST when the first voltage V1 and the second voltage V2 become equal to each other.

Here, referring to Figs. 1, 14 and 16, at time t1, a set signal S in the form of a pulse is generated. The switch 20 is turned on based on the set signal S. A sampling voltage CSS is generated, and REF + Va is generated. The second voltage V2 is REF + Va and the first voltage V1 is the monitoring voltage CS.

The monitoring voltage (CS) gradually increases from the start level to the final level.

At time t2, when the monitoring voltage CS becomes equal to REF + Va, a reset signal RST is generated. That is, when CS = REF + Va = REF + (REF-CSS) = 2REF-CSS, the switch 20 is turned off.

15, the offset canceling unit 115 includes a first capacitor Co1, a second capacitor Co2, first and second switches S21 and S22, third and fourth switches S31 and S32, A buffer OP2, and a sixth switch S4.

The first switch S21 and the second switch S22 are connected with the first capacitor Co1 interposed therebetween and the first switch S21 is connected to the other end N2 of the comparing unit 113 via the second switch S22) is connected to one end (N1) of the comparing unit (113).

The second capacitor Co2 is connected in parallel with the first capacitor Co1. And the third switch S31 and the fourth switch S32 are connected with the second capacitor Co2 in between. One end of the second capacitor Co2 is connected to one end N1 of the comparator 113 and the other end of the second capacitor Co2 is connected to the buffer OP2.

Meanwhile, the sixth switch S4 may be connected in parallel with the second capacitor Co2.

The buffer OP2 can generate the third offset voltage Vo3 and the buffer OP2 can receive the second voltage V2. The first voltage V1 may be applied to the other end N2 of the comparator 113. [

The comparator 113 may generate the second offset voltage Vo2.

The first and second switches S21 and S22 are also turned on / off. Accordingly, when the first switch S21 is turned on, the second switch S22 is also turned on, and when the first switch S21 is turned off, the second switch S22 is also turned off.

The third and fourth switches S31 and S32 are also turned on / off. Therefore, when the third switch S31 is turned on, the fourth switch S32 is also turned on, and when the third switch S31 is turned off, the fourth switch S32 is turned off.

A method of driving the offset canceling unit 115 will be described with reference to FIGS. 15 and 16. FIG.

First, the sixth switch S4 is turned on. So that the second capacitor Co2 can be initialized.

Subsequently, the first and second switches S21 and S22 are turned on while the first voltage V1, i.e., the monitoring voltage CS gradually increases from the start level to the final level. The sixth switch S4 is turned off before the monitoring voltage CS is at the start level. When the first and second switches S21 and S22 are turned on, the first capacitor Co1 is charged.

Then, when the comparator 113 generates the reset signal RST, the first and second switches S21 and S22 are turned off. REF + Va-Vo2 is applied to the other terminal N2 of the comparator 113 and REF + Va + Vo3 is applied to the terminal N1 of the comparator 113 when the reset signal RST is generated. Co1) is charged with -Vo2-Vo3.

Then, while the reset signal RST is being generated, the third and fourth switches S31 and S32 are turned on. When the third and fourth switches S31 and S32 are turned on, the voltage -Vo2-Vo3 charged in the first capacitor Co1 is distributed to the first and second capacitors Co1 and Co2. When the first capacitor Co1 and the second capacitor Co2 have the same capacitance, (-Vo2-Vo3) / 2 is charged to the second capacitor Co2.

The third and fourth switches S31 and S32 are turned off before the generation of the reset signal RST is stopped.

When the above-described process is repeated several times, the second capacitor Co2 is charged with -Vo2-Vo3. That is, the second capacitor Co2 can charge the sum of the negative voltage of the second offset voltage Vo2 and the negative voltage of the third offset voltage Vo3.

When the second capacitor Co2 charges the sum of the negative voltage of the second offset voltage Vo2 and the negative voltage of the third offset voltage Vo3 and when the comparator 113 generates the reset signal RST, REF + Va-Vo2 is applied to the other terminal N2 of the comparator 113 and REF + Va-Vo2 is applied to the one terminal N1 of the comparator 113. The comparator 113 compares the The reset signal RST can be generated without being influenced by the offset voltage Vo2.

17 to 19 each show an example of the application circuit portion of Fig. Figure 17 is a buck converter, Figure 18 is a light device, and Figure 19 is a power transformer. 17 to 19 are merely illustrative and not restrictive.

17, the buck converter includes, for example, an output load 213 in the form of a resistor and a capacitor 220 connected to both terminals of the output load 213. In addition, an inductive element 215 may be connected to one terminal of the output rod 213, and a diode 204 may be connected to the other terminal.

Referring to Fig. 18, the light device includes an output rod 213a including, for example, a plurality of LEDs. An inductive element 215 may be connected to one terminal of the output rod 213a, and a diode 204 may be connected to the other terminal of the output rod 213a.

Referring to FIG. 19, the power transformer 250 includes a primary winding 251 and a secondary winding 252. The input power source 211 is connected to the primary winding 251. The control diode 253 is connected to the secondary winding 252. The inductive element 215 may be connected to the control diode 253 and the output load 213b in the form of a resistor. An output filter capacitor 260 may be connected across the output load 213b. One terminal of the catch diode 204 is connected to a node between the inductive element 15 and the control diode 253 and the other terminal is connected to the node between the output load 213b and the secondary winding 252 Lt; / RTI >

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, You will understand. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

1: Switching device 10: Application circuit part
11: Input power source 13: Output load
15: Inductive element 20: Switch
30: Monitoring device 40: Oscillator
100: Signal control circuit 110: Reset signal generator
111: integrator 113: comparator
115: cancel offset 117: hold circuit
119: Operation circuit 131:
132: second operation section

Claims (19)

A switch for controlling current flowing in an inductive element;
A monitoring node coupled to the switch; And
And a signal control circuit connected to the monitoring node and a reference voltage for turning on / off the switch,
Wherein the signal control circuit comprises:
An integrator for generating a comparison voltage using the monitoring voltage of the monitoring node and the reference voltage;
A comparator for comparing the comparison voltage with the reference voltage to generate a reset signal,
And an offset cancel to prevent the first offset voltage by the integrator and the second offset voltage by the comparator from affecting the reset signal. The method according to claim 1,
Wherein the offset cancellation is located between the integrator and the comparator,
Wherein the sum of the comparison voltage and the first offset voltage is provided to the offset cancel,
Wherein the offset eliminating unit provides the sum of the reference voltage and the negative voltage of the second offset voltage to the comparator by using the sum of the reference voltage and the first offset voltage. 3. The method of claim 2,
Wherein the offset cancel is connected to one end of the comparator to which the comparison voltage is applied and the other end of the comparator. The method of claim 3,
The offset cancellation may include:
A first capacitor connected to one end of the comparator and the other end of the comparator by first and second switches, a second capacitor connected in parallel with the first capacitor by third and fourth switches, And a buffer connected between one end of the comparison unit and the other end of the comparison unit,
And the reference voltage is applied to the other end of the second capacitor. 5. The method of claim 4,
And the second capacitor charges the sum of the first offset voltage, the negative voltage of the second offset voltage, and the negative voltage of the third offset voltage of the buffer. 5. The method of claim 4,
The first and second switches are also turned on / off,
And the third and fourth switches are turned on / off together. 5. The method of claim 4,
And a fifth switch connected in parallel with the capacitor of the integrator. 8. The method of claim 7,
The turn-on of the fifth switch and the turn-on of the first and second switches partially overlap,
And the third and fourth switches are turned on within a time at which the reset signal is generated. 8. The method of claim 7,
The fifth switch is turned on,
Turning on the first and second switches so as to partially overlap the turn-on of the fifth switch to charge the first capacitor,
The fifth switch is turned off while maintaining the turn-on of the first and second switches,
Turning off the first and second switches,
And turning on the third and fourth switches to charge the second capacitor. 10. The method of claim 9,
Turning off the first and second switches comprises turning off the first and second switches at the same time the reset signal is generated. 10. The method of claim 9,
And turning on the third and fourth switches includes turning on the third and fourth switches only while the reset signal is being generated. 10. The method of claim 9,
Turning on said third and fourth switches comprises turning on said third and fourth switches to distribute a voltage charged to said first capacitor to each of said first and second capacitors, Way. 10. The method of claim 9,
Further comprising turning off the third and fourth switches after turning on the third and fourth switches,
The first to fifth switches are repeatedly applied to the second capacitor until the sum of the first offset voltage, the negative voltage of the second offset voltage, and the negative voltage of the third offset voltage of the buffer is charged, Turning on / off the switching device. A switch for controlling current flowing in an inductive element;
A monitoring node coupled to the switch; And
And a signal control circuit connected to the monitoring node and a reference voltage for turning on / off the switch,
Wherein the signal control circuit comprises:
An operational circuit for generating a first voltage based on the monitoring voltage of the monitoring node and generating a second voltage based on at least one of the sampling voltage and the reference voltage,
A comparator for turning off the switch when the first voltage and the second voltage are equal to each other;
And an offset canceling unit for canceling an offset voltage generated in the comparator. 15. The method of claim 14,
The offset cancellation may include:
A first capacitor connected to the other end of the comparator and one end of the comparator by first and second switches,
A second capacitor connected in parallel to the first capacitor by third and fourth switches, one end of which is connected to one end of the comparator,
And a buffer coupled to the other end of the second capacitor to receive the second voltage. 16. The method of claim 15,
The offset cancellation may include:
And a sixth switch connected in parallel with the second capacitor, for initializing the second capacitor. 16. The method of claim 15,
The first and second switches are also turned on / off,
And the third and fourth switches are turned on / off as well. 16. The method of claim 15,
And the third and fourth switches are turned on only while the switch is turned off. 16. The method of claim 15,
And the second capacitor charges the sum of the negative voltage of the offset voltage of the comparator and the negative voltage of the offset voltage of the buffer.

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