KR20160007338A - METAL GATE STACK HAVING TaAICN LAYER - Google Patents

Abstract

According to the present invention, an integrated circuit device comprises: a semiconductor substrate; and a gate stack arranged on the top of the semiconductor substrate. The gate stack further comprises: a gate dielectric layer arranged on the top of the semiconductor layer; a multi-functional blocking/wetting layer arranged on the top of the gate dielectric layer, and including a tantalum aluminum carbon nitride (TaAlCN); a work function layer arranged on the top of the multi-functional blocking/wetting layer; and a conductive layer arranged on the top of the work function layer.

Description

METAL GATE STACK HAVING < RTI ID = 0.0 > TaAICN LAYER < / RTI >

Cross reference of related application

This application is a continuation-in-part of U.S. Patent Application No. 14 / 328,299, filed on July 10, 2014, which is a continuation-in-part of U.S. Patent Application No. 13 / 244,355, filed September 24, 2011, Priority is claimed on U.S. Provisional Patent Application No. 62 / 056,278, filed September 26, 2014, the entire disclosure of which is incorporated herein by reference.

Technical field

The present invention relates to a semiconductor integrated circuit, and more particularly to a metal gate stack having a TaAlCN layer.

The semiconductor integrated circuit (IC) industry has achieved rapid growth. Technological advances in IC materials and design have produced IC generations with each generation having smaller and more complex circuits than previous generations. This advancement has increased the complexity in IC processing and manufacturing, and similar advances in IC processing and manufacturing have been required for this advancement to be realized. In the course of IC evolution, the functional density (i.e., the number of interconnected devices per chip area) has been increased as the geometric size (i. E., The minimum component (or line) that can be created using the manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering the associated costs. This scaling down has also increased the complexity in processing and manufacturing ICs, and similar developments in IC processing and manufacturing have been required to realize these advances.

Conventional gate stacks include a gate dielectric layer, a work function layer disposed over the gate dielectric layer, a barrier layer such as a tantalum nitride (TaN) barrier layer disposed over the work function layer, a titanium (Ti) wetting layer disposed over the barrier layer, The same wetting layer, and an aluminum (Al) conductive layer disposed over the wetting layer. It has been observed that the TaN barrier layer provides a blocking power below the desired blocking capability and aluminum impurities from the aluminum conductive layer can penetrate the gate dielectric layer during the processing process. In addition, while the Ti wetting layer provides sufficient wettability to the Al conductive layer, a phase transformation occurs between the Ti wetting layer and the Al conductive layer during the treatment process, (In other words, portions of the TaN barrier layer were consumed during the treatment process), leading to the interaction of the TaN barrier layer and eventually the portions of the TaN barrier layer. The missing portions of the TaN barrier layer further minimize the ability of the TaN barrier layer to prevent aluminum impurities from penetrating the gate dielectric layer. Such phase transitions and missing portions of the TaN barrier layer were also observed when the gate stack included a tantalum aluminum (TaAl) wetting layer.

To address this problem, the present disclosure replaces the isolated TaN barrier layer and the Ti wetting layer of a conventional gate stack with a TaAlCN multi-functional barrier / wetting layer 242. The blocking power of TaAlN exceeds the blocking power of TiN and TaN (concretely, the blocking power of TaAlCN> TaAlC >> TaN). In addition, TaAlCN provides sufficient wettability to the Al conductive layer. Thus, the TaAlCN multifunctional interfacial / wetting layer provides improved barrier and wettability, leading to reduced leakage current and improved device performance compared to gate stacks comprising a conventional TaN barrier layer / Ti wetting layer. Specifically, TaAlCN can be deposited on the surface of a substrate such as, for example, titanium aluminum carbon nitride (TiN), in view of formation, particle / residue problems, as resolved in integrated circuit device 200 and method 100 of manufacturing thereof, aluminum carbon nitride (TiAlCN)). Different embodiments may have different advantages, and there is no particular advantage that is necessarily required in certain embodiments.

The present disclosure provides many different embodiments. In some embodiments, the integrated circuit device includes a semiconductor substrate and a gate stack disposed over the semiconductor substrate. The gate stack comprising: a gate dielectric layer disposed over the semiconductor substrate; A multifunctional blocking / wetting layer comprising tantalum aluminum carbon nitride (TaAlCN) as a multifunctional blocking / wetting layer disposed over the gate dielectric layer; A work function layer disposed on top of the multifunction interception / wetting layer; And a conductive layer disposed over the work function layer.

In some other embodiments, an integrated circuit device includes a semiconductor substrate having a first region for an n-channel field effect transistor and a second region for a p-channel field effect transistor; A first gate stack disposed over the semiconductor substrate in the first region; And a second gate stack disposed over the semiconductor substrate in the second region. The first gate stack comprises a high-k dielectric layer disposed over the semiconductor substrate, a first tantalum aluminum carbon nitride (TaAlCN) layer disposed over the high-k dielectric layer, and a second tantalum aluminum nitride layer disposed directly on the first TaAlCN layer And a n work function (nWF) metal layer having a first work function. The second gate stack comprises a high-k dielectric layer disposed on top of the semiconductor substrate, a first TaAlCN layer disposed over the high-k dielectric layer, and a p-work function p (p) having a second work function disposed directly on the first TaAlCN layer. work function (pWF) metal layer, and the second work function is larger than the first work function.

In some other embodiments, the method includes forming a gate stack over a semiconductor substrate; Forming an interlayer dielectric (ILD) layer surrounding the gate stack; Forming an opening in the ILD layer by at least partially removing the gate stack; And forming a multifunction intercepting / wetting layer, a workfunction layer over the multifunction interception / wetting layer, and a conductive layer over the workfunctioning layer. The multifunction interception / wetting layer, work function layer, and conductive layer fill the openings. The multi-functional barrier / wetting layer comprises a first tantalum aluminum carbon nitride (TaAlCN) layer.

This disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. According to industry standard practice, the drawings are not drawn to scale, emphasizing that they are used for illustrative purposes only. In practice, the dimensions of various features may be arbitrarily increased or decreased for clarity of discussion.
1 is a flow diagram of a method for manufacturing an integrated circuit device in accordance with various aspects of the present disclosure.
2 through 7 are schematic cross-sectional views of an integrated circuit device during various stages of the method of FIG. 1 according to various aspects of the present disclosure.
8-11 are schematic cross-sectional views of an integrated circuit device constructed in accordance with various embodiments.
12 is a schematic top view of an integrated circuit device in accordance with some embodiments.
Figures 13 and 14 are schematic cross-sectional views of the integrated circuit device of Figure 12 in accordance with some embodiments.

The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific examples of components and arrangements for simplifying the disclosure of the present invention are described below. Of course, these are for illustrative purposes only and are not intended to be limiting. For example, in the following description, forming the first feature on or above the second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and the first feature and the second feature Embodiments may also include additional features that may be formed between the first feature and the second feature to avoid direct contact. In addition, the present disclosure may repeat the reference numerals and / or characters in various examples. Such repetition is for simplicity and clarity, and such repetition itself does not describe the relationship between the various embodiments and / or configurations disclosed.

1 is a partial or complete flowchart of a method 100 of manufacturing an integrated circuit device according to various aspects of the present disclosure. The method 100 begins at block 110 where a gate structure is formed over the substrate. The gate structure has a gate stack including a high-k dielectric layer disposed over the substrate, and a dummy gate disposed over the high-k dielectric layer. At block 120, the dummy gate is removed from the gate structure to form an opening therein. At block 130, a multifunctional blocking / wetting layer, a work function layer, and a conductive layer are formed to fill the openings. The multifunction interception / wetting layer is formed on the high-k dielectric layer, the work function layer is formed on the multifunction interception / wetting layer, and the conductive layer is formed on the work function layer. The multifunction intercepting / wetting layer is sufficient to prevent metal impurities from penetrating the high-k dielectric layer (e.g., from the conductive layer) during processing, while providing sufficient wettability (in other words, desired interface quality) Or reduced). The method 100 may continue to block 140 to complete the fabrication of the integrated circuit device. Additional steps may be provided before, during, and after method 100, and the steps described may be substituted or eliminated for further embodiments of method 100.

In some embodiments, between operation 110 and operation 120, source and drain features may be formed in the active area on either side of the dummy gate. In one example, an ion implantation process is performed to introduce a dopant (e.g., phosphorous) to form source and drain features, and an annealing process may be followed to activate the dopant. In another embodiment, procedures for forming source and drain may be implemented. The procedure may include performing a first ion implantation process to form a lightly doped drain (LDD) feature; Forming a gate spacer by film deposition and anisotropic etching; Performing a second ion implantation process to form a heavily doped source and drain aligned with the gate spacers; An annealing process may follow to activate the dopant. In yet another example, the source and drain are formed with a strain effect by appropriate procedures. The procedure may include etching the substrate in the source and drain regions to be recessed, and epitaxially growing the semiconductor material different from the substrate in recessing by selective epitaxial growth in-situ doping. have. Semiconductor materials provide suitable strains for channels, such as tensile strains for n-channel field effect transistors by use of silicon carbide and compressive strains for p-channel field effect transistors by the use of silicon germanium, for improved mobility .

The method 100 may have various embodiments. In some embodiments, the method 100 may alternatively implement a high-krast process, in which a high-k dielectric layer is formed after removal of the dummy gate. Going forward to this embodiment, at block 110, a gate stack comprising a gate dielectric (e.g., silicon oxide) and a gate electrode (e.g., polysilicon) is deposited and patterned. In block 120, both the gate dielectric and the gate electrode are removed, resulting in a gate trench. At block 130, a high-k dielectric layer and a gate electrode are formed within the gate trench by deposition and polishing, such as chemical mechanical polishing (CMP). The gate electrode comprises a multifunctional blocking / wetting layer, a work function layer, and a conductive layer.

2-7 illustrate, in part or in whole, a schematic cross-sectional view of an integrated circuit device 200 at various manufacturing stages according to the method 100 of FIG. 2 to 7 have been simplified for clarity in order to better understand the inventive concept of the present disclosure. The integrated circuit device 200 is described with reference to Figures 2-7, and the method 100 is also described in detail in accordance with some embodiments.

In the illustrated embodiment, the integrated circuit device 200 includes a field-effect transistor (FET), such as an n-channel field effect transistor (NFET) or a p-channel field effect transistor Transistor device. The integrated circuit device 200 may include a passive component such as a resistor, a capacitor, an inductor and / or a fuse; Such as a metal oxide semiconductor field effect transistor (MOSFET), a complementary metal-oxide-semiconductor transistor (CMOS), a high voltage transistor, and / or a high frequency transistor component; Other suitable components; Or a memory cell and / or logic circuit that includes a combination thereof. Additional features may be added in the integrated circuit device 200 and some of the features described below may be substituted or eliminated in other embodiments of the integrated circuit device 200. [

In FIG. 2, the integrated circuit device 200 includes a substrate 210. In the illustrated embodiment, the substrate 210 is a semiconductor substrate comprising silicon. Alternatively or additionally, the substrate 210 may comprise another elemental semiconductor, such as germanium; A compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; An alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; Or a combination thereof. In yet another alternative, the substrate 210 is a semiconductor on insulator (SOI). The semiconductor substrate 210 may comprise a semiconductor layer overlying another type of different semiconductor, such as a doped epi layer, a gradient semiconductor layer, and / or a silicon layer on a silicon germanium layer have. The substrate 210 includes various doping configurations that depend on the design requirements of the integrated circuit device 200. For example, the substrate 210 may be a p-type dopant such as boron or BF ₂ ; An n-type dopant such as phosphorus or arsenic; Or combinations thereof. ≪ RTI ID = 0.0 > The doped region may be formed on a semiconductor substrate in a P-well structure, an N-well structure, or a dual well structure.

Isolation features 212 are disposed within substrate 210 to isolate various regions and / or devices of substrate 210. Isolation features 212 utilize isolation techniques such as local oxidation of silicon (LOCOS) and / or shallow trench isolation (STI) to define and electrically isolate the various regions. Isolation features 212 include silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or combinations thereof. Isolation features 212 are formed by any suitable process. In one example, forming the STI feature includes exposing a portion of the substrate using a lithographic process, etching the trench at an exposed portion of the substrate (e.g., by using dry etch and / or wet etch) Filling the trench with one or more dielectric materials (e.g., by using a chemical vapor deposition process), and removing the excess portion of the dielectric material (s) by an abrasive process such as CMP. In some examples, the filled trench may have a multi-layer structure, such as a thermal oxide liner layer filled with silicon nitride or silicon oxide.

In some embodiments, the semiconductor substrate has a non-planar active region, such as a fin-like active region (or pin structure). The pinned active region is a feature of the semiconductor material that is extruded onto the plane of the semiconductor substrate and provides multiple surface coupling between the gate and the corresponding channel. The semiconductor matrix of the pinned active region may be the same semiconductor material as the semiconductor substrate, or alternatively it may be a semiconductor material different from the substrate. In some embodiments, the pinned active region may be formed by epitaxial growth of a semiconductor material on a semiconductor substrate using an appropriate technique, such as etching, or selective epitaxial growth, for recessing the STI feature.

A gate structure 220 is disposed over the substrate 210. In the illustrated embodiment, the gate structure 220 includes a gate stack having an interfacial dielectric layer 222, a high-k dielectric layer 224, and a dummy gate layer 226. The interface dielectric layer 222 and the high-k dielectric layer 224 may collectively be referred to as the gate dielectric layer of the gate structure 220. The gate stack may include additional layers such as a capping layer, a diffusion / barrier layer, a dielectric layer, a metal layer, another suitable layer, or a combination thereof. The gate structure 220 is formed by a deposition process, a lithographic patterning process, an etching process, another suitable process, or a combination thereof. The deposition process may be performed using physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced CVD (PECVD), remote plasma CVD (RPCVD), molecular organic CVD (MOCVD), sputtering, plating, other suitable methods, or combinations thereof. The lithographic patterning process may be performed by any suitable process known in the art, such as resist coating (e.g., spin-on coating), soft bake, mask alignment, exposure, post-exposure baking, photoresist development, Other suitable processes, or combinations thereof. The lithographic exposure process may be implemented or replaced by other suitable methods such as maskless lithography, electron beam writing and ion beam writing, and molecular imprint. The etching process includes dry etching, wet etching, or a combination thereof. In some embodiments, the gate structure 220 comprises depositing a variety of gate material layers; Forming a patterned resist layer by a lithography patterning process; Etching the gate material layer to form a gate structure (220) using a patterned resist layer as an etch mask; And removing the patterned resist layer by wet ablation or plasma ashing. In some other embodiments, a hard mask layer, such as silicon nitride, may be used as an etch mask during the etch process to pattern the gate material layer. In this case, the procedure for forming the gate structure 220 may include depositing various gate material layers; Depositing a hard mask layer on the gate material layer; Forming a patterned resist layer by a lithography patterning process; Etching the hard mask layer to pattern using the patterned resist layer as an etch mask; And etching the gate material layer to form the gate structure 220 using the patterned hard mask layer as the etch mask.

An interfacial dielectric layer 222 is disposed over the substrate 210. In one example, the interfacial dielectric layer 222 has a thickness of about 5 A to about 20 A. [ In the illustrated embodiment, the interfacial dielectric layer 222 is an oxide-containing layer such as a silicon oxide (SiO ₂ ) layer or a silicon oxynitride (SiON) layer. The interfacial dielectric layer 222 may comprise other suitable materials. Interfacial dielectric layer 222 is formed by chemical oxidation techniques, thermal oxidation techniques, atomic layer deposition (ALD), chemical vapor deposition (CVD), or other suitable techniques. A cleaning process such as an HF-last pre-gate cleaning process (e.g., using a hydrogen fluoride (HF) acid aqueous solution) may be used to remove the interfacial dielectric layer 222 Can be performed before.

A high-k dielectric layer 224 is disposed over the interface dielectric layer 222 and a dummy gate layer 226 is disposed over the high-k dielectric layer 224. [ The thickness of the high-k dielectric layer 224 and the dummy gate layer 226 depends on the design requirements of the integrated circuit device 200. In one example, the high-k dielectric layer 224 has a thickness of about 5 A to about 30 ANGSTROM, and the dummy gate layer has a thickness of about 350 ANGSTROM to about 700 ANGSTROM. High -k dielectric layer 224 is _{HfO 2, HfSiO, HfSiON, HfTaO} , HfTiO, HfZrO, zirconium oxide, aluminum oxide, hafnium dioxide-alumina (HfO ₂ -Al ₂ O ₃₎ alloy, other suitable high -k dielectric material, Or a combination thereof. The dummy gate layer 226 includes a material suitable for the gate replacement process. For example, in the illustrated embodiment, the dummy gate layer 226 comprises polysilicon.

The gate structure 220 further includes a spacer 228 formed by a suitable process. For example, the dielectric layer, such as a silicon oxide layer, is a blanket disposed on top of the integrated circuit device 200, and the silicon oxide layer is then patterned to form a spacer 228, And is anisotropically etched to remove the nitride layer. Spacers 228 are positioned adjacent the sidewalls of the gate stacks (interfacial dielectric layer 222, high-k dielectric layer 224, and dummy gate layer 226) of gate structure 220. Alternatively or additionally, the spacers 228 include other dielectric materials such as silicon oxide, silicon carbon nitride, or combinations thereof.

A variety of source / drain features 230 may be disposed within the substrate 210. Source / drain features 230 are interposed by gate structure 220. The source / drain feature 230 may include lightly doped source and drain (LDD) regions and / or heavily doped source and drain (HDD) regions. The LDD and / or HDD region may be formed by ion implantation or diffusion of an n-type dopant such as phosphorus or arsenic, or a p-type dopant such as boron or BF ₂ . Annealing processes such as rapid thermal annealing and / or laser thermal annealing may be performed to activate dopants in the LDD and / or HDD regions. The LDD and / or HDD regions may be formed at any time in the illustrated embodiment. The source / drain features 230 may include raised source / drain features such as epitaxial features (e.g., silicon germanium epitaxial features or silicon epitaxial features). A silicide feature may be disposed over the source / drain feature 230, for example, to reduce contact resistance. A silicide feature may be formed on the source and drain features by a self-aligned salicide process, comprising depositing a metal layer; Annealing the metal layer such that the metal layer can react with silicon to form a silicide; And then removing the unreacted metal layer.

A dielectric layer 232, such as an interlayer dielectric (ILD) layer, is disposed over the substrate 210. Dielectric layer 232 may be formed of any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, tetraethylorthosilicate (TEOS) oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG) And the same dielectric material. Exemplary low-k dielectric materials include fluorinated silica glass (FSG), carbon doped silicon oxide, Black Diamond (Applied Materials, Santa Clara, CA), Xerogel, Aerogel, fluorinated amorphous carbon, Parylene, BCB (bis-benzocyclobutenes ), SiLK (Dow Chemical of Midland, Mich.), Polyimide, other suitable materials, and / or combinations thereof. Dielectric layer 232 may comprise a multi-layer structure comprising multiple dielectric materials. Dielectric layer 232 is formed to a suitable thickness by a suitable process, including CVD, high-density plasma CVD, spin-on, and / or other suitable methods. Following the deposition of the dielectric layer 232, a chemical mechanical polishing (CMP) process is performed until the top of the gate structure 220 is reached / exposed. Specifically, the top of the gate stack of the gate structure 220 (here, the dummy gate layer 226) is exposed as shown in FIG. Additional layers may be formed to lie above and / or below the dielectric layer.

3-7, a gate replacement process is performed in which the dummy gate layer 226 is replaced with a metal gate. In FIG. 3, dummy gate layer 226 is removed from the gate stack of gate structure 220 to form openings (or gate trenches) 240. The openings 240 expose the high-k gate dielectric layer 224. The dummy gate layer 226 may be removed by an etch process, another suitable process, or a combination thereof. In one example, the etch process selectively etches the dummy gate layer 226.

In FIG. 4, a multifunctional blocking / wetting layer 242 is formed over the substrate 210 to partially fill the opening 240 with the multifunction interception / wetting layer 242. The multi-functional barrier / wetting layer 242 is disposed along the sidewalls of the gate structure 220 defining the openings 240. In the illustrated embodiment, the multifunction intercepting / wetting layer 242 is disposed over the high-k dielectric layer 224. In one example, the multifunction intercepting / wetting layer 242 has a thickness of from about 30 A to about 100 A. The multifunction interception / wetting layer 242 functions as both a barrier (or barrier) layer and a wetting layer during the treatment process. For example, the multifunction intercepting / wetting layer 242 may be formed by depositing a metal impurity on any dielectric layer (e. G., The gate dielectric of the gate stack of the gate structure 220) disposed below the multifunctional intercepting / Thereby enhancing the adhesion between the underlying layer and the layer thereon, while preventing or reducing penetration. It also provides the desired interface quality between the multifunction intercepting / wetting layer 242 and any material layers formed above the multifunction intercepting / wetting layer 242. Thus, in the illustrated embodiment, the multifunction intercepting / wetting layer 242 prevents or reduces metal impurities from penetrating into the high-k dielectric layer 224 and the interfacial dielectric layer 222, (For example, the work function layer 244) of the gate structure 220 formed on the high-k dielectric layer 224 and the multi-functional interfacial / wetting layer 242, . Such functionality is described in greater detail below.

In the illustrated embodiment, the multifunction intercept / wet layer 242 comprises tantalum aluminum nitride (TaAlN), and in an exemplary embodiment, the TaAlN is tantalum aluminum carbon nitride (TaAlCN) Lt; / RTI > The atomic concentration of the nitrogen and carbon in the TaAlCN layer is such that the multifunctional blocking / wetting layer 242 minimally affects the work function of the integrated circuit device 200 while minimizing the dielectric constant of the dielectric layer (e. G., High- k dielectric layer 224 and the interfacial dielectric layer 222). Therefore, the nitrogen atom concentration and the carbon atom concentration are selected to balance the blocking ability with the desired work function. In the illustrated embodiment, the TaAlCN layer includes a nitrogen atom concentration of about 5% to about 15%, and a carbon atom concentration of about 5% to about 20%. At lower nitrogen and carbon atom concentrations (e.g., less than about 5%), the blocking ability may be moved in an undesired direction, closer to the desired work function. On the other hand, at higher nitrogen and carbon atom concentrations (e.g., nitrogen atom concentrations greater than 15% and greater than 20% carbon atom concentrations), the balance moves away from the desired work function to the desired blocking capacity. In the illustrated embodiment, the TaAlCN ratio comprises a Ta: Al ratio that improves the interface quality (which may be referred to as wettability) between the multifunction intercept / wetting layer 242 and the overlying layer, including aluminum. For example, the TaAlCN layer 242 includes a Ta: Al ratio of about 1: 1 to about 1: 3.

The multifunction interception / wetting layer 242, wherein the process used to form the TaAlCN layer, is adjusted to achieve optimal blocking and wetting functionality of the multifunctional interfacial / wetting layer 242. In the illustrated embodiment, physical vapor deposition (PVD) is used to form the multifunctional blocking / wetting layer 242. Various process parameters of the PVD process, such as substrate temperature, gas type, gas flow rate, chamber pressure, DC voltage, bias voltage, process time, other suitable parameters, or combinations thereof, are adjusted to achieve desired blocking and wetting functionality . Alternatively, atomic layer deposition (ALD) is used to form the multifunctional blocking / wetting layer 242. Various process parameters of the ALD process, such as substrate temperature, gas type, gas flow rate, chamber pressure, process time, other suitable parameters, or combinations thereof, are adjusted to achieve desired blocking and wetting functionality. Alternatively, the multifunction intercepting / wetting layer 242 may be formed by any suitable method, including but not limited to chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), remote plasma CVD (RPCVD), MOCVD, PVD, ALD, , Or a combination thereof. Various process parameters of such alternative processes are adjusted to achieve the desired barrier and wetting functionality of the multifunctional barrier / wetting layer 242.

In the illustrated embodiment, a high pressure PVD process that maintains a chamber pressure of about 0.1 Torr to about 5 mTorr deposits a multifunction intercept / wet layer 242 at a temperature of about 250 ° C to about 450 ° C. The high pressure PVD process can ensure that the multifunction intercepting / wetting layer 242 fills the opening 240 sufficiently fully. The high pressure PVD process provides adequate coverage, e.g., for high aspect ratio openings, such as openings 240. For example, in the illustrated embodiment, a high aspect ratio opening refers to an opening having a height to width ratio (height / width > 2.2) greater than or equal to 2.2. Alternatively, the high aspect ratio openings may be defined by different height-to-width ratios.

In another embodiment, the multifunction intercept / wetting layer 242 comprises multiple layers of TaAlCN having different N%. For example, the underlying TaAlCN layer has a higher N%, such as from about 5% to about 15%, and the upper TaAlCN layer has a lower N%, such as from about 2% to about 5%. In this case, the lower TaAlCN layer mainly serves as a barrier layer, and the upper TaAlCN layer mainly serves as a work function layer. By choosing the appropriate C% and N%, optimized blocking capabilities are achieved. In one example, C% is in the range of about 5% to about 20% and N% is in the range of about 5% to 15%.

In Figure 5, a workfunction layer 244 is formed over the substrate 210 to partially fill the opening 240 with the work function layer 244. In the illustrated embodiment, the work-function layer 244 is disposed above the multifunctional interfacial / wetting layer 242. In one example, work function layer 244 has a thickness of from about 30 A to about 100 A. [ The work function layer 244 disposed on the multifunction intercepting / wetting layer 242 has a thickness of from about 30 A to about 100 A and has a work function layer 244 disposed along the sidewalls of the opening 240, May have a thickness of less than 30 ANGSTROM, or a thickness of from about 30 ANGSTROM to about 100 ANGSTROM. The work function layer 244 includes a material that can be adjusted to have an appropriate work function for improved performance of the associated device. For example, for a p-type field effect transistor (PFET) device, the workfunction layer 244 may have a desired work function value (for example, close to 5.2 eV, or from 4.7 eV to 5 eV Lt; RTI ID = 0.0 > p-type < / RTI > work function material. On the other hand, in the case of an n-type field effect transistor (NFET) device, the workfunction layer 244 may have a desired work function value (for example, close to 4.2 eV, or from 4.1 eV to 4.5 eV (E. G., TaAlCN) that can be configured to have a < / RTI > The workfunction layer 244 may be formed by any suitable process known in the art including but not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced CVD (PECVD), remote plasma CVD (RPCVD), molecular organic CVD , Plating, other suitable methods, or a combination thereof.

In some embodiments, the TaAlCN layer is formed using a precursor comprising a tantalum-based chemical, an aluminum-based chemical, a carbon-based gas, and a nitrogen-based gas. In some examples, the tantalum-based chemistry includes pentakis (dimethylamino) tantalum (PDMAT), triethylaluminum, tantalum chloride (TaCl ₅ ), other suitable Ta-containing chemicals, or combinations thereof. In some examples, the aluminum-based chemistry includes triethyl aluminum (TEAl), trimethyl aluminum (TMA), aluminum borohydride trimethylamine (AlBT), other suitable Al-containing chemicals, or combinations thereof. In some examples, the nitrogen-based gas comprises NH ₃ , N ₂ , other suitable N-containing chemicals, or combinations thereof. In some examples, the carbon-based gas includes CH _x such as CH ₃ .

In some embodiments, work function layer 244 is a n-functional layer comprising TaAlCN. In the illustrated embodiment, work function layer 244 includes TaAlCN having a composition different from TaAlCN in multifunctional blocking / wetting layer 242. For example, the concentration of nitrogen atoms in the work function layer 244 is lower than the concentration of nitrogen atoms in the multifunctional blocking / wetting layer 242. The nitrogen atom concentration is chosen to balance the blocking ability and the desired work function. In one embodiment, the nitrogen atom concentration in the work function layer 244 is from about 2% to about 5%. Aluminum in the work function layer 244 has high mobility and can readily penetrate the lower layer when the nitrogen atom concentration is lower (e.g., less than about 2%). At a higher nitrogen atom concentration (e.g., greater than about 2%), the nitrogen in the work function layer 244 bonds to aluminum, forms a stable state, and can reduce aluminum penetration into the underlying layer. However, much higher nitrogen atom concentrations can cause a desired work function or migration from the target (e.g., greater than about 5%).

In some embodiments, work function layer 244 is a n-function layer for NFETs and has a work function range from about 4.1 eV to about 4.5 eV. Further in this embodiment, the n-work function layer comprises titanium (Ti), aluminum (Al), titanium aluminum (TiAl), tantalum (Ta), or zirconium silicon (ZrSi ₂ ).

In Figure 6, a conductive layer 246 is formed over the substrate 210 to partially fill the opening 240 with the conductive layer 246. [ The conductive layer 246 is disposed over the work-function layer 244. In one example, the conductive layer 246 has a thickness of about 300 ANGSTROM to about 1,500 ANGSTROM. In the illustrated embodiment, the conductive layer 246 comprises aluminum. Alternatively or additionally, the conductive layer 246 includes copper, tungsten, a metal alloy, a metal silicide, another conductive material, or a combination thereof. The conductive layer 246 may be formed by any suitable process known in the art such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced CVD (PECVD), remote plasma CVD (RPCVD), molecular organic CVD Plating, another suitable method, or a combination thereof.

7, a chemical mechanical polishing (CMP) process is performed until the dielectric layer 232 is reached or exposed. Thus, the CMP process removes portions of the multifunctional blocking / wetting layer 242, work function layer 244, and conductive layer 246 disposed over the dielectric layer 232. The remaining portions of the multifunction intercepting / wetting layer 242, work function layer 244, and conductive layer 246 may be formed such that the gate stack of the gate structure 220 is formed by the interfacial dielectric layer 222, the high-k dielectric layer 224, Wettable layer 242, work-function layer 244, and conductive layer 246, as shown in FIG. Multifunctional blocking / wetting layer 242, work function layer 244, and conductive layer 246 can be collectively referred to as the gate electrode of gate structure 200.

The integrated circuit device 200 may include other features. For example, a multilayer interconnection (MLI) including a metal layer and an intermetal dielectric (IMD) layer may be formed on the substrate 210, such as on top of the dielectric layer 232 to form an integrated circuit device 200 ) May be electrically connected to each other. The multilayer wiring includes vertical wiring such as via or contact, and horizontal wiring such as a metal wire. In one example, the MLI includes line features to the source / drain feature 230 and / or the gate stack of the gate structure 220. Various wiring features include various conductive materials including aluminum, copper, titanium, tungsten, alloys thereof, silicide materials, other suitable materials, or combinations thereof. In one example, a damascene process or a dual damascene process is used to form a copper or aluminum multilayer interconnection structure.

The integrated circuit device 200 exhibits reduced leakage current, which leads to improved device performance. Such reduced leakage current and improved device performance can be achieved by the multifunction blocking / wetting layer 242 in the gate stack of the gate structure 220. The multifunction intercepting / wetting layer 242 can adequately block metal impurities from penetrating the underlying dielectric layer while providing sufficient wettability (interface quality) to the overlying layers.

The integrated circuit device 200 and method of manufacturing 100 thereof may have other embodiments without departing from the scope of the present disclosure. Several embodiments are provided below. Similar features and similar operations are not repeated for simplicity.

Figure 8 illustrates an integrated circuit device 200 in accordance with some embodiments. The integrated circuit device 200 further includes a capping layer 250 disposed between the high-k dielectric layer 224 and the multi-functional interfacial / wetting layer 242. The capping layer 250 also protects the high-k dielectric layer and / or enhances the function of the multifunctional blocking / wetting layer 242. The capping layer 250 includes titanium nitride (TiN), tantalum nitride (TaN), or a combination thereof. The capping layer may be formed by a suitable technique such as PVD. The capping layer may be formed in operation 110 of method 100, alternatively in operation 130. [ In some embodiments, when the high-k dielectric layer 224 is formed in operation 110, the capping layer 250 may likewise be formed in operation 110, thus protecting the high-k dielectric layer during fabrication. In this case, both the high-k dielectric layer 224 and the capping layer 250 are formed only at the bottom of the opening 240, but as shown in FIG. 8, the multi-functional barrier / wetting layer 242 and the work- Are disposed on the lower and side walls of the opening 240, or, in other words, U-shaped. If method 100 utilizes a high-krast process, a high-k dielectric layer is also formed at operation 130. [ In this case, capping layer 250 is likewise formed in operation 130. Therefore, both the high-k dielectric layer 224 and the capping layer 250 are formed on the sidewalls and are U-shaped.

Figure 9 illustrates an integrated circuit device 200 in accordance with some embodiments. The method 100 uses a high-k.sub.rast process and the high-k dielectric layer is formed in operation 130 after removal of the dummy gate stack by operation 120. [ In this case, the dummy gate formed by operation 110 may comprise a silicon oxide layer and a polysilicon layer above the silicon oxide layer. In operation 120, the gate stack is removed by etching. Then, in operation 130, a gate dielectric layer is formed in the opening 240. Other gate material layers (e.g., 242, 246, and 248) are formed in the opening 240 in a manner similar to the steps for forming the material layers 242, 246, and 248 described above. Therefore, the high-k dielectric layer is also U-shaped. Again, the capping layer 250 is between the high-k dielectric layer 224 and the multifunction intercepting / wetting layer 242, and both the high-k dielectric layer 224 and the capping layer 250 are formed on the sidewalls, U shape. The interface layer 222 may be removed at operation 120 and re-deposited at operation 130 by, for example, thermal oxidation (not U-shaped) or ALD (U-shaped).

FIG. 10 illustrates an integrated circuit device 200 in accordance with some embodiments. Source and drain (S / D) features 230 are formed of different semiconductor materials for strain effects, which improves channel mobility and device performance. In operation 120, the source and drain features 230 are formed by appropriate procedures. For example, the procedure may include etching the substrate in the source and drain regions to be recessed, and epitaxially growing the semiconductor material different from the substrate in recessing by selective epitaxial growth in situ doping. Semiconductor materials provide suitable strains for channels, such as tensile strains for n-channel field effect transistors by use of silicon carbide and compressive strains for p-channel field effect transistors by the use of silicon germanium, for improved mobility . In one example, device 200 is an nFET, the semiconductor material is phosphorus doped silicon carbide for S / D feature 230, and substrate 210 is a silicon substrate. In one example, the device 200 is a pFET, the semiconductor material is silicon germanium doped with boron for the S / D feature 230, and the substrate 210 is a silicon substrate. In another example, the integrated circuit device 200 includes an nFET and a pFET, and the silicon carbide of the phosphorous dopant is epitaxially grown to form the S / D feature 230 for the nFET, and the silicon of the boron dopant Germanium is epitaxially grown to form the S / D feature 230 for the pFET, and the substrate 210 is a silicon substrate. The S / D feature 230 may be epitaxially grown such that the top surface of the S / D feature 230 is substantially coplanar with the top surface of the semiconductor substrate 210. Alternatively, the S / D feature 230 may be epitaxially grown over the top surface of the semiconductor substrate 210 as illustrated in FIG.

FIG. 11 illustrates an integrated circuit device 200 in accordance with some embodiments. In Figure 11, the gate stack 220 includes a multi-functional intercepting / wetting layer 242 on the high-k dielectric layer 224 and a conductive layer 246 disposed directly on the multifunction interception / wetting layer 242. The conductive layer 246 may be, for example, aluminum. The multifunction intercepting / wetting layer 242 comprises TaAlCN and is adjusted to function as well as an n-work function layer. The atomic concentration of the nitrogen and carbon in the TaAlCN layer is such that the multifunctional interfacial / wetting layer 242 has a dielectric constant with a metallic work function, such as a work function within the range of about 4.1 eV to about 4.5 eV, The high-k dielectric layer 224, and the interfacial dielectric layer 222). In the illustrated embodiment, the TaAlCN layer comprises a nitrogen atom concentration of about 3% to about 10%. The TaAlCN layer may comprise from about 5% to about 20% carbon atom concentration. The TaAlCN ratio may include a Ta: Al ratio that improves the interface quality (which may be referred to as wettability) between the multifunction intercepting / wetting layer 242 and the overlying layer, including aluminum. For example, the TaAlCN layer 242 includes a Ta: Al ratio of about 1: 1 to about 1: 3.

12-14 illustrate an integrated circuit (IC) structure 270 in accordance with some embodiments. 12 is a top view of an IC structure 270 in accordance with some embodiments. 13 is a cross-sectional view of an IC structure 270 along dashed line AA ', in accordance with some embodiments. 14 is a cross-sectional view of an IC structure 270 according to broken line BB ', in accordance with some embodiments. The IC structure 270 includes a first pin active region 272 and a second pin active region 274 formed on a semiconductor substrate 210. The pin active regions 272 and 274 extend vertically above the top surface of the STI feature 212. The semiconductor material of the pin active region may be the same as, or alternatively may be different from, the semiconductor substrate 210. The pin active region may be formed by etching to recess the STI feature or by selective epitaxial growth. In one embodiment, the first pin active region 272 is for an nFET and the second pin active region 274 is for a pFET. Doped well 276 is formed in the first pin active region 272 and the n-doped well 278 is formed in the second pin active region 274 by ion implantation, for example, . Thus, the first channel region 280 and the second channel region 282 are defined in the first and second pin active regions, respectively.

In some embodiments, the S / D feature 230 is formed by epitaxial growth for strain effects, as illustrated in FIG. A gate stack is formed above the pin active region. The gate stack 220 is similar to the gate stack 220 of FIG. 7 or the gate stack 220 of either of FIGS. 8-11, in various embodiments. In one embodiment, when the active areas 272 and 274 are of different conductivity types, the gate stack 220 may include two portions of a different material stack, for example, a first portion above the first pin active region 272, And a second portion above the two-pin active region 274. The two portions are similar in configuration except for the workfunction metal layer 244. In a first portion of the gate stack, the workfunction metal layer comprises an nWF metal layer. In the second portion of the gate stack, the workfunction metal layer comprises a pWF metal layer.

Different embodiments are also described. There is an integrated circuit device of another embodiment in which two or more of the above embodiments are combined. For example, an integrated circuit device includes both an epitaxial growth S / D feature and a U-shaped high-k dielectric layer. In another example, one passive circuit device includes both a pin active region and an additional capping layer 250.

The foregoing is a summary of features of various embodiments to enable those skilled in the art to more fully understand aspects of the disclosure of the present invention. Those skilled in the art should appreciate that the present invention can readily be used on the basis of the disclosure of the present invention to accomplish the same objects as the embodiments disclosed herein and / or to design or modify other processes and structures that achieve the same advantages. Also, those skilled in the art should appreciate that such equivalent constructions do not depart from the spirit and scope of the disclosure, and various modifications, substitutions and alterations are possible without departing from the spirit and scope of the disclosure.

Claims (10)

In an integrated circuit device,
A semiconductor substrate; And
And a gate stack
/ RTI >
Wherein the gate stack comprises:
A gate dielectric layer disposed on the semiconductor substrate,
A multi-functional blocking / wetting layer disposed over the gate dielectric layer, the multi-functional blocking / wetting layer comprising tantalum aluminum carbon nitride (TaAlCN)
A work function layer disposed above the multifunction interception / wetting layer, and
And a conductive layer
And an integrated circuit device. The method according to claim 1,
Wherein the gate dielectric layer comprises a high-k dielectric layer. 3. The method of claim 2,
Wherein the gate dielectric layer comprises an interfacial dielectric layer disposed between the high-k dielectric layer and the semiconductor substrate. The method according to claim 1,
Wherein the multifunction intercept / wet layer has a concentration of nitrogen atoms and a concentration of carbon atoms that prevent metal impurities from penetrating the gate dielectric layer. The method according to claim 1,
Wherein the multifunctional blocking / wetting layer comprises multiple layers of TaAlCN having different nitrogen atom concentrations. The method according to claim 1,
Wherein the multifunction intercept / wet layer has a Ta: Al ratio of 1: 1 to 1: 3. The method according to claim 1,
Further comprising a capping layer disposed between the gate dielectric layer and the multifunctional blocking / wetting layer, wherein the capping layer comprises one of titanium nitride, tantalum nitride, and combinations thereof. The method according to claim 1,
Wherein the semiconductor substrate comprises a fin active region,
Wherein the gate stack is formed on the pin active region. In an integrated circuit device,
a semiconductor substrate having a first region for an n-channel field effect transistor and a second region for a p-channel field effect transistor;
A first gate stack disposed above the semiconductor substrate in the first region; And
A second gate stack disposed above the semiconductor substrate in the second region,
/ RTI >
Wherein the first gate stack comprises a high-k dielectric layer disposed over the semiconductor substrate, a first tantalum aluminum carbon nitride (TaAlCN) layer disposed over the high-k dielectric layer, And a n work function (nWF) metal layer having a first work function,
Wherein the second gate stack comprises a high-k dielectric layer disposed over the semiconductor substrate, the first TaAlCN layer disposed over the high-k dielectric layer, and a second work function disposed directly on the first TaAlCN layer Wherein the second work function comprises a p-work function (pWF) metal layer having a first work function, wherein the second work function is greater than the first work function. In the method,
Forming a gate stack over the semiconductor substrate;
Forming an interlayer dielectric (ILD) layer surrounding the gate stack
Forming an opening in the ILD layer by at least partially removing the gate stack; And
Forming a multi-functional intercepting / wetting layer, a workfunction layer above said multifunction intercepting / wetting layer, and a conductive layer above said workfunctioning layer
/ RTI >
Wherein the multifunctional blocking / wetting layer, the work function layer, and the conductive layer fill the opening and the multifunctional intercepting / wetting layer comprises a first tantalum aluminum carbon nitride (TaAlCN) layer / RTI >

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