KR20160001879A - Display device and method for fabricating the same - Google Patents

Abstract

The present invention relates to a display device and a method for manufacturing the same. According to an embodiment of the present invention, the display device comprises: data lines disposed on a substrate in a first direction to deliver data signals; gate lines disposed on the substrate in a second direction to deliver gate signals; and thin film transistors disposed in each pixel defined by intersecting the gate lines and data lines. The thin film transistor includes: a crystallized oxide semiconductor including atoms of metal materials inside the thin film; a source electrode and a drain electrode which are in contact with the oxide semiconductor; a gate insulating layer disposed on one side surface of the oxide semiconductor; and a gate disposed on one side surface of the gate insulating layer.

Description

DISPLAY APPARATUS AND METHOD FOR FABRICATING THE SAME

The present invention relates to a display device for displaying an image and a method of manufacturing the same.

2. Description of the Related Art [0002] As an information-oriented society develops, there have been various demands for a display device for displaying images. Recently, a liquid crystal display (LCD), a plasma display panel (PDP) Various display devices such as an organic light emitting display (OLED) device are being used. Such various display apparatuses include display panels corresponding thereto.

The display panel included in such a display device may be one of a plurality of display panels formed on one substrate. That is, according to various process procedures, elements, signal lines, power supply lines, or the like that constitute pixels in one substrate are formed for each display panel unit, and then a substrate is scribed in units of display panels using a scribe equipment You can cut several display panels.

An amorphous silicon thin film transistor has a higher electron mobility than an amorphous silicon semiconductor and has a lower manufacturing cost than a polysilicon thin film transistor. Active research is underway. In forming the active layer of the oxide thin film transistor, the crystallization temperature may have a large influence on the process, and therefore, a technique of crystallizing it at a low temperature is needed.

In view of the above, it is an object of the present invention to provide a display device in which IGZO is crystallized at a low temperature using diffusion of a metal material for improving mobility of the oxide TFT and improving reliability of the TFT, and a method of manufacturing the same .

In order to accomplish the above object, in one aspect, the present invention provides a liquid crystal display device including a data line positioned in a first direction on a substrate and transmitting a data signal, a gate line positioned in a second direction on the substrate, And a thin film transistor positioned in each pixel defined by intersecting the gate line and the data line, wherein the thin film transistor includes a crystallized oxide semiconductor including atoms of a metal material in a thin film, a source electrode And a drain electrode, a gate insulating layer located on one side of the oxide semiconductor, and a gate located on one side of the gate insulating layer.

In another aspect, the present invention includes a method of manufacturing a semiconductor device comprising forming an oxide semiconductor on a substrate, applying a layer of metal material on the oxide semiconductor, heat treating the layer of metal material, and removing the layer of metal material To a display device.

INDUSTRIAL APPLICABILITY As described above, according to the present invention, crystallization is performed at 350 占 폚 using metal diffusion without performing a high-temperature heat treatment or laser annealing to crystallize IGZO, thereby improving the performance and reliability of the TFT. .

1 is a view schematically showing a display device according to embodiments.
2 is a view showing a simplified structure of an IGZO oxide semiconductor.
FIG. 3 is a view showing a process of performing a high-temperature heat treatment on the low-temperature deposited IGZO.
FIG. 4 is a view showing a process of performing laser annealing of low-temperature deposited IGZO.
5 is a view showing a process of crystallizing IGZO at a low temperature according to an embodiment of the present invention.
FIG. 6 is a view showing a structure of a TFT and a process of crystallizing an oxide semiconductor at a low temperature in a top gate type coplanar structure according to another embodiment of the present invention. FIG.
7 is a view illustrating a process of crystallizing an oxide semiconductor at a low temperature and a structure of a TFT in a top gate type staggered structure according to another embodiment of the present invention.
8 is a view illustrating a process of crystallizing an oxide semiconductor at a low temperature and a structure of a TFT in an ESL structure of a bottom gate-scrambler method according to another embodiment of the present invention.
9 is a view illustrating a process of crystallizing an oxide semiconductor at a low temperature and a structure of a TFT in a BCL structure of a bottom gate-scrambled method according to another embodiment of the present invention.
10 is a view showing an embodiment in which a metal material layer is not completely removed by a process and structure in which an oxide semiconductor is crystallized at low temperature in a coplanar structure according to another embodiment of the present invention.
11 is a view illustrating a process of depositing a metal material layer according to an embodiment of the present invention to crystallize an oxide semiconductor at a low temperature.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In the drawings, like reference numerals are used to denote like elements throughout the drawings, even if they are shown on different drawings. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

In describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are intended to distinguish the components from other components, and the terms do not limit the nature, order, order, or number of the components. When a component is described as being "connected", "coupled", or "connected" to another component, the component may be directly connected or connected to the other component, Quot; intervening "or that each component may be" connected, "" coupled, "or " connected" through other components.

1 is a view schematically showing a display device according to embodiments.

Referring to FIG. 1, a display device 100 according to an embodiment includes a plurality of first lines VL1 to VLm formed in a first direction (e.g., a vertical direction) A display panel 110 on which a plurality of second lines HL1 to HLn are formed, a first driver 120 for supplying a first signal to a plurality of first lines VL1 to VLm, A second driver 130 for supplying a second signal to the first and second lines HL1 to HLn and a timing controller 140 for controlling the first and second drivers 120 and 130.

The display panel 110 is provided with a plurality of first lines VL1 to VLm formed in a first direction (e.g., a vertical direction) and a plurality of second lines HL1 to HLn formed in a second direction (e.g., A plurality of pixels (P) are defined according to the intersection of the pixels.

Each of the first driving unit 120 and the second driving unit 130 may include at least one driver IC for outputting a signal for displaying an image.

A plurality of first lines VL1 to VLm formed in the first direction on the display panel 110 are formed in a vertical direction (first direction) to transmit a data voltage (first signal) And the first driver 120 may be a data driver for supplying the data voltage to the data line.

A plurality of second lines HL1 to HLn formed in the second direction on the display panel 110 are formed in a horizontal direction (second direction) to form a gate signal (first signal) And the second driver 130 may be a gate driver for supplying a scan signal to the gate line.

In addition, a pad portion is formed on the display panel 110 to connect the first driver 120 and the second driver 130. When the first driver 120 supplies a first signal to the plurality of first lines VL1 through VLm, the pad unit transmits the first signal to the display panel 110 and the second driver 130 similarly applies a plurality of second lines HL1 to HLn), and transmits the second signal to the display panel (110). Therefore, the pad portion is formed together in the process of forming the regions of the pixels of the display panel 110. [

The structure of the oxide semiconductor to which the present invention can be applied is applicable to an ESL (Etch Stopper Layer) structure and a BCL (Back Channel Etch) structure in a bottom gate type staggered structure, but is not limited thereto Do not. But is not limited to, a top gate type coplanar structure and a staggered structure.

The present invention also relates to a method of manufacturing a semiconductor device, including a zinc oxide (ZnO) semiconductor, an indium zinc oxide (IZO) semiconductor, an indium aluminum zinc oxide (IAZO) semiconductor, an indium gallium zinc oxide (IGZO) Semiconductor, or indium tin zinc oxide (ITZO) semiconductor. However, the present invention is not limited thereto. IGZO will be mainly described according to the embodiment.

In the case of oxide semiconductors such as IGZO, ACT IGZO can be easily deposited at low temperatures by sputtering to ensure high mobility versus a-Si or ~ 10 cm2 / Vs. 2 is a view showing a simplified structure of an IGZO oxide semiconductor.

An IGZO 210 constituting an activation layer made of an oxide semiconductor is formed on a substrate 200, a gate 202 and a gate insulator (GI) 205, and an etch stopper layer (ESL 220 and a source / drain 230 are formed. IGZO 210 can be deposited at low temperatures, which can be applied to substrates of plastic substrates for glass substrates and flexible display devices. Further, other materials may be deposited on the substrate 200 to improve the performance of the display device such as a buffer layer (not shown) or a light shielding layer.

However, when a large-sized display device is implemented, it is necessary to secure high mobility and reliability for high-speed response, and it is necessary to crystallize low-temperature deposited IGZO. For the crystallization, it is necessary to perform a heat treatment at a high temperature, or to carry out a laser heat treatment with a separate equipment.

FIG. 3 is a view showing a process of performing a high-temperature heat treatment on the low-temperature deposited IGZO.

The IGZO 210 is deposited on the gate insulating layer 205 at a low temperature as indicated by 310. FIG. The high temperature heat treatment is performed to crystallize the IGZO 210 to form the crystallized IGZO 215 as shown in 315.

FIG. 4 is a view showing a process of performing laser annealing of low-temperature deposited IGZO. The substrate is omitted for convenience of explanation.

The laser 405 is annealed to the IGZO 210 deposited on the gate insulating layer 205 to crystallize the IGZO 210 to form the crystallized IGZO 215 as shown at 415.

Crystallization of IGZO as shown in Figs. 3 and 4 all requires heat treatment. However, in order to heat-treat the low-temperature deposited IGZO, a separate process or separate equipment is required. Accordingly, in one embodiment of the present invention, a process for crystallization through a low-temperature heat treatment and a structure for enabling the crystallization process will be described.

5 is a view showing a process of crystallizing IGZO at a low temperature according to an embodiment of the present invention. The substrate is omitted for convenience of explanation.

The IGZO 210 is deposited on the gate insulating film 205 as shown in FIG. A metal material layer 550 is deposited thereon as shown in 504. Examples of the metal molybdenum include reactivity with IGZO such as Ti, Zr, Hf, Mg, Ca, Sr, V, Nb, Ta, Cr, Mo, W, Mn, Fe, Ni, Co, Ru, Pd, May be a large metal material but is not limited thereto and includes all metal materials which react with IGZO to crystallize IGZO at a low temperature.

After depositing the metal material layer 550, a low temperature heat treatment such as 506 is performed. The temperature at which the low-temperature heat treatment is performed is different from the high temperature of 600 to 700 ° C in FIG. 3 and FIG. 4, and may be 350 ° C or less in one embodiment, but is not limited thereto. IGZO is crystallized as shown in the low temperature heat treatment 520 of FIG. A thin film transistor can be formed using the crystallized IGZO 520 as an activation layer after removing the upper metal material layer 550. [

As a result of performing the process of FIG. 5, the thin film of the IGZO activation layer may include an element of a diffusion metal material layer.

The process shown in FIG. 5 can be applied to various oxide semiconductor structures.

 Hereinafter, an embodiment will be described in accordance with the type of each oxide semiconductor.

6 illustrates a process of crystallizing an oxide semiconductor at a low temperature and a structure of a TFT in a top gate type coplanar structure according to another embodiment of the present invention. 601, a metal material layer 650 is deposited on the IGZO 210 deposited at a low temperature as shown at 603, and a low temperature heat treatment such as 605 is performed. As a result of the low temperature heat treatment, the amorphous IGZO (210) of 603 crystallizes like 620. In this process, the thin film of the crystallized IGZO 620 may include an element of the metal material layer 650. After the metal material layer 650 is removed as in 607, a gate insulating layer 615 and a gate 617 are formed on the crystallized IGZO layer 620 and an interlayer dielectric layer (ILD) 619 is formed on the crystallized IGZO layer 620 Source / drain electrodes 672 and 674 are formed which are in contact with the IGZO 620 through the contact hole 691. [ It is possible to additionally conduct a process of conducting the region to be contacted by the source / drain electrodes 672 and 674 in the crystallized IGZO 620 although not shown in FIG.

7 illustrates a process of crystallizing an oxide semiconductor at a low temperature and a structure of a TFT in a staggered structure of a top gate type according to another embodiment of the present invention. The IGZO 210 is low-temperature deposited on the source / drain electrodes 772 and 774 as shown in 701. [ After the metal material layer 750 is deposited on the IGZO 210 as shown at 703, a low temperature heat treatment such as 705 is performed. As a result of the low temperature heat treatment, the amorphous IGZO (210) of 703 crystallizes like 720. In this process, the thin film of the crystallized IGZO 720 may include an element of the metal material layer 750. After the metal material layer 750 is removed as in 707, a gate insulating film 715 and a gate 717 are formed on the crystallized IGZO 720 as shown in 709.

FIG. 8 illustrates a process of crystallizing an oxide semiconductor at a low temperature and a structure of a TFT in an ESL structure of a bottom gate-scrambler method according to another embodiment of the present invention. After the metal material layer 850 is deposited on the low-temperature deposited IGZO 210 as shown in 801, the low-temperature heat treatment is performed as shown in 805. As a result of the low temperature heat treatment, the amorphous IGZO (210) of 803 crystallizes like 820. In this process, the thin film of the crystallized IGZO 820 may contain an element of the metal material layer 850. After the metal material layer 850 is removed as in 807, an etch stopper layer 880 is formed on the crystallized IGZO 820 as shown in 809, and source / drain electrodes 872 and 874 are formed thereon. A contact hole 891 is formed in the etch stopper layer 880 so that the source / drain electrodes 872 and 874 can contact the IGZO 820, which is an oxide semiconductor, through the contact hole. The ohmic contact layer of FIG. 10 to be described later can also be formed on the contact hole of FIG.

FIG. 9 illustrates a process of crystallizing an oxide semiconductor at a low temperature and a structure of a TFT in a BCL structure of a bottom gate-scrambled method according to another embodiment of the present invention. After the metal material layer 950 is deposited on the low-temperature deposited IGZO 210 as shown in 901, the low-temperature heat treatment is performed as shown in 905. As a result of the low temperature heat treatment, the amorphous IGZO (210) of 903 crystallizes like 920. In this process, the thin film of the crystallized IGZO 920 may include an element of the metal material layer 950. Then, after the metal material layer 950 is removed as in 907, source / drain electrodes 972 and 974 are formed on the crystallized IGZO 920 as shown in 909.

FIG. 10 shows an embodiment in which a metal material layer is not completely removed by a process and structure in which an oxide semiconductor is crystallized at a low temperature in a coplanar structure according to another embodiment of the present invention. The process results of 601 to 605 are the same as those of Fig. 605, the metal material layer 650 is not removed completely but is removed by removing the metal material layer in a region where the source electrode and the drain electrode are in contact with each other. As a result, 650a and 650b are left, and these become ohmic contact layers. The source electrode 672 and the drain electrode 674 contact the oxide semiconductor 620 through the ohmic contact layers 600a and 600b as shown in FIG. As a result, it is possible to omit the step of separately making the portion of the oxide semiconductor in contact with the source electrode 672 and the drain electrode 674 into a conductor.

As shown in FIG. 10, leaving some of the metal material layers as the ohmic contact layer can be applied to other oxide semiconductors other than the coplanar structure of FIG. For example, the ohmic contact layer can be formed without removing the metal material layer in the region corresponding to the contact hole 891 in FIG. 8, and also in the region where the source / drain electrodes 972 and 974 contact with each other The ohmic contact layer can be formed without removing the metal material as it is.

A display device including an oxide semiconductor to which the processes shown in FIGS. 5 to 10 are applied will be described below.

A display area (110 in FIG. 1) of the display device is provided with a data line (wiring extending in 120 in FIG. 1) which is located in the first direction on the substrate and transmits a data signal, In a thin film transistor including a gate line (wiring extending from 130 in FIG. 1) for transmitting a signal, and located in each pixel defined by intersecting gate lines and data lines, the thin film transistor includes the structures shown in FIGS. 5 to 10 . That is, the thin film transistor includes a low-temperature crystallized oxide semiconductor containing atoms of a metal material in a thin film, a source electrode and a drain electrode in contact with the oxide semiconductor, and a gate insulating layer and a gate insulating layer And has a structure including a gate located on one side surface.

The metal material may be one of Ti, Zr, Hf, Mg, Ca, Sr, V, Nb, Ta, Cr, Mo, W, Mn, Fe, Ni, Co, Ru, Pd, Pt, , And a material constituting a gate, a source electrode, or a drain electrode. For example, if the source or drain electrode is comprised of a Mo / Ti (molybdenum / titanium) alloy, the metal material may be titanium. Here, the metal material may be a material highly reactive with the oxide semiconductor, and as a result, the oxide semiconductor may be crystallized at 350 DEG C or less.

When the metal material layer is thinly deposited, it is not necessary to remove a separate metal material layer. Further, instead of the metal material layer, a metal oxide material layer capable of reacting with IGZO may be laminated to allow the oxide semiconductor to be crystallized at a low temperature.

As the oxide semiconductor to which the embodiment of the present invention can be applied, the semiconductor layer may include at least one of zinc oxide (ZnO) semiconductor, indium zinc oxide (IZO) semiconductor, indium aluminum zinc oxide (IAZO) Gallium zinc oxide (IGZO) semiconductor, or indium tin zinc oxide (ITZO) semiconductor. Although the case of IGZO has been described above, the present invention is not limited thereto. But is not limited to.

In the thin film transistor of the coplanar structure shown in FIG. 6, a gate insulating film, a gate and an interlayer insulating film are stacked on the oxide semiconductor, and the source electrode and the drain electrode are in contact with the oxide semiconductor through the contact hole of the interlayer insulating film. The contact hole of the interlayer insulating film means a contact hole like 691 in Fig. 10, the metal material may form the ohmic contact layers 650a and 650b at the interface between the oxide semiconductor and the source electrode or the drain electrode.

7, the oxide semiconductor is partially overlapped with the source electrode and the drain electrode, and is positioned on the source and drain electrodes, and the gate insulating film and the gate are stacked on the oxide semiconductor in opposition to the source and drain electrodes .

In the ESL structure shown in FIG. 8, an etch stopper layer is formed on the oxide semiconductor so that a part of the oxide semiconductor is exposed, and the source electrode and the drain electrode are in contact with the exposed region. An example of forming the ohmic contact layer in the metal material in the exposed region has been described above.

In the bottom gate BCE structure of FIG. 9, the oxide semiconductor is located on the gate insulating film, and the gate insulating film is located on the gate. Similarly, in FIG. 9, only a part of the metal material layer is removed, and the ohmic contact layer can be formed by holding the metal material layer in a region where the source electrode and the drain electrode are in contact with each other.

In the present invention, at least one alloy material including Cu, Al, Au, Ag, Ti, Mo, W, Ta and alloys thereof may be used as the wiring material constituting the gate line, the data line, the source electrode and the drain electrode. Other materials that can be used include Ca, Mg, Zn, Mn, Ti, Mo, Ni, Nd, Zr, Cd, Au, Ag, Co, Fe, Rh, In, Ta, Hf, However, the present invention is not limited thereto.

11 is a view illustrating a process of depositing a metal material layer according to an embodiment of the present invention to crystallize an oxide semiconductor at a low temperature.

A substrate is prepared (S1110). Then, an oxide semiconductor is formed on the substrate (S1120). Then, a metal material layer is coated on the oxide semiconductor (S1130), and heat treatment is performed (S1140). After the heat treatment step, the metal material layer on the crystallized oxide semiconductor is removed (S1150). The heat treatment step may be a step of heat-treating at 350 ° C or less, because low-temperature crystallization is possible due to a metal material highly reactive with the oxide semiconductor. The metal material may be a metal material which is the same as or a constituent element of the conductive material made of the conductive material or the alloy constituting the source electrode or the drain electrode.

As described above, all of the metal material layers may be removed or a portion of the metal material layer may be removed to form the ohmic contact layer according to the structure of the thin film transistor including the oxide semiconductor.

In the case of a coplanar structure, a more detailed examination of the process can form a buffer layer on a substrate. Then, after removing the metal material layer, an interlayer insulating film having a gate insulating film, a gate, and a contact hole is formed on the oxide semiconductor, and a source electrode and a drain electrode which are in contact with the oxide semiconductor through the contact hole can be formed. And removing the metal material layer (S1150) includes removing the metal material layer from the contact surface between the oxide semiconductor and the source electrode or the drain electrode, leaving the metal material in the ohmic contact layer.

7, a buffer layer may be formed on a substrate before forming an oxide semiconductor, and a source electrode and a drain electrode may be formed on the buffer layer. After the metal material layer is removed, a gate insulating film can be formed on the source electrode, the drain electrode, and the oxide semiconductor, and a gate can be formed on the gate insulating film.

After removing the metal material layer in the ESL structure of FIG. 8, an etch stopper layer may be formed on the oxide semiconductor to expose a part of the oxide semiconductor, and the source electrode and the drain electrode may be formed in contact with the oxide semiconductor in the exposed region. Of course, in this process, only a part of the metal material layer can be removed for the ohmic contact layer.

In the bottom gate BCE structure of FIG. 9, a gate may be formed before forming the oxide semiconductor, a gate insulating film may be formed on the gate, and an oxide semiconductor may be formed thereon.

When an embodiment of the present invention is applied, crystallization of amorphous IGZO in an oxide TFT is performed at a low temperature without any heat treatment at a high temperature and without a separate crystallization equipment. . A process for depositing a thin film of IGZO series as an activation layer, a process for depositing a gold material layer (for example, a metal material layer such as Ti) on the thin film, a process for annealing the thin film deposited for IGZO crystallization at 350 ° C Etching the entire or a part of the metal material layer after the heat treatment, and applying the crystallized IGZO to the TFT as an activation layer by patterning.

Although not shown in FIG. 11, a process of forming an oxide semiconductor layer for an oxide semiconductor, forming a low temperature crystallization layer, and then etching the oxide semiconductor layer to form an activation layer may be added.

Embodiments of the present invention include an etch stopper layer (ESL) structure and a coplanar structure of an inverse staggered type, and the present invention is applicable to both the ESL structure and the coplanar structure In addition, it is applicable to all semiconductors which crystallize and activate amorphous oxides.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. , Separation, substitution, and alteration of the invention will be apparent to those skilled in the art. Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents thereof should be construed as falling within the scope of the present invention.

100: display device 110: display panel
120: first driving part 130: second driving part
140: timing controller 200: substrate
210: Amorphous IGZO 202: Gate
205: gate insulating films 650a and 650b: ohmic contact layer
520, 620, 720, 820, 920: Crystallized IGZO
550, 650, 750, 850, 950: metal material layer

Claims (13)

A data line positioned on a substrate in a first direction and transmitting a data signal;
A gate line positioned on the substrate in a second direction and transmitting a gate signal; And
And a thin film transistor located at each pixel defined by intersecting the gate line and the data line,
Wherein the thin film transistor comprises: a crystallized oxide semiconductor containing atoms of a metal material in a thin film;
A source electrode and a drain electrode in contact with the oxide semiconductor;
A gate insulating layer disposed on one side of the oxide semiconductor; And
And a gate located on one side of the gate insulating layer.
The method according to claim 1,
Wherein the metal material is one of Ti, Zr, Hf, Mg, Ca, Sr, V, Nb, Ta, Cr, Mo, W, Mn, Fe, Ni, Co, Ru, Pd, Pt, Cu, .
The method according to claim 1,
Wherein the metal material is at least one of a material constituting the gate, a source electrode or a drain electrode.
The method according to claim 1,
The oxide semiconductor layer may include at least one of zinc oxide (ZnO) semiconductor, indium zinc oxide (IZO) semiconductor, indium aluminum zinc oxide (IZO) semiconductor, indium gallium zinc oxide (IGZO) A semiconductor, or an indium tin zinc oxide (ITZO) semiconductor.
The method according to claim 1,
Wherein the crystallized oxide semiconductor is an oxide semiconductor crystallized at 350 DEG C or lower.
The method according to claim 1,
Wherein a gate insulating film, a gate and an interlayer insulating film are stacked on the oxide semiconductor, and a source electrode and a drain electrode are in contact with the oxide semiconductor through contact holes of the interlayer insulating film.
The method according to claim 6,
Wherein the metal material forms an ohmic contact layer at a contact surface between the oxide semiconductor and the source electrode or the drain electrode.
The method according to claim 1,
Wherein the oxide semiconductor is partially overlapped with the source electrode and the drain electrode and is positioned on the source electrode and the drain electrode and the gate insulating film and the gate are stacked on the oxide semiconductor in opposition to the source electrode and the drain electrode.
The method according to claim 1,
An etch stopper layer is formed on the oxide semiconductor so that a part of the oxide semiconductor is exposed, and the source electrode and the drain electrode contact the exposed region.
Forming an oxide semiconductor on the substrate;
Applying a layer of a metal material on the oxide semiconductor;
Heat treating the metal material layer; And
And removing the metal material layer.
11. The method of claim 10,
Wherein the heat-treating step is a step of heat-treating at 350 DEG C or less.
11. The method of claim 10,
Further comprising forming a buffer layer on the substrate prior to the step of forming the oxide semiconductor,
After the step of removing the metal material layer
Forming an interlayer insulating film having a gate insulating film, a gate, and a contact hole on the oxide semiconductor; And
And forming a source electrode and a drain electrode in contact with the oxide semiconductor through the contact hole.
13. The method of claim 12,
The step of removing the metal material layer
And removing the other metal material layer while leaving the metal material in the ohmic contact layer at a contact surface between the oxide semiconductor and the source electrode or the drain electrode.

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