KR20160001875A - Fringe field switching liquid crystal display device and method of fabricating the same - Google Patents

Abstract

The present invention relates to a fringe field switching (FFS) liquid crystal display device and a manufacturing method thereof. A drain electrode is connected to a pixel electrode by applying a color filter on thin film transistor structure and using a connection pattern to reduce a step, so the drain electrode and the pixel electrode are safely connected. In addition, a process is simplified by forming a connection pattern and a black matrix on an array substrate along with a common electrode by using halftone exposure. Since the black matrix is formed on the array substrate, it is not required to consider an array margin with the array substrate, so a line width can be reduced and an aperture ratio can be improved.

Description

Field of the Invention [0001] The present invention relates to a fringe field type liquid crystal display device and a method of manufacturing the same. BACKGROUND OF THE INVENTION [0002]

The present invention relates to a fringe field type liquid crystal display device and a method of manufacturing the same, and more particularly, to a fringe field type liquid crystal display device using a color filter on thin film transistor structure and a method of manufacturing the same.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, a liquid crystal display device includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix form, and a driving circuit for driving the liquid crystal panel.

In general, a liquid crystal panel has a thin film transistor substrate and a color filter substrate facing each other, a liquid crystal injected between two substrates, and a spacer for maintaining a cell gap between the two substrates.

The thin film transistor substrate and the color filter substrate are bonded to each other to inject and encapsulate the liquid crystal to complete the liquid crystal panel. Alternatively, liquid crystal is formed on one of the two substrates and is then cemented to complete the liquid crystal panel. At this time, the two substrates are aligned so that the color filters of the color filter substrate correspond one-to-one with the pixel electrodes of the thin film transistor substrate. However, if the alignment of the two substrates is not correct, a light leakage defect occurs.

In order to prevent this, there is a method of forming the black matrix width of the color filter substrate to be wide, but this causes a decrease in the aperture ratio.

Accordingly, a color filter on thin film transistor (COT) structure in which a color filter is formed on a thin film transistor substrate has been devised.

1, in a COT type liquid crystal display device in which a color filter and a thin film transistor are simultaneously provided on one substrate, the substrate 10 includes a color filter 50 and a thin film A transistor (TFT) is formed in the pixel region. The pixel region includes a gate line (not shown) and a data line 40 which are perpendicular to each other and define a unit pixel, a thin film transistor formed at an intersection of the two lines, A color filter 50 formed on each of the pixel regions including the thin film transistor, a black matrix 60 made of an opaque organic material for shielding light leakage on the color filter 50 in a portion defining the pixel region, And a first protective layer 70 formed on the black matrix 60 to planarize the surface.

 A common electrode 80 and a pixel electrode 100 are formed in the pixel region with a second protective film 90 interposed therebetween to form a fringe field. And the pixel electrode 100 is formed to have a plurality of slits (not shown).

 The pixel electrode 100 is electrically connected to the drain electrode 45b exposed through the contact hole (not shown) passing through the second protective film 90, the common electrode 80, the first protective film 70 and the color filter 50. [ .

The fringe field type liquid crystal display employing the conventional color filter on thin film transistor structure in which the pixel electrode is formed on the upper part has the second protective film 90 for connection between the pixel electrode 100 and the drain electrode 45b, (Not shown) through the common electrode 80, the first protective film 70, and the color filter 50.

However, in the conventional process for connecting the pixel electrode of the array substrate for the liquid crystal display device to the drain electrode, the contact holes may be deepened due to the step difference, and a residual film may be generated.

Such a conventional problem will be described with reference to FIG.

2 is a view showing a contact failure of the pixel electrode 100 and the drain electrode 45b. 2, due to the deep step of the second protective film 90 formed in the contact hole in the etching process for forming the contact hole (not shown), the second protective film is not completely etched, A problem may occur that contact between the drain electrode 45b and the pixel electrode 200 is not achieved due to the residual film 70a of the second protective film 90. [

 In addition, conventionally, in a fringe field type liquid crystal display device of a COT structure, a black matrix is formed by patterning an opaque organic material that shields the light leakage. However, in order to form a black matrix, a mask process is additionally required, so that the number of processes increases, resulting in a problem that productivity and manufacturing cost are increased.

SUMMARY OF THE INVENTION The present invention provides a fringe field type liquid crystal display device and a method of manufacturing the same that can solve the problem of a residual film caused by a deep step and reduce the number of mask processes.

A fringe field type liquid crystal display device according to the present invention includes: a substrate including a pixel portion; A gate line and a data line crossing the pixel portion of the first substrate to define a pixel region; A thin film transistor formed at a crossing region of the gate line and the data line and including a gate electrode, a semiconductor layer, a source electrode, and a drain electrode; A color filter formed on each pixel region on the substrate on which the thin film transistor is formed; A first contact hole through which a part of the color filter is removed to expose the drain electrode; A first protective film formed on the color filter; A second contact hole through which a part of the first protective film is removed to expose the drain electrode; A common electrode formed on the first protective film and spaced apart from a region where the thin film transistor is formed and formed in a pixel pattern in a single pattern; A connection pattern formed on a region where the thin film transistor is formed ; A second protective layer formed on the common electrode and the connection pattern; A third contact hole through which a part of the second protective film is removed to expose the connection pattern; And a pixel electrode formed on the second passivation layer and electrically connected to the drain electrode through the connection pattern.

A method of manufacturing a fringe field type liquid crystal display device according to the present invention includes: providing a first substrate including a pixel portion; Forming a gate electrode and a gate line made of a first conductive film in a pixel portion of the substrate; Forming a gate insulating film on the first substrate on which the gate electrode and the gate line are formed; Forming a source electrode and a drain electrode including a semiconductor layer and a second conductive film in a pixel portion of the first substrate on which the gate insulating film is formed and forming a data line crossing the gate line and defining a pixel region; Forming a color filter in each pixel region of the first substrate; Forming a first contact hole exposing a part of the drain electrode by selectively removing the color filter; Forming a first protective film on the substrate on which the color filter is formed; Forming a second contact hole exposing a portion of the drain electrode by selectively removing the first protective film; Sequentially forming a third conductive film and a fourth conductive film on the drain electrode exposed by the first protective film and the first and second contact holes; Forming a common electrode by patterning a third conductive film on the pixel region using a half-tone mask on the substrate on which the third conductive film and the fourth conductive film are formed, forming a third conductive film and a fourth conductive film on the thin film transistor region, Forming a connection pattern by patterning the conductive film; Forming a second protective film on the first substrate; Forming a third contact hole exposing a part of the connection pattern by selectively removing the second protective film; And forming a fifth conductive film on the connection pattern exposed through the second protective film and the third contact hole; And forming a pixel electrode by patterning a fifth conductive film in a pixel region of the substrate.

As described above, the fringe field type liquid crystal display device and the method of manufacturing the same according to the present invention provide the effect that the step is lowered when the pixel electrode is electrically connected to the drain electrode, and is stably connected.

A fringe field type liquid crystal display device and a method of manufacturing the same according to the present invention are characterized in that a black matrix (BM) is formed on an array substrate together with a common electrode using halftone exposure to form a single photolithography process The manufacturing cost can be reduced.

1 is a cross-sectional view schematically showing a fringe field type liquid crystal display device in which a conventional color filter is formed on a thin film transistor substrate.
2 is a cross-sectional view showing a conventional residual film problem.
3 is a cross-sectional view of an array substrate of a fringe field type liquid crystal display device according to an embodiment of the present invention.
Fig. 2 is a plan view schematically showing a part thereof.
4 is a cross-sectional view schematically showing a part of an array substrate along the line A1-A2 of the array substrate shown in Fig.
5A to 5G are plan views sequentially showing manufacturing steps along the line A1-A2 of the array substrate shown in FIG.
6A to 6G are cross-sectional views sequentially showing manufacturing steps along the line A1-A2 of the array substrate shown in FIG.

Hereinafter, preferred embodiments of a fringe field type liquid crystal display device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. It should be understood, however, that the invention is not limited to the disclosed embodiments, but is capable of many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, To fully disclose the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification. The dimensions and relative sizes of the layers and regions in the figures may be exaggerated for clarity of illustration.

It will be understood that when an element or layer is referred to as being another element or "on" or "on ", it includes both intervening layers or other elements in the middle, do. On the other hand, when a device is referred to as "directly on" or "directly above ", it does not intervene another device or layer in the middle.

The terms spatially relative, "below," "lower," "above," "upper," and the like, And may be used to easily describe the correlation with other elements or components. Spatially relative terms should be understood to include, in addition to the orientation shown in the drawings, terms that include different orientations of the device during use or operation. For example, when inverting an element shown in the figures, an element described as "below" or "beneath" of another element may be placed "above" another element. Thus, the exemplary term "below" can include both downward and upward directions.

The terminology used herein is for the purpose of describing embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. &Quot; comprise "and / or" comprising ", as used in the specification, means that the presence of stated elements, Or additions.

3 is a plan view schematically showing a part of an array substrate of a fringe field type liquid crystal display device according to an embodiment of the present invention.

4 is a cross-sectional view schematically showing a part of an array substrate along the line A1-A2 of the array substrate shown in Fig.

For reference, in the figure, one pixel constituted by a red (R) sub-color filter is shown as an example for the sake of convenience of explanation. In an actual liquid crystal display device, M gate lines and N data lines cross There are NxM pixels, but one pixel is shown in the figure for the sake of simplicity.

An array substrate 110 according to an embodiment of the present invention includes an array substrate 110, a gate electrode 121, a gate insulating layer 130, a semiconductor layer 141, a source electrode 145a A common electrode 170, a black matrix 180, a connection pattern 185, a second passivation layer 190, and a pixel electrode 200 (not shown), a drain electrode 145b, a color filter 150, a first passivation layer 160, ).

A gate line 120 and a data line 140, which are vertically and horizontally arranged on the array substrate 110, define a pixel region. In addition, a thin film transistor, which is a switching device, is formed in an intersection region of the gate line 120 and the data line 140. In the pixel region, a common electrode 170 for driving liquid crystal molecules by generating a fringe field, The pixel electrode 200 having the slit op of the pixel electrode 200 is formed.

The thin film transistor includes a gate electrode, a semiconductor layer, a source electrode, and a drain electrode.

The gate electrode 121 is formed on the array substrate 110. At this time, the gate electrode 121 may be formed of the same gate metal layer as the gate line 120, and the gate metal layer may be formed of a metal such as molybdenum (Mo), aluminum (Al), chrome (Cr), gold (Au) (Ni), neodymium (Nd), copper (Cu), or an alloy thereof, and may be a single layer of the metal or alloy, or multiple layers of two or more layers.

The gate insulating layer 130 is formed on the gate electrode 121 to insulate the gate electrode 121 from the source electrode 145a and the drain electrode 145b. The gate insulating layer 130 may be formed of an inorganic insulating material such as silicon oxide or silicon nitride

The semiconductor layer 141 is formed on the gate insulating layer 130. A conduction channel is formed between the source electrode 145a and the drain electrode 145b by a gate voltage supplied to the gate electrode 121. [ The semiconductor layer 141 may be formed of a silicon-based semiconductor material or an oxide semiconductor material.

In addition, the source region and the drain region of the semiconductor layer 141 form an ohmic contact with the source and drain electrodes 145a and 145b through the ohmic-contact layer 143, respectively.

The source electrode 145a and the drain electrode 145b are spaced apart from each other on the semiconductor layer 141. The source electrode 145a and the drain electrode 145b may be formed of the same data metal layer as the data line 140. The data metal layer may include at least one of molybdenum (Mo), aluminum (Al), chromium (Cr) ), Titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or alloys thereof. The metal or alloy may be a single layer or a multilayer of two or more layers.

The color filter 150 is formed in a box shape so as to be divided into pixel regions on the array substrate 110 on which the thin film transistors are formed. In this case, the color filter 150 is formed so as to be spaced apart or partially overlapped with the gate line 120 and the data line 140 so as not to overlap with each other, and includes a first contact hole 150a exposing a part of the drain electrode 145b, .

The first passivation layer 160 is formed on the color filter 150. The first passivation layer 160 is formed of an organic insulating material such as PAC to planarize the lower substrate.

The first passivation layer 160 is formed to have a second contact hole 160a exposing a portion of the drain electrode 145b.

The common electrode 170 is formed on the first protective layer 160. The common electrode 170 forms a fringe field together with the pixel electrode 200 with the second protective layer 190 interposed therebetween to adjust the alignment direction of the liquid crystal (not shown).

The common electrode 170 may be formed of indium tin oxide (ITO), indium zinc oxide (IZO), or indium zinc oxide (IZO) ) Having a high transmittance.

The black matrix 180 is formed in a region overlapping with the gate line 120 and the data line 140 in order to distinguish the pixel region and prevent light from leaking into the gate line 120 and the data line 140. [ The black matrix 180 is formed of an opaque metal material on the common electrode.

The black matrix 180 may be formed of indium-tin-oxide (ITO) or indium zinc oxide (IZO) and aluminum (Al) A copper alloy such as copper (Cu) and copper nitride (CuNx), and a molybdenum alloy such as molybdenum (Mo) and molybdenum titanium (MoTi).

The connection pattern 185 is formed of at least two layers in the upper region of the thin film transistor and is formed of an upper connection pattern 180a and a lower connection pattern 170a.

The lower connection pattern 170a is formed of a transparent conductive material having excellent transmittance such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO), and the upper connection pattern 180a Is formed of an opaque conductive material such as a copper alloy such as aluminum (Al), copper (Cu), copper nitride (CuNx), molybdenum alloy such as molybdenum (Mo) and molybdenum titanium (MoTi).

A second passivation layer 190 is formed on the common electrode 170, the black matrix 180, and the connection pattern 185. The second passivation layer 190 may be formed of an inorganic insulating layer such as a silicon nitride layer (SiNx) or a silicon oxide layer (SiO2).

The second passivation layer 190 may have a third contact hole 190a exposing a portion of the connection pattern 185. At this time, the first contact holes, the second contact holes, and the third contact holes are formed on the thin film transistors but are not overlapped with each other.

The pixel electrode 200 is formed in a box shape on the connection pattern 180a through the second protective film 190 and the third contact hole 190a in the pixel region and has a plurality of slits op .

And is formed of a transparent conductive material having excellent transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO).

The lower connection pattern 170a of the connection pattern 185 is in direct contact with the drain electrode through the first contact hole 150a and the second contact hole 160a, 3 contact hole directly through the contact hole. The connection pattern 185 thus formed electrically connects the drain electrode 145b and the pixel electrode 200. [ At this time, the common voltage Vcom is supplied to the common electrode 170, but the common voltage Vcom is not supplied to the connection pattern 185.

The drain electrode 145b exposed through the first contact hole 150a and the second contact hole 160a and the third contact hole 150a formed so as not to overlap with the first contact hole 150a and the second contact hole 160a, The drain electrode 145b and the pixel electrode 200 are connected to each other through the connection pattern 185 because the pixel electrode 200 is not directly contacted through the contact hole 190a but is connected through the connection pattern 185. [ The color filter is formed on the lower substrate to solve the problem of the bottom residual film which can not be etched in one process when the contact hole is deep.

Hereinafter, a method of fabricating an array substrate of a fringe field type liquid crystal display device constructed as above will be described in detail with reference to the drawings.

5A to 5G are plan views sequentially illustrating the manufacturing steps of the array substrate shown in FIG.

6A to 6G are cross-sectional views sequentially showing manufacturing steps along line A1-A2 of the array substrate shown in FIG. 3

As shown in FIGS. 5A and 6A, a gate electrode 121 and a gate line 120 are formed in a pixel portion of an array substrate 110 made of a transparent insulating material such as glass.

 At this time, the gate electrode 121 and the gate line 120 are formed by selectively depositing a first conductive film on the entire surface of the array substrate 110 and then performing a photolithography process (a first mask process).

Here, the first conductive layer may be formed of aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), chromium (Cr), molybdenum A low resistance opaque conductive material such as a molybdenum alloy can be used. The first conductive layer may have a multi-layer structure in which two or more low resistance conductive materials are stacked.

5B and 6B, a gate insulating layer 130, an amorphous silicon thin film, an n + amorphous silicon thin film, and an amorphous silicon thin film are formed on the entire surface of the array substrate 110 on which the gate electrode 121 and the gate line 120 are formed. Thereby forming a second conductive film.

The second conductive layer may be formed of a low-resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum, and molybdenum alloy to form a source electrode, a drain electrode, and a data line. The second conductive layer may have a multi-layer structure in which two or more low resistance conductive materials are stacked.

Thereafter, the amorphous silicon thin film, the n + amorphous silicon thin film, and the second conductive film are selectively removed through a photolithography process (second mask process) to form a semiconductor layer of the amorphous silicon thin film on the pixel portion of the array substrate 110 And a source electrode 145a and a drain electrode 145b are formed on the semiconductor layer 141. The source electrode 145a and the drain electrode 145b are formed of the second conductive layer.

At this time, a data line 140 made of the second conductive film is formed in the data line region of the array substrate 110 through the second mask process.

At this time, the n + amorphous silicon thin film is formed on the semiconductor layer 141 and ohmic contact is made between the source / drain region of the semiconductor layer 141 and the source / drain electrodes 145a and 145b The ohmic contact layer 143 is formed.

A first amorphous silicon thin film pattern formed of the amorphous silicon thin film and the n + amorphous silicon thin film and patterned in substantially the same pattern as the data line 140 is formed under the data line 140, Respectively.

Here, the semiconductor layer 141, the source electrode 145a, the drain electrode 145b and the data line 140 according to the embodiment of the present invention may be formed by a single mask process (a second mask process ) At the same time. However, the present invention is not limited thereto, and the semiconductor layer 141, the source electrode 145a, the drain electrode 145b, and the data line 140 may be formed through two mask processes.

Next, as shown in FIGS. 5C and 6C, on the entire surface of the array substrate 110 on which the semiconductor layer 141, the source electrode 145a, the drain electrode 145b and the data line 140 are formed, (R), green (G), and blue (B) colors are applied to each pixel region by applying a color resist, irradiating light using a mask (third to fifth mask processes) The color filter 150 is formed.

At this time, each of the color filters overlaps with a part of the gate line 120 and a part of the data line 140, and is formed so as to be spaced apart or partially overlapped with each color filter, and to expose a part of the drain electrode 145b And is formed to have the first contact hole 150a.

Next, as shown in FIGS. 5D and 6D, a first protective layer 160 is formed on the entire surface of the array substrate 110 on which the color filter 150 is formed.

At this time, the first passivation layer 160 may be formed of an organic insulating material such as photoacid (PAC).

Thereafter, the first protective film 160 is selectively removed through a photolithography process (a sixth mask process) to form a second contact hole 160a exposing a part of the drain electrode 145a.

5E and 6E, a third conductive film and a fourth conductive film are sequentially formed on the entire surface of the array substrate 110 on which the first protective film 160 is formed.

The third conductive layer may be a transparent conductive material having a high transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO) to form a common electrode and a connection pattern. Lt; / RTI >

The fourth conductive layer may be a black matrix, a copper alloy such as aluminum (Al), copper (Cu), copper nitride (CuNx), or the like having good low reflection effect when used as a double layer with ITO or IZO to form a connection pattern. And an opaque conductive material such as a molybdenum alloy such as molybdenum (Mo) and molybdenum titanium (MoTi).

Thereafter, the third conductive film and the fourth conductive film are selectively removed through a photolithography process (seventh mask process) to form a common electrode 170 made of the third conductive film in the pixel region of the array substrate 110 .

Further, a lower connection pattern 170a made of the third conductive film and an upper connection pattern 180a made of the fourth conductive film are formed in the upper region of the thin film transistor, and the lower connection pattern 170a and the upper connection pattern 170a, (180a) are patterned in the same shape to form a connection pattern (185).

At this time, a black matrix 180 made of a fourth conductive film is formed on the common electrode in the gate line and the data line region of the array substrate 110 through the seventh mask process.

 Here, the common electrode 170, the connection pattern 185, and the black matrix 180 according to the embodiment of the present invention may be simultaneously formed through a single mask process (seventh mask process) by using a half-tone mask . However, the present invention is not limited thereto, and the common electrode 170, the connection pattern 185, and the black matrix 180 may be formed through two mask processes.

The gate lines 120 and the data lines 140 may be formed in the thin film transistors and the gate lines 120 and the data lines 140 in order to prevent light from leaking into the thin film transistors and the gate lines 120 and the data lines 140. [ A black matrix 180 is formed of an opaque metal material on the common electrode 170 in the region where the black matrix 180 is formed on the array substrate 110 together with the common electrode 170 using halftone exposure. By forming the matrix 180, one photolithography step can be omitted.

In addition, since the black matrix 180 is formed on the lower array substrate 110, it is not necessary to consider the alignment margin with respect to the array substrate 110, so that the line width can be reduced and the aperture ratio can be improved.

Next, as shown in FIGS. 5F and 6F, a silicon nitride film (SiNx) or a silicon oxide film (silicon nitride film) is formed on the entire surface of the array substrate 110 on which the common electrode 170, the connection pattern 185, A second protective film 190 is formed to planarize the array substrate with an inorganic insulating material such as SiO2.

Thereafter, the second protective film 190 is selectively removed through a photolithography process (eighth mask process), thereby forming a third contact hole 190a exposing a part of the connection pattern 185.

At this time, the third contact hole 190a is formed on the thin film transistor, but it is formed so as not to overlap with the first contact hole 150a and the second contact hole 160a.

Next, as shown in FIGS. 5G and 6G, a fifth conductive film made of a transparent conductive material is formed on the entire surface of the array substrate 110 on which the second protective film 190 is formed, and then a photolithography process The pixel electrode 200 having a plurality of slits op in the pixel region of the array substrate 110 is formed.

At this time, the pixel electrode 200 is formed also in the third contact hole 190a in the second passivation layer 190. [ The drain electrode 145b and the pixel electrode 200 are electrically connected through the connection pattern 185. [

Although not shown, the array substrate 110 according to the embodiment of the present invention includes a counter substrate (not shown) formed by a sealant (not shown) formed on the periphery of an image display area in a state where a certain cell gap is maintained by a column spacer And a liquid crystal layer is formed therebetween to form a fringe field type liquid crystal display device according to an embodiment of the present invention.

The fringe field type liquid crystal display device of the present invention has been described above with respect to the bottom gate structure in which the gate electrode 121 is formed under the semiconductor layer 141. However, The present invention includes a top gate structure in which the gate electrode 121 is formed on the semiconductor layer 141. In this case,

While a great many are described in the foregoing description, it should be construed as an example of preferred embodiments rather than limiting the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

110: array substrate
120: gate line 121: gate electrode
140: Data line 141: Active layer
145a: source electrode 145b: drain electrode
150: color filter 160: first protective film
170: common electrode 180: black matrix
185: Connection pattern
170a: Lower connection pattern 180a: Upper connection pattern
190: second protective film 200: pixel electrode
150a: first contact hole 160a: second contact hole
190a: Third contact hole

Claims (12)

A liquid crystal display comprising: a substrate including a pixel portion;
A gate line and a data line crossing the pixel portion of the first substrate to define a pixel region;
A thin film transistor formed at a crossing region of the gate line and the data line and including a gate electrode, a semiconductor layer, a source electrode, and a drain electrode;
A color filter formed on each pixel region on the substrate on which the thin film transistor is formed;
A first contact hole through which a part of the color filter is removed to expose the drain electrode;
A first protective film formed on the color filter;
A second contact hole through which a part of the first protective film is removed to expose the drain electrode;
A common electrode formed on the first protective film and spaced apart from a region where the thin film transistor is formed and formed in a pixel pattern in a single pattern;
A connection pattern formed on a region where the thin film transistor is formed ;
A second protective layer formed on the common electrode and the connection pattern;
A third contact hole through which a part of the second protective film is removed to expose the connection pattern;
And a pixel electrode formed on the second passivation layer and electrically connected to the drain electrode through the connection pattern. The method according to claim 1,
Wherein the third contact hole is formed so as not to overlap the first contact hole or the second contact hole. The method according to claim 1,
Wherein the connection pattern comprises a double layer of a lower connection pattern and an upper connection pattern. The method of claim 3,
Wherein the lower connection pattern is in contact with the drain electrode through the first contact hole and the second contact hole and the upper connection pattern is in contact with the pixel electrode through the third contact hole. . The method as claimed in claim 3, wherein the lower connection pattern is formed of a transparent conductive material of indium tin oxide (ITO) or indium zinc oxide (IZO) Display device. The method of claim 3,
Wherein the upper connection pattern is made of an opaque conductive material of aluminum (Al), copper (Cu), copper (CuNx) alloy, molybdenum (Mo), or molybdenum titanium (MoTi) . The method according to claim 1,
Further comprising a black matrix in a region where a gate line and a data line are formed on the first passivation layer. Providing a first substrate comprising a pixel portion;
Forming a gate electrode and a gate line made of a first conductive film in a pixel portion of the substrate;
Forming a gate insulating film on the first substrate on which the gate electrode and the gate line are formed;
Forming a source electrode and a drain electrode including a semiconductor layer and a second conductive film in a pixel portion of the first substrate on which the gate insulating film is formed and forming a data line crossing the gate line and defining a pixel region;
Forming a color filter in each pixel region of the first substrate;
Forming a first contact hole exposing a part of the drain electrode by selectively removing the color filter;
Forming a first protective film on the substrate on which the color filter is formed;
Forming a second contact hole exposing a portion of the drain electrode by selectively removing the first protective film;
Sequentially forming a third conductive film and a fourth conductive film on the drain electrode exposed by the first protective film and the first and second contact holes;
Forming a common electrode by patterning a third conductive film in the pixel region using a half-tone mask on the substrate on which the third conductive film and the fourth conductive film are formed, and forming a third conductive film and a fourth conductive film Forming a connection pattern by patterning the conductive film;
Forming a second protective film on the first substrate;
Forming a third contact hole exposing a part of the connection pattern by selectively removing the second protective film; And
Forming a fifth conductive film on the connection pattern exposed through the second protective film and the third contact hole;
And forming a pixel electrode by patterning a fifth conductive film in a pixel region of the substrate. 9. The method of claim 8,
Wherein the first connection pattern and the second connection pattern are patterned in the same manner when the connection pattern is formed, thereby forming a double layer of an upper connection pattern and a lower connection pattern. 10. The method of claim 9,
Wherein the third conductive layer is formed of a transparent conductive material of Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). . 10. The method of claim 9,
Wherein the fourth conductive film is formed of an opaque conductive material of aluminum (Al), copper (Cu), copper nitride (CuNx) alloy, molybdenum (Mo), or molybdenum titanium (MoTi) ≪ / RTI > 9. The method of claim 8,
Wherein a black matrix is further formed in a region where the gate line and the data line are formed when forming the common electrode and the connection pattern on the first protective film.

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