KR20160000676A - Method of sample and hold of feedback voltage - Google Patents

Method of sample and hold of feedback voltage Download PDF

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Publication number
KR20160000676A
KR20160000676A KR1020140078115A KR20140078115A KR20160000676A KR 20160000676 A KR20160000676 A KR 20160000676A KR 1020140078115 A KR1020140078115 A KR 1020140078115A KR 20140078115 A KR20140078115 A KR 20140078115A KR 20160000676 A KR20160000676 A KR 20160000676A
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South Korea
Prior art keywords
time
voltage
primary side
hold
sample
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KR1020140078115A
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Korean (ko)
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이경호
김기현
김형우
서길수
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한국전기연구원
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Publication of KR20160000676A publication Critical patent/KR20160000676A/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The present invention relates to a feedback voltage sample and hold method. The present invention is to sample and hold a feedback voltage by using a simple method without using a complex algorithm or circuit. According to an embodiment of the present invention, the feedback voltage sample and hold method using a transistor connected to a primary side of a primary side regulation (PSR) fly-back converter and an auxiliary winding on the primary side comprises the following steps of: receiving a gate-on signal for conducting the transistor; generating a sampling clock having a pulse for sampling during a preset second time interval from a time after a preset first time interval in the gate-on signal; and sensing and maintaining a voltage level of voltage (Vfb) obtained by the primary side auxiliary winding by using the sampling clock. Accordingly, the feedback voltage may be simply sampled and held without using the complex algorithm or circuit, and a sample-and-hold time may be controlled according to parameters of external components, so an accurate output voltage may be fed back using in easy method.

Description

METHOD OF SAMPLE AND HOLD OF FEEDBACK VOLTAGE BACKGROUND OF THE INVENTION [0001]

The present invention relates to a feedback voltage sample and hold method and more particularly to a method of sampling and holding a feedback voltage in a control IC of a primary side regulation (PSR) flyback converter.

A typical flyback AC-DC converter system uses a transformer having an insulation structure of primary and secondary windings. When the secondary side output voltage is accurately sensed while the primary side and the secondary side are insulated, the primary side control circuit switches the switching element so that the secondary side voltage can be maintained.

At this time, since the primary side and the secondary side are insulated through the windings, the grounds of the primary and secondary sides are separated and the primary side circuit can not be driven immediately by sensing the voltage of the secondary side. To this end, a reference voltage circuit for maintaining the secondary voltage constant and an optocoupler for feedback to the primary are used. The secondary side voltage can be controlled / maintained more precisely according to the accuracy of the secondary side reference voltage circuit. However, a complicated circuit formed of two or more semiconductors and a large number of resistors, capacitors, etc. is required for this purpose.

However, it is difficult to use the SSR (Secondary Side Regulation) circuit of the conventional type in a charger / adapter or a small LED driver circuit which requires a small-sized system specification. For this purpose, if the secondary side voltage is known even if many elements or circuits for secondary voltage sensing and feedback are removed, the system can be reduced in size and weight, and the power consumption, especially standby power, can be reduced do. In fact, the PSR system applied to the charger / adapter shows a reduction of about 20 points or more compared to the conventional SSR system. However, the PSR method is often used for small chargers and adapters because it is difficult to precisely maintain and manage the secondary output voltage compared to the conventional SSR.

PSR system is widely used for small size and small adapters because of its size and low cost, but there is a limitation in accurately detecting the secondary voltage compared to the conventional SSR method. This can be a fundamental problem that arises from the way in which the secondary voltage is derived from the primary voltage rather than directly sensing the secondary voltage. The primary side auxiliary winding voltage is represented by the addition of the secondary side output voltage (V O ) and the diode voltage (V F ). When the gate is turned off and energy is transferred to the secondary side, the diode current I D begins to flow. At the time when the diode current decreases to '0', that is, at the end of the inductor current discharge time (t DIS ), V F becomes '0', and the primary auxiliary winding voltage becomes V O. After t DIS, since the primary side auxiliary winding voltage oscillates, the error of V O becomes large. It is therefore important to sense the primary side auxiliary winding voltage exactly at the end of t DIS .

However, it is not easy to detect and maintain the primary-side auxiliary winding voltage precisely because sudden fluctuations occur in the auxiliary winding voltage at the end of t DIS

According to the related art, sampling and holding are performed by detecting the polling edge of the primary side auxiliary winding voltage. However, when the primary side auxiliary winding voltage is used, the sampling signal is generated, It is necessary to provide a delay circuit for delaying and outputting the primary side auxiliary winding voltage, or a complicated algorithm must be added.

KR 10-0894378 B1 KR 10-0889076 B1

SUMMARY OF THE INVENTION An object of the present invention is to provide a feedback voltage sample and hold method capable of simply sampling and holding a feedback voltage without using a complicated algorithm or circuit.

The above object is achieved by a feedback voltage sample and hold method using a transistor connected to a primary side of a PSR (Primary Side Regulation) flyback converter and a primary side auxiliary winding according to an embodiment of the present invention, Receiving a GateOn signal; Generating a sampling clock having a pulse for sampling for a predetermined second time interval from a time after a predetermined first time interval in the gate-on signal; And sensing and maintaining a voltage level of a voltage (Vfb) obtained in the primary side auxiliary winding using the sampling clock.

The step of generating the sampling clock includes the steps of: detecting a time at which a falling edge of the gate-on signal is generated; obtaining a time delayed by the first time at a time point when the polling edge is generated; And generating a sampling clock during the second time interval from the time delayed by the first time.

The set values of the first time and the second time may be adjusted by an external signal.

In addition, the set values of the first time and the second time may be adjusted to match the inductor current discharge time (tDIS) determined according to the flyback converter component parameters.

According to the feedback voltage sample and hold method of the present invention, the feedback voltage can be easily sampled and held without using a complicated algorithm or circuit, and it is possible to sample and hold the feedback voltage according to parameters of external components. The time can be adjusted so that the accurate output voltage can be fed back in an easy way.

1 is a circuit diagram showing an example of a PSR type power supply device,
FIG. 2 is a graph showing a voltage waveform in the auxiliary winding of FIG. 1,
3 is a flowchart illustrating a feedback voltage sample and hold method according to an embodiment of the present invention,
4 is a circuit diagram illustrating a method of sampling and holding a secondary winding voltage by applying a method according to an embodiment of the present invention,
5 is a graph showing a simulation result waveform in Fig.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Brief Description of Drawings FIG. 1 is a block diagram of a computer system according to an embodiment of the present invention; FIG. 2 is a block diagram of a computer system according to an embodiment of the present invention; FIG.

Before describing the present invention in detail, a method of indirectly sensing an output voltage will be described with reference to FIGS. 1 and 2. FIG.

In Fig. 1, the control IC turns the MOSFET on and off so that a desired output voltage is obtained. To this end, the auxiliary winding voltage is divided by the resistance divider to receive the feedback voltage Vfb, and the output voltage V O is indirectly sensed. V O voltage must be accurately sensed to ensure smooth control. As shown in FIG. 2, the auxiliary winding voltage Vfb is V O And V f, which is the secondary diode voltage. Here, in order to accurately sense V O , Vfb should be sensed at the time (t DIS ) at which the secondary side diode current is completely discharged. To this end, in the present invention, V O is indirectly sensed from the V fb value at a time point when the gate off signal is delayed by a specific time. Since the secondary side diode current starts to discharge from the gate off signal, it is possible to adjust to match t DIS if the gate off signal is delayed by a certain time.

A feedback voltage sample and hold method according to an embodiment of the present invention uses a transistor connected to a primary side of a PSR (Primary Side Regulation) flyback converter and a primary side auxiliary winding. As shown in FIG. 3, (S100) for receiving a gate-on signal for conducting a gate-on signal, a sampling clock (Sampling) signal having a pulse for sampling for a predetermined second time interval from a time after a predetermined first time interval in the gate- (S500) of sampling and holding a voltage level of a voltage (Vfb) obtained in the primary side auxiliary winding using the sampling clock (S500).

Here, the step S300 of generating the sampling clock may include detecting a time at which a falling edge of the gate-on signal is generated (S310), determining a time at which the falling edge of the gate- (S330), and generating a sampling clock during the second time interval from the time delayed by the first time (S350).

The set value of the first time and the second time may be controlled by an external signal, and any element may be used as long as it can adjust the amount of current determined by the external voltage and the delay time such as a capacitor.

In addition, the set values of the first time and the second time may be adjusted to match an inductor current discharge time (t DIS ) determined according to the flyback converter component parameter.

According to the circuit diagram and the simulation result waveform illustrated in FIGS. 4 and 5, when the sampling clock is high, the voltage level is sampled according to the embodiment of the present invention. If the sampling clock is low And holds the voltage level. That is, if the holding time is equal to t DIS , the Vfb value of the sample and hold becomes V O. Here, t DIS can be calculated when the transformer, frequency, and load used in the power supply are determined. If the load fluctuation is small and the V f value is small, the error for V O is not large unless the sample and hold time exceeds t DIS . Therefore, when the transformer, the frequency, and the like are determined according to the present invention, the sample and hold time can be determined through ADJ_ST and ADJ_SW shown in the circuit diagram of FIG. The ADJ_ST determines the delay time from the gate off signal to the start of sampling according to the voltage, and ADJ_SW determines the pulse width of the sampling clock. That is, the ADJ_ST determines the first time, and the ADJ_SW determines the second time, which is the pulse width of the sampling clock.

Hereinafter, the feedback voltage sample and hold apparatus according to the above-described embodiment will be described in detail with reference to the circuit diagram of FIG.

The feedback voltage sample and hold apparatus 10 includes a sampling clock generating unit 100 and a sample and hold unit 200 as shown in FIG.

The sampling clock generating unit 100 receives a gate-on signal and generates a sampling clock signal for sampling at a predetermined second time interval from a time point after a predetermined first time interval at the time when the polling edge of the gate- And generates a sampling clock having a pulse.

The sampling clock generating unit 100 includes a first delay unit 110, a second delay unit 120, and an output unit 130.

The first delay unit 110 is connected to the first current source 111 whose amount of current can be changed according to the external voltage ADJ_ST so that the first delay unit 110 charges or charges the first capacitor C1 according to a gate- And a first transistor 113 for discharging.

One end of the first capacitor C1 may be grounded and the other end may be connected to the first transistor 113. [

Here, the first current source 111 regulates the amount of the output current according to the external voltage ADJ_ST. In this case, the first current source 111 may include a current mirror having an input terminal for receiving the external voltage ADJ_ST, and the current value of the current output from the current mirror may be a voltage value of the external voltage ADJ_ST Can be changed accordingly. The first delay unit 110 may be configured such that the output current output from the first current source 111 charges the first capacitor C1 according to the operation of the first transistor 113. [

The second delay unit 120 is connected to the second current source 121 whose amount of current can be changed according to the external voltage ADJ_SW and is connected to the second capacitor C2 based on the output of the first delay unit 110, And a second transistor 123 for charging or discharging the second transistor 123. One terminal of the second capacitor C2 may be grounded, and the other terminal may be connected to the second transistor 123. [

In this case, the second current source 121 may include a current mirror having an input terminal for receiving the external voltage ADJ_SW, and the current value of the current output from the current mirror may be a voltage value of the external voltage ADJ_SW Can be changed accordingly. The second delay unit 120 may be configured such that the output current output from the second current source 121 charges the second capacitor C2 according to the operation of the second transistor 123. [

The output unit 130 generates and outputs a sampling clock based on the output of the first delay unit 110 and the output of the second delay unit 120.

The sample and hold unit 200 receives the primary side auxiliary winding voltage Vfb of the PSR flyback converter and the sampling clock generated by the sampling clock generation unit 100, And detects and maintains the voltage level of the winding voltage (Vfb).

In the feedback voltage sample and hold apparatus 10 according to the above-described configuration, as the voltage level of the external voltage ADJ_ST increases or decreases, the value of the output current outputted from the first current source 111, which is a current mirror, It becomes larger or smaller. The first capacitor C1 is charged by receiving the current from the first current source 111. Therefore, when the voltage level of the external voltage ADJ_ST increases, the first capacitor C1 can be charged relatively quickly, When the voltage level of the external voltage ADJ_ST becomes small, the first capacitor C1 can be charged relatively slowly.

The output of the first delay unit 110 is delayed compared with the input of the gate ON signal by reflecting the charging time of the first capacitor C1 and therefore the voltage level of the external voltage ADJ_ST or the voltage level of the first capacitor C1 It is possible to adjust the first time interval.

Similarly, as the voltage level of the external voltage ADJ_SW increases or decreases, the value of the output current output from the second current source 121, which is a current mirror, also becomes larger or smaller. The second capacitor C2 is charged by receiving the current from the second current source 121. Therefore, when the voltage level of the external voltage ADJ_SW is increased, the second capacitor C2 can be charged relatively quickly, When the voltage level of the external voltage ADJ_SW becomes small, the second capacitor C2 can be charged relatively slowly.

The first capacitor C1 or the second capacitor C2 is discharged when the first transistor 113 or the second transistor 123 is turned on and the first transistor 113 or the second transistor 123 Are respectively turned off, they are supplied with the respective output currents from the first current source 111 or the second current source 121 and are charged. On the other hand, there is no time delay at the time of discharging the first capacitor C1 or the second capacitor C2. When the first capacitor C1 or the second capacitor C2 is charged, time delay occurs due to the influence of the capacitance do.

On the other hand, the first capacitor C1 is charged or discharged by the gate-on signal, and the second capacitor C2 is charged or discharged by the output of the first delay unit 110. [

The first transistor 113 is turned off and charges the first capacitor C1 and the output of the first delay unit 110 is coupled to the first capacitor C1 ) Due to the influence of the capacitance of the gate electrode.

The output of the first delay unit 110 is inverted by the inverter INV1 to turn off the second transistor 123 so that the second capacitor C2 is charged. At this time, the capacitance of the second capacitor C2 A delay is generated by the second time in the output.

The output unit 130 generates a sampling clock on the basis of the output of the first delay unit 110 and the output of the second delay unit 120. The output unit 130 includes a first capacitor C1, The sampling clock may be generated until the second capacitor C2 is charged.

According to the feedback voltage sample and hold method of the present invention described above, the feedback voltage can be simply sampled and held without using a complicated algorithm or circuit, and the sample and hold time can be adjusted according to the parameter of the external component The output voltage can be fed back in an easy and easy manner.

The foregoing has outlined rather broadly the features and technical advantages of the present invention in order to better understand the scope of the claims that follow. The embodiments described above are susceptible to various modifications and changes within the technical scope of the present invention by those skilled in the art. These various modifications and changes are also within the scope of the technical idea of the present invention, and will be included in the claims of the present invention described below.

10: Feedback voltage sample and hold device
100: sampling clock generating unit 110: first delay unit
111: first current source 113: first transistor
120: second delay unit 121: second current source
123: second transistor 130:
200: sample and hold section

Claims (4)

In a feedback voltage sample and hold method using a transistor connected to the primary side of a primary side regulation (PSR) flyback converter and a primary side auxiliary winding,
Receiving a gate-on signal for conducting the transistor;
Generating a sampling clock having a pulse for sampling for a predetermined second time interval from a time after a predetermined first time interval in the gate-on signal; And
Sensing and maintaining a voltage level of a voltage (Vfb) obtained in the primary side auxiliary winding using the sampling clock;
/ RTI > The method of claim 1, further comprising: The method according to claim 1,
Wherein the step of generating the sampling clock comprises:
Detecting a time at which a falling edge of the gate-on signal occurs;
Obtaining a time delayed by the first time from the time when the polling edge is generated; and
And generating a sampling clock during the second time interval from a time delayed by the first time. The method according to claim 1,
Wherein the set values of the first time and the second time are adjusted by an external signal. The method according to claim 1,
Wherein the set values of the first time and the second time are adjusted to coincide with the inductor current discharge time (tDIS) determined according to the flyback converter component parameter.
KR1020140078115A 2014-06-25 2014-06-25 Method of sample and hold of feedback voltage KR20160000676A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105811780A (en) * 2016-05-03 2016-07-27 东南大学 Constant voltage control method for output voltage of primary-side feedback flyback type converter

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100889076B1 (en) 2000-05-31 2009-03-17 텍사스 인스트루먼츠 인코포레이티드 A system and method for reducing timing mismatch in sample and hold circuits using the clock
KR100894378B1 (en) 2000-06-28 2009-04-22 텍사스 인스트루먼츠 인코포레이티드 Sample and hold circuit, and method for reducing timing mismatch in sample and hold circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100889076B1 (en) 2000-05-31 2009-03-17 텍사스 인스트루먼츠 인코포레이티드 A system and method for reducing timing mismatch in sample and hold circuits using the clock
KR100894378B1 (en) 2000-06-28 2009-04-22 텍사스 인스트루먼츠 인코포레이티드 Sample and hold circuit, and method for reducing timing mismatch in sample and hold circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105811780A (en) * 2016-05-03 2016-07-27 东南大学 Constant voltage control method for output voltage of primary-side feedback flyback type converter

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