KR20150138890A - Surface Plasmon Resonance-based Light Emitting Diode Using insulator film - Google Patents

Abstract

The present invention relates to a light emitting diode capable of realizing improved luminous efficiency by surface plasmon resonance between an active layer of an LED structure and a metal region surrounded by a protective film.
The light emitting diode (LED) device according to the present invention can exhibit improved quantum efficiency by inducing surface plasmon resonance phenomenon between the active layer and the metal region located inside the periodically arranged hole pattern. Specifically, the metal is located inside the hole structure periodically arranged, so that the light extracting effect can be enhanced, the metal can be positioned near the active layer while maintaining the thickness of the second conductivity type semiconductor layer, The second conductivity type semiconductor layer can induce surface plasmon phenomenon without optical loss or leakage of the active layer. Furthermore, it is possible to prevent the insulating film from being formed on the metal and being deformed by air, heat, and oxidation during the process.

Description

[0001] The present invention relates to a surface plasmon resonance-based light emitting diode

The present invention relates to a surface plasmon resonance-based light emitting diode using an insulating film. More particularly, the present invention relates to a light emitting diode capable of realizing improved luminous efficiency by surface plasmon resonance between an active layer of an LED structure and a metal region surrounded by a protective film.

BACKGROUND ART [0002] LEDs that are applied to a backlight light source, a display light source, a general light source, a full color display, and the like are widely spotlighted by using the characteristics of a compound semiconductor as a semiconductor light emitting device. III-V group nitride semiconductors such as GaN (Gallium Nitride), AlN (Aluminum Nitride), and InN (Indium Nitride) are known as materials for such LEDs. These materials have a large energy band gap gap), so that light of almost the propagation region can be obtained depending on the composition of the nitride. ZnO is also attracting attention as an LED material because it has a high exciton binding energy of 60 meV and can produce a highly efficient light emitting device by using recombination of excitons even at room temperature.

On the other hand, a nitride semiconductor based on GaN has a spontaneous polarization in a growth direction when a device structure is fabricated on a (0001) plane. In particular, LEDs with a quantum well structure of a typical InGaN / GaN have an internal strain due to lattice mismatch in the quantum well structure when the structure is grown on the (0001) plane, and by the piezoelectric fields A quantum-confined Stark effect (QCSE) is generated, so there is a limitation in increasing the internal quantum efficiency.

In recent years, attempts have been made to improve internal quantum efficiency using surface plasmon resonance due to interaction between light and metal. A surface plasmon is a collective charge density oscillation of electrons that occurs on the surface of a metal thin film and is limited to a boundary between a metal and a dielectric (air or semiconductor, etc.), that is, Is known as surface electromagnetic wave. The surface electromagnetic waves generated in this way have different resonance energy depending on the kind of metal, and energy coupling occurs when the energy of the surface electromagnetic wave is matched with the active layer sufficiently close to the inside of the LED. At this time, energy coupling occurs not only to the emission recombination energy occurring in the active layer but also to the non-emission recombination energy, and the internal quantum efficiency is increased due to the emission by the surface plasmon. Generally, metals such as Pd and Al in the UV light emitting region and Ag, Pt, Cu, and Au in the visible light region are mainly used. In this way, the recombination speed of the carriers existing in the LED is improved by mutual coupling between the surface plasmon formed according to the group vibration of the free electrons present in the metal and the active layer. At present, in the case of an LED device using a surface plasmon resonance phenomenon, an effective active layer-surface plasmon bonding is carried out by using an n-type GaN layer (or a p-type GaN layer), an active layer (multi quantum well structure) a p-type GaN layer (or an n-type GaN layer) is sequentially layered and a metal layer is deposited on the p-type GaN layer (or the n-type GaN layer).

For example, Korean Patent Laid-Open Publication No. 2008-74474 discloses a semiconductor light emitting device including first and second conductivity type semiconductor layers, an active layer formed between the first and second conductivity type semiconductor layers, And is disposed at a predetermined distance from the active layer to excite a surface plasmon existing at an interface with the second conductivity type semiconductor layer by light emitted from the active layer, And a metal layer having a periodic concavo-convex structure formed on the interface so as to be emitted through the surface plasmon resonance.

As described above, in most of the conventional LED devices using surface plasmon resonance, there is a restriction that a metal layer in the form of a thin film should be formed only on the upper surface of the upper conductive semiconductor layer in the LED element. Further, the surface plasmon of the active layer and the metal layer In order to cause resonance, the thickness of the upper conductive type semiconductor layer must be kept small. Therefore, there is a limitation in improving the flexibility and electrical performance of the LED element structure.

As another structure, the constitution of the LED element in which the surface plasmon of the metal layer resonates with the well layer of the active layer by providing a metal layer in the form of a thin film on the upper or lower side of the active layer of single or multiple quantum well structure is also known have.

However, when a metal thin film layer is formed between the lower conductive type semiconductor layer and the active layer, or between the upper conductive type semiconductor layer and the active layer, there is a phenomenon that the metal is later lost under the high temperature growth conditions of the active layer and / do. Also, when the metal is located in or directly in contact with the active layer region, leakage of metal may also occur.

Korean Patent No. 10-1134191 discloses a structure in which nanoparticles are positioned between rods formed over a first conductivity type semiconductor, an active layer, and a second conductivity type semiconductor layer. In this structure, the active layer exists in a rod shape A large number of air / GaN interfaces exist), there is a problem that light leakage loss may occur. - Refer to attached 10-1134191 ... Describe limitations and problems of this patent ...

The present invention provides a light emitting device capable of inducing a surface plasmon phenomenon without reducing the thickness of the upper conductive semiconductor layer (second conductive semiconductor layer).

A method of forming a metal region capable of inducing plasmon resonance between an active layer and a top conductive type semiconductor layer (second conductive type semiconductor layer) so as not to be affected by a high temperature due to growth of an active layer or an upper conductive type semiconductor layer, and Device.

The present invention provides a method and device capable of inducing a surface plasmon phenomenon without optical loss or leakage of an active layer.

According to a first aspect of the present invention,

Providing a semiconductor device including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer;

Forming a plurality of hole patterns in the second conductive type semiconductor layer;

Sequentially depositing an insulating film and a metal layer on the second conductive semiconductor layer and the hole pattern;

Depositing the insulating film on the metal layer again; And

Removing the insulating layer and the metal layer on the second conductive type semiconductor layer,

The method includes forming the metal layer surrounded by the insulating film in a hole pattern to cause surface plasmon resonance between the metal layer and the active layer.

According to a second aspect of the present invention,

Providing a semiconductor device having a first conductivity type semiconductor layer, an active layer region, and a second conductivity type semiconductor layer;

Forming a plurality of hole patterns in the second conductive type semiconductor layer;

Coating nanoparticles of a metal core-protective film shell structure on the second conductivity type semiconductor layer; And

Removing the nanoparticles located above the second conductivity type semiconductor layer, the method comprising: The method includes placing the nanoparticles of the core-shell structure surrounded by a protective film in a hole pattern, and generating surface plasmon resonance between the metal particles and the active layer.

According to a third aspect of the present invention,

A first conductive semiconductor layer;

A second conductivity type semiconductor layer;

An active layer formed between the first conductive semiconductor layer and the second conductive semiconductor layer;

A hole pattern periodically repeatedly formed in the second conductivity type semiconductor layer to a predetermined depth;

An insulating film deposited on the upper and lower walls of the hole pattern,

And a metal region surrounded by the insulating film, wherein surface plasmon resonance occurs between the metal region and the active layer.

According to a fourth aspect of the present invention,

A first conductive semiconductor layer;

A second conductivity type semiconductor layer;

An active layer formed between the first conductive semiconductor layer and the second conductive semiconductor layer;

A hole pattern periodically repeatedly formed in the second conductivity type semiconductor layer to a predetermined depth; And

And nanoparticles of a metal core-insulating shell structure located inside the hole pattern, wherein surface plasmon resonance occurs between the metal core and the active layer.

The light emitting diode (LED) device according to the present invention can exhibit improved quantum efficiency by inducing surface plasmon resonance phenomenon between the active layer and the metal region located inside the periodically arranged hole pattern. Specifically, the metal is located inside the hole structure periodically arranged, so that the light extracting effect can be enhanced, the metal can be positioned near the active layer while maintaining the thickness of the second conductivity type semiconductor layer, The second conductivity type semiconductor layer can induce surface plasmon phenomenon without optical loss or leakage of the active layer. Furthermore, it is possible to prevent the insulating film from being formed on the metal and being deformed by air, heat, and oxidation during the process.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view showing a manufacturing process of a surface plasmon resonance-based LED device according to an embodiment of the present invention; FIG.
2 is a schematic diagram of a surface plasmon resonance-based LED element made by FIG.
3 is a view showing a manufacturing process of a surface plasmon resonance-based LED device according to another embodiment of the present invention.
Fig. 4 is a schematic view of the surface plasmon resonance-based LED element manufactured by Fig.

The present invention can be all accomplished by the following description. The following description should be understood to describe preferred embodiments of the present invention, but the present invention is not necessarily limited thereto.

The accompanying drawings may be exaggeratedly expressed relative to the actual layer thickness (or height) or the ratio with respect to other layers in order to facilitate understanding, and the meaning thereof may be appropriately understood according to the concrete purpose of the related description to be described later .

In this specification, the expressions "on" and "on" are used to refer to the relative position concept and include not only the case where other elements or layers are directly present in the mentioned layer, (Interlayers) or components may be interposed or present, and also in the context of the mentioned layers, but not completely covering the surface of the mentioned layer (e.g. embedded structure) can do. Similarly, the expressions "underneath", "underneath", and "underneath" may also be understood as relative concepts of position. Also, the expression "between" can be relatively understood as described above, and can be understood as a longitudinal or lateral positional concept.

In this specification, each of the "first conductivity type semiconductor" and the "second conductivity type semiconductor" may mean "n-type" or "p-type" and typically has opposite conductivity characteristics. At this time, semiconductors such as unintentionally doped GaN as the first conductivity type semiconductor are also possible. More preferably, the first conductivity type semiconductor may be a p-type semiconductor when the first conductivity type semiconductor is located on the lower side, and the second conductivity type semiconductor may be an n-type semiconductor.

Also, the term "region" can be understood in a broad sense, for example, as meaning, in general, the term "continuous layer" structure as well as various steric structures (rod, hollow cylinder or ring, etc.) And may further include a case where a specific component or a particle (for example, a quantum dot) is contained, or a specific component or particle is regularly / irregularly distributed, or continuously / discontinuously distributed or formed.

Hereinafter, surface plasmon resonance-based LED devices according to various embodiments of the present invention will be described in detail.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view showing a manufacturing process of a surface plasmon resonance-based LED device according to an embodiment of the present invention; FIG. 2 is a schematic diagram of a surface plasmon resonance-based LED element made by FIG.

Referring to FIGS. 1 and 2, the LED device of the present invention basically includes a substrate 101, a first conductive semiconductor region 102, a second conductive semiconductor 104, And an active layer 103 formed between the two-conductivity-type semiconductor layers.

The LED device includes a hole pattern 107 periodically and repeatedly formed at a predetermined depth in the second conductive semiconductor layer 104, an insulating film 108 deposited on the lower and upper surfaces of the hole pattern, and a metal Area < / RTI >

The LED device induces a metal region and a surface plasmon phenomenon by the light emitted from the active layer. The metal region is a region where the metal is located, and represents a metal portion positioned within the hole pattern at a predetermined thickness.

The light emitting diode (LED) device according to the present invention can increase the light extracting effect because the metal is located inside the hole structure periodically arranged. The metal can be positioned near the active layer while maintaining the thickness of the second conductivity type semiconductor layer. Further, since the second conductive type semiconductor layer and the insulating film are interposed between the metal and the active layer, surface plasmon phenomenon can be induced without optical loss or leakage of the active layer. Furthermore, it is possible to prevent the insulating film from being formed on the metal and being deformed by air, heat, and oxidation during the process.

The method of manufacturing the LED element of the present invention will be described in detail below.

The first conductivity type semiconductor layer 102 may be formed on a substrate 101. The first conductivity type semiconductor layer 102 may be a p-type semiconductor layer. The thickness of the first conductivity type semiconductor layer may typically range from about 50 nm to 10 μm, more typically about 100 to 500 nm, although the present invention is not necessarily limited to the specific numerical range.

The substrate 101 may be a substrate known in the art for manufacturing LEDs, typically a substrate for growing a semiconductor single crystal, such as sapphire, silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN) (Si), gallium phosphide (GaP), indium phosphide (InP), zinc oxide (ZnO), MgAl ₂ O ₄ MgO, LiAlO ₂ , LiGaO ₂ and the like can be grown from a substrate capable of epitaxially growing semiconductors such as GaN As an alternative, a sapphire substrate can be used more typically. Also, the thickness of the substrate may range typically from about 100 to 500 microns, more typically from about 250 to 450 microns, unless otherwise noted in the following description, which should be understood in an exemplary sense.

Also. A buffer layer (not shown) may be formed prior to the formation of the first conductivity type semiconductor layer 102. That is, a buffer layer may be selectively formed between the substrate 101 and the first conductivity type semiconductor layer 102 to mitigate lattice constant mismatch and induce two-dimensional growth. When the semiconductor layer is grown on the cushioning layer as described above, the interfacial energy is reduced as compared with the case where the semiconductor layer is directly grown on the heterogeneous substrate. Therefore, nucleation of a high density becomes possible, There is an advantage of promoting the growth, and the lattice mismatch can be relaxed to some extent.

The active layer 103 is formed on the first conductive semiconductor layer 102. According to a preferred embodiment of the present invention, the active layer is formed of at least one selected from GaN, AlN, InN, InGaN, AlGaN, InAlGaN, It can be made of two materials. Among them, a material having a small energy bandgap may be a quantum well, a material having a large energy bandgap may be a quantum barrier, and both single and multiple quantum well structures are possible.

The active layer 103 may be formed to a thickness of about 1 to 10 nm in the case of a single quantum well structure and a thickness of about 40 to 80 nm in the case of a multiple quantum well (for example, five pairs of active layers). The above numerical ranges are merely exemplary and the present invention is not necessarily limited thereto.

According to a preferred embodiment of the present invention, a second conductivity type semiconductor layer 104 is formed on the active layer 103 to provide a p-n junction to the LED structure.

The first conductive semiconductor, the active layer, and the second conductive semiconductor may be formed of various semiconductor materials (III-V, II-VI, etc.) known in the art for manufacturing LEDs such as GaN, InN, AlN, InP , InS, GaAs, CdS, CdSe , CdTe, ZnS, ZnSe, ZnTe, ZnO, Al x Ga 1-x N, In x Ga 1-x N, In x Ga 1-x As, Zn x Cd 1-x S , InZnO (IZO), may be used _{InSnO 2 (ITO), ZTO (} zinc tin oxide), AZO (Al-doped zinc oxide), In 2 O 3, Ga 2 O 3, InGaZnO (IGZO) , etc., thereof alone (In the above, 0 < x < 1).

Unless otherwise specified in the present specification, the formation of the conductive semiconductor region (and the buffer layer) and the active layer region can be applied without any particular limitation to the layer formation or growth method involved in a typical LED manufacturing process, (MOCVD), molecular beam growth (MBE), and hydride vapor phase growth (HVPE). In some cases, sputtering may also be used.

  The thickness of the second conductivity type semiconductor layer 104 may be in the range of about 100 to 300 nm, more typically about 100 to 130 nm, which should be interpreted in an exemplary sense.

Referring to FIG. 1, the present invention includes a step of forming a plurality of hole patterns in the second conductive semiconductor layer 104.

The method for forming a hole pattern includes the steps of applying polystyrene particles on the second conductive type semiconductor layer, reducing the particle size by etching the polystyrene particles, depositing a mask metal, Removing the polystyrene particles, and vertically etching the second conductive type semiconductor layer under the region where the polystyrene is removed.

First, a polystyrene colloid having a self-assembled property is deposited on the surface of the second conductivity type semiconductor 104 by a spin coating method or a drop method to form aligned polystyrene particles ) 105 are formed as a single layer.

The polystyrene particles are etched to reduce the particle size to 500 to 600 nm. Then, a mask metal is deposited on the second conductivity type semiconductor and polystyrene particles. The mask metal may be nickel, copper, aluminum, or the like.

Subsequently, the polystyrene particles are removed with acetone and IPA (isopropyl alcohol), and then the second conductive type semiconductor layer under the region where the polystyrene is removed is vertically etched.

Since the mask metal is not deposited in the lower region where the polystyrene particles are located, the etching is performed vertically in the region where the mask metal is not deposited.

In the present invention, a hole pattern may be periodically and repeatedly formed in the second conductivity type semiconductor layer at predetermined intervals and a predetermined size through a process of coating the polystyrene particles with a single layer, etching, and depositing a mask metal.

That is, the size, interval and the like of the hole pattern can be controlled by controlling the size of the polystyrene particles, the etching time, and the like.

In the present invention, a selective etching process using a nano patterning technique may be applied to selectively remove the polystyrene particles or LED structures. For such a selective etching process, electron-beam lithography, focused ion beam (FIB) lithography, nano-imprint, mask formation using SiO2 nanoparticles, A mask patterning method such as a self-assembled metal mask can be applied. As the etching method after the formation of the mask, a dry etching method such as reactive ion etching (RIE), inductively coupled plasma reactive ion etching (ICP-RIE) Chemically assisted ion beam etching (CAIBE) or the like may be used.

When the ICP-RIE is used, the etching can be performed by appropriately adjusting process parameters such as selectivity and etch rate, for example, to etch the second conductivity type semiconductor layer.

In this method, a hole pattern can be formed by etching the second semiconductor layer to a depth of 80 to 120 nm, preferably a depth of 100 to 120 nm.

In this method, the distance between the lower end of the hole pattern and the active layer is 5 to 120 nm, preferably 10 to 40 nm, more preferably 10 to 20 nm. For example, when the metal is Ag, the closer the interval between the lower end of the hole pattern and the active layer, the better.

The method may be such that the size of the hole pattern is 400 to 600 nm, preferably 400 to 500 nm.

The present invention can deposit an insulating film after forming the hole pattern. The insulator or non-conductive material typically has a higher energy band gap than the metal, for example, at least about 3 eV. It is also preferable that the insulating film has a melting point higher than that of the metal. The insulating film may be silica (SiO2), titania (TiO2), zirconia (ZrO2), alumina (Al2O3) or a combination thereof.

The insulating layer may be deposited not only on the upper portion of the mask layer, the lower portion of the hole, but also on the side wall. The insulating film deposition can be preferably performed by plasma enhanced chemical vapor deposition (PECVD) or sputtering.

The thickness of the insulating film may be 5 to 50 nm, preferably 10 to 50 nm, and more preferably 10 to 20 nm.

The method deposits a metal on the insulating film. Examples of the metal suitable for generating the surface plasmon resonance include palladium (Pd), aluminum (Al), silver (Ag), platinum (Pt), copper (Cu), gold (Au), chromium Or in combination. Preferably, silver (Ag) or gold (Au), and most preferably silver (Ag) can be used. The metals listed above are for illustrative purposes only, and the invention is not necessarily so limited.

An electron-beam evaporation system, such as an e-beam coater, may be used for the formation of the metal layer.

The method further deposits the insulating film after the metal deposition. The above-mentioned contents can be referred to for the above insulation film deposition.

In order to obtain a surface plasmon resonance effect between the metal and the active layer in the hole pattern, various factors (for example, the wavelength of incident light, the refractive index of a substance in contact with the metal, and the like) It is important to keep within a certain distance.

In general, the distance between the metal and the active layer for plasmon resonance can typically range from about 5 to 300 nm, more typically from about 30 to 80 nm, so that the distance between the metal and the active layer, which is located in the hole pattern, . That is, for example, a desirable surface plasmon effect can be obtained in the range of about 42 to 50 nm in the case of Ag, about 70 to 80 nm in case of Al, and about 30 to 35 nm in case of Au.

The method includes removing a mask metal layer, a metal layer, and an insulating layer formed on the second conductive type semiconductor layer.

The hole pattern formed in the second semiconductor layer with a periodic arrangement can be manufactured by the removing step. In the hole pattern, the active layer and a metal that generates surface plasmon resonance are located. The metal is protected by an insulating film and is stable against air or heat.

3 is a view showing a manufacturing process of a surface plasmon resonance-based LED device according to another embodiment of the present invention. Fig. 4 is a schematic view of the surface plasmon resonance-based LED element manufactured by Fig.

3 and 4, the LED device of the present invention basically includes a substrate 201, a first conductivity type semiconductor region 202, a second conductivity type semiconductor 204, And an active layer 203 formed between the two-conductivity-type semiconductor layers.

The LED device includes a hole pattern 207 periodically and repeatedly formed at a predetermined depth in the second conductive semiconductor layer 204 and nanoparticles 210 of a metal core-insulating shell structure located inside the hole pattern do.

The LED element induces surface plasmon resonance between the metal core and the active layer to exhibit light extraction improvement effect.

The light emitting diode (LED) device according to the present invention may enhance the light extraction effect because the metal nanoparticles 210 of the metal core-insulating shell structure are located inside the hole structure periodically arranged. In addition, the metal core can be positioned near the active layer while maintaining the thickness of the second conductivity type semiconductor layer. In addition, since the second conductive semiconductor layer and the insulating film-shell are provided between the metal core and the active layer, surface plasmon phenomenon can be induced without optical loss or leakage of the active layer. Furthermore, it is possible to prevent the insulating film from being formed on the metal core and being deformed by air, heat, and oxidation during the process.

3 and 4, a method of fabricating a surface plasmon resonance-based LED device includes providing a semiconductor device having a first conductivity type semiconductor layer, an active layer region, and a second conductivity type semiconductor layer, A step of forming a plurality of hole patterns on the first conductivity type semiconductor layer, a step of coating nanoparticles of a metal core-insulating film shell structure on the second conductivity type semiconductor layer, .

The first conductivity type semiconductor layer 202, the active layer 203 and the second conductivity type semiconductor layer 204 are first formed on the substrate 201 and then the second conductivity type semiconductor layer 203, A plurality of hole patterns 207 are formed.

As a method of forming the hole pattern, the above description can be referred to. That is, the method may include applying polystyrene particles 205 to the second conductive semiconductor layer 204 and etching the polystyrene particles to reduce the particle size, A mask metal 206 is deposited on the semiconductor layer 204 and the polystyrene particles 205 to remove the polystyrene particles and vertically etch the second conductive type semiconductor layer under the polystyrene- The hole pattern 207 can be formed.

The method includes coating nanoparticles of a metal core-insulating shell structure on the second conductivity type semiconductor layer. The core-shell structure nanoparticles may be filled into the hole pattern by the coating, for example, drop coating.

The thickness of the nanoparticle layer filled in the hole pattern may be 5 to 100 nm.

The nanoparticles of the metal core-insulating shell structure can be manufactured using the above-described metal and insulating film.

For example, in the case of a metal core, a method of producing a metal precursor by reducing the metal precursor in a liquid phase using a reducing agent can be exemplified, and an insulator shell can be formed on the metal nanoparticles (typically, colloid) , A sol-gel process (hydrolysis-condensation reaction of a silica precursor such as TEOS, for example, in the case of silica shell) or spray pyrolysis in the process of forming the insulator shell. Although the nanoparticles of the core-shell structure used in the present invention are not limited to the specific manner described above, preferably the metal core can be prepared by a liquid phase reduction process and the insulator shell can be prepared by a sol-gel process. For example, in the case of preparing nanoparticles of Ag core-silica shell structure, silver nitrate, silver phosphite and the like can be used as the silver precursor, and tetraethyl orthosilicate (TEOS) (APS), sodium silicate, and the like can be used.

As the reducing agent, typically, ascorbic acid, formaldehyde, etc., and cetyltrimethylammonium bromide (CTAB) as a protective agent and polyvinylpyrrolidone as a protonic nonionic polymer can be used.

The shape of the core-shell nanoparticles is not particularly limited, and may have various shapes such as a sphere, a rod, a wire, and a pyramid. However, it is preferable to have a spherical shape.

In the case of the core-shell structure, the size (diameter) of the metal core is not particularly limited. However, considering the absorption of nanoparticles, it is typically about 10 to 300 nm, more typically about 30 to 100 nm lt; / RTI &gt; nm.

The insulating film constituting the shell preferably has a metal region or a metal core having a dimension suitable for generating the surface plasmon resonance with the active layer. In view of the above, the thickness of the insulating film may be in the range of about 5 to 100 nm, preferably about 10 to 60 nm, and most preferably in the range of 10 to 30 nm.

The method can remove the nanoparticles partially formed on the second conductive type semiconductor layer by a stamping method.

The method may partially etch the LED structure to a portion of the first conductive semiconductor layer and then form a first electrode and a second electrode over the second conductive layer.

Hereinafter, preferred embodiments of the present invention will be described in order to facilitate understanding of the present invention. However, the present invention is not limited thereto.

Example 1

A low-temperature GaN buffer layer was grown on a c-plane sapphire substrate heated at 1100 ° C for 10 minutes using trimethylindium (TMGa), trimethylindium (TMIn) and ammonia gas as precursors of Ga, In and N. next, Undoped GaN and 2 탆 Si-doped n-type GaN were grown at 1060 캜. GaN barrier and InGaN wells were grown at 850 ℃ and 750 ℃ with five pairs of InGaN / GaN quantum wells. Finally, a Mg doped p-type GaN layer with a thickness of 130 nm was grown.

Next, a pattern hole was formed in the p-type GaN layer by the following method. First, 1μmm polystyrene (PS) was coated on p-GaN by spin coating (400rpm for 6 seconds, 1200rpm for 7 seconds). Then, the PS size was etched to 600 nm with an ICP-RIE apparatus under conditions of O ₂ 50 sccm and 5 min, and Ni was deposited to a thickness of 70 nm by an E-beam deposition apparatus. The PS on the p-GaN layer was removed with acetone and IPA, and p-GaN was etched to a depth of 100 nm with ICP-RIE equipment to form holes.

Next, a metal region protected by an insulating film in the hole was prepared as follows. First, SiO ₂ was deposited to a thickness of 10 to 20 nm on a p-GaN layer having a hole by using a PECVD apparatus. Subsequently, Ag was deposited to a thickness of 40 to 60 nm using an E-beam deposition apparatus, and then SiO ₂ was deposited to a thickness of 10 to 20 nm using a PECVD apparatus. Finally, the Ni layer, the upper metal layer and the insulating film were removed with hydrochloric acid and nitric acid.

Example 2

The steps of forming the holes by etching the p-GaN to a depth of 100 nm were carried out in the same manner as in Example 1. Next, the Ni mask layer was removed with hydrochloric acid, and the Ag @ SiO ₂ nanoparticles prepared by the sol-gel method were drop-coated. The device was fabricated by removing the nanoparticles on the p-GaN surface by the stamping method.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

101, 201: substrate
102. 202: first conductivity type semiconductor layer
103, 203: active layer
104, 204: a second conductivity type semiconductor layer
105, and 205: polystyrene particles
106, 206: mask layer
107, 207: pattern hole
108: insulating film
109: metal area
210: core-shell nanoparticles

Claims (13)

A first conductive semiconductor layer;
A second conductivity type semiconductor layer;
An active layer formed between the first conductive semiconductor layer and the second conductive semiconductor layer;
A hole pattern periodically repeatedly formed in the second conductivity type semiconductor layer to a predetermined depth;
A metal region located within the hole pattern; And
And an insulating film formed between the hole pattern and the metal region, wherein surface plasmon resonance occurs between the metal region and the active layer. A first conductive semiconductor layer;
A second conductivity type semiconductor layer;
An active layer formed between the first conductive semiconductor layer and the second conductive semiconductor layer;
A hole pattern periodically repeatedly formed in the second conductivity type semiconductor layer to a predetermined depth; And
And a nanoparticle of a metal core-insulator shell structure located inside the hole pattern, wherein surface plasmon resonance occurs between the metal core and the active layer. The LED device according to claim 1 or 2, wherein an interval between the lower end of the hole pattern and the active layer is in a range of 5 to 120 nm. The LED device according to claim 1 or 2, wherein the insulating film has a thickness of 5 to 50 nm. The LED device according to claim 1 or 2, wherein the hole pattern is periodically and repeatedly formed inside the two-conductive semiconductor layer. The method of claim 1 or 2, wherein the metal is selected from the group consisting of Pd, Al, Ag, Pt, Cu, Au, Cr, Rh) or a combination thereof. The LED device according to claim 1 or 2, wherein the insulating film is made of silica (SiO2), titania (TiO2), zirconia (ZrO2), alumina (Al2O3) or a combination thereof. The LED device according to claim 2, wherein the nanoparticle layer of the metal core-insulating shell structure has a thickness of 5 to 100 nm. Providing a semiconductor device including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer;
Forming a plurality of hole patterns in the second conductivity type semiconductor layer, the hole patterns being periodically repeatedly formed in the two-conductivity type semiconductor layer;
Sequentially depositing an insulating film and a metal layer on the second conductive semiconductor layer and the hole pattern;
Depositing the insulating film on the metal layer again; And
Removing the insulating layer and the metal layer on the second conductive type semiconductor layer,
Wherein the metal layer surrounded by the insulating film is formed in the hole pattern to cause surface plasmon resonance between the metal layer and the active layer. Providing a semiconductor device including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer;
Forming a plurality of hole patterns in the second conductivity type semiconductor layer, the hole patterns being periodically repeatedly formed in the two-conductivity type semiconductor layer;
Coating nanoparticles of a metal core-insulating shell structure on the second conductivity type semiconductor layer;
Removing the nanoparticles located above the second conductivity type semiconductor layer, the method comprising:
Wherein the nanoparticles of the core-shell structure surrounded by the insulating film are disposed in the hole pattern to cause surface plasmon resonance between the metal particles and the active layer. 11. The method according to claim 9 or 10, wherein a hole pattern is formed in the second conductivity type semiconductor layer
Applying polystyrene particles on the second conductivity type semiconductor layer;
Etching the polystyrene particles to reduce the particle size;
Depositing a mask metal;
Removing the polystyrene particles; And
And vertically etching the second conductive type semiconductor layer under the region where the polystyrene is removed. 11. The method according to claim 9 or 10, wherein the etching is performed so that a distance between a lower end of the hole pattern and the active layer is in a range of 10 to 40 nm. 10. The method according to claim 9, wherein the insulating film is PECVD-deposited to form the insulating film on the upper and lower sides and the side surfaces of the hole.

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