KR20150121790A - embedded PCB and method of manufacturing the same - Google Patents

Abstract

In a method of manufacturing an embedded PCB according to an embodiment of the present invention, a first circuit pattern layer is formed on a carrier substrate which has a plating seed layer. A first stack structure which has a first interfacial insulating layer equipped with a cavity to selectively expose the first circuit pattern layer is formed on the carrier substrate. A device chip is disposed in the inside of the cavity while the first circuit pattern layer is electrically insulated from the device chip using a nonconductive bonding layer. A second stack structure which has a second interfacial insulating layer to cover the device chip is formed on the first stack structure. The first circuit pattern layer is exposed by separating the carrier substrate from the first and the second stack structures. The device chip is exposed by selectively removing the nonconductive bonding layer between the first circuit pattern layer, and a connecting structure, which is electrically connected with the device chip, is formed.

Description

[0001] Embedded printed circuit board and method of manufacturing same [0001]

The present invention relates to a printed circuit board (PCB), and more particularly, to an embedded printed circuit board and a manufacturing method thereof.

With the miniaturization of electronic devices, electronic components are becoming more sophisticated and smaller. Due to the advancement of digital networks, portable information terminal devices such as mobile phones and portable computers are becoming more sophisticated and sophisticated, and various functions are being combined and integrated into one device.

As electronic devices are miniaturized and highly functionalized, the number of component elements to be mounted on a printed circuit board is greatly increased. On the other hand, the area of the substrate is not reduced. Rather, it is demanded to reduce the thickness of the existing printed circuit board and the thickness of the component element in accordance with the trend of downsizing described above.

Recently, as a method of manufacturing a printed circuit board to satisfy the above-mentioned requirements, an embedded printed circuit board technology in which a device chip or a circuit pattern is embedded in a printed circuit board has appeared. Embedded printed circuit board technology can be advantageous in reducing the thickness of the entire component by embedding the component chip or circuit pattern in the printed circuit board.

As an example of a manufacturing technique of such an embedded printed circuit board, there is a technique disclosed in Korean Patent Publication No. 2012-0070075.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing an embedded printed circuit board in which a device chip or a circuit pattern is embedded to further reduce the thickness of a printed circuit board.

An object of the present invention is to provide an embedded printed circuit board having a thinner thickness by embedding a device chip or a circuit pattern.

A method of manufacturing an embedded printed circuit board according to one aspect is provided. In the method for manufacturing an embedded printed circuit board, a first circuit pattern layer is formed on a carrier substrate including a plating seed layer. A first laminated structure including a first interlayer insulating layer having a cavity for selectively exposing the first circuit pattern layer is formed on the carrier substrate. The device chip is disposed inside the cavity, and the first circuit pattern layer and the device chip are electrically insulated by using an insulating adhesive layer. And a second layered structure including a second interlayer insulating layer covering the device chip is formed on the first layered structure. The carrier substrate is separated from the first and second laminated structures to expose the first circuit pattern layer. The insulating adhesive layer between the first circuit pattern layers is selectively removed to expose the device chip, and a connection structure electrically connected to the device chip is formed.

A method of manufacturing an embedded printed circuit board according to another aspect is provided. In the method of manufacturing the embedded printed circuit board, a first circuit pattern layer is formed on the carrier substrate. A first interlayer insulating layer covering the first circuit pattern layer is formed on the carrier substrate. A cavity for selectively exposing the first circuit pattern layer is formed in the first interlayer insulating layer. An insulating adhesive layer covering the first circuit pattern layer in the cavity is formed and the device chip is placed in the cavity in a state electrically insulated from the first circuit pattern layer. And the cavity is filled with the second interlayer insulating layer. The carrier substrate and the first circuit pattern layer are separated from each other to expose the first circuit pattern layer, the first interlayer insulating layer, and the insulating adhesive layer. The insulating adhesive layer under the device chip is selectively removed to expose the electrode portion of the device chip.

An embedded printed circuit board according to another aspect is provided. The embedded printed circuit board includes: a first interlayer insulating layer having a first circuit pattern layer therein and including a cavity selectively exposing at least a portion of the first circuit pattern layer; A device chip disposed in the cavity and electrically insulated from the first circuit pattern layer by an insulating adhesive layer; A second interlayer insulating layer disposed on the first interlayer insulating layer to cover the device chip; And a connection structure that is electrically connected to the device chip through the first circuit pattern layer under the device chip.

According to one embodiment, an embedded printed circuit board can be manufactured by applying a carrier substrate. By adopting a method of forming a laminated circuit pattern structure on a carrier substrate and removing the carrier substrate without directly applying a copper clad laminate (CCL) to the main circuit substrate, a built-in device chip or a built- It is possible to easily manufacture the embedded printed circuit board.

According to one embodiment, the device chip can be configured to be embedded by an interlayer insulating layer together with a circuit pattern layer. At this time, the device chips may be disposed adjacent to each other with the embedded circuit pattern and the insulating adhesive layer insulated from each other.

According to one embodiment, an element chip may be disposed on an embedded circuit pattern layer, and an external connection structure may be formed to penetrate between the embedded circuit pattern layers. By applying the above-described structure, it is possible to provide a thin printed circuit board having an improved degree of integration and improved structural stability.

1 is a flowchart schematically showing a method of manufacturing an embedded printed circuit board according to an embodiment of the present invention.
2 to 14 are sectional views schematically showing a method of manufacturing an embedded printed circuit board according to an embodiment of the present invention.
15 is a cross-sectional view schematically showing a connection form of an embedded printed circuit board and another external printed circuit board.
16 is a cross-sectional view schematically showing an embedded printed circuit board according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the techniques disclosed in the present invention are not limited to the embodiments described herein but may be embodied in other forms. It should be understood, however, that the embodiments disclosed herein are provided so that this disclosure will be thorough and complete, and will fully convey the concept of this disclosure to those skilled in the art. In the drawings, the width, thickness, and the like of the components are enlarged in order to clearly illustrate the components of each device. It is to be understood that when an element is described as being located on another element, it is meant that the element is directly on top of the other element or that additional elements can be interposed between the elements .

Like numbers refer to like elements throughout the several views. It is to be understood that the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise, and the terms "comprise" Or combinations thereof, and does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Further, in carrying out the method or the manufacturing method, the respective steps of the method may occur differently from the stated order unless clearly specified in the context. That is, each process may occur in the same order as described, may be performed substantially concurrently, or may be performed in the opposite order.

As used herein, the term " top surface " or " bottom " of a substrate or device chip is a relative concept observed at an observer's viewpoint. Therefore, one of the two surfaces except the side of the substrate or the element chip may be referred to as an 'upper surface' or 'lower surface', and the other surface may be referred to as 'lower surface' or 'upper surface' correspondingly. Likewise, in the present specification, the concept of 'upper', 'upper' or 'lower' and 'lower' can be used as a relative concept as well.

1 is a flowchart schematically showing a method of manufacturing an embedded printed circuit board according to an embodiment of the present invention. Referring to step 110 of FIG. 1, a first circuit pattern layer is formed on a carrier substrate including a plating seed layer. In one embodiment, the carrier substrate includes an insulating core layer, and the carrier substrate may further include a carrier copper layer sequentially stacked on the insulating core layer and the plating seed layer. In one embodiment, the first circuit pattern layer may be formed by a copper plating method using a resist pattern layer on the plating seed layer.

Referring to step 120 of FIG. 1, a first laminated structure including a first interlayer insulating layer is formed on the carrier substrate. At this time, the first interlayer insulating layer may include a cavity for selectively exposing the first circuit pattern layer.

As a specific example of the above-described method, first, a first interlayer insulating layer is laminated on the first circuit pattern layer. Then, a first via layer is formed in the first interlayer insulating layer. Further, a second circuit pattern layer is formed on the first interlayer insulating layer. The first via layer may be formed by selectively etching the first interlayer insulating layer to form a via hole exposing the first circuit pattern layer and then filling the via hole with a copper plating layer. The second circuit pattern layer can be formed, for example, by applying a resist pattern layer and a semi-additive process (SAP) or a modified semi-additive process (MSAP) using a copper plating method. Then, the first interlayer insulating layer is processed to form the cavity that selectively exposes the first circuit pattern layer.

Referring to step 130 of FIG. 1, a device chip is disposed in the cavity. At this time, the first circuit pattern layer and the element chip are electrically insulated by using an insulating adhesive layer.

As a specific example of the above-described method, an insulating adhesive material is applied to the inside of the cavity so as to cover the first circuit pattern layer, thereby forming the insulating adhesive layer first. Thereafter, the device chip is attached onto the insulating adhesive layer. Thereby, the device chip can be disposed inside the cavity.

Or as another embodiment, an insulating adhesive material is provided on at least one side of the device chip. As an example, an insulating adhesive material may be provided to cover the bottom surface of the device chip. Next, the device chip including the insulating adhesive material is attached on the first circuit pattern layer. Thereby, the device chip can be disposed inside the cavity.

Referring to step 140 of FIG. 1, a second stacked structure including a second interlayer insulating layer covering the device chip is formed on the first stacked structure.

As a specific example of the above-described method, first, the second interlayer insulating layer filling the cavity is laminated on the first laminated structure. Then, a second via layer is formed in the second interlayer insulating layer, and a third circuit pattern layer is formed on the second interlayer insulating layer. The second via layer may be formed by selectively etching the second interlayer insulating layer to form a via hole exposing the second circuit pattern layer and then filling the via hole with the copper plating layer. The third circuit pattern layer may be formed by applying a resist pattern layer and a Semi-Additive Process (SAP) or a Modified Semi-Additive Process (MSAP) using a copper plating method.

Referring to step 150 of FIG. 1, the carrier substrate is separated from the first and second stacked structures. Thus, the first circuit pattern layer can be exposed.

As a specific example of the above-described method, the interface between the carrier copper layer and the seed copper layer is separated from the carrier substrate. As a result, the first laminated structure and the second laminated structure may be sequentially positioned on the separated seed copper layer. Subsequently, the seed copper layer may be removed by an etching method to expose the first circuit pattern layer, the first interlayer insulating layer, and the insulating adhesive layer.

Referring to step 160 of FIG. 1, the insulating adhesive layer between the first circuit pattern layers is selectively removed to expose the device chip, thereby forming a connection structure electrically connected to the device chip.

As a specific example of the above-described method, a solder resist pattern layer is formed on the first circuit pattern layer. Then, the insulating adhesive layer exposed by the solder resist pattern layer and located under the device chip is selectively removed. As a result, the electrode portion of the device chip is exposed. Next, a conductive bump structure is formed on the exposed portion of the device chip.

By the above-described method, an embedded printed circuit board can be manufactured. The method for manufacturing an embedded printed circuit board according to the present embodiment is a method for manufacturing a printed circuit board by forming a laminated circuit pattern structure on a carrier substrate and removing the carrier substrate without directly applying a copper clad laminate (CCL) .

Further, in the method of manufacturing an embedded printed circuit board according to the present embodiment, the device chip can be configured to be embedded in the cavity in the interlayer insulating layer together with the circuit pattern layer. At this time, the device chips may be disposed on the embedded circuit pattern insulated from each other by an insulating adhesive layer.

Further, in the method of manufacturing an embedded printed circuit board according to this embodiment, the device chip may be disposed on the built-in circuit pattern layer, and the external connection structure may be formed so as to penetrate between the embedded circuit pattern layers.

By applying the above-described structure, it is possible to manufacture a thin embedded printed circuit board having embedded device chips or built-in circuit pattern layers, with improved integration and improved structural stability.

2 to 14 are sectional views schematically showing a method of manufacturing an embedded printed circuit board according to an embodiment of the present invention. Referring to FIG. 2, a carrier substrate 200 is prepared. The carrier substrate 200 may include an insulating core layer 210. In addition, the carrier substrate 200 may include a carrier copper layer 212 and a plating seed layer 214 that are sequentially stacked on the insulating core layer 210. As an example, the plating seed layer 214 may be made of a copper material and function as a seed layer for the copper plating process described below. As an example, the insulating core layer 210 may comprise a prepreg and may have a thickness of about 0.1 mm or 0.2 mm. The carrier copper layer 212 may serve to support a later-described layered structure on the insulating core layer 210, and may, for example, have a thickness of about 18 [mu] m. The plating seed layer 214 may have a thickness of about 2 占 퐉 or 5 占 퐉. However, this thickness is only provided as an example, and various variations of the thickness range are possible.

Referring to FIG. 3, a first circuit pattern layer 220 is formed on the plating seed layer 214. According to a specific embodiment, the process of forming the first circuit pattern layer 220 may proceed as follows. First, on the plating seed layer 214, a first resist pattern layer having a contact region for selectively exposing the plating seed layer 214 is formed. A copper plating process is performed using the plating seed layer 214 inside the contact region exposed by the first resist pattern layer. Thus, a copper pattern layer is formed by a copper plating process. Since the. By removing the first resist pattern layer, the first circuit pattern layer 220 can be formed.

4, a first intermediate substrate having a first interlayer insulating layer 232 and a first interlayer copper layer 234 is bonded to a carrier substrate 200 on which a first circuit pattern layer 220 is formed, . The first interlayer insulating layer 232 may include a polymer material such as epoxy or polyimide. According to a specific embodiment, the first intermediate substrate may be aligned on the carrier substrate 200, and the first intermediate substrate may be bonded to the carrier substrate 200 by heating, pressing, or a combination thereof.

Referring to FIG. 5, a first interlayer copper layer 234 and a first interlayer insulating layer 232 are sequentially formed to form a via hole 236 for selectively exposing the first circuit pattern layer 220. As a method of forming the first interlayer copper layer 234, a dry etching method, a wet etching method, or a combination thereof may be used. Next, as a method of processing the first interlayer insulating layer 232, a laser processing method, a mechanical drilling method, or the like can be applied. As the laser processing method, for example, a YAG laser, a ruby laser, an argon laser, a CO2 laser, an excimer laser, or the like can be applied.

6, a copper plating process is carried out to form a via layer 244 filling the inside of the via hole 236 and a copper pattern layer 242 disposed on the first interlayer copper layer 234. As shown in FIG. As a method of forming the via layer 244 and the copper pattern layer 242, an AP (Semi-Additive Process) or MSAP (Modified Semi-Additive Process) using a resist pattern layer and a copper plating method can be applied .

According to a specific embodiment, first, a chemical plating layer is formed inside the via hole 236 of FIG. Or a chemical plating layer may be formed on the inner surface of the via hole 236 and on the upper surface of the first interlayer copper layer 234. Next, a second resist pattern layer having a contact region corresponding to a position at which the copper pattern layer 242 is to be formed is formed on the first interlayer copper layer 242. The copper pattern layer 242 is then subjected to a copper plating process using a lower copper layer (for example, the chemical plating layer or the first interlayer copper layer 242) selectively exposed by the second resist pattern layer. . Subsequently, the second resist pattern layer is removed.

Referring to FIG. 7, the underlying first interlayer copper layer 242 is etched using the copper pattern layer 242 as an etch mask. As a result, the second circuit pattern layer 246 can be formed on the first interlayer insulating layer 232.

The first interlayer insulating layer 232 is then processed to form a cavity 250 selectively exposing the first circuit pattern layer 220 and the plating seed layer 214. As a method of processing the first interlayer insulating layer 232, a laser processing method, a mechanical drilling method, or the like can be applied. As the laser processing method, for example, a YAG laser, a ruby laser, an argon laser, a CO2 laser, an excimer laser, or the like can be applied.

A first via layer 244 and a second circuit pattern layer 246 with a cavity 250 selectively exposing the first circuit pattern layer 220. The first interlayer dielectric layer 232, The first stacked structure can be formed on the carrier substrate 200. [

Referring to FIG. 8, an insulating adhesive layer 260 is formed by coating an insulating adhesive material on the inside of the cavity 250 so as to cover the first circuit pattern layer 220 and the plating seed layer 214. Although the insulating adhesive layer 260 is formed to cover the first circuit pattern layer 220 and the plating seed layer 214 located on the bottom surface of the cavity 250, the insulating adhesive layer 260 is not limited thereto. Although not shown in the drawings, the insulating adhesive layer 260 may be formed to cover at least a portion of the first interlayer insulating layer 232, which is the side wall portion of the cavity 250. Alternatively, an insulating adhesive layer 260 may be formed to fill the cavity 250.

Referring to FIG. 9, the device chip 300 is disposed on the insulating adhesive layer 260. The device chip 300 may be disposed inside the cavity 250 while being electrically insulated from the first circuit pattern layer 220 by the insulating adhesive layer 260. [ The device chip 300, as an example, may include an active device or a passive device. The passive element may be, for example, a capacitor, a resistor, or an inductor. Although a capacitor including the first electrode unit 310, the dielectric unit 330, and the second electrode unit 320 is illustrated as a device chip 300 for convenience of explanation, the present invention is not limited thereto.

Although not shown in the drawings, when the insulating adhesive layer 260 is formed to cover at least a portion of the first interlayer insulating layer 232, which is the side wall portion of the cavity 250, or is formed to fill the cavity 250, The side wall of the semiconductor chip 300 or the whole of the device chip 300 may be surrounded by the insulating adhesive layer 260. In this manner, when the side wall of the device chip 300 or the entirety of the device chip 300 is surrounded by the insulating adhesive layer, the bonding property between the device chip 300 and the structure including the cavity 250 is improved, The structural stability of the circuit board can be improved. In addition, the electrical insulation between the device chip 300 and the peripheral circuit pattern can be improved.

In some other embodiments, an insulating adhesive material may be provided first on at least one side of the device chip 300, unlike the process shown in Figs. Subsequently, the device chip 300 having the insulating adhesive material may be disposed in the cavity 250. In this case, the method of providing the insulating adhesive material to the element chip 300 may be a method of immersing the element chip 300 in a container containing an insulating adhesive material, or applying an insulating adhesive material to at least one surface of the element chip 300 Method can be applied.

Referring to FIG. 10, a second interlayer insulating layer 272 filling the cavity 250 may be laminated on the first laminated structure. The second interlayer insulating layer 272 can bury the device chip 300 therein. The second interlayer insulating layer 272 may include a polymer material such as epoxy or polyimide. In a specific embodiment, the second intermediate substrate including the second interlayer insulating layer 272 and the second interlayer copper layer 274 may be formed by heating, pressing, 1 laminated structure.

Referring to FIG. 11, a second via layer 284 is formed in the second interlayer insulating layer 272, and a copper pattern layer 282 is formed on the second interlayer copper layer 274. The second via layer 284 may be electrically connected to the second circuit pattern layer 246 and the first and second electrode units 310 and 320 of the device chip 300.

The method of forming the second via layer 284 and the copper pattern layer 282 is substantially the same as the process described above with reference to Figures 5 and 6. Therefore, a detailed description is omitted in order to exclude duplication.

Referring to FIG. 12, the lower second interlayer copper layer 274 is etched using the copper pattern layer 282 as an etching mask. As a result, the third circuit pattern layer 286 can be formed on the second interlayer insulating layer 272. The third circuit pattern layer 286 may be connected to the second via layer 284. Thus, a second stacked structure including a second interlayer insulating layer 272, a second via layer 284, and a third circuit pattern layer 286 covering the device chip 300 is formed on the first stacked structure can do.

Then, the interface between the carrier copper layer 212 of the carrier substrate 200 and the seed copper layer 214 is separated. At this time, the first stacked structure and the second stacked structure may be disposed on the separated seed copper layer 214.

The seed copper layer 214 may then be removed by etching to selectively expose the first circuit pattern layer 220, the first interlayer insulating layer 232 and the insulating adhesive layer 260. The etching method may be, for example, dry etching, wet etching, or a combination thereof. As an example of the etching method, a known flash etching method can be applied.

Referring to FIG. 13, a solder resist pattern layer 290 is formed on the first circuit pattern layer 220. In addition, a solder resist pattern layer 290 can be formed on the third circuit pattern layer 286. The solder resist pattern layer 290 can form a hole pattern 262 for selectively exposing the first circuit pattern layer 220 or the third circuit pattern layer 286.

Then, the insulating adhesive layer 260 located under the device chip 300 and exposed by the solder resist pattern layer 290 is selectively removed. As a method for removing the insulating adhesive layer 260, for example, laser drilling can be applied. As another example, a chemical etching method may be applied. As a result, the first and second electrode units 310 and 320 of the device chip 300 can be exposed.

Referring to FIG. 14, a first conductive bump structure 295 is formed on the first and second electrode portions 310 and 320 of the exposed device chip 300. Also, a second conductive bump structure 297 may be formed on the exposed first circuit pattern layer 220. The first conductive bump structure 295 and the second conductive bump structure 297 can function as an external connection structure. The external connection structure may electrically connect an external substrate or device to the first circuit pattern layer 220 or electrically connect an external substrate or device to the device chip 300.

In one embodiment, the method of forming the first conductive bump structure 295 and the second conductive bump structure 297 includes a method of printing a conductive paste on the first and second electrode portions 310, 320 Can be applied. As an example, the conductive paste may be made of a solder material. As another example, the method of forming the first conductive bump structure 295 and the second conductive bump structure 297 may be performed by applying a copper plating technique such as SAP (semi additive process) or MSAP (modified SAP) And the second electrode portions 310 and 320 may be formed. For this purpose, a separate plating seed layer may be formed on the first and second electrode portions 310 and 320, or the connection pad layer 224. A solder layer for connection may be further added on the formed copper posts. As another embodiment, a first conductive bump structure (not shown) filling the interior of the hole pattern 262 may be formed by previously preparing a solder structure in the form of a micro ball, placing it around the hole pattern 262 of FIG. 13 and reflowing the solder structure 295 and a second conductive bump structure 297 may be formed.

As a result, an embedded printed circuit board including the first circuit pattern layer 220, the second circuit pattern layer 246, and the device chip 300 can be manufactured.

2 to 14, a manufacturing method for forming the first laminated structure and the second laminated structure on one side of the carrier substrate 200 is shown for the sake of simplicity in the manufacturing method of the embedded printed circuit board described above with reference to FIGS. 2 to 14 However, the present invention is not limited thereto. A method of removing the carrier substrate 200 after forming the first laminated structure and the second laminated structure on both sides of the carrier substrate 200 may be applied. By this method, a pair of embedded printed circuit boards can be manufactured.

15 is a cross-sectional view schematically showing a connection form of an embedded printed circuit board and another external printed circuit board. Referring to FIG. 15, the first conductive bump structure 295 and the second conductive bump structure 297 can be used to electrically connect the embedded printed circuit board to another printed circuit board outside. The connection method may include disposing the first and second first conductive bump structures 295 and 297 adjacent the pad portions on the external printed circuit board and then placing the first and second first conductive bump structures 295 and 297 ) May be reflowed and bonded to each other.

Referring to FIG. 15, the embedded printed circuit board manufactured according to the present embodiment includes a first circuit pattern layer 220 inside the first printed circuit board 220, And a first interlayer insulating layer 232 including a cavity 250 selectively exposing at least a portion thereof. At this time, the embedded printed circuit board includes a second circuit pattern layer 246 disposed on the first interlayer insulating layer 232 and a first via layer 244 electrically connected to the first circuit pattern layer 220 .

The embedded printed circuit board may include a device chip 300 disposed in the cavity 250 and electrically insulated from the first circuit pattern layer 220 by an insulating adhesive layer 260. The insulating adhesive layer 260 may cover the first circuit pattern layer 220 which is the bottom surface of the cavity 300. In another embodiment, it may be arranged to cover at least a part of the first interlayer insulating layer 232 which is the side wall portion of the cavity 300. [

In addition, the embedded printed circuit board includes a second interlayer insulating layer 272 disposed on the first interlayer insulating layer 232 to cover the device chip 300. At this time, the embedded printed circuit board includes a third circuit pattern layer 286 disposed on the second interlayer insulating layer 272 and a second via layer 284 electrically connected to the second circuit pattern layer 246 .

The embedded printed circuit board may include a connection structure such as a first conductive bump structure 295 that penetrates between the first circuit pattern layers 220 at the bottom of the device chip 300 and is electrically connected to the device chip 300, .

16 is a cross-sectional view schematically showing an embedded printed circuit board according to an embodiment of the present invention. Specifically, the embedded printed circuit board of FIG. 16 is an enlarged view of the vicinity of the connection structure 295 of the printed circuit board of FIG.

Referring to FIG. 16, the first circuit pattern layer 220 may include a circuit layer 222 and a connection pad layer 224. The circuit layer 222 constitutes a portion of the electrical circuit in the embedded printed circuit board and the first via layer 244, the second via layer 284, the second circuit pattern layer 246, And may be electrically connected to the pattern layer 286. The connection pad layer 224 may function as a pad for external connection and may be electrically connected to the first and second electrode portions 310 and 320 via the first conductive bump structure 295. The connection pad layer 224 may be embedded in the first interlayer insulating layer 232. The width W1 of the connection pad layer 224 may be greater than the width W2 of the circuit layer 222. [

Referring again to the drawings, the first conductive bump structure 295 as a connection structure can contact the first and second electrode portions 310, 320 of the device chip 300 and at least a portion of the insulating adhesive layer 260 have. Alternatively, the connection structure 295 may contact the first and second electrode portions 310 and 320 of the device chip 300 and the connection pad layer 224 of the first circuit pattern layer 220.

The first circuit pattern layer 220 embedded in the lower part of the device chip 300 can be disposed in the structure in which the device chip 300 is embedded in the first interlayer insulating layer 232. [ At this time, a part of the first circuit pattern layer 232 functions as the wiring circuit layer 222, and the degree of integration of the printed circuit board can be increased. A part of the first circuit pattern layer 232 is connected By functioning as the pad layer 224, the thickness of the printed circuit board can be reduced. By arranging the first conductive bump structure 295 to be filled in the space between the connection pad layers 224, the structural stability can be increased.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. It can be understood that

200: carrier substrate, 210: insulating core layer,
212: a carrier copper layer, 214: a plating seed layer,
220: first circuit pattern layer, 222: circuit layer,
224: connection pad layer, 232: first interlayer insulating layer,
234: first interlayer copper layer, 236: first via hole,
242: copper pattern layer, 244: first via layer,
246: second circuit pattern layer, 250: cavity,
260: insulating adhesive layer, 300: element chip,
310: first electrode unit, 320: second electrode unit,
330: dielectric portion, 272: second interlayer insulating layer,
274: second interlayer copper layer, 282: copper pattern layer,
284: second via layer, 286: third circuit pattern layer,
290: solder resist pattern layer, 295: first conductive bump structure,
297: Second conductive bump structure.

Claims (22)

(a) forming a first circuit pattern layer on a carrier substrate including a plating seed layer;
(b) forming a first laminate structure on the carrier substrate, the first laminate structure including a first interlayer dielectric layer having a cavity selectively exposing the first circuit pattern layer;
(c) disposing a device chip in the cavity, and electrically insulating the first circuit pattern layer and the device chip using an insulating adhesive layer;
(d) forming a second laminate structure on the first laminate structure, the second laminate structure including a second interlayer insulating layer covering the device chip;
(e) exposing the first circuit pattern layer by separating the carrier substrate from the first and second laminate structures;
(f) selectively removing the insulating adhesive layer between the first circuit pattern layers to expose the device chip, and forming a connection structure electrically connected to the device chip
A method of manufacturing an embedded printed circuit board. The method according to claim 1,
wherein the carrier substrate in step (a)
An insulating core layer; And
A carrier copper layer sequentially deposited on the insulating core layer, and a plating seed layer
A method of manufacturing an embedded printed circuit board. The method according to claim 1,
wherein forming the first circuit pattern layer in step (a) comprises:
Forming a first resist pattern layer selectively exposing the plating seed layer on the plating seed layer; And
And forming a plating pattern layer by performing a plating method using the plating seed layer exposed between the first resist pattern layers
A method of manufacturing an embedded printed circuit board. The method according to claim 1,
(b)
(b1) laminating a first interlayer insulating layer on the first circuit pattern layer;
(b2) forming a first via layer in the first interlayer insulating layer and forming a second circuit pattern layer on the first interlayer insulating layer; And
(b3) forming the cavity for selectively exposing the first circuit pattern layer by processing the first interlayer insulating layer
A method of manufacturing an embedded printed circuit board. The method according to claim 1,
(c)
(c1) forming an insulating adhesive layer by coating an insulating adhesive material on the inside of the cavity so as to cover the first circuit pattern layer; And
(c2) attaching the device chip on the insulating adhesive layer
A method of manufacturing an embedded printed circuit board. The method according to claim 1,
(c)
(c1) providing an insulating adhesive material on at least one side of the device chip; And
(c2) attaching the device chip including the insulating adhesive material on the first circuit pattern layer
A method of manufacturing an embedded printed circuit board. The method according to claim 5 or 6,
The insulating adhesive material is applied to cover the first circuit pattern layer on the bottom surface of the cavity and is applied to cover at least a part of the first interlayer insulating layer which is the side wall portion of the cavity
A method of manufacturing an embedded printed circuit board. The method according to claim 1,
(d)
(d1) depositing the second interlayer insulating layer filling the cavity on the first laminated structure; And
(d2) forming a second via layer in the second interlayer insulating layer and forming a third circuit pattern layer on the second interlayer insulating layer
A method of manufacturing an embedded printed circuit board. 3. The method of claim 2,
(e)
(e1) separating the interface between the carrier copper layer and the seed copper layer of the carrier substrate to dispose the first stack structure and the second stack structure on the exposed seed copper layer; And
(e2) removing the seed copper layer by an etching method to expose the first circuit pattern layer, the first interlayer insulating layer and the insulating adhesive layer
A method of manufacturing an embedded printed circuit board. The method according to claim 1,
(f)
(f1) forming a solder resist pattern layer on the first circuit pattern layer;
(f2) exposing the electrode portion of the device chip by selectively removing the insulating adhesive layer exposed by the solder resist pattern layer and located under the device chip; And
(f3) forming a conductive bump structure on the exposed portion of the device chip
A method of manufacturing an embedded printed circuit board. (a) forming a first circuit pattern layer on a carrier substrate;
(b) forming a first interlayer insulating layer on the carrier substrate to cover the first circuit pattern layer;
(c) forming a cavity in the first interlayer insulating layer to selectively expose the first circuit pattern layer;
(d) forming an insulating adhesive layer covering the first circuit pattern layer in the cavity, and placing the device chip in the cavity in a state electrically insulated from the first circuit pattern layer;
(e) filling the cavity with the second interlayer insulating layer;
(f) exposing the first circuit pattern layer, the first interlayer insulating layer, and the insulating adhesive layer by separating the carrier substrate and the first circuit pattern layer from each other; And
(g) selectively removing the insulating adhesive layer under the device chip to expose the electrode portion of the device chip
A method of manufacturing an embedded printed circuit board. 12. The method of claim 11,
In the step (a)
The carrier substrate
An insulating core layer; And
A carrier copper layer sequentially deposited on the insulating core layer, and a plating seed layer
A method of manufacturing an embedded printed circuit board. 13. The method of claim 12,
(a)
Forming a resist pattern layer on the plating seed layer; And
And forming a plating pattern layer by a plating method using the plating seed layer
A method of manufacturing an embedded printed circuit board. 13. The method of claim 12,
wherein the cavity of step (c) exposes at least a portion of the first circuit pattern layer and the plating seed layer together
A method of manufacturing an embedded printed circuit board. 13. The method of claim 12,
and separating the carrier substrate and the first circuit pattern layer from each other in step (f)
(f1) separating the carrier copper layer and the plating seed layer from each other; And
(f2) removing the exposed plating seed layer by an etching method
A method of manufacturing an embedded printed circuit board. A first interlayer insulating layer having a first circuit pattern layer therein and including a cavity for selectively exposing at least a portion of the first circuit pattern layer;
A device chip disposed in the cavity and electrically insulated from the first circuit pattern layer by an insulating adhesive layer;
A second interlayer insulating layer disposed on the first interlayer insulating layer to cover the device chip; And
And a connection structure that is electrically connected to the device chip through the first circuit pattern layer under the device chip
Embedded printed circuit board. 17. The method of claim 16,
A second circuit pattern layer disposed on the first interlayer insulating layer; And
And a first via layer electrically connected to the first circuit pattern layer
Embedded printed circuit board. 17. The method of claim 16,
A third circuit pattern layer disposed on the second interlayer insulating layer; And
And a second via layer electrically connected to the second circuit pattern layer
Embedded printed circuit board. 17. The method of claim 16,
Wherein the insulating adhesive layer covers the first circuit pattern layer which is the bottom surface of the cavity,
And at least a portion of the first interlayer insulating layer which is the side wall portion of the cavity
Embedded printed circuit board. 17. The method of claim 16,
Wherein the connection structure is in contact with an electrode portion of the device chip and at least a part of the insulating adhesive layer
Embedded printed circuit board. 17. The method of claim 16,
Wherein the connection structure contacts the electrode part of the device chip and the connection pad layer of the first circuit pattern layer
Embedded printed circuit board. 17. The method of claim 16,
The connection structure may be a conductive bump structure including any one of a solder material layer, a copper post, and a stacked structure of a copper post and a solder layer
Embedded printed circuit board.

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