KR20150111529A - Cleaning composition applied to semiconductor device - Google Patents

Abstract

A cleaning composition applied to a semiconductor device is provided. The cleaning composition, as an etchant in a wet etching process applied in a substance pattern formed from a substance film through a dry etching process on a semiconductor silicon substrate, comprises, with respect to the total 100 wt%, 10-20 wt% of hydroxylamine, 5-20 wt% of hydrazine hydrate, 10-30 wt% of an organic solvent, and water.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a cleaning composition applied to a semiconductor device,

Embodiments according to the technical idea of the present invention relate to a cleaning composition applied to a semiconductor device.

Generally, a magnetoresistive random access memory (MRAM) has a larger storage capacity than a conventional dynamic RAM. To this end, the magnetoresistive memory is fabricated with magnetic tunnel junction (MTJ) structures corresponding to the capacitors of the dynamic memory. Thus, the magnitude of the volume of the magnetic tunnel junction structures affects the storage capacity of the magnetoresistive memory.

In this case, the magnetic tunnel junction structures are formed by applying a dry etching process on the magnetic tunnel junction film including the insulating layers (MgO) between the metal layers and the metal layers on the semiconductor silicon substrate. During the dry etching process, each of the magnetic tunnel junction structures has polymers on the sidewalls in response to a dry etch gas, metal layers and an insulating layer.

After the dry etching process is completed, the magnetic tunnel junction structures are subjected to a wet etching process with a cleaning solution containing an amine and an organic solvent. The cleaning solution may have a high etching rate or a low etching rate in order to remove the polymer from the magnetic tunnel junction structure depending on the content of amine and organic solvent.

Therefore, even when the contents of amine and organic solvent in the cleaning solution are appropriately controlled, the magnetic tunnel junction structures can be electrically short-circuited on the semiconductor substrate due to the polymer residue after application of the cleaning solution. In addition, the cleaning solution has a large etching rate for the insulating layer, which makes the pattern profile of the magnetic tunnel junction structure poor. The defective pattern profile of the magnetic tunnel junction structure can not have a constant storage capacity of the magnetoresistive memory.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method and apparatus for forming a pattern of a material including an insulating layer (MgO) in a multi-layered structure on a semiconductor silicon substrate by a dry etching process, To remove the polymers properly and to maintain a good pattern profile of the material pattern.

There is provided a cleaning composition applied to a semiconductor device according to embodiments of the present invention. Wherein the cleaning composition is an etchant of a wet etching process applied to the material pattern in a material pattern formed from a material film through a dry etching process on a semiconductor silicon substrate, % Of hydroxylamine, 5 to 20 wt.% Of hydrazine hydrate, 10 to 30 wt.% Of an organic solvent, and water, wherein the material film has a multi-layer structure, (MgO).

Wherein the organic solvent is at least one of diethylene glycol, dipropylene glycol, dibutylene glycol, ethylene glycol, propylene glycol, ethylene glycol monoethyl ether, dipropylene glycol methyl ether, ethylene glycol monopropyl ether, and tetraethylene glycol ether .

The cleaning composition comprising a surface active agent 0.001 to 0.1% by weight, further, the surfactant is ammonium fluoroalkyl sulfone _{imide, C n F 2n + 1 CH} 2 CH 2 SO 3 - NH 4 +, C n F 2n + 1 _{CH 2 CH 2 SO 3 H,} (C n F 2n + 1 CH 2 CH 2 O) x PO (ONH 4 +) y (OCH 2 CH 2 OH) z, C n F 2n + 1 CH 2 CH 2 O ( _{OCH 2 CH 2 OH) x H} , C n F 2n + 1 SO 2 n (C 2 H 5) (CH 2 CH 2) x H, C n F 2n + 1 CH 2 CH 2 OCH 2 (OH) CH 2 _{CH 2 N (C n F 2n} + 1) 2, and _{C n F 2n + 1 CH 2} CH 2 OCH 2 (OCH 2 CH 2) n CH 2 CH 2 N (C n F 2n + 1) at least one of the ₂ Wherein n is an integer of 1 to 20, and x, y and z satisfy x + y + z = 3.

The cleaning composition further comprises an ammonium salt in an amount of 0.01 to 10 wt%, wherein the ammonium salt includes at least one of ammonium persulfate, ammonium sulfate, ammonium chloride, ammonium phosphate, and ammonium nitride.

The cleaning composition further comprises an ammonium salt in an amount of 0.01 to 10 wt%, wherein the ammonium salt includes a compound having an ammonium ion in addition to ammonium persulfate, ammonium sulfate, ammonium chloride, ammonium phosphate, and ammonium nitride.

The material pattern may include a magnetic tunnel junction (MTJ) structure of a magnetoresistive random access memory (MRAM) including an antiferromagnet, a first ferromagnetic material, an insulator, a second ferromagnetic material and tungsten (W) And the insulator includes the magnesium oxide (MgO).

The material pattern is a cell string structure of a flash memory including a first insulator, a first conductor, a second insulator, a second conductor, and a third conductor, which are sequentially stacked. Wherein the cell string structure has a horizontal channel in the semiconductor substrate, the first insulator comprises the magnesium oxide (MgO), the second insulator comprises an insulating material different from the first insulator, The sieve and the second conductor comprise doped polysilicon, and the third conductor comprises a metal.

Wherein the material pattern includes a first insulation pattern, second insulation patterns having an annular shape cut out at one side of the first insulation pattern and sequentially positioned vertically and opening toward a side of the first insulation pattern, A cell string structure of a flash memory including a conductive pattern positioned in a first insulation pattern and sequentially positioned horizontally from second insulation patterns and a third insulation pattern, the cell string structure including a vertical channel Wherein one of the first and third insulation patterns comprises at least one of silicon oxide, silicon nitride and silicon oxynitride, each of the second insulation patterns including at least one of magnesium oxide (MgO) Wherein the conductive pattern comprises one of doped polysilicon and doped monocrystalline silicon.

As described above, the cleaning composition applied to the semiconductor device according to the embodiments of the present invention comprises 10 to 20% by weight of hydroxylamine, 5 to 20% by weight of hydrazine hydrate ), 10 to 30 wt% of an organic solvent, 0.001 to 0.1 wt% of a surfactant, and 0.01 to 10 wt% of an ammonium salt,

The cleaning composition can be applied to a pattern of material comprising an insulating layer (MgO) in a multi-layered structure on a semiconductor silicon substrate to remove the polymer well from the side walls of the patterned material.

The cleaning composition can be applied to a material pattern including an insulating layer (MgO) in a multi-layer structure on a semiconductor silicon substrate to maintain a good pattern profile of the insulating layer and other layers in the multi-layer structure.

1 is a schematic diagram showing a magnetoresistive memory according to embodiments of the present invention.
FIGS. 2 to 9 are cross-sectional views illustrating a method of forming a magnetic tunnel junction structure taken along a cutting line I-I 'in FIG.
10 is a circuit diagram showing one cell string having horizontal channels in the flash memory according to the embodiments of the present invention.
11 is a schematic diagram showing cell string structures in a first check area P of the cell string of FIG.
12 is a circuit diagram showing cell strings each having vertical channels in a flash memory according to embodiments of the present invention.
13 is a schematic diagram illustrating cell string structures in the cell strings of FIG.

Hereinafter, the semiconductor device according to the embodiments of the present invention and the cleaning composition applied to the semiconductor device will be sequentially described. However, the semiconductor device is limited to the magnetoresistive memory and the flash memory in the embodiments of the present invention, but may be extended to other memories.

1 is a schematic diagram showing a magnetoresistive memory according to embodiments of the present invention. In this case, the magnetoresistive memory is illustrated only by way of example without considering the influence of the semiconductor manufacturing process.

Referring to FIG. 1, a semiconductor device 110 according to embodiments of the present invention firstly refers to a magnetoresistive random access memory (MRAM). The magnetoresistive memory 110 includes magnetic tunnel junction structures 90 between the word lines 5 and the bit lines 100. The word lines 5 and bit lines 100 have a plurality of intersecting regions intersecting with each other.

The magnetic tunnel junction structures 90 are located in intersecting regions between the word lines 5 and the bit lines 100. Each of the magnetic tunnel junction structures 90 electrically connects one word line 5 and one bit line 100 through one crossing region. Each of the magnetic tunnel junction structures 90 includes a first material pattern 25, a second material pattern 35, a third material pattern 45, a fourth material pattern 55 and a fifth material pattern 65, Lt; RTI ID = 0.0 >

The first material pattern 25, the second material pattern 35, the third material pattern 45, the fourth material pattern 55 and the fifth material pattern 65 will be described in detail with reference to FIGS. 2 to 4 .

FIGS. 2 to 9 are cross-sectional views illustrating a method of forming a magnetic tunnel junction structure taken along a cutting line I-I 'in FIG. In this case, the method of forming the magnetic tunnel junction structure will be of interest only below the bit line. Further, the magnetic tunnel junction structure is shown in close proximity to the actual one in consideration of the influence of the semiconductor manufacturing process in order to explain the embodiments of the present invention in detail.

Referring to FIG. 2, a semiconductor base structure 10 is prepared. The semiconductor base structure 10 may include a semiconductor silicon substrate and a word line 5. The word line 5 is formed as a conductive layer. A first material layer 20 and a second material layer 30 are sequentially formed on the semiconductor base structure 10.

The first material layer 20 is a semi-magnetic material containing IrMn, PtMn, MnO, MnS, MnTe, MnF2, FeF2, FeCl2, FeO, CoCl2, CoO, NiCl2 or NiO. The second material layer 30 is a ferromagnetic material containing Fe, Co, Ni, Gd, Dy, NiFe, CoFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO or Y3Fe5O12.

Referring to FIG. 3, a third material layer 40 and a fourth material layer 50 are sequentially formed on the second material layer 30. The third material layer 40 is an insulator including magnesium oxide (MgO) to serve as a tunneling barrier between the second material layer 30 and the fourth material layer 50.

The fourth insulating film 40 is a ferromagnetic material including Fe, Co, Ni, Gd, Dy, NiFe, CoFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO or Y3Fe5O12.

Referring to FIG. 4, a fifth material layer 60 is formed on the fourth material layer 50. The fifth material layer 60 includes tungsten (W). Here, the fifth material layer 60 constitutes the material layer 70 together with the first to fourth material layers 20, 30, 40, and 50. Subsequently, photoresist patterns 75 are formed on the material film 70.

The photoresist patterns 75 have the same occupancy area as the magnetic tunnel junction structures 90 of FIG. 1 on the semiconductor base structure 10.

Referring to Fig. 5, a first dry etching process is applied on the material film 70 of Fig. More specifically, the first dry etching process uses the photoresist patterns 75 as the etch mask and the fourth material layer 50 as an etch buffer layer to etch the fifth material layer 60 of FIG. 4 can do.

The fifth material film 60 is etched using the first dry etching process to form the fifth preliminary material film patterns 65A. Here, the first dry etching process forms the first polymers 83 on the sidewalls of the fifth preliminary material film patterns 65A. The first polymers are a reactant of the fifth material film 60, the photoresist patterns 75, and the process gas of the first dry etching process.

The first dry etching process etches the edges between the sidewalls and the upper surfaces of the fifth preliminary material film patterns 65A to form round shapes between the sidewalls and the upper surfaces of the fifth preliminary material film patterns 65A .

Referring to FIG. 6, after the fifth preliminary film material patterns 65A are formed, the photoresist patterns 75 and the first polymers 83 of FIG. 5 are formed from the fifth preliminary film material patterns 65A Can be removed. More specifically, the photoresist patterns 75 and the first polymers 83 can be removed from the fifth pre-material film patterns 65A using a photoresist ashing process and a photoresist strip process .

Referring to FIG. 7, a second dry etching process is applied to the third material film 40, the fourth material film 50, and the fifth preliminary material film pattern 65A in FIG. More specifically, the second dry etching process uses the fifth preliminary material film patterns 65A as an etch mask and the second material film 30 as an etch buffer film to form the fourth material film 50 and the 3 material film 40 can be sequentially etched.

The third material layer 40 and the fourth material layer 50 are etched using the second dry etching process to form the third material patterns 45 and the fourth material patterns 55. Here, the second dry etching process may form the fifth material film pattern 65B by partially etching the fifth preliminary material film patterns 65A.

The second dry etching process may further include forming a third material film 40 and a fourth material film 40B during the etching of the third material film 40, the fourth material film 50 and the fifth preliminary material film pattern 65A. 50 and the fifth preliminary material film pattern 65A are reacted with the process gas to form second material patterns 45 on the sidewalls of the fourth material patterns 55 and the fifth material film patterns 65B Polymers 86 can be formed.

The third material patterns 45 and the fourth material patterns 55 are formed on the semiconductor base structure 10 using the second polymers 86 while the second dry etching process is being performed, (65B). In addition, the second dry etching process may etch the edges between the sidewalls and top surfaces of the fourth material patterns 55 to form round shapes between the sidewalls and top surfaces of the fourth material patterns 65A .

Referring to FIG. 8, a third dry etching process is applied to the first material 20 film, the second material film 30, and the fifth material film pattern 65B in FIG. More specifically, the third dry etching process uses the fifth material film patterns 65B and the second polymers 86 as an etch mask and the semiconductor base structure 00 as an etch buffer film, The film 30 and the first material film 20 can be sequentially etched.

The first material layer 20 and the second material layer 30 are etched using the third dry etching process to form the first material patterns 25 and the second material patterns 35. Here, the third dry etching process may form the fifth material pattern 65 by partially etching the fifth material film patterns 65B.

The third dry etching process may further include a first material film 20 and a second material film 30B during the etching of the first material film 20, the second material film 30 and the fifth material film pattern 65B. And the fifth material film pattern 65B are reacted with the process gas to form the first material pattern 25, the second material pattern 35, the third material pattern 45, the fourth material pattern 55 And the third polymers 89 on the sidewalls of the fifth material patterns 65.

During the third dry etching process, the first material patterns 25 and the second material patterns 35 are formed on the semiconductor base structure 10 using the third polymers 89, 45 and the fourth material pattern 55. In this case,

In addition, the third dry etching process may etch the edges between the sidewalls and top surfaces of the second material patterns 35 to form round shapes between the sidewalls and top surfaces of the second material patterns 55 . The first material patterns 25, the second material patterns 35, the third material patterns 45, the fourth material patterns 55 and the fifth material patterns 65 are formed on the material pattern 90, .

Referring to FIG. 9, after the material patterns 90 are formed, the first material patterns 25, the second material patterns 35, the third material patterns 45, the fourth material patterns 55 ) And the fifth material pattern 65 are subjected to a wet etching process. The wet etch process is performed to remove the first material patterns 25, the second material patterns 35, the third material patterns 45, the fourth material patterns 55, The third polymers 89 can be removed.

The wet etch process may comprise 10 to 20 wt% hydroxylamine, 5 to 20 wt% hydrazine hydrate, 10 to 30 wt% organic solvent, 0.001 to 0.1 wt% By weight of a surfactant, and 0.01 to 10% by weight of an ammonium salt.

Wherein the organic solvent is at least one of diethylene glycol, dipropylene glycol, dibutylene glycol, ethylene glycol, propylene glycol, ethylene glycol monoethyl ether, dipropylene glycol methyl ether, ethylene glycol monopropyl ether, and tetraethylene glycol ether .

Wherein the surfactant is ammonium fluoroalkyl sulfone _{imide, C n F 2n + 1 CH} 2 CH 2 SO 3 - NH 4 +, C n F 2n + 1 CH 2 CH 2 SO 3 H, (C n F 2n + 1 CH ₂ CH ₂ O) _x PO (ONH ₄ ⁺ ) _y (OCH ₂ CH ₂ OH) _z , C _n F _{2n + 1} CH ₂ CH ₂ O (OCH ₂ CH ₂ OH) _x H, C _n F _{2n + 2 n (C 2 H 5)} (CH 2 CH 2) x H, C n F 2n + 1 CH 2 CH 2 OCH 2 (OH) CH 2 CH 2 n (C n F 2n + 1) 2, and C _n and _{F 2n + 1 CH 2 CH 2} OCH 2 (OCH 2 CH 2) n CH 2 CH 2 and N includes at least one of _{(C n F 2n + 1)} 2 ( stage, wherein n is an integer from 1 to 20, X, y and z satisfy x + y + z = 3).

The ammonium salt includes at least one of ammonium persulfate, ammonium sulfate, ammonium chloride, ammonium phosphate, and ammonium nitride. However, the ammonium salt may include a compound having an ammonium ion in addition to ammonium persulfate, ammonium sulfate, ammonium chloride, ammonium phosphate, and ammonium nitride.

In the cleaning composition, if the hydroxylamine and the hydrazine hydrate have 10 to 20% by weight and 5 to 20% by weight, the hydroxylamine and hydrazine hydrate react with the material pattern 90 to generate the first material pattern The third polymers 89 from the side walls of the first material patterns 25, the second material patterns 35, the third material patterns 45, the fourth material patterns 55 and the fifth material patterns 65 Thereby contributing to easy removal.

Thus, if the hydroxylamine and the hydrazine hydrate have 10 to 20 wt% and 5 to 20 wt%, the hydroxylamine and hydrazine hydrate may form a material pattern 90 Only the third polymers 89 are removed.

In this case, if the hydroxylamine and the hydrazine hydrate are out of the range of 10 to 20 wt% and 5 to 20 wt%, the hydroxylamine and hydrazine hydrate may form a third material pattern 45 containing magnesium oxide (MgO) Or the etch rate for the third polymers 89 may be small.

In addition, in the cleaning composition, if the organic solvent has 10 to 30 wt%, the organic solvent prevents damage to the third material pattern 45 including magnesium oxide (MgO) in the material pattern 90 And is mixed well with water to improve the wetting property, thereby increasing the removal efficiency of the third polymers 89.

In this case, if the amount of the organic solvent is 10 wt% or less, the first material pattern 25, the second material pattern 35, the fourth material pattern 55, and the fifth material pattern 65 And at least 20% by weight of the organic solvent reduces the solubility of the hydroxylamine and the hydrazine hydrate, thereby reducing the removal efficiency of the third polymers 89.

In addition, if the surfactant is less than 0.001 wt%, the surfactant is less abundant in the cleaning composition and does not reduce the surface tension of the cleaning composition, thereby reducing the reaction of the cleaning composition with the third polymers 89. If the amount of the surfactant is 0.001% by weight or more, the surfactant does not decrease the surface tension of the cleaning composition and causes excessive foam in the cleaning composition, which is difficult to use.

Then, if the ammonium salt is less than or equal to 0.01 wt.%, Or more than 10 wt.%, The ammonium salt will form the first material pattern 25, the second material pattern 35, the fourth material pattern 55, 5 can not prevent corrosion of the material patterns 65.

10 is a circuit diagram showing one cell string having horizontal channels in the flash memory according to the embodiments of the present invention.

Referring to FIG. 10, a flash memory according to embodiments of the present invention has a plurality of cell strings (CSTRs). In this case, the cell strings CSTR have the same circuit configuration. Therefore, in this figure, only one of the cell strings (CSTR) is described.

The cell string CSTR includes two ground selection transistors GST and two string selection transistors SST and a memory cell transistor MCT between the ground selection transistors GST and the string selection transistors SST. ). The ground selection transistors GST, the memory cell transistors MCT and the string selection transistors SST are electrically connected in series to each other.

The ground selection transistors GST, the memory cell transistors MCT and the string selection transistors SST are electrically connected to the ground selection line GSL, the gate lines GL and the string selection line SSL. The cell string CSTR is electrically grounded through the ground selection transistors GST and is electrically connected to the bit line BL through the string selection transistors SST. That is, each of the cell strings CSTR corresponds to one bit line BL.

11 is a schematic diagram showing cell string structures in a first check area P of the cell string of FIG. In this case, the cell string structures are shown with the exception of the bit lines in FIG. In addition, the cell string structures are illustratively shown only to illustrate embodiments of the present invention without considering the effects of the semiconductor manufacturing process. In addition, the cell string structures exhibit a pattern profile after application of the cleaning composition of FIG.

Referring to FIG. 11, the cell string structures CSTR-S1 are formed on a semiconductor silicon substrate 120 by a word line WL corresponding to the ground selection line GSL and the gate line GL of the cell strings CSTRs of FIG. . The cell string structures CSTR-S1 include active regions 123 and device isolation films 126 on a semiconductor silicon substrate 120. [ The active regions 123 are electrically separated from the semiconductor silicon substrate 120 by the device isolation films 126.

The cell string structures CSTR-S1 include a first material layer 130, a second material pattern 140, a third material pattern 150, a fourth material pattern 160, And fifth material patterns 170, as shown in FIG. The first material layer 130, the second material patterns 140, the third material pattern 150, the fourth material pattern 160 and the fifth material pattern 170 constitute material patterns 175 .

The first material layer 130, the second material pattern 140, the third material pattern 150, the fourth material pattern 160 and the fifth material pattern 170 are formed on the semiconductor silicon substrate 120 10 ground select transistor (GST) and memory cell transistors (MCT). In this case, the first material layer 130 is a first insulator including magnesium oxide (MgO). The first material layer 130 acts as a tunneling barrier between the semiconductor silicon substrate 120 and the second material patterns 140.

The second material patterns 140 are first conductors comprising doped polysilicon. The second material patterns 140 serve as floating gates. The third material patterns 150 are a second insulator including a first insulator and a second insulator. The fourth material patterns 160 are second conductors comprising doped polysilicon. The fourth material patterns 160 serve as control gates (CG).

The fifth material patterns 170 are third conductors including a metal. The cell string structure (CSTR-S1) has horizontal channels below the material patterns 175 in the semiconductor silicon substrate 120. Again, the material patterns 175 have polymers on the sidewalls because they are formed by applying at least one dry etching process to a multi-layered material film. However, the material patterns 175 do not have the polymers (not shown in the drawings) on the sidewalls to which the cleaning composition of FIG. 9 is applied in the wet etching process.

Accordingly, the cleaning composition does not damage the first material layer 130 including magnesium oxide (MgO) even after performing the wet etching process. The cleaning composition also does not damage the second material patterns 140, the third material pattern 150, the fourth material pattern 160, and the fifth material pattern 170. Thus, the material patterns 175 have the same pattern profile before and after the wet etching process.

12 is a circuit diagram showing cell strings each having vertical channels in a flash memory according to embodiments of the present invention.

Referring to FIG. 12, a flash memory according to embodiments of the present invention has a plurality of cell strings (CSTRs). In this case, the cell strings CSTR have the same circuit configuration. In the figure, the two cell strings CSTR are connected to one bit line BL.

Each of the cell strings CSTR has a structure similar to the cell string of FIG. More specifically, each of the cell strings CSTR in FIG. 11 includes one ground selection transistor GST and one string selection transistor SST, a ground selection transistor GST and a string selection transistor SST, And memory cell transistors (MCTs).

The ground selection transistor GST, the memory cell transistors MCT and the string selection transistor SST are electrically connected in series to each other. Each of the ground selection transistor GST, the memory cell transistors MCT and the string selection transistor SST is electrically connected to the gate line GL.

13 is a schematic diagram illustrating cell string structures in the cell strings of FIG. In this case, the cell string structures are shown with the exception of the gate lines and bit lines of FIG. In addition, the cell string structures are illustratively shown only to illustrate embodiments of the present invention without considering the effects of the semiconductor manufacturing process. In addition, the cell string structures exhibit a profile after application of the cleaning composition of FIG.

Referring to FIG. 13, the cell string structures CSTR-S2 are formed on the semiconductor silicon substrate 180 to vertically locate the word lines corresponding to the gate lines GL of the cell strings CSTRs of FIG. 12 Structures. The cell string structures CSTR-S2 include a diffusion region 190 in the semiconductor silicon substrate 120. The diffusion regions 190 are prepared for the source region or the drain region of the ground selection transistor GST of FIG. 12 in the semiconductor silicon substrate 120.

In this figure, the cell string structures (CSTR-S2) further include material patterns 240, 250 on a semiconductor silicon substrate 120. Each of the material patterns 240 and 250 includes a first material pattern 200, a second material pattern 210, a third material pattern 220 and a fourth material pattern 230. In this case, each of the material patterns 240 and 250 may receive the two cell strings CSTR0 and CSTR1 of FIG.

In order to illustrate the acceptance of the two cell strings CSTR0 and CSTR1, each of the material patterns 240 and 250 includes a rectangular first material pattern 200, a first material pattern 200, The second material patterns 210 are sequentially opened vertically with an annular shape cut in the first material pattern 200 and are opened toward both sides of the first material pattern 200, And third material patterns 220 and fourth material patterns 230 that are sequentially horizontally positioned from the second material patterns 210.

The first material pattern 210 is an insulating pattern including at least one of silicon oxide, silicon nitride, and silicon oxynitride. The second material patterns 220 are insulating patterns including magnesium oxide (MgO). The third material patterns 230 are conductive patterns including one of doped polysilicon and doped single crystal silicon.

The fourth material pattern 240 is an insulating pattern including at least one of silicon oxide, silicon nitride, and silicon oxynitride. Here, the cell string structures CSTR-S2 have vertical channels of the transistors GST, MCT, and SST of FIG. 13 in the third material patterns 220.

The cell string structures CSTR-S2 are arranged in the order of the word lines corresponding to the gate lines GL of the ground selection transistors GST at the first level L1, which is the lowest level of the first material patterns 210, 2 material patterns 210 and word lines corresponding to the gate lines GL of the string selection transistors SST at the fourth level L4, which is the uppermost level of the first material patterns 210, 2 < / RTI > material patterns 210 as shown in FIG.

In addition, the cell string structures CSTR-S2 may include word lines corresponding to the gate lines GL of the cell memory transistors in the second material pattern 210 between the first level L1 and the fourth level L4, Lt; / RTI > Here, since the material patterns 240 and 250 are formed by applying dry etching processes to a plurality of material films (not shown in the figure), the first material patterns 210 and the second material patterns 220 Polymers (not shown in the figure) are formed on the sidewalls.

Specifically, when the second material patterns 220 are exposed from the first material pattern 200, a wet etching process is applied to the material patterns 240 and 250 for removal of the polymers. The wet etch process may remove the polymers from the sidewalls of the first material pattern 210 and the second material pattern 220 using the cleaning composition of FIG.

The cleaning composition does not damage the second material patterns 210 including magnesium oxide (MgO) even after performing the wet etching process. The cleaning composition also does not damage the first material patterns 200, the third material patterns 220, and the fourth material patterns 230. Accordingly, the material patterns 240 and 250 have the same pattern profile before and after the wet etching process.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

5; Word line, 25; The first material pattern
35; Second material pattern, 45; Third material pattern
55; A fourth material pattern, 65; Fifth material pattern
90; Magnetic tunnel junction structure, 100; Bit line
110; Magnetoresistive memory.

Claims (8)

In a material pattern formed from a material film through a dry etching process on a semiconductor silicon substrate,
As an etchant of a wet etching process applied to the material pattern,
Wherein the composition comprises 10 to 20 wt% hydroxylamine, 5 to 20 wt% hydrazine hydrate, 10 to 30 wt% organic solvent, and water in a total amount of 100 wt%
Wherein the material layer comprises a multi-layer structure, wherein the multi-layer structure comprises magnesium oxide (MgO). The method according to claim 1,
Wherein the organic solvent is at least one of diethylene glycol, dipropylene glycol, dibutylene glycol, ethylene glycol, propylene glycol, ethylene glycol monoethyl ether, dipropylene glycol methyl ether, ethylene glycol monopropyl ether, and tetraethylene glycol ether ≪ / RTI > The method according to claim 1,
Further comprising 0.001 to 0.1% by weight of a surfactant,
Wherein the surfactant is ammonium fluoroalkyl sulfone _{imide, C n F 2n + 1 CH} 2 CH 2 SO 3 - NH 4 +, C n F 2n + 1 CH 2 CH 2 SO 3 H, (C n F 2n + 1 CH ₂ CH ₂ O) _x PO (ONH ₄ ⁺ ) _y (OCH ₂ CH ₂ OH) _z , C _n F _{2n + 1} CH ₂ CH ₂ O (OCH ₂ CH ₂ OH) _x H, C _n F _{2n + 2 N (C 2 H 5)} (CH 2 CH 2) x H, C n F 2n + 1 CH 2 CH 2 OCH 2 (OH) CH 2 CH 2 N (C n F 2n + 1) 2, and C _n And at least one of F _{2n + 1} CH ₂ CH ₂ OCH ₂ (OCH ₂ CH ₂ ) _n CH ₂ CH ₂ N (C _n F _{2n + 1} ) ₂ ,
Wherein n is an integer from 1 to 20, and x, y and z satisfy x + y + z = 3. The method according to claim 1,
0.01 to 10% by weight of an ammonium salt,
Wherein the ammonium salt comprises at least one of ammonium persulfate, ammonium sulfate, ammonium chloride, ammonium phosphate, and ammonium nitride. The method according to claim 1,
0.01 to 10% by weight of an ammonium salt,
Wherein the ammonium salt comprises a compound having an ammonium ion in addition to ammonium persulfate, ammonium sulfate, ammonium chloride, ammonium phosphate, and ammonium nitride. The method according to claim 1,
The material pattern may include a magnetic tunnel junction (MTJ) structure of a magnetoresistive random access memory (MRAM) including an antiferromagnet, a first ferromagnetic material, an insulator, a second ferromagnetic material and tungsten (W) Respectively,
Wherein the insulator comprises the magnesium oxide (MgO). The method according to claim 1,
The material pattern is a cell string structure of a flash memory including a first insulator, a first conductor, a second insulator, a second conductor, and a third conductor, which are sequentially stacked.
The cell string structure having a horizontal channel in the semiconductor substrate,
Wherein the first insulator comprises the magnesium oxide (MgO)
Wherein the second insulator comprises an insulating material different from the first insulator,
Wherein the first conductor and the second conductor comprise doped polysilicon, and
Wherein the third conductor comprises a metal. The method according to claim 1,
Wherein the material pattern includes a first insulation pattern, second insulation patterns having an annular shape cut out at one side of the first insulation pattern and sequentially positioned vertically and opening toward a side of the first insulation pattern, A cell string structure of a flash memory including a conductive pattern positioned in a first insulation pattern and sequentially horizontally positioned sequentially from second insulation patterns and a third insulation pattern,
The cell string structure having a vertical channel in the conductive pattern,
Wherein one of the first insulating pattern and the third insulating pattern includes at least one of silicon oxide, silicon nitride, and silicon oxynitride,
Wherein each of the second insulation patterns includes the magnesium oxide (MgO)
Wherein the conductive pattern comprises one of doped polysilicon and doped monocrystalline silicon.

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