KR20150102793A - Frequency Synthesizer and Phase synchronizing control device based on initial phase offsetting - Google Patents

Abstract

Disclosed are a frequency synthesizer and a phase synchronizing control device for the same. The frequency synthesizer, which includes a voltage control oscillator, a phase frequency detector, a charge pump, a loop filter, and a divider, includes an initial phase setting device which calculates an optical initial phase offset by using a difference value between a target frequency and a start frequency, which is a digitized output frequency feed-backed by the voltage control oscillator; and outputs a control signal for synchronizing the phase of the phase frequency detector in a closed-loop state by using the optimal initial phase offset.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an initial phase adjusting frequency synthesizer,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an RF frequency synthesizer based on a phase locked loop (PLL) and a phase synchronization controller for a frequency synthesizer.

An RF frequency synthesizer is a device that generates a signal of a predetermined frequency and is an essential element circuit in a wireless communication transceiver. The RF frequency synthesizer is generally implemented in a phase-locked loop (PLL) manner, and the synchronization time of the PLL is determined by the loop bandwidth. To reduce the synchronization time of the PLL, loop bandwidth switching technology is widely used.

1 is a diagram schematically showing a structure of a conventional PLL-based frequency synthesizer.

Referring to FIG. 1, a PLL-based frequency synthesizer includes a phase frequency detector (PFD) 110, a charge pump (CP) 115, a loop filter A frequency control oscillator (VCO) 125, and a frequency divider (hereinafter referred to as a frequency divider) (hereinafter, referred to as a frequency divider) 130).

The PFD 110 and the CP 115 detect the difference between the reference frequency f _R and f _V and output a charge pulse, which adjusts the output frequency of the VCO via the LPF 120.

The frequency divider 130 divides the output frequency f _VCO of the _VCO 125 by a division ratio N and outputs a signal having a frequency of f _V.

In general, an initial phase offset (hereinafter referred to as " _offset "), which is an input signal of the PFD 110, greatly affects the synchronization time of the PLL. The initial phase offset? _Offset is obtained by multiplying the reference frequency f _ref applied to the PFD 110 when the PLL starts synchronization in the closed loop state and the signal f _div fed back after the VCO signal is divided by N, Lt; / RTI >

2 is a diagram for explaining pulse generation according to three states of an initial phase offset (? _Offset ). 2 (a) depicts the case where the initial phase offset _{(? Offset) 0, (b} ) will showing an initial phase offset (? _Offset) in this case positive value, (c) is the initial phase offset ( ? _offset ) is a negative value.

As with the 2 (a), when the initial phase offset _{(? Offset) 0, UP /} DN does pulses from occurring, if the initial phase offset (? _Offset) value of the amount of as in (b) UP pulse is First, when the initial phase offset (? _Offset ) is negative as shown in (c), it can be seen that the DN pulse is generated first.

With the above three pulses, the initial movement direction of the VCO tuning voltage is determined. For example, if f _div is f _ref initial phase offset in a situation than (? _Offset) it is or negative value of the initial phase offset is f _div in large situation than f _ref (? _Offset) value is a positive, a synchronized action initial The UP and DN pulses are generated opposite to the desired result, and the VCO frequency change direction is output in the opposite direction of the desired result. This causes undesired undershoot or overshoot of the VCO frequency during PLL synchronous operation, resulting in a problem of slowing down the synchronization time of the PLL.

The present invention provides a frequency synthesizer capable of quickly controlling a phase synchronization time by performing phase synchronization of a frequency synthesizer using a phase difference between a start frequency of a frequency synthesizer and a target frequency, and a phase synchronization control apparatus therefor.

According to an aspect of the present invention, there is provided a frequency synthesizer capable of rapidly controlling a phase synchronization time by performing phase synchronization of a frequency synthesizer using a phase difference between a start frequency of a frequency synthesizer and a target frequency, and a phase synchronization control device therefor do.

According to an embodiment of the present invention, there is provided an apparatus for controlling phase synchronization of a PLL-based frequency synthesizer including a voltage controlled oscillator, a phase frequency detector, a charge pump, a loop filter, and a frequency divider, A frequency-to-digital converter for outputting a start frequency obtained by converting the digital value into a digital value; A calculation unit for calculating an optimal initial phase offset using a phase difference value between the target frequency and the start frequency; And a controller for outputting a control signal for phase synchronization of the frequency synthesizer in a closed loop state using the optimum initial phase offset.

A first edge detector for outputting a first control signal for activating the operation of the phase frequency detector when the first rising edge of the reference frequency is detected in the closed loop state; A programmable counter for generating a phase difference corresponding to an output frequency fed back by the voltage controlled oscillator using the optimal initial phase offset; And a second edge detector for outputting a second control signal for resetting the frequency divider after a phase difference generated by the programmable counter.

The programmable counter may adjust the phase difference by counting the feedback frequency according to a set value corresponding to the optimal initial phase offset.

The controller may further include a phase-to-digital converter for converting the optimal initial phase offset to a digital value, and the phase-to-digital converter may adjust the set value of the programmable counter using the converted digital value.

If the difference value is a positive value, the setting value may be a value calculated such that the rising edge of the feedback output frequency is generated later than the second rising edge of the reference frequency by the optimum initial phase offset.

If the difference value is a negative value, the setting value may be a value calculated so that the rising edge of the feedback output frequency is generated earlier than the second rising edge of the reference frequency as the optimum initial phase offset.

According to another embodiment of the present invention, there is provided a frequency synthesizer including a voltage controlled oscillator, a phase frequency detector, a charge pump, a loop filter, and a frequency divider, And an initial phase setter for calculating an optimal initial phase offset using the phase difference value between the frequency and the target frequency and outputting a control signal for phase synchronization of the phase frequency detector in the closed loop state using the optimal initial phase offset A frequency synthesizer may be provided.

The start frequency is an output frequency fed back from the voltage controlled oscillator in an open loop state.

Wherein the initial phase setter comprises: a frequency-to-digital converter for outputting a start frequency obtained by converting an output frequency fed back by the voltage-controlled oscillator into a digital value; A calculation unit for calculating an optimal initial phase offset using a phase difference value between the target frequency and the start frequency; And a first edge detector for outputting a first control signal for activating the phase frequency detector when the first rising edge of the reference frequency is detected in the closed loop state; A programmable counter for generating a phase difference corresponding to an output frequency fed back by the voltage controlled oscillator using the optimal initial phase offset; And a second edge detector for outputting a second control signal for resetting the frequency divider after a phase difference generated by the programmable counter.

The optimal initial phase offset is calculated using the following equation,

는 최적의 초기위상오프셋을 나타내고,

는 목표주파수와 시작주파수의 차이값을 나타내고,

는 기울기에 해당하는 비례상수이며,

은

가 0일 때 기본적으로 요구되는 위상오프셋값을 나타낸다.here,

Lt; / RTI > represents the optimal initial phase offset,

Represents the difference value between the target frequency and the start frequency,

Is a proportional constant corresponding to the slope,

silver

Represents a phase offset value basically required when the value of the phase offset is zero.

The frequency synthesizer according to the embodiment of the present invention and the synchronization time controller for the frequency synthesizer according to an embodiment of the present invention can perform phase synchronization of the frequency synthesizer using the difference between the start frequency and the target frequency of the frequency synthesizer, There is an advantage.

1 is a block diagram illustrating an internal configuration of a conventional PLL-based frequency synthesizer
FIG. 2 is a diagram illustrating pulse generation according to three states of an initial phase offset (? _Offset ); FIG.
3 is a block diagram schematically illustrating an internal configuration of a PLL-based frequency synthesizer according to an embodiment of the present invention;
4 is a graph illustrating a simulation result of a synchronization time of a PLL according to an initial phase offset according to an embodiment of the present invention.
5 is a graph illustrating an optimal initial phase offset according to a difference between a start frequency and a target frequency in PLL synchronization according to an embodiment of the present invention.
6 illustrates an internal configuration of an initial phase setter according to an embodiment of the present invention.
FIG. 7 is a diagram comparing a VCO tuning voltage, a signal timing, and a synchronization time with a conventional case when a target frequency according to an embodiment of the present invention is larger than a start frequency; FIG.
FIG. 8 is a diagram comparing a VCO tuning voltage, a signal timing, and a synchronization time with a conventional case when a target frequency according to an embodiment of the present invention is smaller than a start frequency.
9 is a diagram illustrating a simulation result for explaining a phase synchronization process according to an initial phase offset according to an embodiment of the present invention.
10 is a graph comparing phase synchronization according to an initial phase offset according to an embodiment of the present invention and synchronization time of a PLL frequency synthesizer according to a conventional method.

The present invention is capable of various modifications and various embodiments, and specific embodiments are illustrated and described in the drawings. It is to be understood, however, that the invention is not to be limited to the specific embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a block diagram schematically illustrating an internal configuration of a PLL-based frequency synthesizer according to an embodiment of the present invention. FIG. 4 is a diagram illustrating a synchronization time of a PLL according to an initial phase offset according to an exemplary embodiment of the present invention. FIG. 5 is a graph illustrating an optimal initial phase offset according to a difference between a start frequency and a target frequency in PLL synchronization according to an embodiment of the present invention. FIG. 7 is a view for comparing a VCO tuning voltage, a signal timing, and a synchronization time with the conventional case when a target frequency according to an embodiment of the present invention is larger than a start frequency , FIG. 8 is a diagram comparing the VCO tuning voltage, the signal timing, and the synchronization time with the conventional case when the target frequency is smaller than the start frequency according to an embodiment of the present invention, FIG. 10 is a diagram illustrating a phase synchronization according to an initial phase offset according to an embodiment of the present invention. FIG. 10 is a diagram illustrating a phase synchronization according to an initial phase offset according to an embodiment of the present invention, Of the PLL frequency synthesizer according to the second embodiment of the present invention.

3, a PLL-based frequency synthesizer 300 according to an exemplary embodiment of the present invention includes an initial phase offsetting (IPO) 310, a phase frequency detector 315, a charge pump 320, A filter 325, a voltage controlled oscillator 330, and a frequency divider 335.

The initial phase setter 310 is a means for locating and setting the optimal initial phase offset. The initial phase setter 310 calculates an optimal initial phase offset using the difference between the start frequency and the target frequency of the voltage controlled oscillator 330 and outputs it to the phase frequency detector 315 and the frequency divider 335 .

The synchronization time of the PLL is not the fastest when the initial phase offset is 0 °. For this purpose, a PLL frequency synthesizer is designed and simulated using a 0.18um CMOS process, and the result is shown in FIG.

That is, FIG. 4 is a graph showing a simulation result of a PLL synchronization time according to a change of an initial phase offset. As simulation results when a PLL output frequency value changes from 1031 MHz to 1040 MHz, 35 °, 70 °, and 105 °.

It can be seen that the initial phase offset having the fastest synchronization time in the above four cases is 70 °. That is, in the case of 0 ° and 35 °, the target frequency is slowly reached, whereas in case of 105 °, the time for reaching the target frequency is delayed because the overshoot of the frequency change is large.

That is, it can be seen that the optimal initial phase offset that minimizes the synchronization time of the PLL is determined by the difference between the target frequency and the start frequency.

FIG. 5 is a graph showing an optimal initial phase offset according to a difference between a start frequency and a target frequency in PLL synchronization, and an optimal initial phase offset is obtained in most regions except a case where there is little difference between a start frequency and a target frequency Linear relationship.

Accordingly, the initial phase setter 310 according to an exemplary embodiment of the present invention uses the above-described characteristic to calculate the optimal initial phase offset using the difference between the start frequency f _initial and the target frequency f _target 1 can be calculated as follows.

는 최적의 초기위상오프셋을 나타내고,

는 목표주파수와 시작주파수의 차이(즉,

)를 나타내고,

는 기울기에 해당하는 비례상수로,

에 대한

의 민감도를 나타낸다. 또한,

은

가 0일 때 기본적으로 요구되는 위상 오프셋 값을 나타낸다.

과

은 루프대역폭이나 전하펌프 이득 등 PLL 구조 및 동작 변수에 따라 달라질 수 있는 실험적인 값이다. 그러나 동일한 PLL에서는 일정한 관계식이 유지되므로, 실제 PLL에 적용하는 경우 실험적 또는 이론적으로 적절한 값을 찾은 후 적용될 수 있다.here,

Lt; / RTI > represents the optimal initial phase offset,

( I.e., the difference between the target frequency and the start frequency)

) ,

Is a proportional constant corresponding to the slope,

For

. Also,

silver

Represents a phase offset value basically required when the value of the phase offset is zero.

and

Is an experimental value that can vary depending on PLL structure and operating parameters such as loop bandwidth or charge pump gain. However, since a constant relation is maintained in the same PLL, when applied to an actual PLL, it can be applied after finding an appropriate value experimentally or theoretically.

As described above, the initial phase setter 310 has an advantage of improving the synchronization time of the PLL by finding and setting an optimal initial phase offset using the difference between the target frequency and the start frequency.

6 shows an internal configuration of the initial phase setter.

The detailed operation of the initial phase setter 310 will be described with reference to FIG.

6, the initial phase setter 310 includes a frequency-to-digital converter (FDC) 610, a first calculator 615, a second calculator 620, a phase- A phase-to-digital converter (PDC) 625, a programmable counter 630, a first edge detector 635, and a second edge detector 640.

First, the frequency-to-digital converter 610 converts the current frequency value (i.e., the feedback output frequency) of the voltage-controlled oscillator to a digital value in an open loop before the PLL performs the closed loop phase synchronization. Here, the value obtained by converting the current frequency (feedback output frequency) of the voltage-controlled oscillator into a digital value corresponds to the start frequency ( f _initial ) of the PLL frequency synthesizer 300. Hereinafter, the feedback output frequency value of the voltage-controlled oscillator is converted into a digital value by the frequency-to-digital converter 610 and the output value is referred to as a start frequency f _initial .

The frequency-to-digital converter 610 outputs the start frequency f _initial to the first calculator 615.

The first calculator 615 calculates the difference between the _target frequency f _target and the start frequency and outputs the result to the second calculator 620. Here, the first calculator 615 may be an adder / subtracter.

)와 기본 위상 오프셋값(

) 및 제1 계산기(615)를 통해 입력된 차이값을 이용하여 최적의 초기위상오프셋을 도출할 수 있다. 제2 계산기(620)는 이와 같이 도출된 초기위상오프셋을 위상-디지털 변환기(625)로 출력한다.The second calculator 620 calculates the proportionality constant of the gradient (

) And the basic phase offset value (

) And the first calculator 615, the optimal initial phase offset can be derived. The second calculator 620 outputs the thus obtained initial phase offset to the phase-to-digital converter 625.

)를 곱한 후 기본 위상 오프셋값(

)을 더하여 최적의 초기위상오프셋을 도출할 수 있다.For example, the second calculator 620 may calculate the proportional constant of the slope (the difference value) input through the first calculator 615

) And then multiplies the basic phase offset value (

) Can be added to obtain an optimal initial phase offset.

The phase-to-digital converter 625 converts the phase of the initial phase offset inputted through the second calculator 620 into a digital value and outputs it to the programmable counter 630.

The set value of the programmable counter 630 can be adjusted by the initial phase offset converted into the digital value by the phase-to-digital converter 625. [

The set value of the programmable counter 630 may be adjusted to adjust the time at which the first rising edge of the applied frequency f _div is N-divided by the frequency divider 335 and fed back. Here, the frequency f _div represents a frequency obtained by dividing the output frequency fed back by the voltage-controlled oscillator by N divided by a frequency divider (hereinafter, referred to as a divided output frequency).

This allows the first rising edge of the divided output frequency ( f _div ) and the second rising edge of the reference frequency ( f _ref ) to be widened by an initial phase offset (? _Offset ).

The time for generating the first control signal EN _PFD and the second control signal RST _DIV , which are active signals of the phase frequency detector 315 and the frequency divider 335, can be adjusted through such adjustment.

The operation of the frequency synthesizer will be described by dividing the difference value between the target frequency and the start frequency calculated by the initial phase setter 310 into a positive value and a negative value, respectively.

If the difference between the target frequency and the start frequency is a positive value

)이 양의값이라는 것은 결과적으로 목표주파수가 시작주파수보다 큰 것을 의미한다. 이는 도 7의 (a)와 같이, VCO 주파수가 증가되어야 하므로 VCO 튜닝전압이 올라가야 하는 것을 의미한다. Difference between target frequency and start frequency (

) Is a positive value means that the target frequency is larger than the start frequency. This means that the VCO tuning voltage should be increased since the VCO frequency should be increased as shown in FIG. 7 (a).

로 설정되고, PLL 루프는 개방되게 된다. When the operation of the PLL frequency synthesizer 300 is started, the first switch 327a is short-circuited and the second switch 327b is opened so that the VCO tuning voltage

And the PLL loop is opened.

In this state, the initial phase setter 310 can extract a start frequency ( f _initial ) value obtained by converting an output frequency of the VCO to a digital value through an internal frequency-to-digital converter 610. The initial phase setter 310 derives the optimal initial phase offset using the extracted starting frequency value and the externally inputted target frequency, converts the phase into a digital value through the phase-to-digital converter 625, It is possible to adjust the setting value of the display unit 630.

Thereby, the first switch 327a is opened and the second switch 327b is short-circuited so that the PLL frequency synthesizer 300 is changed to the closed loop state. The initial phase setter 310 generates the first control signal EN _PFD and outputs the first control signal EN _PFD to the phase frequency detector 315 at the first rising edge of the reference frequency f _ref generated after the state is changed to the closed loop state. Accordingly, the phase frequency detector 315 is activated by the first control signal EN _PFD input from the initial phase setter 310 to start operation

The initial phase setter 310 generates a phase difference with respect to the output frequency value fed back by the voltage controlled oscillator 330 in correspondence with the initial phase offset and then generates a second control signal for resetting the frequency divider 335 RST _DIV ) and outputs it to the frequency divider 335.

That is, the initial phase setter 310 generates the second control signal by counting the output frequency value fed back by the VCO 125 according to the set value for the initial phase offset, .

At this time, the set value is a value calculated so that the rising edge of the feedback frequency of the VCO 125 is generated later than the second rising edge of the reference frequency by an initial phase offset since the target frequency is larger than the starting frequency. Accordingly, the initial phase setter 310 may generate the second control signal after the counting of the output frequency value fed back by the VCO 125, and output it to the frequency divider 335. The divider 335 may be reset in response to the second control signal to cause the first rising edge of the N-divide frequency to occur.

As a result, the rising edge of the reference frequency f _ref can be inputted to the phase frequency detector 315 faster than the rising edge of the divided output frequency (N-divided frequency f _div ) by the initial phase offset.

Therefore, since the reference frequency f _ref is input before the divided output frequency (N-divided frequency f _div ), the phase frequency detector 315 first outputs the UP signal and the charge pump outputs the loop filter (LPF) The operation of raising the voltage of the voltage-controlled oscillator 330 is started. As a result, the synchronization time of the PLL-based frequency synthesizer is shortened through the above-described process.

FIG. 7C shows a case in which the initial phase offset is adjusted according to an embodiment of the present invention and a conventional method in which the initial phase offset is set to 0 (this method is generally referred to as Zero Phase Start (ZPS)) In the case of the PLL frequency synthesizer.

As shown in FIG. 7 (c), the method of adjusting the initial phase offset using the difference between the start frequency and the target frequency according to an embodiment of the present invention is faster than the conventional method, It can be seen that it is fast synchronized.

If the difference between the target frequency and the start frequency is negative

The negative value of the difference between the target frequency and the start frequency means that the target frequency is smaller than the start frequency. This indicates that the frequency of the voltage controlled oscillator 330 should be reduced when the frequency synthesizer 300 starts the synchronizing operation as shown in FIG. 8A, and as a result, the voltage controlled oscillator 330 tunes It means that the voltage should go down.

로 설정되고, PLL 루프는 개방되게 된다. When the operation of the PLL frequency synthesizer 300 is started, the first switch 327a is short-circuited and the second switch 327b is opened so that the VCO tuning voltage

And the PLL loop is opened.

In this state, the initial phase setter 310 can extract a start frequency ( f _initial ) value obtained by converting an output frequency of the VCO to a digital value through an internal frequency-to-digital converter 610. The initial phase setter 310 derives the optimal initial phase offset using the extracted starting frequency value and the externally inputted target frequency, converts the phase into a digital value through the phase-to-digital converter 625, It is possible to adjust the setting value of the display unit 630.

Thereby, the first switch 327a is opened and the second switch 327b is short-circuited so that the PLL frequency synthesizer 300 is changed to the closed loop state.

The initial phase setter 310 generates the first control signal EN _PFD and outputs the first control signal EN _PFD to the phase frequency detector 315 at the first rising edge of the reference frequency f _ref generated after the change to the closed loop state. Accordingly, the phase frequency detector 315 is activated and operated by the first control signal EN _PFD input from the initial phase setter 310.

At the same time, the initial phase setter 310 generates a phase difference for the output frequency value fed back by the voltage controlled oscillator 330 in correspondence with the optimal initial phase offset (i.e., corresponding to the set value for the initial phase offset) Generates a second control signal RST _DIV for resetting the frequency divider 335 and outputs the second control signal RST _DIV to the frequency divider 335 after counting the output frequency value fed back by the voltage controlled oscillator 330. [

Namely, since the target frequency is smaller than the start frequency, the rising edge of the divided output frequency (N-divided output frequency f _div ) fed back by the voltage-controlled oscillator 330 becomes the second rise of the reference frequency f _ref So that a phase corresponding to the initial phase offset is generated earlier than the edge.

As a result, the phase of the divided output frequency (N-divided output frequency f _div ) is first input to the phase frequency detector 315 and the phase frequency detector 315 outputs the DN signal first, The tuning voltage of the voltage controlled oscillator 330 can start the falling operation.

FIG. 8C is a graph illustrating the synchronization time of the PLL frequency synthesizer in the case of performing the initial phase offset adjustment according to an embodiment of the present invention and the conventional ZPS method in which the initial phase offset is adjusted to zero.

As shown in (c) of FIG. 8, the method of adjusting the initial phase offset according to an embodiment of the present invention is faster than the conventional method in that the falling speed to the target frequency is early in the initial stage of the synchronization operation, .

FIG. 9 is a diagram illustrating a simulation result for explaining a phase synchronization process according to an initial phase offset according to an embodiment of the present invention. FIG. 10 is a flowchart illustrating a phase synchronization according to an initial phase offset according to an embodiment of the present invention. FIG. 4 is a graph comparing the synchronization time of a PLL frequency synthesizer according to a conventional method. FIG.

For the simulation, a PLL based frequency synthesizer was designed and verified using CMOS .018μm process. The power supply voltage used in the simulation was 1.8 V and the designed PLL frequency synthesizer had an output frequency ( f _VCO ) in the range of 1 to 2 GHz, a reference frequency ( f _ref ) set at 26 MHz, and a loop bandwidth set at 50 kHz .

As shown in FIG. 9, when the optimum initial phase offset using the difference between the start frequency and the target frequency is applied, the initial phase offset is not controlled for the case where the initial phase offset is set to 0 ° using the conventional ZPS The phase synchronization time is arbitrarily determined according to the initial state.

FIG. 9A is a graph showing the overall synchronization process, and FIG. 9B is a graph showing the vicinity of the target frequency. As shown in FIGS. 9A and 9B, when an optimal initial phase offset using a difference between a start frequency and a target frequency according to an embodiment of the present invention is applied, . The results are summarized in FIG. 9 (c), which shows that the present invention is about 27? It is possible to reduce the synchronization time by about 40%.

FIG. 10 shows how the synchronization time decreases according to the difference between the target frequency and the start frequency. As shown in Fig. 10, when the difference between the target frequency and the start frequency is small, there is almost no improvement in synchronization time. However, in this case, since the synchronization time is already very small, there is no problem even if the synchronization time is not improved. However, when the difference between the target frequency and the start frequency is equal to or greater than 1 MHz, 35% improvement in synchronization time can be seen.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It will be understood that the invention may be varied and varied without departing from the scope of the invention.

610: frequency-to-digital converter
615: first calculator
620: second calculator
625: Phase-to-digital converter
630: programmable counter
635: first edge detector
640: second edge detector

Claims (10)

CLAIMS 1. A phase locked loop (PLL) based frequency synthesizer comprising a voltage controlled oscillator, a phase frequency detector, a charge pump, a loop filter, and a frequency divider,
A frequency-to-digital converter for outputting a start frequency obtained by converting the output frequency fed back by the voltage-controlled oscillator into a digital value;
A calculation unit for calculating an optimal initial phase offset using a phase difference value between the target frequency and the start frequency; And
And a control unit for outputting a control signal for phase synchronization of the frequency synthesizer in a closed loop state using the optimum initial phase offset. The method according to claim 1,
Wherein,
A first edge detector for outputting a first control signal for activating the phase frequency detector when the first rising edge of the reference frequency is detected in the closed loop state;
A programmable counter for generating a phase difference relative to an output frequency fed back by the voltage controlled oscillator using the optimal initial phase offset; And
And a second edge detector for outputting a second control signal for resetting the frequency divider after a phase difference generated by the programmable counter. 3. The method of claim 2,
Wherein the programmable counter adjusts the phase difference by counting the feedback output frequency according to a set value corresponding to the optimal initial phase offset. The method of claim 3,
Wherein,
Further comprising a phase-to-digital converter for converting the optimal initial phase offset to a digital value,
And the phase-to-digital converter adjusts the set value of the programmable counter using the converted digital value. 5. The method of claim 4,
If the difference value is a positive value, the set value is a value calculated such that a rising edge of the feedback output frequency is generated later than the second rising edge of the reference frequency by the optimum initial phase offset. Device. 5. The method of claim 4,
Wherein the set value is a value calculated such that the rising edge of the feedbacked output frequency is generated so as to be earlier than the second rising edge of the reference frequency by the optimal initial phase offset if the difference value is a negative value. Device. A frequency synthesizer comprising a voltage controlled oscillator, a phase frequency detector, a charge pump, a loop filter and a frequency divider,
Calculating an optimal initial phase offset using a phase difference value between a start frequency and a target frequency that are obtained by converting the output frequency fed back by the voltage controlled oscillator into a digital value, And an initial phase setter for outputting a control signal for phase synchronization of the frequency detector. 8. The method of claim 7,
Wherein the start frequency is an output frequency fed back from the voltage controlled oscillator in an open loop state. 9. The method of claim 8,
Wherein the initial phase setter comprises:
A frequency-to-digital converter for outputting a start frequency obtained by converting the output frequency fed back by the voltage-controlled oscillator into a digital value;
A calculation unit for calculating an optimal initial phase offset using a phase difference value between the target frequency and the start frequency; And
A first edge detector for outputting a first control signal for activating the phase frequency detector when the first rising edge of the reference frequency is detected in the closed loop state;
A programmable counter for generating a phase difference corresponding to an output frequency fed back by the voltage controlled oscillator using the optimal initial phase offset; And
And a second edge detector for outputting a second control signal for resetting the frequency divider after a phase difference generated by the programmable counter. 8. The method of claim 7,
Wherein the optimal initial phase offset is calculated using the following equation: < EMI ID = 14.0 >

here,

Lt; / RTI > represents the optimal initial phase offset,

Represents the difference value between the target frequency and the start frequency,

Is a proportional constant corresponding to the slope,

silver

Represents the phase offset value required basically when 0 is zero.

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