KR20150101395A - Thin Film Transistor Substrate And Display Using The Same - Google Patents

Abstract

The present invention relates to a thin film transistor substrate on which different types of thin film transistors are arranged and a display apparatus using the same. The thin film transistor substrate according to the present invention includes a substrate, a first thin film transistor, and a second thin film transistor. The first thin film transistor is disposed on the substrate and includes a polycrystal semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode. The second thin film transistor is disposed on the substrate and includes an oxide semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode. The first gate electrode is overlapped with the polycrystal semiconductor layer with a gate insulating film therebetween. A middle insulating film including a nitride film is disposed on the upper part of the first gate electrode. The second gate electrode is disposed on the middle insulating film covering the first gate electrode. An oxide film covering the second gate electrode is disposed on the middle insulating film. The oxide semiconductor layer is disposed to be overlapped with the second gate electrode on the oxide film. The first source electrode and the first drain electrode are arranged between the middle insulating film and the oxide film. The second source electrode and the second drain electrode are arranged on the oxide semiconductor layer.

Description

[0001] The present invention relates to a thin film transistor substrate and a display using the thin film transistor substrate.

The present invention relates to a thin film transistor substrate in which different types of thin film transistors are disposed on the same substrate, and a display device using the thin film transistor substrate.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. The display field has rapidly changed to a thin, light, and large-area flat panel display device (FPD) that replaces bulky cathode ray tubes (CRTs). The flat panel display includes a liquid crystal display (LCD), a plasma display panel (PDP), an organic light emitting display (OLED), and an electrophoretic display device : ED).

In the case of a liquid crystal display device, an organic light emitting display device, and an electrophoretic display device which are actively driven, the thin film transistor substrate includes thin film transistors arranged in pixel regions arranged in a matrix manner. BACKGROUND ART Liquid crystal display devices (LCDs) display images by adjusting the light transmittance of a liquid crystal using an electric field. The organic light emitting display device displays an image by forming an organic light emitting element in a pixel itself arranged in a matrix manner.

The organic light emitting diode display device is a self-luminous element that emits light by itself, has a high response speed, and is advantageous in luminous efficiency, luminance, and viewing angle. In particular, a passive matrix type organic light emitting diode (OLED) display device (Passive Matrix Type Organic Light Emitting Diode Display) (PMOLED) is used for an organic light emitting diode display (OLEDD) And an active matrix type organic light emitting diode display device (Active Matrix type Organic Light Emitting Diode Display (AMOLED)).

As the development of personal electronic devices becomes more active, display devices are being developed as products that are superior in portability and / or wearability. As described above, in order to be applied to a portable or wearable device, a display device implementing low power consumption is required. Techniques related to display devices developed so far have limitations in realizing low power consumption.

It is an object of the present invention to provide a thin film transistor substrate having two or more types of thin film transistors on the same substrate and a display using the thin film transistor substrate. It is another object of the present invention to provide a thin film transistor substrate in which two or more types of thin film transistors are formed through an optimized manufacturing process and a minimized mask process, and a display device using the same.

In order to achieve the above object, a display device according to the present invention includes a first thin film transistor, a second thin film transistor, an intermediate insulating film, and an oxide film. The first thin film transistor includes a polycrystalline semiconductor layer, a first gate electrode disposed on the polycrystalline semiconductor layer, a first source electrode, and a first drain electrode. The second thin film transistor includes a second gate electrode, an oxide semiconductor layer disposed over the second gate electrode, a second source electrode, and a second drain electrode. The intermediate insulating film is disposed on the first gate electrode and includes a nitride film. An oxide film is disposed on the intermediate insulating film and covers the second gate electrode. The oxide semiconductor layer is arranged to overlap the second gate electrode on the oxide film. The first source electrode, the first drain electrode, and the second gate electrode are disposed between the intermediate insulating film and the oxide film. The second source electrode and the second drain electrode are disposed on the oxide semiconductor layer.

In one example, it further includes a driving circuit. At least one of the first thin film transistor and the second thin film transistor is included in the pixel. At least one of the first thin film transistor and the second thin film transistor is included in the driving circuit.

For example, it further includes a gate insulating film covering the polycrystalline semiconductor layer. The first gate electrode is disposed on the gate insulating film and overlaps with the polycrystalline semiconductor layer.

For example, the second thin film transistor is a switch element for selecting a pixel. The first thin film transistor is a driving element for driving the organic light emitting diode of the pixel selected by the second thin film transistor.

In one example, the driving circuit includes a data driver, a multiplexer, and a gate driver. The data driver outputs the data voltage. The multiplexer distributes the data voltage from the data driver to the data lines. The gate driver outputs the scan pulse to the gate wiring. Either one of the first thin film transistor and the second thin film transistor is included in either the multiplexer or the gate driver.

In one example, the first source electrode is connected to one side of the polycrystalline semiconductor layer through a source contact hole penetrating the intermediate insulating film and the gate insulating film. The first drain electrode is connected to the other side of the polycrystalline semiconductor layer through the intermediate insulating film and the drain contact hole penetrating the gate insulating film. The second source electrode is in contact with one side of the oxide semiconductor layer. The second drain electrode is in contact with the other side of the oxide semiconductor layer.

In one example, the first source electrode and the first drain electrode comprise the same material as the second gate electrode.

In one example, the second gate electrode is connected to the gate wiring including the same material as the first gate electrode through the gate contact hole penetrating the intermediate insulating film.

In one example, the second source electrode is connected to the data line including the same material as the second gate electrode through the data contact hole passing through the oxide film.

For example, the intermediate insulating film further includes a lower oxide film.

For example, a nitride film is disposed on the lower oxide film.

A display device according to the present invention includes a first semiconductor layer, a gate insulating film, a first gate electrode, an intermediate insulating film, a second gate electrode, a first source electrode, a first drain electrode, an oxide film, A source electrode and a second drain electrode. The first semiconductor layer includes a polycrystalline semiconductor material. The gate insulating film covers the first semiconductor layer. The first gate electrode overlaps the first semiconductor layer on the gate insulating film. The intermediate insulating film covers the first gate electrode and includes a nitride film. The second gate electrode, the first source electrode, and the first drain electrode are disposed on the intermediate insulating film. The oxide film covers the second gate electrode, the first source electrode, and the first drain electrode. The second semiconductor layer is disposed over the oxide film, overlapping the second gate electrode, and includes an oxide semiconductor material. The second source electrode and the second drain electrode are disposed on the second semiconductor layer.

For example, one semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode are included in the first thin film transistor. The second semiconductor layer, the second gate electrode, the second source electrode, and the second drain electrode are included in the second thin film transistor.

In one example, it further includes a driving circuit. At least one of the first thin film transistor and the second thin film transistor is included in the pixel. At least one of the first thin film transistor and the second thin film transistor is included in the driving circuit.

For example, the second thin film transistor is a switch element for selecting a pixel. The first thin film transistor is a driving element for driving the organic light emitting diode of the pixel selected by the second thin film transistor.

In one example, the driving circuit includes a data driver, a multiplexer, and a gate driver. The data driver outputs the data voltage. The multiplexer distributes the data voltage from the data driver to the data lines. The gate driver outputs the scan pulse to the gate wiring. Either one of the first thin film transistor and the second thin film transistor is included in either the multiplexer or the gate driver.

In one example, the first source electrode is connected to one side of the first semiconductor layer through a source contact hole penetrating the intermediate insulating film and the gate insulating film. The first drain electrode is connected to the other side of the first semiconductor layer through the intermediate insulating film and the drain contact hole passing through the gate insulating film. The second source electrode is in contact with one side of the second semiconductor layer. The second drain electrode is in contact with the other side of the second semiconductor layer.

In one example, the first source electrode and the first drain electrode comprise the same material as the second gate electrode.

In one example, the second gate electrode is connected to the gate wiring including the same material as the first gate electrode disposed on the gate insulating film through the gate contact hole passing through the intermediate insulating film.

In one example, the second source electrode is connected to the data line including the same material as the second gate electrode disposed on the intermediate insulating film through the data contact hole passing through the oxide film.

In one example, the intermediate insulating film further includes a lower oxide film.

For example, a nitride film is disposed on the lower oxide film.

The thin film transistor substrate and the display device using the thin film transistor substrate according to the present invention may have the feature that two different thin film transistors are formed on the same substrate so that the defects of one thin film transistor are complemented by other thin film transistors. Particularly, by providing a thin film transistor having low-speed driving characteristics, it is possible to provide a display device suitable for portable and / or wearable appliances by reducing power consumption.

FIG. 1A is a cross-sectional view illustrating a thin film transistor substrate for a flat panel display device including different types of thin film transistors according to a first embodiment of the present invention. FIG.
FIG. 1B is a cross-sectional view illustrating a connection structure between a data line and a source electrode, and a gate line and a gate electrode in FIG. 1A. FIG.
FIG. 2 is a flow chart illustrating a process of fabricating a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a first embodiment of the present invention. FIG.
3 is a cross-sectional view illustrating a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a second embodiment of the present invention.
FIG. 4 is a flowchart illustrating a process for fabricating a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a second embodiment of the present invention. FIG.
5 is a cross-sectional view illustrating a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a third embodiment of the present invention.
6 is a flowchart illustrating a process of fabricating a thin film transistor substrate for a flat panel display device including different types of thin film transistors according to a third embodiment of the present invention.
7 is a block diagram schematically showing a configuration of a display device according to a first application example of the present invention.
8 is a plan view showing a thin film transistor substrate having an oxide semiconductor layer included in a fringe field type liquid crystal display device, which is a kind of horizontal electric field type according to a second application example of the present invention.
9 is a sectional view of the thin film transistor substrate shown in FIG. 8 taken along the perforated line II '.
10 is a plan view showing the structure of one pixel in an active matrix organic light emitting diode display device according to a third application example of the present invention.
11 is a cross-sectional view showing the structure of an active matrix organic light emitting diode display device cut into a perforated line II-II 'in FIG. 10;
12 is a plan enlarged view showing a schematic structure of an organic light emitting diode display device according to a fourth application example of the present invention.
FIG. 13 is a cross-sectional view cut along the perforated line III-III 'in FIG. 12, showing a structure of a conventional organic light emitting diode display device. FIG.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description, a detailed description of known technologies or configurations related to the present invention will be omitted when it is determined that the gist of the present invention may be unnecessarily obscured. In addition, the component names used in the following description may be selected in consideration of easiness of specification, and may be different from the parts names of actual products.

A thin film transistor substrate for a flat panel display according to the present invention includes a first thin film transistor arranged in a first region on a glass substrate and a second thin film transistor arranged in a second region. The substrate may include a display area and a non-display area. In the display area, a plurality of pixel regions are arranged in a matrix manner. Display elements for display function are arranged in the pixel region. The non-display region is disposed in the periphery of the display region, and driving elements for driving the display elements formed in the pixel region may be disposed.

Here, the first area may be a part of the non-display area, and the second area may be a part of the display area. In this case, the first thin film transistor and the second thin film transistor may be arranged far away. Alternatively, both the first area and the second area may be included in the display area. In particular, when a plurality of thin film transistors are included in a single pixel region, the first thin film transistor and the second thin film transistor may be disposed adjacent to each other.

Since the polycrystalline semiconductor material has high mobility (100 cm 2 / Vs or more), low energy consumption power and high reliability, it can be applied to a gate driver and / or a multiplexer (MUX) for driving elements for thin film transistors for display devices have. Or an in-pixel driving thin film transistor in an organic light emitting diode display device. Since the oxide semiconductor material has low off-current, it is suitable for a switching thin film transistor which has a short on time and a long off time. Further, since the off current is small, the voltage holding period of the pixel is long, which is suitable for a display device requiring low speed driving and / or low power consumption. Thus, by arranging two different kinds of thin film transistors simultaneously on the same substrate, a thin film transistor substrate exhibiting an optimum effect can be obtained.

When a semiconductor layer is formed of a polycrystalline semiconductor material, an impurity implantation process and a high-temperature heat treatment process are required. On the other hand, when the semiconductor layer is formed of an oxide semiconductor material, the process is performed at a relatively low temperature. Therefore, it is preferable to form the polycrystalline semiconductor layer for performing the process under harsh conditions first, and then form the oxide semiconductor layer later. To this end, the first thin film transistor including the polycrystalline semiconductor material has a top-gate structure, and the second thin film transistor including the oxide semiconductor material has a bottom-gate structure.

Also, in the manufacturing process, the polycrystalline semiconductor material is degraded in the presence of vacancy, and therefore, a process of filling the pores with hydrogen through the hydrogenation process is required. On the other hand, since the oxide semiconductor material can serve as a carrier in which the covalent bond is not formed, a process for stabilizing the oxide semiconductor material to a certain degree of voids is required. These two processes can be performed through a subsequent heat treatment process at 350 ° C to 380 ° C.

In order to perform the hydrogenation process, a nitride film containing a large amount of hydrogen particles is interposed on the polycrystalline semiconductor material. Since the nitride film contains a large amount of hydrogen in the material used for production, a considerable amount of hydrogen is contained in the deposited nitride film itself. In the heat treatment process, hydrogen is diffused into the polycrystalline semiconductor material. As a result, the polycrystalline semiconductor layer can be stabilized. During the heat treatment process, the hydrogen should not diffuse too much into the oxide semiconductor material. Therefore, it is preferable that an oxide film is interposed between the nitride film and the oxide semiconductor material. After the heat treatment process is performed, the oxide semiconductor material is maintained in a state in which the oxide semiconductor material is not so much affected by hydrogen, so that device stabilization can be achieved.

In the following description, it is assumed that the first thin film transistor is a thin film transistor for a driver element formed in a non-display region and the second thin film transistor is a thin film transistor for a display element arranged in a pixel region of the display region. However, the present invention is not limited thereto, and in the case of an organic light emitting diode display device, both the first thin film transistor and the second thin film transistor can be disposed in the pixel region of the display region. In particular, a first thin film transistor including a polycrystalline semiconductor material may be applied to a driving thin film transistor, and a second thin film transistor including an oxide semiconductor material may be applied to a switching thin film transistor.

≪ Embodiment 1 >

A first embodiment of the present invention will be described with reference to Figs. 1A and 1B. 1A is a cross-sectional view illustrating a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a first embodiment of the present invention. FIG. 1B is a cross-sectional view illustrating a connection structure between a data line and a source electrode, and a gate line and a gate electrode in FIG. 1A. Here, the cross-sectional views capable of reliably showing the features of the present invention will be mainly described, and the planar structure is not shown for the sake of convenience.

Referring to FIG. 1A, a thin film transistor substrate for a flat panel display according to a first embodiment of the present invention includes a first thin film transistor T1 and a second thin film transistor T2 disposed on a substrate SUB. The first and second thin film transistors T1 and T2 may be disposed apart from each other or adjacent to each other. Alternatively, two thin film transistors may be arranged in a superimposed manner.

On the entire surface of the substrate SUB, a buffer layer BUF is laminated. Optionally, the buffer layer BUF may be omitted. Alternatively, the buffer layer BUF may have a structure in which a plurality of thin film layers are stacked. Here, for the sake of simplicity, it is described as a single layer. In addition, a light shielding layer may be selectively provided only at a necessary portion between the buffer layer BUF and the substrate SUB. The light-shielding layer can be formed for the purpose of preventing external light from flowing into the semiconductor layer of the thin film transistor disposed thereon.

The first semiconductor layer A1 is disposed on the buffer layer BUF. The first semiconductor layer A1 includes the channel region of the first thin film transistor T1. The channel region is defined as a region where the first gate electrode G1 and the first semiconductor layer A1 overlap. Since the first gate electrode G1 overlaps with the central portion of the first thin film transistor T1, the central portion of the first thin film transistor T1 becomes a channel region. Both sides of the channel region are regions doped with impurities and defined as a source region (SA) and a drain region (DA).

When the first thin film transistor T1 is a thin film transistor for a driving element, it is preferable that the first thin film transistor T1 has a characteristic suitable for performing a high speed driving process. For example, a P-MOS or N-MOS type thin film transistor may be used, or a C-MOS type thin film transistor including both of them may be provided. The P-MOS, N-MOS and / or C-MOS type thin film transistors preferably include a polycrystalline semiconductor material such as poly-silicon. Further, it is preferable that the first thin film transistor T1 has a top-gate structure.

A gate insulating film GI is laminated on the entire surface of the substrate SUB on which the first semiconductor layer A1 is disposed. The gate insulating film GI may be formed of silicon nitride (SiNx) or silicon oxide (SiOx). In the case of the gate insulating film GI, it is preferable that the gate insulating film GI has a thickness of about 1,000 ANGSTROM to 1,500 ANGSTROM considering the stability and characteristics of the device. When the gate insulating film GI is formed of silicon nitride (SiNx), a large amount of hydrogen can be contained in the gate insulating film GI in the manufacturing process. These hydrogen atoms may diffuse out of the gate insulating film GI in a subsequent process, and it is preferable that the gate insulating film GI is formed of a silicon oxide material.

The first semiconductor layer (A1) including the polycrystalline silicon material can exhibit a positive effect of hydrogen diffusion. However, a negative effect can be given to the second thin film transistor T2 having a property different from that of the first thin film transistor T1. Therefore, in the case where thin film transistors using different materials are formed on the same substrate as in the present invention, it is more preferable to use silicon oxide (SiOx) which does not particularly affect the device. Unlike the case of the first embodiment, the gate insulating film GI may be formed to have a thickness of about 2,000 to 4,000 ANGSTROM depending on the case. In this case, when the gate insulating film GI is formed of silicon nitride (SiNx), the diffusion degree of hydrogen may be large. Therefore, in consideration of various cases, the gate insulating film GI is preferably formed of silicon oxide (SiOx).

A first gate electrode G1 is disposed on the gate insulating film GI. The first gate electrode G1 is disposed so as to overlap the central portion of the first semiconductor layer A1. A central portion of the first semiconductor layer A1 overlapping with the first gate electrode G1 is defined as a channel region.

An intermediate insulating film ILD is laminated on the entire surface of the substrate SUB on which the first gate electrode G1 is formed. The intermediate insulating film ILD is preferably formed of a nitride film (SIN) including an inorganic nitride material such as silicon nitride (SiNx). The nitride film (SIN) diffuses the hydrogen contained therein through a subsequent heat treatment process to deposit the first semiconductor layer (A1) including the polycrystalline silicon for hydrogenation treatment.

A first source electrode S1, a first drain electrode D1 and a second gate electrode G2 are disposed on the intermediate insulating film ILD. The first source electrode S1 is in contact with the source region SA which is one side of the first semiconductor layer A1 through the intermediate insulating film ILD and the source contact hole SH penetrating the gate insulating film GI. The first drain electrode D1 contacts the drain region DA which is the other side of the first semiconductor layer A1 through the intermediate insulating film ILD and the drain contact hole DH penetrating the gate insulating film GI. On the other hand, the second gate electrode G2 is arranged in the region of the second thin film transistor T2. The first source electrode S1, the first drain electrode D1 and the second gate electrode G2 are formed of the same material on the same layer with the same mask, so that the manufacturing process can be simplified.

An oxide film SIO is formed on an intermediate insulating film ILD on which a first source electrode S1, a first drain electrode D1 and a second gate electrode G2 are formed. The oxide film SIO preferably includes an inorganic oxide material such as silicon oxide (SiOx). The oxide film SIO has a structure stacked on the nitride film SIN so that the hydrogen emitted from the nitride film SIN is prevented from being excessively diffused into the semiconductor material of the second thin film transistor by the subsequent heat treatment process.

It is preferable that the hydrogen emitted from the intermediate insulating film ILD made of the nitride film SIN is diffused into the first semiconductor layer A1 disposed under the gate insulating film GI therebetween. On the other hand, it is preferable that the hydrogen emitted from the nitride film SIN is prevented from diffusing into the semiconductor material of the second thin film transistor T2 formed thereon. Therefore, it is preferable that the nitride film SIN is stacked on the gate insulating film GI close to the first semiconductor layer A1. It is preferable that the nitride film SIN selectively covers the first thin film transistor T1 including the first semiconductor layer A1 and is not disposed in the region where the second thin film transistor T2 is disposed.

Also, considering the manufacturing process and the hydrogen diffusion efficiency, the intermediate insulating film (ILD) made of a nitride film (SIN) is preferably laminated to a thickness of 1,000 ANGSTROM to 3,000 ANGSTROM. The thickness of the oxide film SIO is set to be larger than the thickness of the gate insulating film GI in order to allow the hydrogen in the nitride film SIN to be diffused into the first semiconductor layer A1 in a large amount while minimizing the influence on the second semiconductor layer A2. ). ≪ / RTI > In particular, the oxide film SIO is for controlling the degree of diffusion of hydrogen emitted from the nitride film SIN, and the thickness of the oxide film SIO is preferably thicker than that of the nitride film SIN. In addition, the oxide film SIO has to function as a gate insulating film in the second thin film transistor T2. Considering this situation, it is preferable to laminate the oxide film (SIO) to a thickness of about 1,000 Å to 3,000 Å.

On the upper surface of the oxide film SIO, a second semiconductor layer A2 overlapping the second gate electrode G2 is disposed. The second semiconductor layer A2 includes the channel region of the second thin film transistor T2. When the second thin film transistor T2 is a thin film transistor for a display element, it is preferable that the second thin film transistor T2 has characteristics suitable for performing display function processing. For example, an oxide semiconductor material such as indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), and indium zinc oxide (IZO) . The oxide semiconductor material has low off-current characteristics and can be driven at a low frequency. Because of this characteristic, the capacity of the auxiliary capacity can be sufficiently driven, so that the area occupied by the auxiliary capacity can be reduced. Therefore, it is advantageous to realize an ultra-high resolution display device having a small unit pixel area. When an oxide semiconductor material is included, it is preferable to have a bottom-gate structure which can secure the stability of the device more effectively.

A second source electrode S2 and a second drain electrode D2 are disposed on the second semiconductor layer A2 and the oxide film SIO. The second source electrode S2 and the second drain electrode D2 are disposed at a distance from each other in contact with the upper surface of the one side portion and the other side portion of the second semiconductor layer A2. The second source electrode S2 is arranged to be in contact with the upper surface of the oxide film SIO and the upper surface of one side of the second semiconductor layer A2. The second drain electrode D2 is arranged to be in contact with the upper surface of the oxide film SIO and the upper surface of the other side of the second semiconductor layer A2.

A protective film PAS is formed on the first thin film transistor T1 and the second thin film transistor T2. Thereafter, a contact hole may be formed by patterning the passivation film PAS to expose the first drain electrode D1 and / or the second drain electrode D2. In addition, the passivation layer PAS may further include a pixel electrode which is in contact with the first drain electrode D1 and / or the second drain electrode D2 through a contact hole. Here, for convenience, only those portions showing the structure of the thin film transistors representing the main features of the present invention have been shown and described.

As described above, in the thin film transistor substrate for a flat panel display according to the first embodiment of the present invention, the first thin film transistor T1 including a polycrystalline semiconductor material and the second thin film transistor T2 including an oxide semiconductor material are the same And has a structure formed on the substrate SUB. In particular, the first semiconductor layer A1 including the polycrystalline semiconductor material of the first thin film transistor T1 is disposed under the first gate electrode G1, and the second semiconductor layer A1 including the oxide semiconductor material of the second thin film transistor T2 And the second semiconductor layer A2 is disposed on the second gate electrode G2. The second gate electrode G2 is disposed on the intermediate insulating film ILD covering the first gate electrode G1. Therefore, after the first semiconductor layer (A1) formed at a relatively high temperature is formed first and then the second semiconductor layer (A2) formed at a relatively low temperature is formed later, the oxide semiconductor material is exposed to a high temperature state And the like. Therefore, the first thin film transistor has a top-gate structure since the first semiconductor layer A1 must be formed first than the first gate electrode G1. The second thin film transistor has a bottom-gate structure since the second semiconductor layer A2 must be formed later than the second gate electrode G2.

In addition, the first semiconductor layer A1 including the polycrystalline semiconductor material may be simultaneously subjected to the hydrogen treatment during the heat treatment of the second semiconductor layer A2 including the oxide semiconductor material. For this purpose, the intermediate insulating film ILD is formed of a nitride film (SIN), and the oxide film (SIO) is stacked on the intermediate insulating film ILD. A hydrogenation process for diffusing hydrogen contained in the nitride film (SIN) into the first semiconductor layer (A1) by a heat treatment process is required. In addition, a heat treatment process for stabilizing the second semiconductor layer A2 including the oxide semiconductor material is also required. The hydrogenation process may be performed after the intermediate insulating film ILD is laminated on the first semiconductor layer A1 and the heat treatment process may be performed after the second semiconductor layer A2 is formed. According to the first embodiment of the present invention, the second semiconductor (SIN) including the hydrogen-oxide semiconductor material contained in the nitride film (SIN) by the oxide film (SIO) deposited on the nitride film It is possible to prevent excessive diffusion into the layer A2. Therefore, in the structure according to the first embodiment of the present invention, the hydrogenation process may be performed simultaneously in the heat treatment process for stabilizing the oxide semiconductor material.

On the other hand, the nitride film SIN is stacked on the first gate electrode G1 so as to be disposed close to the first semiconductor layer A1 requiring hydrogen treatment. The second thin film transistor T2 including the oxide semiconductor material is formed with an oxide film SIO covering the nitride film SIN and the second gate electrode G2 formed thereon so as to be disposed far away from the nitride film SIN. As shown in Fig. As a result, it is possible to prevent the hydrogen contained in the nitride film (SIN) from being excessively diffused into the second semiconductor layer (A2) in the subsequent heat treatment process.

As described above, the description with reference to FIG. 1A only describes the basic structure of the first thin film transistor and the second thin film transistor. Actually, when the second thin film transistor is used as a display element arranged in the pixel region, the gate wiring and the data wiring are arranged around the pixel region. The gate wirings and the data wirings are preferably formed on the same layer as the gate wirings and the data wirings of the first thin film transistors. Hereinafter, with reference to FIG. 1B, how the gate electrode and the source electrode constituting the second thin film transistor can be connected to the gate wiring and the data wiring will be further described.

Referring to FIG. 1B, the structure of basic thin film transistors is the same as that described above. Therefore, redundant description is omitted. When the first gate electrode G1 constituting the first thin film transistor T1 is formed, the gate wiring GL is arranged in the same layer with the same material and around the second thin film transistor T2. That is, the gate wiring GL has a structure covered with the intermediate insulating film ILD like the first gate electrode G1.

The source contact hole SH for opening the source region SA of the first semiconductor layer A1 and the drain contact hole DH for exposing the drain region DA are formed in the intermediate insulating film ILD. At the same time, a gate wiring contact hole GLH exposing a part of the gate wiring GL is further formed in the intermediate insulating film ILD.

A first source electrode S1, a first drain electrode D1, a second gate electrode G2, and a data line DL are disposed on the intermediate insulating layer ILD. The first source electrode S1 is in contact with the source region SA through the source contact hole SH. The first drain electrode D1 contacts the drain region DA through the drain contact hole DH. Further, the second gate electrode G2 is connected to the gate wiring GL through the gate wiring contact hole GLH. The data line DL is arranged around the second thin film transistor T2 so as to cross the gate line GL with the intermediate insulating film ILD interposed therebetween.

The first source electrode S1, the first drain electrode D1 and the second gate electrode G2 are covered with an oxide film SIO. A second semiconductor layer A2 overlapping the second gate electrode G2 is disposed on the oxide film SIO. The oxide film SIO is further formed with a data line contact hole DLH for exposing a part of the data line DL.

A second source electrode S2 and a second drain electrode D2 are disposed on the second semiconductor layer A2 and the oxide film SIO. The second source electrode S2 is in contact with the one side upper surface of the second semiconductor layer A2 and is connected to the data line DL through the data line contact hole DLH. And the second drain electrode D2 is in contact with the upper surface of the other side of the second semiconductor layer A2.

Hereinafter, a method for fabricating a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a first embodiment of the present invention will be described with reference to FIG. 2 is a flowchart illustrating a process of fabricating a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a first embodiment of the present invention.

A buffer layer (BUF) is deposited on the substrate (SUB). Although not illustrated in the drawings, a light shielding layer may be formed at a necessary portion before the buffer layer BUF is deposited. (S100)

An amorphous silicon (a-Si) material is deposited on the buffer layer (BUF) and crystallized to form poly-silicon. The polycrystalline silicon material is patterned by a first mask process to form the first semiconductor layer A1. (S110)

An insulating material such as silicon oxide is deposited on the entire surface of the substrate SUB on which the first semiconductor layer A1 is formed to form the gate insulating film GI. The gate insulating film GI is preferably formed of silicon oxide. The thickness of the gate insulating film GI is preferably 1,000 ANGSTROM to 1,500 ANGSTROM. (S120)

A gate metal material is deposited on the gate insulating film GI and patterned by a second mask process to form the first gate electrode G1. The first gate electrode G1 is arranged so as to overlap the central portion of the first semiconductor layer A1. (S200)

Using the first gate electrode G1 as a mask, impurities are implanted into the first semiconductor layer A1 arranged at the bottom to define a doped region including the source region SA and the drain region DA. The definition process of the doped region may be slightly different depending on P-MOS, N-MOS or C-MOS. For example, in the case of an N-MOS type thin film transistor, after forming a high concentration doping region first, a low concentration doping region can be formed later. The heavily doped region can be defined by using the photoresist pattern of the first gate electrode G1 having a size larger than that of the first gate electrode G1. The photoresist may be removed and a low density doped area (LDD) may be defined between the heavily doped region and the first gate electrode G1 using the first gate electrode G1 as a mask. The impurity doped region is not shown in the drawing for the sake of convenience. (S210)

An intermediate insulating film ILD made of a nitride film SIN is deposited on the entire surface of the substrate SUB on which the first gate electrode G1 is formed by using an inorganic nitride material such as silicon nitride (SiNx). The nitride film (SIN) can contain a large amount of hydrogen inside the manufacturing process. Considering the manufacturing process and hydrogen diffusion, the intermediate insulating film (ILD) is deposited to a thickness of 1,000 Å to 3,000 Å. (S220)

An intermediate insulating film ILD is patterned by a third mask process to form a source contact hole SH exposing one side of the first semiconductor layer A1 and a drain contact hole DH exposing the other side. This is for connecting the source-drain electrode to be formed later with the first semiconductor layer A1. (S300)

A metal material is deposited on the intermediate insulating film (ILD). A metal material is patterned by a fourth mask process to form a first source electrode S1, a first drain electrode D1 and a second gate electrode G2. The first source electrode S1 is in contact with one side of the first semiconductor layer A1 through the source contact hole SH. The first drain electrode D1 is in contact with the other side of the first semiconductor layer A1 through the drain contact hole DH. The second gate electrode G2 is disposed at a position where the second thin film transistor T2 is to be formed. (S400)

An oxide film SIO is formed on the entire surface of the substrate SUB on which the first source electrode S1, the first drain electrode D1 and the second gate electrode G2 are formed by using an inorganic oxide material such as silicon oxide (SiOx) / RTI > From the structural aspect of the second thin film transistor T2, the oxide film SIO functions as a gate insulating film covering the second gate electrode G2. It is preferable that the oxide film SIO is deposited to a thickness of 1,000 ANGSTROM to 3,000 ANGSTROM so as to prevent hydrogen particles emitted from the nitride film SIN from diffusing into a semiconductor material to be disposed thereon. The thickness of the oxide film (SIO) and the thickness of the nitride film (SIN) which is the intermediate insulating film (ILD) can be appropriately selected in consideration of the degree of hydrogen diffusion and device characteristics. For example, in order to prevent excessive diffusion of hydrogen, the nitride film (SIN) is preferably thinner than the oxide film (SIO). (S410)

An oxide semiconductor material is deposited on the oxide film (SIO). The oxide semiconductor material includes at least one of indium gallium zinc oxide (IGZO), indium gallium oxide (IGO), and indium zinc oxide (IZO). The oxide semiconductor material is patterned by a fifth mask process to form the second semiconductor layer A2. The second semiconductor layer A2 is disposed so as to overlap with the second gate electrode G2. (S500)

The substrate SUB on which the second semiconductor layer A2 is formed is subjected to the subsequent heat treatment to perform the hydrogenation of the first semiconductor layer A1 including polycrystalline silicon and the heat treatment of the second semiconductor layer A2 including the oxide semiconductor material Concurrently. The subsequent heat treatment process is a 350? To 380 ° C. At this time, the hydrogen contained in the nitride film SIN is diffused to the first semiconductor layer A1 in a large amount, while the amount of diffusion into the second semiconductor layer A2 by the oxide film SIO is limited. In some cases, the hydrogenation process of the first semiconductor layer (A1) and the heat treatment process of the second semiconductor layer (A2) may be performed separately. In this case, the hydrogenation process is performed first after the step S220 of depositing the intermediate insulating film (ILD), and the heat treatment of the second semiconductor layer (A2) is performed through the subsequent heat treatment process. (S510)

Source metal material is deposited on the entire surface of the substrate SUB on which the second semiconductor layer A2 is formed. A source-drain metal material is patterned by a sixth mask process to form a second source electrode S2 and a second drain electrode D2. The second source electrode S2 is arranged to be in contact with the upper surface of the one side surface of the second semiconductor layer A2 and the upper surface of the second intermediate insulating film ILD2. Likewise, the second drain electrode D2 is arranged to contact the upper surface of the other side of the second semiconductor layer A2 and the upper surface of the oxide film SIO. (S600)

A protective film PAS is deposited on the entire surface of the substrate SUB on which the first and second thin film transistors T1 and T2 are formed. Although not shown in the drawings, a contact hole may be further formed by patterning the passivation film PAS to expose a part of the first and / or second drain electrodes D1 and D2. (S700)

≪ Embodiment 2 >

Hereinafter, a second embodiment of the present invention will be described with reference to FIG. 3 is a cross-sectional view illustrating a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a second embodiment of the present invention.

The basic configuration of the second embodiment of the present invention is the same as that of the first embodiment. If there is a difference, the intermediate insulating film (ILD) is composed of a double layer. And a structure in which the lower oxide film SIO2 and the nitride film SIN are stacked. For example, it may have a structure in which a nitride film (SIN) is stacked on the lower oxide film SIO2. Or a structure in which a lower oxide film (SIO2) is stacked on a nitride film (SIN). Here, the lower oxide film SIO2 is a named name because it is located below the oxide film SIO, and is not a term limiting the arrangement under the nitride film.

Through the subsequent heat treatment process, hydrogen must be diffused from the nitride film (SIN) containing a large amount of hydrogen into the first semiconductor layer (A1) in the manufacturing process. Considering the diffusion efficiency, it is preferable that the thickness of the nitride film (SIN) of the intermediate insulating film (ILD) has a thickness of 1,000 ANGSTROM to 3,000 ANGSTROM. The lower oxide film SIO2 may be formed to compensate the surface of the damaged gate insulating film GI in the process of forming the first gate electrode G1 (disposed below the nitride film SIN) ) Nitride film (SIN) and has a thickness of about 500 Å to about 1,000 Å.

An oxide film (SIO) is stacked on the intermediate insulating film (ILD) in which the lower oxide film (SIO2) and the nitride film (SIN) are stacked. The oxide film SIO functions as a gate insulating film in the second thin film transistor T2. Therefore, if the oxide film SIO is too thick, the gate voltage may not be normally transferred to the second semiconductor layer A2. Therefore, it is preferable that the thickness of the oxide film SIO has a thickness of 1,000 ANGSTROM to 3,000 ANGSTROM. The gate insulating film GI preferably has a thickness of about 1,000 ANGSTROM to 1,500 ANGSTROM.

In FIG. 3, the intermediate insulating film ILD has a structure in which a nitride film (SIN) is stacked on the lower oxide film SIO2. However, if necessary, the intermediate insulating film ILD may have a structure in which a nitride film (SIN) is stacked on the lower oxide film (SIO2) on the lower side. In this case, the nitride film SIN may be disposed closer to the lower first semiconductor layer A1, while the upper second semiconductor layer A2 may be further separated by a thickness of the lower oxide film SIO2 . Therefore, the diffusion of hydrogen into the first semiconductor layer (A1) is performed more easily, and hydrogen diffusion into the second semiconductor layer (A2) can be prevented more effectively.

It is preferable that the thickness of the intermediate insulating film ILD is 2,000 to 6,000 ANGSTROM and the thickness of the nitride film SIN and the bottom oxide film SIO2 are all 1,000 ANGSTROM to 3,000 ANGSTROM . It is preferable that the oxide film SIO is formed to a thickness of 1,000 Å to 3,000 Å in consideration of the gate insulating film in the second thin film transistor T2.

Other components are the same as those of the first embodiment, and detailed description thereof will be omitted. Hereinafter, a process for manufacturing the thin film transistor substrate for flat panel display according to the second embodiment will be described. Here again, since it is almost the same as that of the first embodiment, the same description without significant significance is omitted. 4 is a flowchart illustrating a process of fabricating a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a second embodiment of the present invention.

A buffer layer (BUF) is deposited on the substrate (SUB). (S100)

An amorphous silicon (a-Si) material is deposited on the buffer layer (BUF) and crystallized to form poly-silicon. The polycrystalline silicon material is patterned by a first mask process to form the first semiconductor layer A1. (S110)

An insulating material such as silicon oxide is deposited on the entire surface of the substrate SUB on which the first semiconductor layer A1 is formed to form the gate insulating film GI. The gate insulating film GI is preferably formed of silicon oxide having a thickness of about 1,000 to 1,500 angstroms. (S120)

A gate metal material is deposited on the gate insulating film GI and patterned by a second mask process to form the first gate electrode G1. The first gate electrode G1 is arranged so as to overlap the central portion of the first semiconductor layer A1. (S200)

Using the first gate electrode G1 as a mask, impurities are implanted into the first semiconductor layer A1 arranged at the bottom to define a doped region including the source region SA and the drain region DA. (S210)

An intermediate insulating film ILD is deposited on the entire surface of the substrate SUB on which the first gate electrode G1 is formed. In particular, a double layer structure in which a lower oxide film (SIO2) and a nitride film (SIN) are stacked is deposited. The intermediate insulating film ILD may be laminated on the lower oxide film SIO2 under the nitride film SIN or vice versa. It is preferable that the lower oxide film SIO2 is formed to have a thickness of 500 Å to 1000 Å and the nitride film SIN to have a thickness of 1,000 Å to 3,000 Å. When the nitride film (SIN) is deposited under the second semiconductor layer (A2), the lower oxide film (SIO2) is also stacked to a thickness of about 1,000 ANGSTROM to 3,000 ANGSTROM to prevent hydrogen from being excessively diffused into the second semiconductor layer (A2). (S220)

An intermediate insulating film ILD is patterned by a third mask process to form a source contact hole SH and a drain contact hole DH exposing one side and the other side of the first semiconductor layer A1. (S300)

A metal material is deposited on the intermediate insulating film (ILD). A metal material is patterned by a fourth mask process to form a first source electrode S1, a first drain electrode D1 and a second gate electrode G2. The first source electrode S1 is in contact with one side of the first semiconductor layer A1 through the source contact hole SH. The first drain electrode D1 is in contact with the other side of the first semiconductor layer A1 through the drain contact hole DH. The second gate electrode G2 is disposed at a position where the second thin film transistor T2 is to be formed. (S400)

An oxide film SIO is formed on the entire surface of the substrate SUB on which the first source electrode S1, the first drain electrode D1 and the second gate electrode G2 are formed by using an inorganic oxide material such as silicon oxide (SiOx) / RTI > The oxide film SIO functions as a gate insulating film in the second thin film transistor T2 and functions to prevent hydrogen diffusion. Therefore, it is preferable that the layers are laminated to a thickness of 1,000 ANGSTROM to 3,000 ANGSTROM. (S410)

An oxide semiconductor material is deposited on the oxide film SIO, and the second semiconductor layer A2 is formed by patterning in the fifth mask process. The second semiconductor layer A2 is disposed so as to overlap with the second gate electrode G2. (S500)

The substrate SUB on which the second semiconductor layer A2 is formed is subjected to the subsequent heat treatment to perform the hydrogenation of the first semiconductor layer A1 including polycrystalline silicon and the heat treatment of the second semiconductor layer A2 including the oxide semiconductor material Concurrently. The subsequent heat treatment step is carried out at a temperature of 350 to 380 占 폚. At this time, the hydrogen contained in the nitride film SIN is diffused to the first semiconductor layer A1 in a large amount, while the amount of diffusion into the second semiconductor layer A2 by the oxide film SIO is limited. In some cases, the hydrogenation process of the first semiconductor layer (A1) and the heat treatment process of the second semiconductor layer (A2) may be performed separately. (S510)

Source metal material is deposited on the entire surface of the substrate SUB on which the second semiconductor layer A2 is formed. A source-drain metal material is patterned by a sixth mask process to form a second source electrode S2 and a second drain electrode D2. (S600)

A protective film PAS is deposited on the entire surface of the substrate SUB on which the first and second thin film transistors T1 and T2 are formed. (S700)

≪ Third Embodiment >

Hereinafter, a third embodiment of the present invention will be described with reference to FIG. 5 is a cross-sectional view illustrating a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a third embodiment of the present invention.

The third embodiment of the present invention is basically the same as the first and second embodiments. If there is a difference, the oxide film SIO functions as an intermediate insulating film for the first thin film transistor T1 and functions as a gate insulating film for the second thin film transistor T2. Specifically, the intermediate insulating film ILD includes a first intermediate insulating film ILD1 and a second intermediate insulating film ILD2. The first intermediate insulating film ILD1 has a structure in which a lower oxide film SIO2 and a nitride film SIN are stacked. Particularly, the nitride film SIN is not disposed in the second region where the second thin film transistor T2 is disposed, and has a structure for selectively covering the first region where the first thin film transistor T1 is disposed. The second intermediate insulating film ILD2 is formed of an oxide film SIO and functions as a gate insulating film of the second thin film transistor T2.

Hydrogen contained in the nitride film SIN can be diffused into the first semiconductor layer A1 through the subsequent heat treatment process by disposing the nitride film SIN in the region where the first thin film transistor T1 is disposed. Considering the hydrogen diffusion efficiency, it is preferable that the nitride film (SIN) has a thickness of 1,000 Å to 3,000 Å. On the other hand, the lower oxide film SIO2 preferably has a thickness of about 500 Å to about 1,000 Å.

The possibility that hydrogen in the nitride film SIN diffuses into the second semiconductor layer A2 is remarkably reduced because the nitride film SIN has a thickness of about 3,000 angstroms and is spaced apart from the second thin film transistor T2 by a considerable distance . In addition, since the oxide film (SIO) which is the second intermediate insulating film ILD2 is further stacked on the nitride film SIN, diffusion of hydrogen to the second semiconductor layer A2 can be reliably prevented.

The third embodiment differs from the first and second embodiments in that the first source-drain electrodes S1 and D1 and the second source-drain electrodes S2 and D2 are formed of the same material in the same layer .

Other components are the same as those of the first and / or the second embodiment, so duplicate descriptions are omitted. Hereinafter, a process for manufacturing the thin film transistor substrate for a flat panel display according to the third embodiment will be described. Here again, since they are almost the same as those of the first and / or second embodiments, redundant explanations are omitted. 5 is a flowchart illustrating a process for fabricating a thin film transistor substrate for a flat panel display including different types of thin film transistors according to a third embodiment of the present invention.

A buffer layer (BUF) is deposited on the substrate (SUB). (S100)

An amorphous silicon (a-Si) material is deposited on the buffer layer (BUF) and crystallized to form poly-silicon. The polycrystalline silicon material is patterned by a first mask process to form the first semiconductor layer A1. (S110)

An insulating material such as silicon oxide is deposited on the entire surface of the substrate SUB on which the first semiconductor layer A1 is formed to form the gate insulating film GI. The gate insulating film GI is preferably formed of silicon oxide having a thickness of about 1,000 to 1,500 angstroms. (S120)

A gate metal material is deposited on the gate insulating film GI and patterned by a second mask process to form the first gate electrode G1. The first gate electrode G1 is arranged so as to overlap the central portion of the first semiconductor layer A1. (S200)

Using the first gate electrode G1 as a mask, impurities are implanted into the first semiconductor layer A1 arranged at the bottom to define a doped region including the source region SA and the drain region DA. (S210)

The first intermediate insulating film ILD1 is deposited on the entire surface of the substrate SUB on which the first gate electrode G1 is formed. In particular, it is formed in a bilayer structure in which a lower oxide film (SIO2) and a nitride film (SIN) are stacked. The first intermediate insulating film ILD1 may be formed by stacking a nitride film SIN on the lower oxide film SIO2 and a nitride film SIN on the lower oxide film SIO2. It is preferable that the lower oxide film SIO2 is formed to have a thickness of 500 Å to 1000 Å and the nitride film SIN to have a thickness of 1,000 Å to 3,000 Å. When the nitride film (SIN) is deposited on the lower layer, the lower oxide film (SIO2) is also stacked to a thickness of about 1,000 ANGSTROM to 3,000 ANGSTROM to prevent hydrogen from being excessively diffused into the second semiconductor layer (A2). (S220)

Only the nitride film SIN of the first intermediate insulating film ILD1 is patterned so as to cover the first semiconductor layer A1 by the third mask process. When the nitride film SIN is disposed at the bottom, a nitride film SIN is deposited and then a nitride film SIN is patterned to form a lower oxide film SIO2. When the nitride film SIN is disposed on the upper portion, only the nitride film SIN is patterned after the lower oxide film SIO2 and the nitride film SIN are continuously deposited. (S300)

A gate metal material is deposited on the first intermediate insulating film ILD1 including the nitride film SIN selectively formed only on the first semiconductor layer A1. A gate metal material is patterned by a fourth mask process to form a second gate electrode G2. The second gate electrode G2 is disposed at a position where the second thin film transistor T2 is to be formed. (S400)

A second intermediate insulating film ILD2 made of an oxide film SIO is deposited on the entire surface of the substrate SUB on which the second gate electrodes G2 are formed by using an inorganic oxide material such as silicon oxide (SiOx). (S410)

An oxide semiconductor material is deposited on the second intermediate insulating film ILD2, and the second semiconductor layer A2 is formed by patterning in the fifth mask process. The second semiconductor layer A2 is disposed so as to overlap with the second gate electrode G2. (S500)

The substrate SUB on which the second semiconductor layer A2 is formed is subjected to the subsequent heat treatment to perform the hydrogenation of the first semiconductor layer A1 including polycrystalline silicon and the heat treatment of the second semiconductor layer A2 including the oxide semiconductor material Concurrently. The subsequent heat treatment step is carried out at a temperature of 350 to 380 占 폚. In some cases, the hydrogenation process of the first semiconductor layer (A1) and the heat treatment process of the second semiconductor layer (A2) may be performed separately. At this time, the hydrogen contained in the nitride film (SIN) is diffused to the first semiconductor layer (A1). On the other hand, since the nitride film SIN covers only the first region where the first channel layer A1 is present, the amount of diffusion of the nitride film SIN into the second channel layer A2 is limited. (S510)

The second intermediate insulating film ILD2 and the first intermediate insulating film ILD1 are patterned to form the source contact hole SH and the drain contact hole DH in the sixth mask process, . (S600)

Source metal material is deposited on the entire surface of the substrate SUB on which the contact holes SH and DH and the second semiconductor layer A2 are formed. The source-drain metal material is patterned by a seventh mask process to form a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode (S1, D1, S2, D2). (S700)

A protective film PAS is deposited on the entire surface of the substrate SUB on which the first and second thin film transistors T1 and T2 are formed. (S800)

≪ First application example >

The thin film transistor substrate having the thin film transistors described above can be applied to various flat panel display devices. As described in the present invention, various advantages can be obtained when the thin film transistors having different characteristics are formed on one substrate. Hereinafter, with reference to FIG. 7, a description will be given in detail of what features and advantages can be expected in a display device using the thin film transistor substrate according to the first application example of the present invention. 7 is a block diagram schematically showing a configuration of a display device according to a first application example of the present invention.

At least one of the first and second thin film transistors T1 and T2 may be a thin film transistor formed in each of the pixels of the display panel 100 to switch the data voltage written to the pixels or drive the pixels. In the case of an organic light emitting diode display device, the second thin film transistor T2 may be applied as a switching element of a pixel, and the first thin film transistor T1 may be applied as a driving element, but is not limited thereto. The first and second thin film transistors T1 and T2 may be combined and applied as one switching element or one driving element.

In order to reduce power consumption in a mobile device or a wearable device, a low-speed driving method of lowering a frame rate has been attempted. In this case, the frame frequency can be lowered in an image in which the update period of a still image or data is slow. However, if the frame rate is lowered, a flickering phenomenon may be seen every time the data voltage is changed, or a flicker phenomenon may occur in which the voltage is discharged for a long time and the luminance is flickered at the data update period. When the first and second thin film transistors T1 and T2 of the present invention are applied to pixels, the flicker problem at low speed driving can be solved.

When the data update period is lengthened at the time of low speed driving, the leakage current amount of the switch thin film transistor becomes large. The leakage current of the switch thin film transistor causes the voltage of the storage capacitor STG and the gate-source voltage of the driving thin film transistor to be lowered. The present invention can be applied to a thin film transistor of a pixel as a second thin film transistor which is an oxide transistor. Since the oxide transistor has a low off-current, the voltage drop of the gate electrode of the storage capacitor and the driving thin film transistor can be prevented. Therefore, the present invention can prevent flicker in low-speed driving.

When the first thin film transistor, which is a polysilicon transistor, is applied to a driving thin film transistor of a pixel, the amount of current supplied to the organic light emitting diode can be increased because of high mobility of electrons. Accordingly, the second thin film transistor T2 is applied to the switching element of the pixel and the first thin film transistor T1 is applied to the driving element of the pixel, thereby reducing the power consumption and preventing the deterioration of image quality.

The present invention is effective for application to a mobile device or a wearable device because it can prevent degradation in image quality when a low-speed driving method is applied to reduce power consumption. For example, a portable electronic watch can update data on the display screen in 1-second increments to reduce power consumption. The frame frequency at this time is 1 Hz. The present invention can realize excellent picture quality without flicker even by using a driving frequency close to 1 Hz or a still image. The present invention significantly reduces the frame rate of a still image on a standby screen of a mobile device or a wearable device, thereby greatly reducing power consumption without deteriorating picture quality. As a result, the present invention improves the image quality of a mobile device or a wearable device and lengthens battery life, thereby enhancing portability. The present invention can significantly reduce the power consumption without lowering the picture quality even in an e-book with a very long data updating period.

One or more of the first and second thin film transistors T1 and T2 are embedded in at least one of a driving circuit, for example, a data driver 200, a multiplexer (MUX) 210, and a gate driver 300 A driving circuit can be constituted. This driving circuit writes data to the pixel. Also, any one of the first and second thin film transistors T1 and T2 may be formed in the pixel and the other may be formed in the driving circuit. The data driver 200 converts the data of the input image into data voltages and outputs the data voltages. The multiplexer 210 reduces the number of output channels of the data driver 200 by time-divisionally distributing the data voltage from the data driver 200 to the plurality of data lines DL. The gate driver 300 outputs a scan signal (or a gate signal) synchronized with the data voltage to the gate line GL to sequentially select the pixels to which the data of the input image is written in units of lines. To reduce the number of output channels of the gate driver 300, a multiplexer (not shown) may be added between the gate driver 300 and the gate lines GL. The multiplexer 210 and the gate driver 300 may be formed directly on the thin film transistor substrate together with the pixel array as shown in FIG. The multiplexer 210 and the gate driver 300 are arranged in the non-display area NA and the pixel array is arranged in the display area AA as shown in FIG.

The display device of the present invention can be applied to an active display device using a thin film transistor, for example, a liquid crystal display device, an organic light emitting diode display device, an electrophoretic display device, or any display device requiring a thin film transistor. Hereinafter, with reference to the drawings, application examples of a display apparatus to which the thin film transistor substrate according to the present invention is applied will be described.

≪ Second application example >

FIG. 8 is a plan view showing a thin film transistor substrate having an oxide semiconductor layer included in a fringe field type liquid crystal display device, which is a horizontal electric field type according to a second application example of the present invention. FIG. 9 is a cross-sectional view of the thin film transistor substrate shown in FIG. 8 taken along the cutting line I-I '.

The thin film transistor substrate having the metal oxide semiconductor layer shown in FIGS. 8 and 9 includes a gate wiring GL and a data wiring DL intersecting each other with a gate insulating film GI interposed therebetween on a lower substrate SUB, And a thin film transistor (T) formed on the substrate. A pixel region is defined by the intersection structure of the gate line GL and the data line DL.

The thin film transistor T includes a gate electrode G branched from the gate line GL, a source electrode S branched from the data line DL, a drain electrode D opposed to the source electrode S, And a semiconductor layer A which overlaps the gate electrode G on the insulating film GI and has a channel region between the source electrode S and the drain electrode D. [

At one end of the gate line GL, a gate pad GP for receiving a gate signal from the outside is disposed. The gate pad GP contacts the gate pad intermediate terminal IGT through the first gate pad contact hole GH1 passing through the gate insulating film GI. The gate pad intermediate terminal IGT contacts the gate pad terminal GPT through the second gate pad contact hole GH2 passing through the first protective film PA1 and the second protective film PA2. On one side of the data line DL, a data pad DP for receiving a pixel signal from the outside is disposed. The data pad DP contacts the data pad terminal DPT through the data pad contact hole DPH passing through the first protective film PA1 and the second protective film PA2.

And a pixel electrode PXL and a common electrode COM disposed in the pixel region with a second protective film PA2 interposed therebetween to form a fringe field. The common electrode COM can be connected to the common wiring CL arranged in parallel with the gate wiring GL. The common electrode COM is supplied with a reference voltage (or common voltage) for liquid crystal driving through the common line CL. Alternatively, the common electrode COM may have a shape arranged on the entire surface of the substrate SUB except for a portion where the drain contact hole DH is disposed. In other words, it covers the upper portion of the data line DL, and the common electrode COM may function to shield the data line DL.

The position and shape of the common electrode COM and the pixel electrode PXL may have various shapes according to the design environment and purpose. A constant reference voltage is applied to the common electrode COM, while a voltage value that varies from time to time is applied to the pixel electrode PXL according to the video data to be implemented. Therefore, parasitic capacitance may occur between the data line DL and the pixel electrode PXL. It is preferable that the common electrode COM is arranged first and the pixel electrode PXL is arranged on the uppermost layer since this parasitic capacitance causes a problem in image quality.

That is, the organic material having a low dielectric constant is thickly deposited on the first protective film PA1 covering the data line DL and the thin film transistor T to form the planarization film PAC, and then the common electrode COM is formed. After the second protective film PA2 covering the common electrode COM is formed, the pixel electrode PXL overlapping the common electrode COM is formed on the second protective film PA2. In this structure, the pixel electrode PXL is separated from the data line DL by the first protective film PA1, the planarization film PAC, and the second protective film PA2, so that the data line DL and the pixel electrode PXL, The parasitic capacitance can be reduced. However, the present invention is not limited thereto. In some cases, the pixel electrode PXL may be arranged first, and the common electrode COM may be arranged on the uppermost layer.

The common electrode COM has a rectangular shape corresponding to the shape of the pixel region, and the pixel electrode PXL has a plurality of line segments. In particular, the pixel electrode PXL has a structure in which the pixel electrode PXL is vertically overlapped with the common electrode COM via the second protective film PA2. Thus, a fringe field is formed between the pixel electrode PXL and the common electrode COM. By the fringe field type electric field, the liquid crystal molecules arranged in the horizontal direction between the thin film transistor substrate and the color filter substrate are rotated by dielectric anisotropy. The transmittance of light passing through the pixel region is varied according to the degree of rotation of the liquid crystal molecules, thereby realizing the gradation.

8 and 9 for describing the second application example of the present invention, the structure of the thin film transistor T in the liquid crystal display device is schematically shown for the sake of convenience. The structures of the first and second thin film transistors T1 and T2 described in the first and second embodiments of the present invention can be applied. For example, when low-speed driving is required, a second thin film transistor T2 having an oxide semiconductor layer can be applied. When a low power consumption is required, the first thin film transistor T1 having a polycrystalline semiconductor layer can be applied. Or the first and second thin film transistors T1 and T2 may be connected to each other so as to complement each other.

<Third Application Example>

10 is a plan view showing the structure of a pixel in a matrix organic light emitting diode display device according to a third application example of the active present invention. 11 is a cross-sectional view showing the structure of an active matrix organic light emitting diode display device cut into a perforated line II-II 'in FIG.

10 and 11, the active matrix organic light emitting diode display device includes a switching thin film transistor ST, a driving thin film transistor DT connected to the switching thin film transistor, an organic light emitting diode OLE connected to the driving thin film transistor DT, .

The switching thin film transistor ST is arranged on the substrate SUB in a region where the gate wiring GL and the data wiring DL cross each other. The switching thin film transistor ST has a function of selecting a pixel by supplying a data voltage from the data line DL to the gate electrode DG and the storage capacitor STG of the driving thin film transistor DT in response to a scan signal . The switching thin film transistor ST includes a gate electrode SG, a semiconductor layer SA, a source electrode SS and a drain electrode SD which branch off from the gate wiring GL. The driving thin film transistor DT drives the organic light emitting diode OLE of the pixel selected by the switching thin film transistor ST by adjusting the current flowing through the organic light emitting diode OLE of the pixel according to the gate voltage.

The driving thin film transistor DT includes a gate electrode DG connected to the drain electrode SD of the switching thin film transistor ST, a source electrode DS connected to the semiconductor layer DA, the driving current wiring VDD, Electrode DD. The drain electrode DD of the driving thin film transistor DT is connected to the anode electrode ANO of the organic light emitting diode OLE. An organic light emitting layer OL is interposed between the anode electrode ANO and the cathode electrode CAT. The cathode electrode CAT is connected to the base wiring VSS.

11, gate electrodes SG and DG of a switching thin film transistor ST and a driving thin film transistor DT are disposed on a substrate SUB of an active matrix organic light emitting diode display device have. A gate insulating film GI covers the gate electrodes SG and DG. The semiconductor layers SA and DA are disposed in a part of the gate insulating film GI overlapping the gate electrodes SG and DG. The source electrodes SS and DS and the drain electrodes SD and DD are disposed to face the semiconductor layers SA and DA at regular intervals. The drain electrode SD of the switching thin film transistor ST is in contact with the gate electrode DG of the driving thin film transistor DT through the drain contact hole DH passing through the gate insulating film GI. A protective film PAS covering the switching thin film transistor ST and the driving thin film transistor DT having such a structure is laminated on the entire surface.

And a color filter CF is disposed at a portion corresponding to the region of the anode electrode ANO. It is preferable that the color filter CF has a large area as much as possible. For example, a shape overlapping many regions of the data line DL, the driving current wiring VDD and the gate wiring GL of the previous stage. Thus, the surface of the substrate on which the switching thin film transistor ST, the driving thin film transistor DT, and the color filters CF are disposed is not flat, and the steps are severe. The organic light emitting layer OL must be laminated on a flat surface so that light emission can be constantly and evenly emitted. Therefore, the planarizing film (PAC) or the overcoat layer (OC) is laminated on the entire surface of the substrate in order to flatten the surface of the substrate.

An anode electrode ANO of the organic light emitting diode OLE is disposed on the overcoat layer OC. The anode electrode ANO is connected to the drain electrode DD of the driving thin film transistor DT through the pixel contact hole PH formed in the overcoat layer OC and the protective film PAS.

On the substrate on which the anode electrode ANO is arranged, a bank BA is formed on a region where the switching thin film transistor ST, the driving thin film transistor DT and the various wirings DL, GL and VDD are arranged to define a pixel region. (Or a bank pattern) is disposed. And the anode electrode ANO exposed by the bank BA becomes a light emitting region. An organic light emitting layer OL is laminated on the anode electrode ANO exposed by the bank BA. A cathode electrode (CAT) is sequentially formed on the organic light emitting layer (OL). In the case where the organic light emitting layer OL is made of an organic material emitting white light, a color assigned to each pixel is represented by a color filter CF positioned below. The organic light emitting diode display device having the structure as shown in FIG. 11 is a bottom emission display device emitting light in a downward direction.

A storage capacitor (or 'Storage Capacitance') STG is disposed between the gate electrode DG and the anode electrode ANO of the driving thin film transistor DT. The storage capacitor STG is connected to the driving thin film transistor DT so that the voltage applied to the gate electrode DG of the driving thin film transistor DT is stably maintained by the switching thin film transistor ST.

By applying the thin film transistor substrate as described above, a high-quality active display device can be realized. Particularly, in order to have more excellent driving characteristics, it is preferable to form the semiconductor layer of the thin film transistor with a metal oxide semiconductor material.

The metal oxide semiconductor material is characterized in that its characteristics are rapidly deteriorated when voltage is driven in a state exposed to light. Therefore, it is preferable that the semiconductor layer has a structure capable of blocking light emitted from the outside at the top and bottom of the semiconductor layer. In the case of the thin film transistor substrate described above, the thin film transistor preferably has a bottom gate structure. That is, the light incident from the bottom can be blocked to some extent by the gate electrode G which is a metal material.

As described above, a plurality of pixel regions arranged in a matrix manner are arranged in the thin film transistor substrate for a flat panel display. In addition, at least one or more thin film transistors are disposed in each unit pixel region. That is, the entire substrate region has a structure in which a plurality of thin film transistors are distributed. The structure of each of the plurality of pixels is formed with the same structure because they all have the same purpose and have the same quality and property.

However, in some cases it may be necessary to vary the characteristics of the thin film transistors. For example, in the case of an organic light emitting diode display, a switching thin film transistor ST and a driving thin film transistor DT are included in one pixel region. Since the switching thin film transistor ST and the driving thin film transistor DT have different purposes, their required characteristics are also different. For this, it is possible to design a semiconductor channel layer having the same structure and the same semiconductor channel layer, but different sizes to suit respective functions. Alternatively, if necessary, a compensation thin film transistor may be further provided to complement the function or performance.

In FIGS. 10 and 11 for explaining the third application example of the present invention, the structure of the thin film transistors ST and DT of the organic light emitting diode display device is schematically shown for convenience. The structures of the first and second thin film transistors T1 and T2 described in the first and second embodiments of the present invention can be applied. For example, the second thin film transistor T2 having an oxide semiconductor layer may be applied to the switching thin film transistor ST. As the driving thin film transistor DT, a first thin film transistor T1 having a polycrystalline semiconductor layer can be applied. As described above, the disadvantages of the counter thin film transistor can be complemented by the advantages of the first and second thin film transistors T1 and T2.

&Lt; Fourth application example >

As another example, a thin film transistor substrate in which a driving element is embedded in a non-display region of a display device may be used. Hereinafter, the case where the driving elements are formed directly on the display panel will be described in detail with reference to FIGS. 12 and 13. FIG.

12 is an enlarged plan view showing a schematic structure of an organic light emitting diode display device according to a fourth application example of the present invention. FIG. 13 is a cross-sectional view showing the structure of an organic light emitting diode display device according to a fourth application example of the present invention, cut in a cutting line III-III 'in FIG. Here, a thin film transistor substrate for a flat panel display in which a driving element is incorporated is described, and a detailed description of the thin film transistor and the organic light emitting diode arranged in the display region is omitted.

First, the structure on a plane will be described with reference to FIG. The organic light emitting diode display device incorporating the gate driver (GIP) according to the fourth application example of the present invention includes a display area AA for displaying image information, a display area AA for driving various elements for driving the display area AA, And a substrate SUB divided into display areas NA. A plurality of pixel areas PA arranged in a matrix manner are defined in the display area AA. In FIG. 5, the pixel regions PA are indicated by dotted lines.

For example, pixel regions PA can be defined in a rectangle of the NxM system. However, it is not necessarily limited to this method, but may be arranged in various ways. Each pixel region may have the same size or different sizes. In addition, three subpixels representing RGB (red-green) colors may be regularly arranged as one unit. In the simplest structure, the pixel regions PA include a plurality of gate lines GL extending in the horizontal direction, a plurality of data lines DL and a plurality of driving current lines VDD extending in the vertical direction, .

A data driving unit (DIC) for supplying a signal corresponding to image information to the data lines DL is formed in the non-display area NA defined at the outer periphery of the pixel area PA, A gate driving unit (GIP) for supplying a scan signal to the gate lines GL may be disposed. The data driver DIC is mounted outside the substrate SUB in the case of a high resolution higher than the VGA level in which the number of the data wirings DL and the driving current wirings VDD increases, ) May be arranged instead of the data connection pads.

In order to simplify the structure of the display device, the gate driver GIP is preferably formed directly on one side of the substrate SUB. A base wire (Vss) for supplying a base voltage is disposed at the outermost portion of the substrate (SUB). It is preferable that the ground wiring Vss is arranged to receive a ground voltage supplied from the outside of the substrate SUB and to supply a base voltage to both the data driving unit DIC and the gate driving unit GIP. For example, the induced wiring Vss is connected to a data driver DIC to be mounted separately on the upper side of the substrate SUB and includes a gate driver GIP disposed on the left and / or right side of the substrate SUB, So as to surround the substrate.

In each pixel region PA, organic light emitting diodes (OLEDs), which are core components of the organic light emitting diode display device, and thin film transistors for driving the organic light emitting diodes are disposed. The thin film transistors may be arranged in the thin film transistor area TA defined at one side of the pixel area PA. The organic light emitting diode includes an anode electrode ANO, a cathode electrode CAT, and an organic light emitting layer OL interposed between the two electrodes. The region in which light is actually emitted is determined by the area of the organic light emitting layer overlapping with the anode electrode ANO.

The anode electrode ANO has a shape occupying a part of the pixel region PA and is connected to a thin film transistor arranged in the thin film transistor region TA. The organic light emitting layer OL is stacked on the anode electrode ANO. The region where the anode electrode ANO and the organic light emitting layer OL overlap is determined as the actual light emitting region. The cathode electrode CAT is formed as a single body so as to cover the entire area of the display area AA where at least the pixel areas PA are arranged on the organic light emitting layer OL.

The cathode electrode CAT contacts the base wiring Vss disposed on the outer side of the substrate SUB beyond the gate driver GIP. That is, the base voltage is applied to the cathode electrode CAT through the base wire Vss. The cathode electrode CAT receives a base voltage, the anode electrode ANO receives an image voltage, and light is emitted from the organic light emitting layer OL due to a voltage difference therebetween to display image information.

13, a cross-sectional structure of an organic light emitting diode display device according to a fourth application example of the present invention will be described in more detail. A non-display area NA in which a gate driver GIP and a base wire Vss are disposed on a substrate SUB and a switching thin film transistor ST, a driving thin film transistor DT and an organic light emitting diode OLE are arranged A display area AA is defined.

The gate driver GIP may include a thin film transistor formed in the process of forming the switching thin film transistor ST and the driving thin film transistor DT. The switching thin film transistor ST disposed in the pixel region PA includes a gate electrode SG, a gate insulating film GI, a channel layer SA, a source electrode SS and a drain electrode SD. The driving thin film transistor DT includes a gate electrode DG connected to the drain electrode SD of the switching thin film transistor ST, a gate insulating film GI, a channel layer DA, a source electrode DS and a drain electrode DD).

A protective film PAS and a planarizing film PL are sequentially stacked on the thin film transistors ST and DT. On the planarizing film PL, an isolated rectangular anode electrode ANO occupying only a certain portion in the pixel region PA is disposed. The anode electrode ANO is in contact with the drain electrode DD of the driving thin film transistor DT through the contact hole passing through the protective film PAS and the flattening film PL.

On the substrate on which the anode electrode ANO is formed, a bank BA defining a light emitting region is disposed. The bank BA has a shape that exposes most of the anode electrode ANO. An organic light emitting layer OL is stacked on the anode electrode ANO exposed by the bank BA pattern. A cathode electrode (CAT) made of a transparent conductive material is laminated on the bank BA and the organic light emitting layer OL. Thereby, an organic light emitting diode (OLE) including an anode electrode ANO, an organic light emitting layer OL, and a cathode electrode CAT is disposed.

The organic light emitting layer OL may emit white light and color may be expressed by a separately formed color filter CF. In this case, the organic light emitting layer OL is preferably laminated so as to cover at least the display area AA.

It is preferable that the cathode electrode CAT covers over the display area AA and the non-display area NA so as to be in contact with the base wiring Vss disposed on the outer side of the substrate SUB beyond the gate driving part GIP. Thereby, the base voltage can be applied to the cathode electrode CAT through the base wire Vss.

On the other hand, the base wiring Vss can be formed on the same layer with the same material as the gate electrode G. [ In this case, it is possible to make contact with the cathode electrode CAT through the protective film PAS covering the base wiring Vss and the contact hole penetrating the gate insulating film GI. Alternatively, the base wire Vss may be formed on the same layer with the same material as the source-drain (SS-SD, DS-DD) electrode. In this case, the base wire Vss can contact the cathode electrode CAT through the contact hole penetrating the protective film PAS.

12 and 13, which illustrate a fourth application example of the present invention, for the sake of convenience, a thin film transistor structure of the thin film transistors ST and DT and the gate driving element GIP of the organic light emitting diode display device is shown schematically. The structures of the first and second thin film transistors T1 and T2 described in the first and second embodiments of the present invention can be applied. For example, the second thin film transistor T2 having an oxide semiconductor layer may be applied to the switching thin film transistor ST. As the driving thin film transistor DT, a first thin film transistor T1 having a polycrystalline semiconductor layer can be applied. The first thin film transistor T1 having a polycrystalline semiconductor layer may be applied to the gate driver GIP. If necessary, the gate driver GIP may be provided with a C-MOS type thin film transistor having both a P-MOS type and an N-MOS type.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

GL: gate wiring PAS: protective film
DL: Data wiring VDD: Driving current wiring
PA: pixel region T: thin film transistor
AA: display area NA: non-display area
G: gate electrode A: semiconductor layer
S: source electrode D: drain electrode
GI: gate insulating film ILD: intermediate insulating film
SIN: nitride film SIO: oxide film
SIO1: upper oxide film SIO2: lower oxide film

Claims (22)

A first thin film transistor including a polycrystalline semiconductor layer, a first gate electrode disposed on the polycrystalline semiconductor layer, a first source electrode, and a first drain electrode;
A second thin film transistor including a second gate electrode, an oxide semiconductor layer disposed over the second gate electrode, a second source electrode, and a second drain electrode;
An intermediate insulating film disposed on the first gate electrode and including a nitride film; And
And an oxide film disposed on the intermediate insulating film and covering the second gate electrode,
Wherein the oxide semiconductor layer is disposed so as to overlap with the second gate electrode on the oxide film,
The first source electrode, the first drain electrode, and the second gate electrode are disposed between the intermediate insulating film and the oxide film;
And the second source electrode and the second drain electrode are disposed on the oxide semiconductor layer.
The method according to claim 1,
Further comprising a drive circuit,
Wherein at least one of the first thin film transistor and the second thin film transistor is included in a pixel,
Wherein at least one of the first thin film transistor and the second thin film transistor is included in the driving circuit.
The method according to claim 1,
And a gate insulating film covering the polycrystalline semiconductor layer,
Wherein the first gate electrode is disposed on the gate insulating film and overlaps with the polycrystalline semiconductor layer.
The method according to claim 1,
The second thin film transistor is a switch element for selecting a pixel,
Wherein the first thin film transistor is a driving element for driving the organic light emitting diode of the pixel selected by the second thin film transistor.
3. The method of claim 2,
Wherein the driving circuit comprises:
A data driver for outputting a data voltage;
A multiplexer for distributing the data voltage from the data driver to the data line; And
And a gate driver for outputting the scan pulse to the gate wiring,
Wherein at least one of the first thin film transistor and the second thin film transistor is included in one of the multiplexer and the gate driver.
The method of claim 3,
The first source electrode is connected to one side of the polycrystalline semiconductor layer through a source contact hole passing through the intermediate insulating film and the gate insulating film,
Wherein the first drain electrode is connected to the other side of the polycrystalline semiconductor layer through a drain contact hole passing through the intermediate insulating film and the gate insulating film,
The second source electrode is in contact with one side of the oxide semiconductor layer,
And the second drain electrode is in contact with the other side of the oxide semiconductor layer.
The method according to claim 6,
Wherein the first source electrode and the first drain electrode comprise the same material as the second gate electrode.
8. The method of claim 7,
Wherein the second gate electrode is connected to a gate wiring including the same material as the first gate electrode through a gate contact hole passing through the intermediate insulating film.
8. The method of claim 7,
Wherein the second source electrode is connected to a data line including the same material as the second gate electrode through a data contact hole passing through the oxide film.
The method according to claim 1,
Wherein the intermediate insulating film further comprises a lower oxide film.
11. The method of claim 10,
And the nitride film is disposed on the lower oxide film.
A first semiconductor layer comprising a polycrystalline semiconductor material;
A gate insulating film covering the first semiconductor layer;
A first gate electrode overlying the first semiconductor layer on the gate insulating film;
An intermediate insulating film covering the first gate electrode and including a nitride film;
A second gate electrode, a first source electrode, and a first drain electrode disposed on the intermediate insulating film;
An oxide film covering the second gate electrode, the first source electrode, and the first drain electrode;
A second semiconductor layer disposed on the oxide film and overlapping the second gate electrode, the second semiconductor layer including an oxide semiconductor material; And
And a second source electrode and a second drain electrode disposed on the second semiconductor layer.
13. The method of claim 12,
Wherein the first semiconductor layer, the first gate electrode, the first source electrode, and the first drain electrode are included in the first thin film transistor,
Wherein the second semiconductor layer, the second gate electrode, the second source electrode, and the second drain electrode are included in the second thin film transistor.
14. The method of claim 13,
Further comprising a drive circuit,
Wherein at least one of the first thin film transistor and the second thin film transistor is included in a pixel,
Wherein at least one of the first thin film transistor and the second thin film transistor is included in the driving circuit.
14. The method of claim 13,
The second thin film transistor is a switch element for selecting a pixel,
Wherein the first thin film transistor is a driving element for driving the organic light emitting diode of the pixel selected by the second thin film transistor.
15. The method of claim 14,
Wherein the driving circuit comprises:
A data driver for outputting a data voltage;
A multiplexer for distributing the data voltage from the data driver to the data line;
And a gate driver for outputting the scan pulse to the gate wiring,
Wherein at least one of the first thin film transistor and the second thin film transistor is included in one of the multiplexer and the gate driver.
13. The method of claim 12,
The first source electrode is connected to one side of the first semiconductor layer through a source contact hole passing through the intermediate insulating film and the gate insulating film,
Wherein the first drain electrode is connected to the other side of the first semiconductor layer through a drain contact hole passing through the intermediate insulating film and the gate insulating film,
The second source electrode is in contact with one side of the second semiconductor layer,
And the second drain electrode is in contact with the other side of the second semiconductor layer.
18. The method of claim 17,
Wherein the first source electrode and the first drain electrode comprise the same material as the second gate electrode.
19. The method of claim 18,
Wherein the second gate electrode is connected to a gate wiring including the same material as the first gate electrode disposed on the gate insulating film through a gate contact hole passing through the intermediate insulating film.
19. The method of claim 18,
Wherein the second source electrode is connected to a data line including the same material as the second gate electrode disposed on the intermediate insulating film through a data contact hole passing through the oxide film.
13. The method of claim 12,
Wherein the intermediate insulating film further comprises a lower oxide film.
22. The method of claim 21,
And the nitride film is disposed on the lower oxide film.

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