KR20150096189A - Semiconductor package for high power transistor - Google Patents

Abstract

A high output semiconductor device package according to the present invention is a package for a high output semiconductor device, comprising: a flange for providing electrical grounding and mechanical connection of an in-package configuration; A die of a high power transistor having a gate, a drain and a source electrically connected to the flange; An input lead frame mechanically connected to the flange and electrically connected to the gate; A gate matching circuit for performing impedance matching between the input lead frame and the gate of the die; A drain matching circuit portion located on the flange and having an input, an output and a bias input, the input conducting impedance matching coupled to a drain of the die; And an output integrated lead frame which is mechanically connected to the flange and connects the die and the external terminal to integrally perform input and output of RF power and DC power.

Description

[0001] DESCRIPTION [0002] SEMICONDUCTOR PACKAGE FOR HIGH POWER TRANSISTOR [0003]

The present invention relates to a high-power semiconductor device package, and more particularly, to a semiconductor device having a high-output semiconductor device package and a method of manufacturing the same. In order to improve the memory effect of a transistor and the asymmetry phenomenon of a cross- Device package.

RF power transistors are commonly used as signal amplifiers in wireless communication devices because of their inherent non-linear components, the input capacitance, gain, and phase transitions of the transistors vary. The nonlinearity of the RF power transistor is increased by the effects of internal and external matching networks designed to optimize the power transfer from the transistor, which adversely affects the broadband, linear performance of the amplifier.

The bias circuit used to deliver DC power to the transistor and the component to control the lower frequency spurious generation are known to affect the operation / video bandwidth of the transistor to improve power delivery and broadband linearity of the transistor have. An example of such a circuit is disclosed in Korean Patent Publication No. 10-2007-0014087. Korean Patent Laid-Open Publication No. 10-2007-0014087 discloses an RF power transistor with a parallel matching circuit. According to this prior art, some of the problems with the broadband performance of the RF power transistor are solved. The video bandwidth of the transistor is 40 to 45 MHz To about 90 to 100 MHz.

However, due to the spread of smart phones and wireless Internet, the demand for wireless communication applications has increased explosively, and the operating frequency of the wireless communication infrastructure has also rapidly increased, and the bandwidth for communication operation has reached from several tens to more than 100 MHz. This increase in communication operating bandwidth requires broadband characteristics for the power semiconductors used in communications, where the transistors are designed with internal and external matching circuits to optimize nonlinearity and power delivery, and the resulting memory device-specific memory effects It limits the improvement of the broadband performance and the linearity of the communication operating frequency of the power semiconductor.

In order to improve such a situation, it is common to construct a low impedance short circuit for a video band and to implement a parallel capacitor with an internal matching circuit which requires a large capacitance value. However, in the case of parallel capacitors, due to the limitations of the capacitor capacitance that can be implemented in the internal matching circuit, the low Q value of the capacitor, and the power loss at the operating frequency due to the influence of the self resonance frequency There is a limitation in improving the output power loss and in adjusting the impedance of the video band to improve the asymmetry phenomenon of the cross modulation component. 1 to 3 are circuit diagrams showing an embodiment of a semiconductor device package according to the prior art. In this case, an additional lead frame 1, 82 for supplying DC power was required, thereby increasing the size of the device and the PCB A problem has occurred. In addition, the second inductor 30 of the related art has a problem that the wire is burned by the overcurrent when a large current flows.

Korean Patent Publication No. 10-2007-0014087

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above problems, and it is an object of the present invention to provide a high-power semiconductor device package, which uses a parallel resonant circuit to improve the memory effect of a transistor caused by impedance variation of an operation band and a video band, In order to solve the problem.

A high output semiconductor device package according to an embodiment of the present invention uses an output integrated lead frame to reduce an additional lead frame for DC power input and output, thereby miniaturizing the device and the PCB, simplifying the manufacturing process of the device, And to save money.

To achieve the above object, a high output semiconductor device package according to the present invention is a package for a high output semiconductor device, comprising: a flange for providing electrical grounding and mechanical connection of an arrangement in a package; A die of a high power transistor having a gate, a drain and a source electrically connected to the flange; An input lead frame mechanically connected to the flange and electrically connected to the gate; A gate matching circuit for performing impedance matching between the input lead frame and the gate of the die; A drain matching circuit portion located on the flange and having an input, an output and a bias input, the input conducting impedance matching coupled to a drain of the die; And an output integrated lead frame which is mechanically connected to the flange and connects the die and the external terminal to integrally perform input and output of RF power and DC power.

A high output semiconductor device package according to an embodiment of the present invention is characterized in that the drain matching circuit portion includes a shunt network and a series inductor.

The shunt network includes a first inductor, a first capacitor, a second inductor, and a second capacitor. The first inductor has a terminal connected to the output integrated lead One terminal of the second inductor is connected to the node between the first inductor and the first capacitor and the other terminal is connected to the second capacitor and the other terminal of the second inductor is connected to the frame and the other terminal is connected to the ground in series with the first capacitor, And connected to the ground in series.

The high output semiconductor device package according to another embodiment of the present invention is characterized in that the first inductor is electrically connected through a bond wire and at least one bond wire is used in parallel.

The high output semiconductor device package according to another embodiment of the present invention is characterized in that the second inductor is electrically connected through a bond wire and at least one or more bond wires are used in parallel.

The high output semiconductor device package according to another embodiment of the present invention is characterized in that the first inductor is 300 to 400 pH, the first capacitor is 20 to 30 pF, the second inductor is 450 to 550 pH, And the capacitor is 15 to 25 nF.

The high output semiconductor device package according to another embodiment of the present invention is characterized in that the second capacitor is larger than the first capacitor and is arranged close to the output integrated lead frame.

The high output semiconductor device package according to another embodiment of the present invention is characterized in that the gate matching circuit portion includes a T network and a parallel network.

The high power semiconductor device package according to another embodiment of the present invention is characterized in that the T network includes a first gate matching inductor 230, a second gate matching inductor 240 and a gate matching capacitor 250, Is coupled to the input leadframe through the first gate matching inductor and to the gate of the die through the second gate matching inductor.

The high output semiconductor device package according to another embodiment of the present invention is characterized in that the first gate matching inductor is electrically connected through a bond wire, and at least one or more bond wires are used in parallel.

The high output semiconductor device package according to another embodiment of the present invention is characterized in that the second gate matching inductor is electrically connected through a bond wire and at least one bond wire is used in parallel.

A high output semiconductor device package according to another embodiment of the present invention is characterized in that the die is a gallium nitride (GaN) transistor.

A high output semiconductor device package according to another embodiment of the present invention is characterized in that the die is bonded to the flange and the source is mechanically and electrically connected.

The high output semiconductor device package according to another embodiment of the present invention is characterized in that the die includes a high output transistor formed of a plurality of unit elements.

A high-power semiconductor device package according to another embodiment of the present invention includes at least one die, at least one gate matching circuit, and at least one drain matching circuit.

The high output semiconductor device package according to the present invention provides an effect of improving the memory effect of the transistor and the asymmetry phenomenon of the intermodulation component caused by the impedance variation of the operation band and the video band by using the parallel resonance circuit.

A high output semiconductor device package according to an embodiment of the present invention uses an output integrated lead frame to reduce an additional lead frame for DC power input and output, thereby miniaturizing the device and the PCB, simplifying the manufacturing process of the device, Saving effect.

1 is a circuit diagram showing an embodiment of a semiconductor device package according to the prior art;
Fig. 2 is an equivalent circuit diagram of the semiconductor device package shown in Fig. 1. Fig.
3 is a view illustrating a physical shape of the semiconductor device package shown in FIG. 1;
4 is a circuit diagram showing a high-power semiconductor device package according to an embodiment of the present invention.
5 is a view showing a physical shape of the high-power semiconductor device package shown in FIG. 4;
6 is an equivalent circuit diagram of the high-power semiconductor device package shown in Fig.
7 is a graph showing the frequency response of a high power semiconductor device package according to an embodiment of the present invention.
FIG. 8 and FIG. 9 are graphs showing the third-order intermodulation characteristic response of the high-output semiconductor device package according to the prior art and the present invention.
10 is a circuit diagram showing a high-power semiconductor device package according to another embodiment of the present invention.
11 is a view showing a physical shape of the high-output semiconductor device package shown in Fig.
12 is a circuit diagram showing a high-power semiconductor device package according to another embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Fig. 4 shows a high-power semiconductor device package according to the present invention, Fig. 5 is an equivalent circuit, and Fig. 6 shows a physical embodiment of such a circuit diagram. The high output semiconductor device package 190 according to the present invention includes a flange 210, a die 100, an input lead frame 220, an output terminal, a gate matching circuit, a drain matching circuit, As shown in FIG. The components are as follows.

The flange 210 includes a bracket that provides a mechanical support for the connector and the element in the semiconductor device package.

The die 100 is a high power transistor having a gate, a drain, and a source. The source is electrically connected to the flange 210, where the die 100 is bonded to the flange 210 and the source is mechanically and electrically connected. Such die 100 may be, for example, a gallium nitride (GaN) transistor, which is typically used as an RF power transistor. This transistor uses shunt inductor 120 to resonate the drain-source output capacitance Cds.

The input lead frame 220 is mechanically connected to the flange 210 and electrically connected to the gate of the die.

The gate matching circuit unit performs impedance matching between the input lead frame 220 and the gate of the die.

The gate matching circuitry serves to effectively transfer the RF power coming from the RF supply to the gate of the die and the drain matching circuitry performs the function of effectively transferring the RF power coming from the drain of the die to the output and load.

The gate matching circuit portion is formed in the same manner as the output matching circuit portion with respect to the bias supply portion and provides compensation for the inductor as well as the capacitor connected to the gate of the die.

According to an embodiment of the present invention, the gate matching circuitry may comprise a T network and a parallel network. T network converts the impedance seen by the transistor input lead frame at the communication operating frequency to match the output impedance of the line connected to the input lead frame 220. [

T network may include a first gate matching inductor 230, a second gate matching inductor 240 and a gate matching capacitor 250. The gate matching capacitor 250 may be coupled to the input leadframe through a first gate matching inductor 230 and to the gate of the die through a second gate matching inductor 240.

The gate matching capacitor 250 is coupled to the input lead frame 220 through a first gate matching inductor 230 and to the gate of the die through a second gate matching inductor 240. At this time, the first gate matching inductor 230 is electrically connected through a bond wire, and the second gate matching inductor 240 is electrically connected through a bond wire. As such, the bond wire is used to electrically connect elements in the semiconductor device package 190, often having a self-inductance that can not be overlooked at normal operating frequencies. At least one bond wire may be used in parallel to reduce the resistivity of a particular bond wire.

The drain matching circuitry is located on the flange 210 and has input, output, and bias inputs, and the input performs impedance matching coupled to the drain of the die. The drain matching circuitry provides compensation for the inductors as well as the capacitors connected to the drain of the die.

The drain matching circuitry may include a shunt network and a series inductor. The shunt network may include a first inductor 120, a first capacitor 130, a second inductor 140, and a second capacitor 150.

One terminal of the first inductor 120 is connected to the output integrated lead frame 170 and the other terminal is connected to the ground in series with the first capacitor 130.

One terminal of the second inductor 140 is connected to the node between the first inductor 130 and the first capacitor 120 and the other terminal is connected to the ground in series with the second capacitor 150. These devices not only provide matching at a predetermined load impedance, but also provide a broadband impedance short to the video band to provide an appropriate power level and balanced enhancement intermodulation component for efficient amplification.

That is, the node between the first inductor 120 and the first capacitor 130 is disposed physically very close to the second capacitor 150 through the second inductor 140. These two capacitors 130 and 150 Are connected in parallel through the very small second inductor 140. [ In general, the value of the second capacitor 150 is much larger than the value of the first capacitor 130.

The output integrated lead frame 170 connects the die 100 and the external terminal 180 to integrate the input and output of RF power and DC power.

The drain bias is connected to the external terminal 180 and the drain terminal through the exterior of the semiconductor device package on the output integrated lead frame 170 and is connected to the first capacitor 130 and the second capacitor 150 to form a low impedance Thereby improving the frequency characteristics of the video band.

4 illustrates an external termination network 200 coupled through external terminals 180 that uses a large external capacitor 160 for controlling low frequency components as an external DC bias input to improve the characteristics of the video band . The specific internal package structure associated with matching circuitry and external DC bias circuitry is selected and deployed to maximize the broadband performance of the packaged device and maximize the power delivery of the RF power transistor.

5 is an equivalent circuit diagram of a circuit diagram of a high-power semiconductor device package according to the present invention. The die 100 shown in FIG. 5 includes a first capacitor 130 and a second capacitor 150 through the output integrated leadframe 170 and the coupling inductor 110 together with the capacitance existing inside the device, 1 inductor 120 and the second inductor 140 to ground. The coupled structure operates as a broadband parallel resonance circuit to form a broadband impedance short circuit with respect to a video band, thereby minimizing power fluctuation in a low frequency band due to impedance variation of a video band. In addition, the second capacitor 150 of a high capacity connected by the second inductor 140 inherently exhibits a characteristic of short-circuiting impedance in a low frequency band which is a video band and a low self-resonant frequency characteristic Inductance characteristics. Therefore, in the communication operating frequency band, the first capacitor 130 functions as a parallel resonant circuit to provide a high impedance to minimize the power loss to the communication operating frequency.

Figure 7 shows the frequency response of an exemplary embodiment of the circuit shown in Figure 4;

More specifically, the first inductor 120 has a pH of about 300 to 400, specifically 350 pH and 0.01 OMEGA in FIG. 7, the first capacitor 130 is about 20 to 30 V, to be. The second inductor 140 has a pH of about 450-550, which is 500 pH in FIG. 7, and the second capacitor 150 is about 15-25 volts, which may be 20 volts in the embodiment of FIG. The external capacitor 160 may have a value of about 10 pF and the external terminal 180 may include a microstrip transmission line having a termination resistance of 50? And a resonance frequency of 1/4?. The frequency response represents the primary peak at 1.95 GHz. The circuit provides attenuation greater than 40 dB below 100 MHz. The secondary peak is due to the value of the second inductor 140. This should be very small, meaning that the second capacitor 150 should be physically located after the first capacitor 130. For example, if a 1 nH inductor is used instead of 0.5 nH in the second inductor 140, the first peak is shifted down to a frequency of 1000 MHz and the decay rate is reduced from 100 MHz to 20 dB.

Generally, a video band used as a communication operation band has been expanded to more than 100 MHz in recent years. Low frequency power caused by the impedance characteristic of this band is the biggest cause of restriction of linearity improvement of a wireless device. Such low frequency power generated in the band of the video band is a main cause of the asymmetric phenomenon of the intermodulation component represented by the memory effect of the high frequency power device. In particular, it is a third-order intermodulation component used as a representative measure of the linearity performance of a wireless device, and it is considered as a direct cause of the limitation of the linearity improvement due to the asymmetry phenomenon in the cross modulation component of the upper side band and the lower side band. In order to improve such a phenomenon, generally, a method of limiting the magnitude of the power due to the low-frequency impedance fluctuation by setting the impedance of the video band band low is generally used. However, broadband wireless devices are required to cope with environmental changes such as the spread of wireless Internet and users, and existing methods for providing a short-circuit characteristic to the impedance of a video band by coupling a high-capacity capacitor from the outside of the package include a broadband The linearity of the base station or the wireless device is limited.

Figure 9 shows the Inter-Modulation Distortion (IMD) response as a two-tone frequency separation function. Generally, this distortion is measured using lower and upper frequencies (f1, f2), resulting in two main third order distortion components: 3L = 2f1-f2 and 3U = 2f2-f1.

In FIG. 9, the low-band curve represents the lower third IMD product and the upper-band curve represents the upper third IMD product. As shown in the graph of FIG. 9, the IMD increase of the low-band characteristic gradually increases as the tone interval increases. The up-band plot shows flatness up to 80 MHz.

One of the characteristics of the available bandwidth is that the deviation of the third order distortion components (3L, 3U) must be minimal over the entire available frequency range. For example, a roughly 3 dB deviation from the normal IMD level defined at lower frequencies can be used to determine the available bandwidth. As can be seen in FIG. 9, the lower frequency distortion levels of both the upper and lower IMD components range from about -27 dB to -20 dB as the two tone frequency separation space increases. The deviation of these two IMD components, which are approximately ± 3 dB, can be observed around 40 MHz. The available bandwidth is therefore extended beyond 40 MHz.

Another feature of the available bandwidth is the existence of an inflection point of the deviation of the third-order distortion components 3L and 3U over the entire available frequency range. The third order distortion components (3L, 3U) are a function of the bandwidth of the two-tone frequency separation band, and as the bandwidth of the tone increases, the deviations of the two major third order distortion components, i.e., 3L = 2f1-f2 and 3U = 2f2-f1 There is an inflection point in a specific frequency band where the degradation proceeds. This inflection point is defined as a third order intermodulation inflection point, and the size of the frequency band up to this inflection point is a section size that can improve intermodulation of the transistor. As can be seen in FIG. 9, the lower frequency distortion levels for both the upper and lower IMD components range from -30 dB to -20 dB as the two tone frequency separation space increases.

FIGS. 8 and 9 show frequency characteristics according to two-tone spacing. FIG. 8 is a characteristic graph before application to the VBW improvement circuit, and FIG. 9 is a characteristic graph after application to the VBW improvement circuit. 8 and 9, according to the embodiment of the present invention, when the generation band of the inflection point is increased by about 30 MHz in the case of the up-band when applied to the VBW improvement circuit according to the embodiment of the present invention, And increased by about 50%. In the case of the low-band, it increased about 150 MHz at 300 MHz and increased about 100% when compared with 150 MHz before application.

4 to 6, if the inductance of the first inductor 120 is reduced by disposing a second capacitor 150, which is physically located next to the first capacitor 130, on the inside of the package, the increase- free IMD bandwidth and the inflection point of the deviation of the third order intermodulation component size relative to the signal amplitude of the basic available band can be further improved.

FIG. 10 is an equivalent circuit diagram of another example of the operation of the high-power semiconductor device package according to another embodiment of the present invention, and FIG. 11 is a diagram illustrating a physical shape of the high-output semiconductor device package shown in FIG. The output terminal of the die is coupled to the output integrated lead frame 170 via a coupling inductor (wire) 110 and the output integrated lead frame 170 is coupled to the external terminal 180 and the first inductor 120. The first inductor 120 is coupled to the transmission line 131 and the transmission line 131 is coupled to the second capacitor 150 through the second inductor 140. In addition, the transmission line 131 is coupled with the first inductor 120 and coupled to the external termination circuit through the output integrated lead frame 170. The transmission line 131 is used to control not only the video band but also the impedance control of the second and third high frequency components of the transistor device according to the physical size of the line, the characteristics of the transmission line, And the output and efficiency of the transistor element can be improved by this effect.

Figure 12 is an exemplary illustration of a high power semiconductor device package in accordance with another embodiment of the present invention. Generally, a high-power large-power transistor element has a structure in which a plurality of unit elements (dies) 100 having a certain width and length are coupled in parallel at each drain end to generate large power. Thus, in accordance with an embodiment of the present invention, at least one die, at least one gate matching circuit, and at least one drain matching circuit may be included. In the present embodiment, a structure in which a unit element (die) 100 is connected in parallel to an output integrated lead frame is applied, coupling of each unit element (die) 100 constituting a power transistor, To minimize the unstable operation of the video band and the internal matching which are varied by the video signal.

It will be apparent to those skilled in the art that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. .

10: transistor
20: The first inductor of the conventional invention
30: The second inductor of the conventional invention
40: The first capacitor of the conventional invention
50: The third inductor of the conventional invention
60: the second capacitor of the conventional invention
70: Fourth inductor of the conventional invention
81: transistor lead frame I of the conventional invention
82: transistor lead frame II of the conventional invention
90: The third capacitor of the conventional invention
100: die
110: Coupling inductor
120: first inductor
130: a first capacitor
131: transmission line
140: Second inductor
150: second capacitor
160: External capacitor
170: Output integrated lead frame
180: External terminal
190: transistor package
210: Flange
220: Input lead frame
230: first gate matching inductor
240: second gate matching inductor
250: Gate matching capacitor

Claims (15)

As a package for a high output semiconductor device,
A flange providing electrical grounding and mechanical connection of the configuration within the package;
A die of a high power transistor having a gate, a drain and a source electrically connected to the flange;
An input lead frame mechanically connected to the flange and electrically connected to the gate;
A gate matching circuit for performing impedance matching between the input lead frame and the gate of the die;
A drain matching circuit portion located on the flange and having an input, an output and a bias input, the input conducting impedance matching coupled to a drain of the die; And
And an output integrated lead frame that is mechanically connected to the flange and connects the die and the external terminal to integrate input and output of RF power and DC power.
The semiconductor memory device according to claim 1,
A shunt network and a series inductor. ≪ RTI ID = 0.0 > A < / RTI >
3. The method of claim 2,
The shunt network includes a first inductor, a first capacitor, a second inductor, and a second capacitor,
The first inductor has one terminal connected to the output integrated lead frame and the other terminal connected to the ground in series with the first capacitor,
Wherein the second inductor has a terminal connected to a node between the first inductor and the first capacitor and another terminal connected to the ground in series with the second capacitor.
4. The inductor according to claim 3,
Wherein at least one bond wire is used in parallel. ≪ Desc / Clms Page number 20 >
4. The inductor according to claim 3,
Wherein at least one bond wire is used in parallel. ≪ Desc / Clms Page number 20 >
The method of claim 3,
Wherein the first inductor has a pH of 300 to 400,
The first capacitor has a capacitance of 20 to 30 pF,
The second inductor has a pH of 450 to 550,
Wherein the second capacitor is between 15 and 25 nF.
The plasma display apparatus of claim 3, wherein the second capacitor comprises:
The first capacitor being larger than the first capacitor and being disposed in proximity to the output integrated leadframe.
The semiconductor memory device according to claim 1,
T network and a parallel network.
9. The method of claim 8,
A first gate matching inductor (230), a second gate matching inductor (240), and a gate matching capacitor (250), the gate matching capacitor coupled to the input lead frame via the first gate matching inductor And is connected to the gate of the die through a second gate matching inductor.
10. The inductor of claim 9, wherein the first gate-
Wherein at least one bond wire is used in parallel. ≪ Desc / Clms Page number 20 >
10. The inductor of claim 9, wherein the second gate-
Wherein at least one bond wire is used in parallel. ≪ Desc / Clms Page number 20 >
2. The apparatus of claim 1,
Gallium nitride (GaN) transistor.
2. The apparatus of claim 1,
Wherein the source and the drain are bonded to the flange, and the source is mechanically and electrically connected.
2. The apparatus of claim 1,
And a high-output transistor composed of a plurality of unit elements.
The semiconductor package according to claim 1, wherein the high-
At least one die, at least one gate matching circuit, and at least one drain matching circuit.

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