KR20150085591A - Vertical memory devices and methods of manufacturing the same - Google Patents

Abstract

A vertical memory device includes a substrate, channels, gate lines, interlayer dielectric patterns, and a first impurity region. The substrate includes a cell region and an extension region arranged on the side of the cell region. The channels are extended to a first direction vertical to the upper side of the substrate. The gate lines are formed on the outside wall of the channel, and are successively stacked from the upper side of the substrate to the first direction to be separated from each other. The interlayer dielectric patterns are formed between the gate lines in the first direction. The first impurity region is formed in the upper part of an uppermost interlayer dielectric pattern among the interlayer dielectric patterns. The operation reliability of the vertical memory device can be improved by forming the first impurity region on a desired part of the uppermost interlayer dielectric pattern.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a vertical memory device,

The present invention relates to a vertical memory device and a method of manufacturing the same. More particularly, the present invention relates to a nonvolatile memory device having a vertical channel to a substrate and a method of manufacturing the same.

In recent years, vertical memory devices have been developed in which memory cells and insulating films are vertically stacked from a substrate surface for high integration of memory devices. In the vertical memory device, channels extending in the vertical direction from the upper surface of the substrate and gate lines in the vertical direction are stacked, and pads may be provided on the channels.

The pad may be doped with impurities to improve electrical characteristics. However, variations and / or deviations in electrical operating characteristics may occur in the vertical memory device, depending on the distribution of the impurities and / or the arrangement of the memory cells.

It is an object of the present invention to provide a vertical memory device with improved electrical operating characteristics.

It is another object of the present invention to provide a method of manufacturing a vertical memory device with improved electrical operating characteristics.

According to an aspect of the present invention, there is provided a vertical memory device including a substrate, a plurality of gate lines, a plurality of interlayer insulating film patterns, and a first impurity region. The substrate includes a cell region and an extension region disposed on a side of the cell region. The channels extend in a first direction perpendicular to the top surface of the substrate. The gate lines are provided on the outer wall of the channel and are sequentially stacked on the substrate from the upper surface thereof along the first direction. The plurality of interlayer insulating film patterns are formed between the gate lines along the first direction. The first impurity region is formed on the uppermost interlayer insulating film pattern of the plurality of interlayer insulating film patterns.

In exemplary embodiments, it may further comprise pads each formed on the channels. The first impurity region and the pads may have a first impurity concentration and a second impurity concentration, respectively, and the second impurity concentration may be higher than the first impurity concentration.

In exemplary embodiments, the first impurity region and the pad may comprise an n-type impurity.

In exemplary embodiments, the gate lines may include a ground selection line (GSL), a word line, and a string selection line (SSL) that are sequentially stacked from the top surface of the substrate. A second impurity region may be formed in the channel portion adjacent to the string selection line (SSL).

In exemplary embodiments, the second impurity region may include a p-type impurity.

In exemplary embodiments, the gate lines may be arranged in a stepped shape with the width decreasing from the top surface of the substrate. The cell region may be defined as a portion overlapping the uppermost interlayer insulating film pattern in the substrate.

According to another aspect of the present invention, there is provided a method of fabricating a vertical type memory device, including the steps of: alternately and repeatedly depositing interlayer insulating films and sacrificial layers on a substrate. The side surfaces of the interlayer insulating films and the sacrificial films are etched to form a stepped mold structure. A mold protecting film covering the side of the mold structure is formed on the substrate. Through the mold structure to form channels that contact the substrate. The interlayer insulating films and the sacrificial films between the channels are partially etched to form openings. Thereby removing the sacrificial films exposed by the opening. Thereby forming the gate lines in the space where the sacrificial films are removed. A stopper film for exposing the uppermost interlayer insulating film among the interlayer insulating films is formed on the mold protective film. Impurity is implanted on the uppermost interlayer insulating film using the blocking film as an ion implantation mask to form a first impurity region.

In exemplary embodiments, the stopper film may cover a part of the uppermost interlayer insulating film.

In exemplary embodiments, a buried film pattern filling the openings can be formed. The blocking film may be formed on the mold protecting film and the buried film pattern.

In the exemplary embodiments, pads may be further formed on each of the channels. The first impurity region and the pad may have a first impurity concentration and a second impurity concentration, respectively, and the second impurity concentration may be higher than the first impurity concentration.

However, the problems to be solved by the present invention are not limited to the above-mentioned problems, but may be variously expanded without departing from the spirit and scope of the present invention.

As described above, according to the vertical memory device according to the embodiments of the present invention, the difference in electrical characteristics generated between the uppermost gate line and the pad is different from the structure formed between the gate lines. And it is possible to prevent an increase in the resistance of the channel and a scattering failure of the gate line threshold voltage value.

Also, in the LDD ion implantation process, impurities can be implanted into only a desired part of the uppermost interlayer insulating film by using a blocking film, thereby preventing a bridge failure in which the channel and the contact are electrically connected by the impurity. Furthermore, since the conventional step of forming the contact spacer for preventing the bridge failure can be omitted, the process can be simplified and productivity can be improved.

1 is a cross-sectional view illustrating a vertical memory device according to exemplary embodiments.
FIGS. 2 to 11 are cross-sectional views and plan views illustrating a method of manufacturing a vertical type memory device according to exemplary embodiments.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the drawings of the present invention, the dimensions of the structures are enlarged to illustrate the present invention in order to clarify the present invention.

In the present invention, the terms first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

In the present invention, it is to be understood that each layer (film), region, electrode, pattern or structure may be formed on, over, or under the object, substrate, layer, Means that each layer (film), region, electrode, pattern or structure is directly formed or positioned below a substrate, each layer (film), region, or pattern, , Other regions, other electrodes, other patterns, or other structures may additionally be formed on the object or substrate.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, But should not be construed as limited to the embodiments set forth in the claims.

That is, the present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the following description. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

1 is a cross-sectional view illustrating a vertical memory device according to exemplary embodiments.

In the drawings, a direction substantially perpendicular to the upper surface of the substrate is defined as a first direction, and two directions substantially parallel to the upper surface of the substrate and substantially perpendicular to each other are defined as a second direction and a third direction, respectively. The direction indicated by the arrow in the figure and the direction opposite thereto are described in the same direction. The definition of the aforementioned direction is the same in all subsequent figures.

1, the vertical memory device includes a channel 135 protruding in a first direction on a substrate 100, a dielectric layer structure 130 surrounding an outer wall of the channel 135, a dielectric layer structure 130 and gate lines 170 surrounding the channel 135 and spaced apart from each other along the first direction. In addition, a pad 150 is provided on the channel 135 and a bit line contact 190 in contact with the pad 150 and a bit line 190 electrically connected to the bit line contact 190 may be disposed have. In addition, interlayer insulating layer patterns 106 may be formed between adjacent gate lines 170 along the first direction. The substrate 100 may comprise a semiconductor material, such as, for example, monocrystalline silicon, monocrystalline germanium. According to exemplary embodiments, the substrate 100 may include a cell region I and an extension region II. In Fig. 1, only one extension region II is shown at one side of the cell region I, but two extension regions II can be defined on both sides of the cell region I.

The channel 135 may be disposed on the cell region I of the substrate 100 and may contact the upper surface of the substrate 100. The channel 135 may have an internal hollow or cup shape. The plurality of channels 135 may be formed along the third direction to form channel rows, and the plurality of channel columns may be disposed along the second direction. The channel 135 may comprise polysilicon or single crystal silicon.

Although only two channels 135 are shown in FIG. 1, the channel sequence may include two or more channels 135, and the number of channels 135 included in one channel sequence may be particularly limited But is not limited thereto.

As shown in FIG. 1, a first buried film pattern 140 having a pillar shape or a hollow cylindrical shape may be provided in the inner space of the channel 135. The first buried film pattern 140 may include an insulating material such as silicon oxide.

In one embodiment, the channel 135 may have a pillar or buccal columnar shape. In this case, the first buried film pattern 140 may be omitted.

The dielectric layer structure 130 may be formed on the outer wall of the channel 135 and may have a cup shape with the bottom center portion open.

The dielectric layer structure 130 may have a structure in which a plurality of layers are stacked from the outer wall of the channel 135 along the third direction. According to exemplary embodiments, the dielectric film structure 130 includes a tunnel insulating film pattern (not shown), a charge storage film pattern (not shown) and a blocking film pattern (not shown) sequentially stacked from the outer wall of the channel 135 (Not shown).

The blocking film pattern may include an oxide such as silicon oxide and the charge storage film pattern may include nitride or metal oxide such as silicon nitride and the tunnel insulating film pattern may include an oxide such as silicon oxide have. According to exemplary embodiments, the dielectric layer structure 130 may have an ONO (Oxide-Nitride-Oxide) structure in which an oxide-nitride-oxide-oxide layer is sequentially stacked.

The pad 150 may be formed on the first buried film pattern 140, the channel 135 and the dielectric layer structure 130 and electrically connected to the bit line 195 through the bit line contact 190. The pad 150 may serve as a source / drain to cause charge to move into the channel 135. The pad 150 may include polysilicon or monocrystalline silicon and may further include n-type impurities such as phosphorus (P), arsenic (As), and the like.

Gate lines 170 are formed on the outer wall of dielectric layer structure 130 and are spaced apart from one another along the first direction. According to exemplary embodiments, each gate line 170 may extend in the third direction, partially surrounding the channels 135 included in the channel column. For example, the gate line 170 may extend around one of the channel rows.

In one embodiment, the gate line 170 may extend around a plurality of the channel rows. Accordingly, the plurality of channel columns can be unitized into a channel column group by the gate line 170. [ Hereinafter, a case where one channel line is included in one gate line 170 will be described as an example.

As shown in FIG. 1, the gate lines 170 may be stacked in a shape of decreasing in length or width along the first direction from the upper surface of the substrate 100. According to exemplary embodiments, the plurality of gate lines 170 may be stacked in a pyramidal or stepped shape along the first direction. According to exemplary embodiments, the plurality of gate lines 170 may have a stepped shape that is symmetrical with respect to the cell region I. In one embodiment, the plurality of gate lines 170 may have an asymmetric step shape with respect to the cell region I.

Further, a plurality of gate lines 170 may be arranged along the second direction in one layer or one level.

1, gate lines 170 are shown stacked in a total of seven layers. However, the number of the gate lines 170 included in the number of layers is not particularly limited.

The gate line 170 may comprise a metal or a metal nitride. For example, the gate line 170 may comprise a low resistance metal or metal nitride such as tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, platinum, and the like. According to one embodiment, the gate line 170 may have a multilayer structure in which a barrier film including a metal nitride and a metal film including a metal are stacked.

The gate line 170a formed at the lowermost portion may be provided as a ground selection line GSL and the four gate lines 170b, 170c, 170d, and 170e stacked on the GSL may be connected to a word line Word Line). Also, the two gate lines 170f and 170g disposed on the word line may be provided in a string selection line (SSL).

For convenience of description, the gate lines 170 of the upper two layers are referred to as a first SSL 170g and a second SSL 170f, respectively. The four gate lines 170 between the SSLs 170f and 170g and the GSL 170a are connected to the first word line 170e, the second word line 170d, the third word line 170c, 4 < / RTI > word line 170b.

As described above, the GSL, the word line, and the SSL may have one layer, four layers, and two layers, respectively, but are not limited thereto. For example, the GSL may have a two-layer structure, and the SSL may have a one-layer structure. In addition, the word line may have a two-layer structure. In one embodiment, the word line may have multiple layer structures than four layers. For example, the word line may have eight or sixteen layer structures. The number of stacked gate lines 170 may be determined in consideration of the circuit design design and / or the capacitance or integration of the vertical memory device.

A portion of the substrate 100 overlapping with the first SSL 170g may be defined as a cell region I and a portion of the substrate 100 on both sides of the cell region I may be defined as an extended region II . According to exemplary embodiments, the portions of the gate lines 170 protruding into the extension region II may have a shape symmetrical with respect to the cell region I.

As shown in FIG. 1, interlayer insulating layer patterns 106 may be provided between adjacent gate lines 170 along the first direction. The interlayer insulating film patterns 106 may include silicon oxide such as silicon oxide (SiO ₂ ), silicon carbonate (SiOC), or silicon oxyfluoride (SiOF). The gate lines 170 included in one string can be insulated from each other by the interlayer insulating film patterns 106. [

In the exemplary embodiments, the uppermost interlayer insulating film pattern 106h may include a first impurity region 108 having a first impurity concentration. For example, the first impurity region 108 may include an n-type impurity such as phosphorus (P), arsenic (As), or the like.

In the exemplary embodiments, the first impurity region 108 may be disposed on the cell region I.

In exemplary embodiments, the pad 150 may have a second impurity concentration and the second impurity concentration may be higher than the first impurity concentration. For example, the pad 150 may include n-type impurities such as phosphorus (P), arsenic (As), and the like.

In one embodiment, the channel portion adjacent to the SSLs 170f, 170g may include a second impurity region 110. [ For example, the second impurity region 110 may include p-type impurities such as boron (B) and gallium (Ga). The second impurity region 110 may be formed to improve the threshold voltage dispersion of the SSLs 170f and 170g.

A third impurity region (not shown) may be formed on the substrate 100 between adjacent channel columns or adjacent strings along the second direction. The third impurity region extends in the third direction and may be provided as a common source line (CSL) of the vertical memory device. The impurity region may include an n-type impurity such as phosphorus, arsenic and the like. Although not shown, a metal silicide pattern such as a cobalt silicide pattern or a nickel silicide pattern may be further formed on the impurity region.

A second embedded film pattern (not shown) for embedding a space between adjacent strings may be provided on the impurity region. The second buried film pattern may include an insulating material such as silicon oxide. The adjacent strings can be insulated from each other by the second buried film pattern.

The upper interlayer insulating film pattern 106h, the pad 150, and the upper insulating film 185 may be formed on the second embedded film pattern. The bit line contact 190 may be provided to contact the pad 150 through the upper insulating layer 185 and the wiring line contacts 192 may be provided in contact with the gate lines 170. The bit line 195 in contact with the bit line contact 190 and the wiring lines 197 in contact with the wiring line contacts 192 may be provided on the upper insulating layer 195.

The mold protection film pattern 119 is formed on the substrate 100 by covering the upper surfaces and sidewalls of the gate lines 170 and the interlayer insulating film patterns 106 and the sidewalls of the pads 150 and the channels 135 . The mold protection film pattern 119 may include an insulating material such as silicon oxide.

According to exemplary embodiments, the bit line contacts 190 may form an array corresponding to the locations where the channels 135 or pads 150 are formed. The bit lines 195 may extend in the third direction and may be formed along the second direction.

According to exemplary embodiments, the wiring line contacts 192 may electrically connect the gate lines 150 to the wiring lines 197, respectively. In addition, the wiring lines 197 may extend in the second direction, and may be formed along the third direction.

The bit line contact 190, the wiring line contacts 192, the bit line 195 and the wiring lines 197 may be formed of a metal, a metal nitride , Doped polysilicon, and the like.

According to the exemplary embodiments of the present invention, the uppermost interlayer insulating film pattern 106h includes the first impurity region 108 having the first impurity concentration, so that the uppermost gate line 170g and the pad 150 Since the structure differs from the structure between the gate lines 170, it is possible to prevent a difference in electrical characteristics from occurring and to prevent an increase in the resistance of the channel and a scattering failure of the gate line threshold voltage value.

Particularly, impurities are contained in a desired region of the interlayer insulating film pattern 106h of the uppermost layer, so that bridge failure between the channel 150 and the wiring line contact 192 can be prevented. Furthermore, since the existing process of forming a contact spacer for preventing a bridge failure can be omitted, the process can be simplified to contribute to productivity.

FIGS. 2 to 11 are cross-sectional views and plan views illustrating a method of manufacturing a vertical type memory device according to exemplary embodiments.

2 to 5 and Figs. 7 to 11 are sectional views for explaining a method of manufacturing a vertical type memory device according to exemplary embodiments, and Fig. 6 is a cross-sectional view illustrating a vertical type memory device according to exemplary embodiments. And FIG.

Referring to FIG. 2, a plurality of interlayer insulating films 102 and sacrificial films 104 are alternately and repeatedly laminated on a substrate 100.

As the substrate 100, a semiconductor substrate including a semiconductor material such as monocrystalline silicon, germanium, or the like can be used.

According to exemplary embodiments, the interlayer insulating films 102 may be formed using silicon oxide such as silicon oxide, silicon carbonitride, or silicon oxide burr. The sacrificial films 104 may have an etch selectivity to the interlayer insulating film 102 and may be formed of a material that can be easily removed by a wet etching process. For example, the sacrificial films 104 may be formed using silicon nitride such as silicon nitride (SiNx), silicon boron nitride (SiBN), or the like.

The interlayer insulating films 102 and the sacrificial films 104 may be formed by a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, a spin coating process, Or an atomic layer deposition (ALD) process. In the case of the lowermost interlayer insulating film 102a directly formed on the upper surface of the substrate 100, it may be formed by a thermal oxidation process.

The sacrificial films 104 are removed through a subsequent process to provide space in which gate lines, e.g., GSL, word lines, and SSL are formed. Therefore, the number of the interlayer insulating films 102 and the sacrificial films 104 stacked may be varied depending on the number of the GSL, the word line, and the SSL formed later. According to exemplary embodiments, the GSL is formed in one layer, the word line is formed in four layers on top of the GSL, and the SSL can be formed in two layers on top of the word line have. Accordingly, the sacrificial films 104 are all stacked in seven layers, and the interlayer insulating films 102 can be stacked in all eight layers. However, for example, the GSL and SSL may be formed in one layer and the word lines may be formed in two, eight, or sixteen layers, wherein the sacrificial layers 104 are all four, Or 18 layers, and the interlayer insulating films 102 may be formed in five, 11, or 19 layers.

Referring to FIG. 3, the interlayer insulating films 102 and the sacrificial films 104 are partially etched to form a mold structure 105 having a stepped shape.

According to the exemplary embodiments, a photoresist pattern (not shown) that partially covers the interlayer insulating film 102h is formed on the uppermost interlayer insulating film 102h, and the interlayer insulating film 102h is formed using the photoresist pattern as an etching mask Both ends of the insulating films 102 and the sacrificial films 104 are etched. Thereafter, the both ends of the photoresist pattern are partially removed to reduce the width of the photoresist pattern. Thereafter, the photoresist pattern is used as an etch mask to form interlayer insulating films 102h, 102g, 102f, 102e, 102d, 102c, Both ends of the first and second electrodes 104g, 104f, 104e, 104d, 104c and 104b are etched. In a similar manner, by repeating the etching process, a stepped mold structure 105 as shown in Fig. 3 can be obtained.

According to exemplary embodiments, the region of the substrate 100 overlapping with the uppermost interlayer insulating film 102h can be defined as the cell region I, and the region of the substrate 100 on both sides of the cell region I Can be defined as an extended area (II). For example, the mold structure 105 may be formed such that the two extension regions II are symmetrical with respect to each other with the cell region I interposed therebetween.

In one embodiment, the mold structure may be formed such that two extension regions II are asymmetrical with respect to each other with the cell region I interposed therebetween. In this case, an asymmetric structure of the mold structure can be obtained by alternately etching the interlayer insulating films 102 and the sacrificial films 104 on the two extension regions (II).

Referring to FIG. 4, after the mold structure 105 is formed, a mold protecting film 117 may be formed on the substrate 100 to cover the sides or steps of the mold structure. For example, an insulating film covering the mold structure 105 is formed through a CVD process using an insulating material such as silicon oxide on the substrate 100. Then, the upper part of the insulating film may be planarized until the interlayer insulating film 102h of the uppermost layer is exposed to form the mold protecting film 117. The planarization process may include a chemical mechanical polishing (CMP) process and / or an etch-back process.

5, channel holes (not shown) are formed to expose an upper surface of the substrate 100, channels (not shown) penetrating the interlayer insulating films 102 and the sacrificial films 104 135 are formed.

According to the exemplary embodiments, a hard mask (not shown) is formed on the uppermost interlayer insulating film 102 and the mold protecting film 117, and a dry etching process using the hard mask as an etch mask, The sacrificial layers 102 and the sacrificial layers 104 may be sequentially etched to form the channel holes exposing the upper surface of the substrate 100. [ The channel hole may be formed to extend from the upper surface of the substrate 100 in the first direction.

The channel holes may be formed in a plurality of along the second direction and the third direction corresponding to a position where the channel 135 is to be formed in the cell region I of the substrate 100.

A dielectric layer (not shown) is formed along the sidewalls and bottom of the channel holes and the upper surface of the hard mask. The dielectric layer may be formed by sequentially laminating a first blocking layer, a charge storage layer, and a tunnel insulating layer on a sidewall and a bottom of the channel hole and an upper surface of the hard mask, though not shown in detail.

The blocking film may be formed using an oxide such as silicon oxide, and the charge storage film may be formed using a nitride such as silicon nitride or a metal oxide, and the tunnel insulating film may be formed using an oxide such as silicon oxide . According to exemplary embodiments, the dielectric layer may be formed to have an ONO structure. The first blocking layer, the charge storage layer, and the tunnel insulating layer may be formed by, for example, a CVD process, a PECVD process, a spin coating process, or an ALD process, respectively.

The bottom surface of the dielectric layer is partially removed through, for example, an anisotropic etching process to expose the upper surface of the substrate 100. Accordingly, the dielectric layer may have a shape in which a central portion of the bottom surface is opened in the channel hole.

A channel film (not shown) may be formed on the exposed upper surface of the dielectric layer and the substrate 100, and a first buried layer (not shown) may be formed on the channel layer to fill the remaining portion of the channel hole have. The channel film and the first buried film may be formed, for example, by a CVD process, a PECVD process, a spin coating process, or an ALD process.

According to one embodiment, the channel film may be formed to completely fill the channel hole. In this case, the formation of the first embedded film may be omitted.

Then, the first buried film, the channel film, the dielectric film, and the hard mask are planarized until the uppermost interlayer insulating film 102h and the mold protecting film 117 are exposed, and the first buried film, the dielectric film and the hard mask are sequentially planarized on the side walls and the bottom surface of the channel hole A channel 135 and a first buried film pattern 140 may be formed on the dielectric film structure 130, which are stacked to fill the channel hole. The planarization process may include a CMP process or an etch-back process.

According to exemplary embodiments, the dielectric film structure 130 may have a cylindrical or cup shape with an open bottom central portion. In addition, the channel 135 may have a cup shape, and the first buried film pattern 140 may have a hollow round column or pillar shape. The dielectric film structure 130 may have a structure in which the tunnel insulating film, the charge storage film, and the first blocking film are stacked from the outer wall of the channel 135.

In the exemplary embodiments, when the channel film is formed to completely fill the channel hole, the first buried film pattern 140 is not formed, and the channel 135 may have a hollow circular column or pillar shape have.

Then, the second impurity region 110 can be formed by implanting p-type impurity into the upper portion of the dielectric film structure 130, the channel 135, and the first buried film pattern 140 by using an ion implantation process. For example, the p-type impurity may include boron (B), gallium (Ga), or the like. In particular, the second impurity region 110 can be formed by controlling the projection distance so that the p-type impurity is diffused only to a portion adjacent to the SSL.

As the channel 135 is formed in the channel hole, a channel column including a plurality of channels 135 may be formed along the third direction, and a plurality of channel columns may be formed along the second direction .

In addition, the top of the dielectric film structure 130, the channel 135 and the first buried film pattern 140 may be removed to form a recess 150 (not shown) and a pad 150 filling the recess .

In the exemplary embodiments, the top of the dielectric layer structure 130, the channel 135, and the first buried film pattern 140 is removed through an etch-back process to form the recess. A pad film filling the recess is formed on the first buried film pattern 140, the channel 135, the dielectric film structure 130, the uppermost interlayer insulating film 102h and the mold protecting film 117, The pad 150 may be formed by planarizing the upper surface of the pad film until the upper surfaces of the insulating film 102h and the mold protecting film 117 are exposed.

According to exemplary embodiments, the pad film may be formed using polysilicon or impurity-doped polysilicon. Alternatively, the pad film may be formed by forming a preliminary pad film using amorphous silicon and then crystallizing the preliminary pad film. The planarization process may include a CMP process. The impurities may include n-type impurities such as phosphorus (P), arsenic (As) and the like.

6, openings 155 are formed through the interlayer insulating films 102, the sacrificial films 104, and the mold protecting film 117 to expose the upper surface of the substrate 100 between adjacent channel columns. do.

According to exemplary embodiments, a mask pattern (not shown) that covers the pads 150 is formed on the mold structure 105 and the mold protection film 117, and a dry etching process using the mask pattern as an etching mask The openings 155 may be formed by sequentially etching the interlayer insulating layers 102 and the sacrificial layers 104 between the adjacent channel columns in the second direction through the etching process.

As the openings 155 are formed, the interlayer insulating films 102, the sacrificial films 104, and the mold protecting film 117 are patterned by the interlayer insulating film patterns 106, the sacrificial film patterns 108, 119 < / RTI > At this time, the interlayer insulating film patterns 106, the sacrificial film patterns 108, and the mold protecting film pattern 119 of each layer may extend along the third direction.

The openings 155 may be formed to have a line shape extending along the third direction.

Referring to FIG. 7, the sacrificial film patterns 108 in which the side walls are exposed by the openings 155 are removed. For example, the sacrificial film patterns 108 may be removed through a wet etch process using an etch solution comprising an acidic solution such as phosphoric acid or sulfuric acid.

The first gap 160 is formed between adjacent interlayer dielectric layer patterns 106 along the first direction and the dielectric layer structure 130 is formed by the first gap 160. [ A part of the outer side wall of the housing can be exposed.

Referring to FIG. 8, the gate lines 170 may be sequentially formed in the first gap 160 in the first direction along the first direction.

For example, a gate electrode film (not shown) is formed along the outer wall of the exposed dielectric film structure 130, the inner wall of the first gap 160, the surface of the interlayer insulating film patterns 106, Can be formed. According to one embodiment, a second blocking film (not shown) may be additionally formed before forming the gate electrode film.

The gate electrode film completely fills the first gap 160 and may be formed to partially fill the openings 155. [

The gate electrode film may be formed using a metal or a metal nitride. For example, the gate electrode film may be formed using a metal or metal nitride having low electric resistance such as tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, and platinum. According to one embodiment, the gate electrode film may be formed of a multilayer film in which a barrier film including a metal nitride and a metal film including a metal are stacked.

The gate electrode film may be formed, for example, by a CVD process, a PECVD process, an ALD process, or a sputtering process.

Subsequently, the gate electrode film may be partially removed to form the gate lines 170 inside the first gap 160 of each layer.

According to exemplary embodiments, the gate lines 170 may be formed by partially etching the gate electrode film formed inside the openings 155. At this time, the upper surface of the substrate 100 may be exposed together. The gate electrode film may be partially removed through a dry etching process.

The gate lines 170 may include a GSL, a word line, and a SSL formed sequentially from the upper surface of the substrate 100 along the first direction. According to exemplary embodiments, the lowermost gate line 170a may be provided as a GSL. The four gate lines 170b, 170c, 170d, and 170e on the GSL may be provided as word lines. The two gate lines 170f and 170g above the word line may be provided by SSL.

A third impurity region (not shown) may be formed on the substrate 100 exposed by the openings 155 and a second buried film pattern (not shown) may be formed to embed the openings 155 have.

The third impurity region may be formed by implanting an n-type impurity such as phosphorous, for example, phosphorus through the openings 155. In one embodiment, a metal silicide pattern (not shown) such as a nickel silicide pattern or a cobalt silicide pattern may be further formed on the impurity region. According to exemplary embodiments, the impurity region may extend in the third direction and be provided in a common source line (CSL) of the vertical memory device.

Thereafter, a second buried film filling the openings 155 on the substrate 100, the interlayer insulating film pattern 106 and the pad 150 is formed, and the upper part of the second buried film is covered with the uppermost interlayer insulating film pattern 106h and The second buried film pattern may be formed by planarization through an etch-back process and / or a CMP process until the mold protecting film is exposed. The second buried film may be formed, for example, by a CVD process using an insulating material such as silicon oxide.

Referring to FIG. 9, a blocking film 121 may be formed on the mold protecting film pattern 119.

In the exemplary embodiments, the stopper film 121 may be formed on the mold protecting film pattern 119 which overlaps the extended region. Also, the blocking film 121 may be formed on a part of the cell region.

In the exemplary embodiments, the stop film 121 may be a photoresist film or a hard mask film.

Referring to FIG. 10, the first impurity region 108 can be formed by implanting phosphorous, such as arsenic, into the uppermost interlayer insulating film pattern 106h. Further, the first impurity region 108 may have a first impurity concentration.

In the exemplary embodiments, the first impurity region 108 may be formed on the cell region I.

Thereafter, the stopper film 121 formed on the uppermost interlayer insulating film pattern 106g which overlaps with the extended region can be removed by an ashing and / or a strip process.

Since the pad 150 is already formed using the polysilicon doped with the impurity, the pad 150 is electrically connected to the second impurity concentration lower than the first impurity concentration through the ion implantation process for forming the first impurity region 108 Concentration.

Referring to FIG. 11, an upper insulating layer 185 may be formed to cover the interlayer insulating layer patterns 106, the second embedded layer patterns, the pads 150, and the mold protecting layer pattern 119. The upper insulating film 185 may be formed by CVD or the like using an insulating material such as silicon oxide.

Thereafter, the bit line contacts 190 that are in contact with the pad 150 through the upper insulating layer 185 and the wiring line contacts 192 that are in contact with the gate lines 170 can be formed. The bit line contact 190 and the wiring line contacts 192 may be formed through a CVD process, an ALD process, a sputtering process, or the like using, for example, metal, metal nitride, or doped polysilicon. The bit line contacts 190 may form an array corresponding to the arrangement of the channels 135 or the pads 150.

A bit line 195 and wiring lines 197 electrically connected to the bit line contact 190 and the wiring line contacts 192 are then formed on the upper insulating film 185. The bit line 195 and the wiring lines 197 are formed by forming a conductive film through a CVD process, an ALD process, or a sputtering process using, for example, a metal, a metal nitride, or a doped polysilicon, .

100: substrate 106: interlayer insulating film pattern
108: first impurity region 110: second impurity region
119: mold protective film pattern 130: dielectric film structure 135: channel
140: First Embedded Film Pattern 150: Pad
155: opening 170: gate line
190: bit line contact 192: wiring line contact
195: bit line 197: wiring line

Claims (10)

A substrate including a cell region and an extension region disposed on a side of the cell region;
Channels extending in a first direction perpendicular to the top surface of the substrate;
Gate lines disposed on an outer wall of the channel and sequentially stacked from the upper surface of the substrate so as to be spaced apart from each other along the first direction;
A plurality of interlayer insulating film patterns formed between the gate lines along the first direction; And
And a first impurity region formed on an uppermost interlayer insulating film pattern of the plurality of interlayer insulating film patterns. 2. The semiconductor device according to claim 1, further comprising pads respectively formed on the channels, wherein the first impurity region and the pads each have a first impurity concentration and a second impurity concentration, Concentration in the vertical direction. 3. The vertical memory device according to claim 2, wherein the first impurity region and the pad include an n-type impurity. The method of claim 1, wherein the gate lines include a ground selection line (GSL), a word line, and a string selection line (SSL) that are sequentially stacked from the top surface of the substrate,
And a second impurity region is formed in a channel portion adjacent to the string selection line (SSL). 5. The vertical memory device according to claim 4, wherein the second impurity region includes a p-type impurity. 2. The liquid crystal display according to claim 1, wherein the gate lines are arranged in a stepwise manner from the upper surface of the substrate,
Wherein the cell region is defined as a portion overlapping the uppermost interlayer insulating film pattern of the substrate. Alternately and repeatedly depositing interlayer insulating films and sacrificial films on a substrate;
Etching the side portions of the interlayer insulating films and the sacrificial films to form a stepped mold structure;
Forming a mold protecting film covering a side of the mold structure on the substrate;
Forming channels through the mold structure to contact the substrate;
Partially etching the interlayer insulating films and the sacrificial films between the channels to form openings;
Removing the sacrificial layers exposed by the opening;
Forming gate lines in a space from which the sacrificial films are removed;
Forming a stopper film for exposing an uppermost interlayer insulating film among the interlayer insulating films on the mold protecting film; And
Forming a first impurity region by implanting impurities on the uppermost interlayer insulating film using the blocking film as an ion implantation mask. 8. The method of manufacturing a vertical type memory device according to claim 7, wherein the blocking film covers a part of the uppermost interlayer insulating film. 8. The method of claim 7, further comprising forming a buried film pattern to fill the opening,
Wherein the stopping film is formed on the mold protecting film and the buried film pattern. 8. The method of claim 7,
Further comprising forming pads on each of the channels,
Wherein the first impurity region and the pad each have a first impurity concentration and a second impurity concentration and the second impurity concentration is higher than the first impurity concentration.

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