KR20150083883A - System and method for controlling central processing unit power with guaranteed transient deadlines - Google Patents

Abstract

Ensuring that the processor does not stay in busy state beyond the amount of predetermined time (e.g., due to transient workloads) than is required for the processor to complete the pre-computed steady state workload Systems, and devices that include a dynamic clock and voltage scaling (DCVS) solution configured to compute and enforce performance guarantees. The DCVS is programmed to determine whether the processing core is to be programmed based on the variable delay based on the variable delay to ensure that the processing core is only behind the steady state work load by a predefined maximum amount of work, Frequency and / or voltage.

Description

[0001] SYSTEM AND METHOD FOR CONTROLLING CENTRAL PROCESSING UNIT POWER WITH GUARANTEED TRANSIENT DEADLINES [0002]

Related Applications

This application is a continuation-in-part of U.S. Provisional Patent Application Serial No. 61 / 542,701 entitled " System and Method of Dynamically Controlling Power in a Central Processing Unit ", filed on December 16, Entitled " System and Method for Controlling Central Processing Unit Power with Guaranteed Transient Deadlines, " filed November 11, 2010, which claims priority to U.S. Provisional Patent Application Ser. System and method), which is incorporated herein by reference in its entirety for all purposes.

Cross-reference applications

This application is a continuation-in-part of U.S. Patent Application entitled " System And Method For Controlling Central Processing Unit Power Based On Inferred Workload Parallelism " by Rychlik et al. 12 / 944,140; U.S. Patent Application No. 12 / 944,202 entitled " System and Method for Controlling Central Processing Unit Power in a Virtualized System ", by Rychlik et al., Entitled " System and Method for Controlling Central Processing Unit Power in a Virtualized System; Rychlik et al., Entitled " System and Method for Asynchronously and Independently Controlling Core Clocks in a Multicore Central Processing Unit " 12 / 944,321; U.S. Patent Application No. 12 / 944,378 entitled " System and Method for Controlling Central Processing Unit Power with Reduced Frequency Oscillations " by Thomson et al .; U.S. Patent Application No. 12 / 944,561 entitled " System and Method for Controlling Central Processing Unit Power With Guaranteed Steady State Deadlines " by Thomson et al., Entitled " System and Method for Controlling Central Processing Unit Power with Guaranteed Steady- number; And Sur et al., &Quot; System and Method for Dynamically Controlling Multiple Cores in a Multicore Central Processing Unit Based on Temperature ", by "System and Method for Dynamically Controlling a Plurality of Cores in a Multicore Central Processing Unit " US patent application < RTI ID = 0.0 > 12 / 944,564, < / RTI >

Portable computing devices (PCDs) are ubiquitous. These devices may include cellular phones, portable digital assistants (PDAs), portable game consoles, palmtop computers, and other portable electronic devices. In addition to the main functions of these devices, many include peripheral functions. For example, a cellular telephone may have a main function of making cellular telephone calls, a still camera, a video camera, a global positioning system (GPS) navigation, web browsing, Transmission and reception of data, and push-to-talk capabilities. As the functionality of these devices increases, the computing or processing power required to support this functionality also increases. Also, as computing power increases, there is a greater need to effectively manage processors or processors that provide computing power.

Thus, what is needed is an improved method of controlling power within a multicore CPU.

BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary aspects of the invention and, together with the general description given above and the detailed description given below, serve to explain the features of the invention.
1 is a front plan view of a first embodiment of a portable computing device (PCD) in a closed position.
2 is a front plan view of a first embodiment of the PCD in an open position;
3 is a block diagram of a second aspect of the PCD;
4 is a block diagram of a processing system.
5 is a flow chart illustrating a first aspect of a method for dynamically controlling power in a CPU.
6 is a flow chart illustrating a first portion of a second aspect of a method for dynamically controlling power in a CPU.
7 is a flow chart illustrating a second portion of a second aspect of a method for dynamically controlling power in a multicore CPU.
Figure 8 is an exemplary graph illustrating dynamic clock and voltage scaling (DCVS) controlled CPU frequency over time.
9 is an exemplary graph illustrating effective transient response times for various performance levels.
10 is a block diagram illustrating logical components and information flows in a computing device implementing a dynamic clock frequency / voltage scaling (DCVS) solution to enforce performance guarantees in accordance with various aspects.
11A-11B are process flow diagrams illustrating a method of one aspect of generating performance guarantees.
Figures 12-13 illustrate how a processing core may be in a busy state beyond an amount of more than a predetermined amount of time than is required to complete its pre-computed, predicted, and / These are process flow diagrams illustrating various aspects of methods for enforcing performance guarantees to ensure that they do not stay.
Figure 14 is a process flow diagram illustrating another method of enforcing performance assurance.
15 is a component block diagram of a mobile device suitable for use in an aspect.
16 is a component block diagram of a server device suitable for use in an aspect.
17 is a component block diagram of a laptop computer device suitable for use in one aspect.

Various embodiments will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. References made to specific examples and implementations are for illustrative purposes only and are not intended to limit the scope of the invention or the claims.

The word "exemplary" is used herein to mean "serving as an example, instance, or illustration. &Quot; Any aspect described herein as "exemplary " is not necessarily to be construed as preferred or advantageous over other aspects.

In this description, the term "application" is also intended to encompass executable code such as object code, scripts, byte code, markup language files, It may contain files with possible content. Additionally, an "application" referred to herein may also include files that are substantially non-executable, such as documents that may need to be opened or other data files that need to be accessed.

The term "content" may also include files having executable content such as object code, scripts, byte code, markup language files, and patches. Additionally, the "content" referred to herein may also include files that are not naturally executable, such as documents that may need to be opened or other data files that need to be accessed.

As used in this description, the terms "component," "database," "module," "system," and the like are intended to refer to a computer-related entity, any combination of hardware, firmware, Is intended to refer to software. For example, a component may be, but is not limited to, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and / or a computer. By way of example, both an application running on a computing device and a computing device may be a component. One or more components may reside within a process and / or thread of execution, and the components may be localized on one computer and / or distributed among two or more computers. Additionally, these components may be executed from various computer readable media having various data structures stored thereon. The components may include, for example, one or more data packets (e.g., from a local system, a distributed system, and / or from one component interacting with another component across a network, such as the Internet, Lt; / RTI > and / or remote processes depending on the signal having the data of the mobile station < RTI ID = 0.0 >

Referring first to Figures 1 and 2, an exemplary handheld computing device (PCD) is shown and generally designated 100. As shown, the PCD 100 may include a housing 102. The housing 102 may include an upper housing portion 104 and a lower housing portion 106. FIG. 1 illustrates that the upper housing portion 104 may include a display 108. In particular aspects, the display 108 may be a touch screen display. The upper housing portion 104 may also include a trackball input device 110. 1, the upper housing portion 104 may also include a power on button 112 and a power off button 114. In addition, The upper housing portion 104 of the PCD 100 may include a plurality of indicator light 116 and a speaker 118, as shown in FIG. Each indicator light 116 may be a light emitting diode (LED).

In a particular aspect, the upper housing portion 104 is movable relative to the lower housing portion 106, as shown in FIG. Specifically, the upper housing portion 104 may be slidable relative to the lower housing portion 106. As shown in FIG. 2, lower housing portion 106 may include a multi-button keyboard 120. In a particular aspect, the multi-button keyboard 120 may be a standard QWERTY keyboard. The multi-button keyboard 120 may be exposed when the upper housing portion 104 is moved relative to the lower housing portion 106. Figure 2 further illustrates that the PCD 100 may include a reset button 122 on the lower housing portion 106. [

Referring to FIG. 3, exemplary non-limiting aspects of a portable computing device (PCD) are shown and generally designated 320. As shown, the PCD 320 includes an on-chip system 322 that includes a multicore CPU 324. The on- The multi-core CPU 324 may include a zeroth core 325, a first core 326, and an Nth core 327. [

As illustrated in FIG. 3, the display controller 328 and the touch screen controller 330 are coupled to the multicore CPU 324. As a result, the display / touch screen 332, which is external to the on-chip system 322, is coupled to the display controller 328 and the touch screen controller 330.

3 is a block diagram of a video encoder 334, such as a phase alternating line (PAL) encoder, a sequential couleur a memoire (SECAM) encoder, or a national television system (s) committee Lt; / RTI > In addition, video amplifier 336 is coupled to video encoder 334 and display / touch screen 332. The video port 338 is also coupled to a video amplifier 336. As shown in FIG. 3, a universal serial bus (USB) controller 340 is coupled to the multicore CPU 324. The USB port 342 is also coupled to the USB controller 340. The memory 344 and the subscriber identity module (SIM) card 346 may also be coupled to the multicore CPU 324. [ 3, the digital camera 348 may also be coupled to the multicore CPU 324. [ In an exemplary embodiment, the digital camera 348 is a charge-coupled device (CCD) camera or a complementary metal-oxide semiconductor (CMOS) camera.

As further illustrated in FIG. 3, a stereo audio codec (CODEC) 350 may be coupled to the multicore CPU 324. FIG. In addition, the audio amplifier 352 may be coupled to the stereo audio codec 350. In an exemplary embodiment, the first stereo speaker 354 and the second stereo speaker 356 are coupled to the audio amplifier 352. 3 illustrates that a microphone amplifier 358 may also be coupled to the stereo audio codec 350. [ Additionally, the microphone 360 may be coupled to a microphone amplifier 358. In a particular aspect, a frequency modulation (FM) radio tuner 362 may be coupled to the stereo audio codec 350. The FM antenna 364 is also coupled to an FM radio tuner 362. The stereo headphones 366 may also be coupled to the stereo audio codec 350.

3 further illustrates that a radio frequency (RF) transceiver 368 may be coupled to the multicore CPU 324. [ The RF switch 370 may be coupled to the RF transceiver 368 and the RF antenna 372. 3, the keypad 374 may be coupled to the multicore CPU 324. The multi- In addition, a mono headset 376 with a microphone may be coupled to the multicore CPU 324. [ In addition, a vibrator device (378) may be coupled to the multicore CPU (324). Figure 3 also shows that the power supply 380 may be coupled to the on-chip system 322. [ In a particular aspect, power supply 380 is a direct current (DC) power supply that provides power to the various components of PCD 320 that require power. Further, in a particular aspect, the power supply is a rechargeable DC battery or a DC power supply derived from an alternating current (AC) to DC transformer connected to an AC power source.

3 illustrates that PCD 320 may also include a network card 388 that may be used to access a data network, e.g., a local area network, a personal area network, or any other network. . The network card 388 may be a Bluetooth network card, a WiFi network card, a personal area network (PAN) card, a personal area network ultra-low-power technology (PEANUT) network card, Or any other well-known network card. In addition, the network card 388 may be incorporated into the chip, i.e., the network card 388 may be a complete solution on the chip, or may not be a separate network card 388.

As shown in FIG. 3, a display / touch screen 332, a video port 338, a USB port 342, a camera 348, a first stereo speaker 354, a second stereo speaker 356, The RF antenna 372, the keypad 374, the mono headset 376, the vibrator 378, and the power supply (not shown) 380 are external to the on-chip system 322.

In particular aspects, one or more of the method steps described herein may be stored in memory 344 as computer program instructions. These instructions may be executed by the multicore CPU 324 to perform the methods described herein. Further, the multi-core CPU 324, the memory 344, or a combination thereof may execute one or more of the method steps described herein to dynamically control the power of each CPU or core in the multi-core CPU 324 It may also serve as a means for accomplishing this.

Referring to FIG. 4, a processing system is shown and generally designated 400. In particular aspects, the processing system 400 may be incorporated into the PCD 320 described above in conjunction with FIG. As shown, the processing system 400 may include a multi-core central processing unit (CPU) 402 and a memory 404 connected to the multi-core CPU 402. The multi-core CPU 402 may include a zeroth core 410, a first core 412, and an Nth core 414. The zero-th core 410 may include a zero-th dynamic clock and voltage scaling (DCVS) algorithm 416 running on it. The first core 412 may include a first DCVS algorithm 417 running on it. The Nth core 414 may also include an Nth DCVS algorithm 418 running on it. In a particular aspect, each DCVS algorithm 416, 417, 418 may be executed independently on each core 410, 412, 414.

In addition, as illustrated, the memory 404 may include an operating system 420 stored thereon. The operating system 420 may include a scheduler 422 and the scheduler 422 may include a first execution queue 424, a second execution queue 426, and an Nth execution queue 428 ). The memory 404 may also include a first application 430, a second application 432, and an Nth application 434 stored thereon.

In one particular aspect, applications 430, 432, and 434 may include one or more tasks 436 in order to be processed at cores 410, 412, and 414 in multi-core CPU 402, ). Tasks 436 may be processed or executed as single tasks, threads, or a combination thereof. Scheduler 422 may also schedule tasks, threads, or a combination thereof for execution within multi-core CPU 402. [ Additionally, the scheduler 422 may place tasks, threads, or a combination thereof in the execution queues 424, 426, 428. [ The cores 410, 412 and 414 may be coupled to execution queues 410 and 412 as commanded by the operating system 420 for processing or execution of their tasks and threads at, for example, 424, 426, 428. In some embodiments,

FIG. 4 also illustrates that the memory 404 may include a parallelism monitor 440 stored thereon. The parallel monitor 440 may be connected to the operating system 420 and the multi-core CPU 402. In particular, the parallel monitor 440 may be connected to the scheduler 422 in the operating system 420.

Referring to FIG. 5, a first embodiment of a method for dynamically controlling the power of a central processing unit is shown and generally designated as 500. The method 500 may be initiated at block 502 with an execution loop in which the following steps may be performed when the device is powered on.

At block 504, a power controller, e.g., a dynamic clock and voltage scaling (DCVS) algorithm, may monitor one or more CPUs. At decision 506, the power controller may determine whether the transient performance deadline for the CPU has expired. Otherwise, the method 500 may terminate. Alternatively, if the transient performance deadline has expired, the method 500 may proceed to block 508 and the power controller may move the CPU to a higher performance level, i.e., the next higher operating frequency. In one aspect, the controller may move the CPU to a maximum performance level, i.e., the maximum CPU frequency. However, in another aspect, the CPU may not jump to the maximum performance level. The CPU may jump to an intermediate level and then jump again to a maximum level or another higher performance level. The number of intermediate jumps, and the amount of time between jumps, may be used to determine the frequency value of the jump.

At block 510, the CPU may enter an idle condition. Also, at block 512, the transient performance deadline may be reset. At block 514, the CPU may terminate the idle condition. Moving to decision 516, the power controller may determine whether the CPU frequency in question is at the maximum CPU frequency. In such a case, the method 500 may terminate. Alternatively, if the CPU frequency is not at the maximum CPU frequency, the method may proceed to block 518 and the timer may be rescheduled. Next, the method 500 may be terminated.

Referring to FIG. 6, a second embodiment of a method for dynamically controlling the power of a central processing unit is shown and generally designated 600. Starting at block 602, the central processing unit (CPU) may enter the idle state. At block 604, a power controller, e.g., a dynamic clock and voltage scaling (DCVS) algorithm, may set the idle start time (StartIdleTime) to be equal to the current time (CurrentTime). Also, at block 606, the power controller may determine the busy time (BusyTime) by subtracting the idle start time (StartIdleTime) from the idle end time (EndIdleTime).

At block 608, the CPU may enter a software wait for interrupt (SWFI) condition. At block 610, the CPU may terminate the SWFI condition. Moving to block 612, the power controller may set the idle end time (EndIdleTime) equal to the current time (CurrentTime). Also, at block 614, the power controller may determine the idle time (IdleTime) by subtracting the idle start time (StartIdleTime) from the idle end time (EndIdleTime). At block 616, the power controller may determine the CPU frequency (CPUFreq) in question from the updated steady state filter (UpdateSteadyStateFilter) busy time (BusyTime) and the idle time (IdleTime). The method 600 may then continue to block 702 of FIG.

At block 702, the power controller may determine an EffectiveTransientBudget using the following formula:

EffectiveTransientBudget = (TransientResponseDeadline * NextCPUFreq) / (NextCPUF-req-CPUFreq)

here,

TransientResponseDeadline = transient response deadline, ie slack budget,

NextCPUFreq = one frequency step higher than the current CPU frequency, the next higher CPU frequency, and

CPUFreq = The CPU frequency (CPUFreq) you are facing.

In a particular aspect, the ClockSchedulingOverhead and ClockSwitchOverhead may also be added to EffectiveTransientBudget. In addition, the VoltageChangeOverhead may be added to EffectiveTransientBudget. Moving to block 704, the power controller may set the deadline (SetJumpToFrequency) for jumping to a higher frequency equal to the idle end time (EndIdleTime) plus plus EffectiveTransientBudget. In another aspect, the deadline for jumping may be current time plus transient budget. The method 600 may then terminate.

In a particular aspect, the method 600 described in conjunction with Figures 6 and 7 can be used to determine the amount of time the CPU may remain at the frequency determined by the DCVS, before the transient deadline is depleted, And may be used to schedule a jump to a higher CPU frequency by the amount of time. If re-entering the idle prior to a jump to a higher frequency, the scheduled jump may be canceled. The method 600 may delay the jump to a higher frequency by an amount of time determined as EffectiveTransientBudget.

It should be understood that the method steps described herein need not necessarily be performed in the order described. Also, words such as "after "," next ", "next ", and the like are not intended to limit the order of the steps. These words are simply used to guide the reader through the description of the method steps. In addition, the methods described herein are described as being executable on a portable computing device (PCD). The PCD may be a mobile phone device, a portable information terminal device, a smart book computing device, a netbook computing device, a laptop computing device, a desktop computing device, or a combination thereof.

In a particular aspect, the DCVS algorithm measures the CPU load / idle time and is a mechanism to dynamically adjust the CPU clock frequency to track the workload in an effort to reduce power consumption while still providing satisfactory system performance. As the workload changes, changes in CPU throughput may not only track changes in the workload, but may also lag it. Unfortunately, this may introduce problems when the workload has QoS requirements because the DCVS algorithm may not be able to track the workload quickly enough. Also, tasks may fail.

Many DCVS techniques include measuring the steady state performance requirements of the CPU and setting the CPU frequency and voltage to the lowest level that may meet the steady state CPU usage. This is typically done by measuring CPU utilization (percent busy) over a period of time and setting the CPU performance level to be between the high and low thresholds of average CPU utilization. The averaging period is optimized to minimize the frequency of changing clock frequencies while maintaining reasonable responsiveness. In order to respond to the onset of transient workloads and / or new workloads, the panic inputs may have been used to quickly raise the CPU frequency.

To avoid the problems of DCVS that lag the workload and cause tasks to fail, the systems and methods disclosed herein provide a transient performance guarantee. Transient performance assurance may be defined as the amount of maximum time in which successive busy pulses may be delayed, as opposed to performing at a higher performance level. This is because, by definition, it is not in an oversubscribed state, by reaching a higher performance level before the transient performance deadline expires, and if the CPU is an idle, May be accomplished by resetting. As disclosed herein, whenever the system comes out of the idle and the system CPU is not running at the maximum frequency, the timer may be rescheduled to preserve QoS guarantees.

To minimize the power impact of transient performance assurance, the present systems and methods minimize the possibility that the incoming pulse may require a frequency increase to meet the deadline. This will delay the frequency, i.e., the performance level change, until the effective over-budget is exhausted, and then jump straight to the higher performance level and stay there until the pulse is complete as shown in FIG. ≪ / RTI >

In a particular aspect, the effective transient budget is calculated as a transient response deadline scaled to the current performance level. For example, if the CPU is running at 75% of the maximum clock rate and the transient response deadline is 16 ms, the effective transient budget is 64 ms, or 16 ms / (1-0.75). Valid transient budget indicates how long the CPU may run at the current performance level before exhausting the budget. If the CPU is idle, the effective transient budget may be the same as the transient response deadline. When at the maximum performance level, the effective transient budget is infinite as shown in FIG.

Using the methods described herein, the system may provide a strict boundary with respect to the amount of maximum time that a task may have been executed at some level other than the maximum level, and therefore, It may implicitly provide a computable boundary on completion for tasks that require assurance. The boundary may be set based on what the tasks are currently executing, global system attributes, DCVS algorithm design, or other attributes, or if the system is not executing any tasks with QoS requirements, It may be completely disabled when it is being executed in the system.

In particular aspects, the methods may be used to set shorter internal valid deadlines, while jumping to the maximum frequency when the deadline has expired, while still ensuring that the CPU is at the maximum frequency before the maximum QoS delay has exhausted, Or by jumping to one or more intermediate frequencies. In addition, the methods may substantially guarantee that a well-defined transient QoS is maintained while simultaneously degrading the overall CPU power.

The systems and methods described herein may use opportunistic sampling. In other words, the system and methods may periodically check for timer expiration. In other aspects, the systems and methods may not use accidental sampling.

As discussed above, various aspects provide a strict and computable boundary (e.g., performance assurance) for completion of tasks. In various aspects, such performance guarantees may be used to improve processor performance and / or to improve performance of the processor and / or to improve performance of the processor and / E-mail receivers, multimedia Internet enabled cellular phones, wireless gaming controllers, and memory, programmable processors or cores (hereinafter collectively referred to as "processing cores"), May be implemented as part of a dynamic clock and voltage / frequency scaling (DCVS) solution to reduce power consumption on portable computing devices (PCDs), including similar personal electronic devices that operate. In addition, while the various aspects are particularly useful for portable and mobile computing devices that run in accordance with battery power, aspects generally include any computing device (e.g., general purpose computers, Desktop computers, servers, etc.).

In general, the dynamic power (switching power) consumed by the chip is C * V ² * f, where C is the capacitance that is switched per clock cycle, V is the voltage, and f is the switching frequency. Thus, as the frequency changes, the dynamic power will change linearly with it. Dynamic power may account for approximately two-thirds of the total power consumed by the processor chip. Since the frequency at which the chip is run may be related to its operating voltage, voltage scaling may be achieved with frequency scaling. The efficiency of some electrical components, such as voltage regulators, may decrease as the temperature increases, such that power consumption increases with temperature. Increasing power utilization may increase the temperature, so increases in voltage or frequency may further increase system power demands. Thus, the battery life of a computing device may be improved by lowering the frequency and / or voltage applied to the processors when the processors are idle or lightly loaded. These degradations in frequency and / or voltage may be achieved in real time or "on the fly" through a dynamic clock and voltage / frequency scaling (DCVS) solution.

In general, the DCVS solution monitors the percentage of time that the processor is idle (compared to the busy time of the processor) and determines how much the frequency / voltage of the processors controls how much the processors are based on the ratio of idle and / ≪ / RTI > Monitoring the percentage of time that a processor is idle means that a value indicating the duration (e.g., the amount of time, the number of CPU cycles, etc.) that the processor is executing an idle process or thread (e.g., a system idle process, / RTI > and / or < / RTI >

An operating system may execute an idle software application, process, or thread (collectively "thread" herein) on the processor when it determines that there are no other threads ready to be scheduled for that processor. The idle thread may perform various tasks (e.g., interrupt waiting task, sleep task, etc.), and each task may include multiple processor operations. When a processor executes an idle thread, the processor may say "idle" in an "idle state" and / or an "idle condition.

In multiprocessor systems, the operating system (or scheduler, controller, etc.) may maintain one or more idle threads for each processor. The idle threads remain ready for execution so that each processor always has a thread ready to run. In this way, whenever a thread relinquishes a processor (e.g., due to a thread completing its scheduled tasks or workloads), even every other thread is completed, waiting for resources, The operating system has a thread ready for execution on that processor (e.g., through the availability of an idle thread) even when it is not currently prepared to run differently.

As discussed above, the DCVS solution may adjust the frequency and / or voltage of the processor based on the workloads of the processor, which may include steady state workloads. The steady state workload may be determined ahead of the execution time, i.e., prior to the processor core entering the busy or active state to perform operations for the enhancement of the workload. A steady state workload may be predetermined by computing, estimating, or predicting the amount of CPU clock cycles, the number of operations, the number of instructions, and / or the amount of time required to complete the scheduled tasks on that processing core . Each processor may have more than one workload (e.g., a steady state workload and an overloaded workload), and each processor may perform a busy, execute , Or in an active state (collectively "busy state" herein).

In some scenarios, the DCVS solution may degrade the frequency and / or voltage of the processor (i. E., The speed of the processor) in order to achieve power savings without affecting the performance of the processor. For example, when the workload of a processor includes a task whose execution time is dominated by memory access times, degradation in frequency may not have a significant impact on processor performance or execution time of the task. In general, however, the DCVS solution may be used to determine the performance of the processor (e.g., the time required to complete a given set of tasks, etc.) and the amount of power consumed (e.g., the amount of battery power consumed in achieving a given set of tasks) ) Trade-offs. Typically, the faster the tasks are accomplished, the more power is consumed by the processor in accomplishing those tasks.

The DCVS solution may be configured to balance performance and power consumption based on steady state workload and steady state performance requirements of the processor. Steady state performance requirements may include computing or measuring values (e.g., amount of time, number of CPU cycles, etc.) indicative of the duration of time that the processor is busy and / or idle, and computing the results of the computed / And determining the amount of time / processing required to complete the steady state workloads of the processor. Based on these operations, the DCVS solution may be adapted to meet the computed steady state requirements while achieving levels of degraded power consumption and acceptable responsiveness (e.g., such that the mobile device user does not recognize differences, etc.) And may compute an upper frequency threshold and a lower frequency threshold that may be operating.

Often, processors are required to process / execute transient workloads that include "bursts of work" where the DCVS solution has not been a priori known and has not been considered in steady state or frequency threshold operations. The transient workload may be a unit of any task or task that is not previously known to the system, including any unit of work that is dynamic, temporary, or causes spikes that are not anticipated in the processor's workload have. By way of example, the transient workload may include any or all of the tasks performed by the processor in response to user inputs, system events, detected environmental conditions, remote procedure calls, and the like. As a further example, the transient workload may be created when a user touches the touch-screen of a portable computing device (PCD) to initiate a user action, and the PCD (e.g., Displaying it, launching a new action, etc.).

As noted above, transient workloads are not continuous steady state workloads that the DCVS solution can properly pre-consider (e.g., as part of determining upper and lower thresholds). As a result, transient workloads may cause the processor to remain in a busy state longer than expected, and / or otherwise cause uncertainties in processor execution times. These uncertainties may cause computing devices to inefficiently or inappropriately allocate processing and system resources and may have a significant impact on the overall performance and / or responsiveness of the computing device, particularly when the computing device includes multiple processing cores It is possible.

Modern computing devices are often multiprocessor systems that include system-on-chip (SoCs) and / or multiple processing cores (e.g., processors, cores, etc.). In multiprocessor systems, it is common for a single thread to be processed by a first processing core, then by a second processing core, and then again by a first processing core. It is also common for the results of one thread in the first processing core to trigger operations in another thread executing in the second processing core. For example, the one or more processing cores may be dependent on the results generated by the currently active processor, and may be dependent on the currently active processor until it finishes its workloads and / or finishes processing one or more tasks , Idle or in a waiting state. In these situations, each processing core may alternatively enter the idle / standby state while waiting for the results of processing from the currently active processor. These processing cores wait for the results produced by the currently active processor, but their respective DCVS solutions may degrade their operating speeds (i. E., Through a decrease in frequency / voltage) - May be responsive or slow. That is, a DCVS solution implemented on multiprocessor computing devices must be operated at a lower frequency or voltage than some of the processing cores are optimal for running currently active threads, and the computing device may be non-responsive It can be misleadingly concluded that it makes you look slow.

Various aspects may be implemented in a computing system that does not allow the processing core to be busy (e.g., due to transient workloads) beyond a predetermined amount of time than is required for that processing core to complete its pre- By computing and enforcing performance guarantees to ensure that they do not stay in a state. These performance guarantees may be used by operating systems, resources, DCVS solutions, and / or the like to better estimate, schedule, and / or plan future operations such as allocating resources and scheduling threads for execution But may be used by other processing cores. In this way, performance guarantees enable a computing device to meet its responsiveness requirements, thereby improving the user experience.

Performance guarantees enable the DCVS solution to adjust the frequency and / or voltage of the processor based on the variable delay, which allows the processing core to define at most the task, regardless of the processor's current or previous operating frequencies / Of the normalized workload by the maximum amount of work being done.

10 illustrates logical components and information flows in an aspect of computing device 1000 implementing a dynamic clock frequency / voltage scaling (DCVS) solution to enforce performance guarantees. The computing device 1000 may include a hardware unit 1002, a kernel space software unit 1004, and a user space software unit 1006. In an aspect, kernel space software unit 1004 and user space software unit 1006 may be included within the operating system or kernel of computing device 1000. For example, a computing device may include a user space (where non-privileged code is executed) and a kernel organized into kernel space (where privileged code is executed). This separation requires that the code that is part of the kernel space be GPL-licensed, while the code running in user-space is not specifically GPL-enabled in Android and other general public license environments It is important.

The hardware unit 1002 includes a plurality of processing cores (e.g., CPU 0, CPU 1, 2D-GPU 0, 2D-GPU 1, 3D-GPU 0, Including resources (e.g., clocks, power management integrated circuits or "PMICs ", scratchpad memories or" SPMs " .

The kernel space software unit 1004 includes processor modules corresponding to at least one of the processing cores in the hardware unit 1002 such as CPU_0 idle statistics, CPU_1 idle statistics, 2D-GPU_0 driver, 2D-GPU_1 driver, 3D- Etc.), each of which may communicate with one or more idle statistics device modules 1008. The kernel space software unit 1004 may further include a timer driver module 1014, input event modules 1010, and a CPU request statistics module 1012. In an aspect, timer driver module 1014 may drive (or maintain) a timer for each processing core.

User space software unit 1006 may receive inputs from each of idle statistics device modules 1008, input event modules 1010, timer driver module 1014 and CPU request statistics module 1012, and / And a DCVS control module 416 configured to send outputs to the CPU frequency hot-plug module 1018. [ The CPU frequency hot plug module 1018 may be configured to transmit communication signals to the resources module 1020. The CPU frequency hot plug module 1018 may be configured to add voltage / frequency changes to each core individually (e.g., one at a time, one at a time, etc.) or concurrently (e.g., at about the same time in time) .

The DCVS control module 1016 is suitable for execution on any or all of the processing cores (e.g., CPU 0, CPU 1, 2D-GPU 0, 2D-GPU 1, 3D-GPU 0, , And / or threads suitable for implementing a DCVS solution on computing device 1000. [ In one aspect, the DCVS control module 1016 may be configured to cause the DCVS control module 1016 to collect events from one or more processing cores and to perform events (e.g., , A timer expiration, a state transition, etc.). In an aspect, the DCVS control module 1016 may include a single-threaded DCVS solution that monitors two or more processing cores. In an aspect, the DCVS control module 1016 may include a DCVS solution thread for each processing core.

In an aspect, the DCVS control module 1016 may be configured to generate pulse trains. DCVS control module 1016 may generate pulse trains by monitoring or sampling busy and / or idle states (or transitions between states) of the processing cores. The DCVS control module 1016 may also generate pulse trains based on information obtained from monitoring the depth of one or more processor run-cues. The run-time queue may include a set of one or more threads that can be executed on the processing core as well as a running thread, but which may not yet be able to do so (for example, due to another active thread currently executing). Each processing core may have its own run-queue, or a single run-queue may be shared by multiple processing cores. The threads may be removed from the run queue when the threads are requesting entry into the sleep state, waiting on the resource to be made available, or terminated. Thus, the number of threads in the run queue (i. E., The run queue depth) is determined by the number of active threads that are currently processing (executing) and including threads waiting to be processed (e.g., The number may be identified.

In an aspect, the DCVS control module 1016 may be configured to calculate steady state workloads, steady state requirements, and / or upper and lower frequency / voltage thresholds based on the generated pulse trains. The upper and lower frequency / voltage thresholds may be set to a frequency / voltage range that may be operative to simultaneously achieve reduced power consumption and meet the responsiveness requirements of the computing device 1000, while meeting the steady state performance requirements thereof May be defined. Meeting the responsiveness requirements may include performing all tasks in the workloads such that a user of the computing device 1000 is not aware of a degradation in performance or speed of the computing device.

The DCVS control module 1016 may be configured to monitor the overall computing device 1000 performance and / or to ensure that one or more of the processing cores operate between established upper and lower frequency thresholds. The DCVS control module 1016 may adjust the operating frequencies of the processing resources and / or processing cores such that the operating frequencies of the processing resources and / or processing cores are proportional to the thresholds.

As discussed above, the DCVS control module 1016 may generate pulse trains. In one aspect, the pulse trains generated for two or more of the processing cores may be synchronized in time, and may be synchronized in time and may include appropriate information to determine whether the processing cores are performing cooperative and / May be cross-correlated in order to generate correlation models including < RTI ID = 0.0 > In one aspect, the DCVS control module 1016 is configured to determine the upper and lower frequency thresholds, the initial operating frequency, the steady state requirements, and the processor workloads so that this value considers interdependencies among the processing cores Correlation models may be used to determine.

In an aspect, DCVS control module 1016 may be configured to compute and / or enforce performance guarantees. As noted above, the processing cores may be required to process / execute transient workloads that the DCVS solution can not pre- Thus, transient workloads may cause the DCVS control module 1016 to operate one or more of the processing cores at a frequency of a lane or within a frequency range of a lane. For example, since the DCVS control module 1016 can not pre-consider transient workloads, it is not necessary for the processing cores to have a steady state workload and a transient workload in a reasonable time period to meet the responsive requirements of the computing device 1000 It may be improperly concluded that it may operate at a lower frequency level than that required to complete both.

Performance assurance is achieved when the processing core is in a busy state (e.g., due to transient workloads) beyond a predetermined amount of time / work than is required for that processing core to complete its steady state workload requirements To the computing device 1000, a rigid and computable boundary that may be used by the DCVS control module 1016 to ensure that the DCVS control module 1016 does not stay in the DCVS control module 1016. [ Performance assurance ensures that the DCVS control module 1016 completes both its steady state workload and its transient workloads in a reasonable time period to satisfy the responsiveness requirements of the computing device 1000 .

In various aspects, performance assurance may be computed in any unit of measurement suitable for measuring processor performance or duration, such as the amount of time, the amount of work, the number of tasks, the number of instructions, the number of CPU cycles, And may be defined in any unit, and / or may include any unit. In various aspects, performance assurance may be associated with frequency, and / or may be a function of frequency.

In an aspect, the performance assurance may include one or more performance assurance values. In various aspects, performance assurance values (e.g., deadline value, budget value, jump-to-max value, etc.) may be determined by the amount of time, the amount of work, May be represented by any unit of measurement suitable for measuring processor performance or duration, such as the number, number of CPU cycles, and so on.

In various aspects, the performance assurance values may include one or more of the following: a value of a budget (e.g., loose budget, excessive budget, etc.), a deadline value (e.g., transient deadline, transient response deadline, performance deadline, etc.) It may also contain a jump-to-max value.

The deadline value may be a value indicating the relative time at which the processing core should complete its workload processing before and / or a value indicating the relative time at which the frequency of the processing core should then be increased.

The value of the budget may be the amount of time remaining, a value indicating the amount of time remaining before the processing core must complete its workload processing and / or the frequency of the processing core must then be increased .

The jump-to-max value may be a value that indicates the time at which the processing core must complete its workload processing and / or the relative time at which the frequency of the processing core should then be increased.

The performance assurance values may be related to a function of frequency or voltage, and / or may be a function of frequency or voltage. For example, each of the budget, deadline, and / or jump-to-values may be a time value that is computed as a function of the operating frequency of the corresponding processing core. Thus, each of these values may be 10 milliseconds when the processing core is operating at a frequency of 100 MHz, 20 milliseconds at a frequency of 200 MHz, 40 milliseconds at a frequency of 400 MHz, etc. . In this manner, the performance assurance values may be used by the DCVS solution to implement a variable delay to increase the frequency of the processing core.

As mentioned above and illustrated in FIG. 9, the DCVS solution may implement variable delays. These variable delays ensure that the processing cores are inferior to their steady state workloads at most by the amount of maximum work defined, regardless of the actual operating frequencies of the processing cores. In one aspect, the DCVS solution is designed to provide the same amount of defined maximum work (i. E., Thereby the processing core may belong to the rear of its steady state work load) to a deadline value multiplied by the maximum frequency / voltage of the processing core . In this way, performance guarantees are unaffected by DCVS solutions that regulate the frequency / voltage of the processing cores based on steady state requirements or dynamically or "on the fly."

In one aspect, the DCVS control module 1016 is configured to determine whether a corresponding processing core is transitioning from idle to busy, entering a busy state (e.g., processing a workload, etc.) and / , And the idle state terminates the idle state, such as when the idle thread abandons the processing core, etc.).

In an aspect, the DCVS control module 1016 may be configured to cause the corresponding processing core to transition from busy to idle, enter an idle state (e.g., running an idle thread, etc.) and / (E.g., to complete all tasks in a workload, etc.), the system may be configured to set or reset an existing deadline value.

Figures 11A-11B illustrate a method for a processing core to request a processing core to complete its pre-computed, predicted, and / or actual steady state workload (e.g., due to transient workloads, etc.) / RTI > illustrates a DCVS solution method 1100 of one aspect of generating / computing a performance guarantee that ensures that a user does not stay in a busy state beyond an amount of more than a predetermined amount of time. In various aspects, the operations of the DCVS solution may be performed by a thread executing on a processing core or on another processing core. In an aspect, one or more of the operations of the DCVS solution may be performed by an idle thread executing on the processing core.

At block 1102, the DCVS solution may cause the processing core to transition from the idle state to the busy state. At block 1104, the DCVS solution may set the value of the idle end time parameter (EndIdleTime) equal to the current time value (CurrentTime). Thus, the idle end time parameter (EndIdleTime) may store a value indicating the time at which the processing core last terminated the idle state.

In various aspects, the operations of blocks 1102 and 1104 may be performed sequentially, concurrently, and / or in any order. For example, in one aspect, the DCVS solution may set the value of the idle end time parameter (EndIdleTime) before transitioning the processing core from idle to busy. In another aspect, the DCVS solution may set the value of the idle end time parameter (EndIdleTime) after transitioning the processing core from idle to busy.

At block 1106, the DCVS solution may monitor the operating frequency or voltage of the processing core and make adjustments as needed. At block 1108, the DCVS solution may cause the processing core to transition from busy state to idle state. In an aspect, the DCVS solution may transition the processing core to the idle state by initiating the execution of the idle thread on the processing core. In an aspect, the DCVS solution may transition the processing core to the idle state after the processing core has completed all tasks associated with all its workloads.

In optional block 1110, the DCVS solution may set or reset an existing deadline value. As discussed above, the deadline value may be a performance assurance value included in or associated with the performance assurance. Additional details regarding operations to set, reset, and / or compute deadline values are provided further below.

At block 1112, the DCVS solution may set the idle start time parameter (StartIdleTime) equal to the current time value (CurrentTime). At block 1114, the DCVS solution compares the value of the busy time parameter BusyTime with the time at which the processing core last terminated the previous idle state (which may be represented by the idle end time parameter "EndIdleTime & To the current idle state (which may be represented by the idle start time parameter "StartIdleTime"). Thus, the Busy Time parameter BusyTime may store a value indicating the last time the processing core stays in the busy state most recently.

At block 1116, the DCVS solution may cause the processing core to perform various idle state operations, such as sleep operations, deep sleep operations, or software interrupt wait operations. Thus, at block 1116, the DCVS solution may cause the processing cores to enter a sleep state, a deep sleep state, an interrupt wait state, etc. (e.g., via idle threads, operating, etc.).

At block 1118, the DCVS solution and / or the idle thread may receive an interrupt request and / or otherwise determine that the processing core should transition from its current state to the busy state. This may be accomplished by a DCVS solution that receives notifications (e.g. from an operating system scheduler, controller, etc.) that the tasks have been scheduled for execution on the processing core and / or the scheduled tasks are ready for execution have.

At block 1120, the DCVS solution may set the value of the idle end time parameter (EndIdleTime) equal to the current time value (CurrentTime). At block 1122, the DCVS solution may set the value of the idle time parameter (IdleTime) equal to the difference between the value of the StartIdleTime parameter and the value of the EndIdleTime parameter. Thus, the idle time parameter IdleTime may store a value indicating the duration that the processing core last stayed in the idle state.

At block 1124, the DCVS solution may compute operating frequency, frequency range, and / or frequency thresholds at which the processing core must operate. In an aspect, the DCVS solution may include a time duration (e.g., BusyTime) during which the processing core stays last in the busy state and / or a duration of the time the processing core last stayed in the idle state (e.g., IdleTime). ≪ / RTI > In one aspect, the DCVS solution may be used to determine whether the processor is in the history information, such as an average (or moving average) of durations that were previously in the busy and / or idle states (e.g., over a predetermined time period or time window) Frequency ranges, and / or frequency thresholds based on the operating frequency, frequency range, and / or frequency threshold. In an aspect, the DCVS solution may compute operating frequency, frequency range, and / or frequency thresholds based on the pulse trains. As discussed above, the pulse trains may be generated based on sampling of busy and / or idle states, transitions between states, depth of run-cues, and the like.

At block 1126, the DCVS solution may compute or select a deadline value. The deadline value may be a value indicating the relative time, after which the frequency of the processing core should be set to increase to the next higher frequency step or to the maximum frequency. In various aspects, the deadline value may be computed based on configuration settings, driver inputs, the amount and / or types of scheduled tasks, the predicted steady state workload, and / or the responsiveness requirements of the computing device It is possible. The deadline value may be determined based on static and / or dynamic values. For example, the deadline value may be determined based on static configuration values, or based on types of tasks scheduled to be performed on the processing core (e.g., 1080p video stream vs. 720p video stream, etc.).

In an aspect, the deadline value may be inversely proportional to the responsiveness requirements of the computing device (i.e., the higher the responsiveness requirements, the shorter the deadline). In one aspect, the deadline value is a time value that is a function of the current operating frequency of the processing core (e.g., 10 milliseconds at a frequency of 100 MHz, 20 milliseconds at a frequency of 200 MHz, 40 milliseconds at a frequency of 400 MHz, Seconds, etc.).

At block 1128, the DCVS solution may compute or select a budget value. The value of the budget is the amount of time that the processing core may remain in the active or busy state without exceeding the sum of the deadline value and the time determined to be required for the processing core to complete its steady state workload requirements Or may be a value to be displayed. In one aspect, the value of the budget is a time value that is a function of the current operating frequency of the processing core (e.g., 10 milliseconds at a frequency of 100 MHz, 20 milliseconds at a frequency of 200 MHz, 40 milliseconds at a frequency of 400 MHz Etc.).

In various aspects, the budget value may be computed based on a deadline value, a plurality of frequency levels or steps, a maximum processor frequency, a steady state processor frequency, and the like. In an aspect, the value of the budget may be an effective over-budget, and / or may be computed via any of the formulas discussed above.

In optional block 1130, the DCVS solution may compute a jump-to-maximum value. The jump-to-max value may be a relative time, and then a value indicating the relative time at which the frequency of the processing core should be set to the maximum processing frequency. In an aspect, the jump-to-max value may be computed by summing the value of the EndIdleTime parameter and the value of the budget.

At block 1132, the DCVS solution may transition the processing core from the idle state to the busy state. In an aspect, as part of block 1132, the DCVS solution may set the deadline value equal to the budget value. In various aspects, the DCVS solution may be implemented in such a way that the processing core transitions from idle to busy and enters an active or busy state (e.g., processing a workload, etc.) and / May be configured to set the deadline value equal to the < RTI ID = 0.0 > budget < / RTI > value each time the idle state is terminated.

Figure 12 is a graphical representation of what is required for a processing core to complete its pre-computed, predicted, and / or actual steady state workload (e.g., due to the presence of transient workloads) Illustrate one form of DCVS solution method 1200 that enforces a performance guarantee that ensures that the system does not stay in busy state beyond an amount of more than a predetermined amount of time. At block 1202, the DCVS solution may compute a predicted steady state workload based on the scheduled tasks. At block 1204, the DCVS solution may compute various performance requirements for the processing core, such as frequency thresholds to meet power consumption and / or responsiveness requirements of the computing device. Performance requirements (e.g., frequency thresholds, etc.) may be based on steady state workload, historical information (e.g., amount of time previously spent in busy state), processor characteristics, responsiveness requirements, May be determined.

At block 1206, the DCVS solution may compute and set the initial operating frequency and / or various performance assurance values (e.g., deadline, budget, jump-to-max, etc.). At block 1208, the DCVS solution may determine the amount of time or work required for the processing core (e.g., CPU cycles, instructions, etc.) to complete all tasks in a steady state workload while meeting various performance requirements ). ≪ / RTI >

At block 1210, the DCVS solution is programmed to cause the processing core to operate in an idle state (e.g., within the computed thresholds) and / or to satisfy various device or system requirements at an initial operating frequency / To the busy state. At block 1212, the DCVS solution may monitor the actual workload and / or operating frequency of the processing core and may monitor frequency / voltage (e. G., According to the default clock and voltage scaling algorithm) . In optional block 1214, the DCVS solution may update the performance assurance values based on the current operating frequency / voltage of the processing core.

At decision block 1216, the DCVS solution determines whether the processing core is more than the computed time / task (i.e., the amount of time / task determined to be required for the processing core to complete all tasks in the predicted steady state workload) You may decide whether you have stayed in a long busy state. When the DCVS solution determines that the processing core has not stayed in busy state longer than the computed time / task (i.e., decision step 1216 = "NO"), at block 1212, / You may continue to monitor the frequency and make adjustments as needed.

When the DCVS solution determines that the processing core has stayed in busy state for a longer duration than the computed time / task (i.e., decision step 1216 = "YES"), at decision block 1218, May be determined to be exhausted. The DCVS solution can be used to determine when the budget value equals zero and / or when the processing core has stayed in busy state for a duration (measured in either time or work) that is greater than the computed time / task plus deadline value May be determined to have been depleted.

When the DCVS solution determines that the budget has not been exhausted (i.e., decision step 1218 = "NO"), at block 1212, the DCVS solution continues to monitor the actual workload / frequency and make adjustments as needed It is possible. At block 1220, the DCVS solution may increase the operating frequency / voltage of the processing core when the DCVS solution determines that the budget is depleted (i.e., decision step 1218 = "yes"). In an aspect, at block 1220, the DCVS solution may increase the operating frequency / voltage of the processing core to a maximum processor frequency. In an aspect, at block 1220, the DCVS solution may increase the operating frequency / voltage thresholds. In an aspect, at block 1220, a DCVS solution may increase the operating frequency / voltage of the processing core in steps.

FIG. 13 illustrates another embodiment of a DCVS solution method 1300 that enforces performance guarantees. In blocks 1302-1314, the DCVS solution may perform the same or similar operations as the operations discussed above for blocks 1202-1214 in FIG. At decision block 1316, the DCVS solution calculates the plus deadline value (the amount of time that the processing core is determined to be required for the processing core to complete all tasks in the predicted steady state workload) ≪ / RTI > time + deadline) before the current workload is completed.

When the DCVS solution determines that the processing core is likely to complete its current workload before the computed time plus deadline value (i.e., decision step 1316 = "YES"), at block 1312, It may monitor this actual workload / frequency and continue to make adjustments to the operating frequency / voltage as needed.

When the DCVS solution determines that the processing core is not likely to complete its current workload before the computed time value plus deadline value (i.e., decision 1316 = "NO"), The DCVS solution may also increase the operating frequency / voltage of the processing core. The operating frequency / voltage of the processing core may be increased to the maximum processor frequency or steps.

Various aspects include determining a steady state workload of a processor, determining the amount of work required to perform a steady state workload determined on the processor, computing a performance guarantee value for the processor, Performing dynamic clock and voltage scaling operations to scale the frequency of the processor based on the actual workload of the processor, updating the performance guarantee value based on the scaled frequency, Determining whether the processor stays in the busy state for a period equal to or greater than the sum of the determined amount of work and the performance guarantee value and when the processor is determined to have stayed in the busy state for a period equal to or greater than the sum of the determined amount of work and the performance guarantee value , Increasing the frequency of the processor Having a processor, which may include that include methods for improving the performance of the computing device.

In one aspect, increasing the frequency of the processor when it is determined that the processor stays in the busy state for a period of time equal to or greater than the sum of the determined work and performance guarantees may include increasing the frequency of the processor to the maximum processor frequency have. In a further aspect, increasing the frequency of the processor when it is determined that the processor has stayed in busy state for a period of time equal to or greater than the sum of the determined work and performance guarantee values may include increasing the frequency of the processor to steps have. In a further aspect, the method updates the performance assurance value based on the scaled frequency, and determines whether the processor has stayed in the busy state for a period of time equal to or greater than the sum of the determined amount of work and the performance assurance value, And increasing the frequency of the processor when it is determined that it has stayed in the busy state for a period of time equal to or greater than the sum of the amount and the performance guarantee value of the processor.

In a further aspect, computing a performance guarantee value for a processor may involve computing a deadline value. In a further aspect, computing the performance guarantee value for the processor may involve computing the budget value. In a further aspect, determining a steady state workload of a processor may include determining requirements of tasks scheduled to run on the processor. In a further aspect, the method may comprise generating pulse trains by sampling transitions between busy and idle states. In a further aspect, operations that determine the steady state workload of the processor, determine the amount of work required to perform a steady state workload on the processor, and compute the performance guarantee value for the processor are performed by a single thread . In a further aspect, a single thread is executed on the processor. In a further aspect, a single thread is executing on a second processor of the computing device.

Various aspects may include means for determining a steady state workload of a processor, means for determining an amount of work required to perform a steady state workload determined on the processor, means for computing a performance guarantee value for the processor, Means for performing dynamic clock and voltage scaling operations to scale the frequency of the processor based on the actual workload of the processor, means for performing a performance guarantee on the basis of the scaled frequency Means for determining whether the processor has stayed in a busy state for a period of time equal to or greater than the sum of the determined amount of work and the performance guarantee value, and means for determining whether the processor has stayed in the busy state for a period of time equal to or greater than the sum of the determined amount of work, I stayed in state When it is determined, and a computing device having means for increasing the frequency of the processor.

In one aspect, the means for increasing the frequency of the processor when it is determined that the processor has stayed in the busy state for a period of time equal to or greater than the sum of the determined work and performance guarantee values comprises means for increasing the frequency of the processor to a maximum processor frequency .

In a further aspect, when it is determined that the processor has stayed in busy state for a period of time equal to or greater than the sum of the determined work and performance guarantee values, the means for increasing the frequency of the processor comprises means for increasing the frequency of the processor to steps . In a further aspect, the computing device updates the performance assurance value based on the scaled frequency, and determines whether the processor has stayed in busy state for a period of time equal to or greater than the sum of the determined amount of work and the performance assurance value, And may further comprise means for iteratively performing operations to increase the frequency of the processor when it is determined that it has stayed in busy state for a period equal to or greater than the sum of the amount of work and the performance guarantee value.

In a further aspect, the means for computing the performance guarantee value for the processor may comprise means for computing a deadline value. In a further aspect, the means for computing the performance guarantee value for the processor may comprise means for computing the budget value. In a further aspect, the means for determining a steady state workload of a processor may comprise means for determining requirements of tasks scheduled to run on the processor. In a further aspect, a computing device may include means for generating pulse trains by sampling transitions between busy and idle states.

In a further aspect, a computing device may be configured to determine a steady state workload of a processor, to determine an amount of work required to perform a steady state workload on the processor, to compute a performance guarantee value for the processor via a single thread, May also include means for accomplishing the above. In a further aspect, a computing device may include means for executing a single thread on a processor. In a further aspect, a computing device may comprise means for executing a single thread on a second processor of the computing device.

Additional aspects include determining a steady state workload of a second processor, determining an amount of work required to perform a steady state workload determined on the second processor, computing a performance guarantee value for the second processor Performing the dynamic clock and voltage scaling operations to scale the frequency of the second processor based on the actual workload of the second processor, performing the scaled Determining whether the second processor has stayed in the busy state for a period of time equal to or greater than the sum of the determined amount of work and the performance guarantee value based on the frequency and the amount of the determined work And the performance guarantee value for a period equal to or greater than the sum of the performance guarantee values Includes a processor configured with processor-executable instructions for performing operations that may include a first processor configured with processor-executable instructions for performing operations, including increasing a frequency of a second processor Lt; RTI ID = 0.0 > a < / RTI >

In one aspect, the first processor is configured to increase the frequency of the second processor when it is determined that the second processor has stayed in busy state for a period of time equal to or greater than the sum of the determined performance and the performance guarantee value, To a maximum processor frequency. The processor-executable instructions may also include instructions that, when executed,

In a further aspect, the first processor is configured to increase the frequency of the second processor when it is determined that the second processor has stayed in busy state for a period of time equal to or greater than the sum of the determined work and the performance guarantee value, May also comprise processor-executable instructions that may include increasing the frequency to steps.

In a further aspect, the first processor also updates the performance assurance value based on the scaled frequency and determines whether the second processor stays in the busy state for a period of time equal to or greater than the sum of the determined amount of work and the performance assurance value And processor-executable instructions for repeatedly performing operations to increase the frequency of the second processor when it is determined that the second processor has stayed in busy state for a period of time equal to or greater than the sum of the determined work and performance guaranteed values As shown in FIG. In a further aspect, the first processor may be comprised of processor-executable instructions that may include computing a deadline value for computing the performance guarantee value for the second processor.

In a further aspect, the first processor may be comprised of processor-executable instructions that enable computing the performance assurance value for the second processor to include computing the value of the budget. In a further aspect, the first processor is configured with processor-executable instructions that may include determining the requirements of tasks scheduled to run on the second processor, wherein determining the steady state workload of the second processor . In a further aspect, the first processor may be comprised of processor-executable instructions for performing operations further comprising generating pulse trains by sampling transitions between busy and idle states.

In a further aspect, a first processor is configured to determine a steady state workload of a second processor, to determine an amount of work required to perform a steady state workload on a second processor, May be configured with processor-executable instructions to be performed by a single thread. In a further aspect, the first processor may be comprised of processor-executable instructions that cause a single thread to be executed on the first processor. In a further aspect, a first processor is configured to determine a steady state workload of a second processor, to determine an amount of work required to perform a steady state workload on a second processor, May be comprised of processor-executable instructions that may include executing a single thread on a second processor to accomplish operations to compute a first thread.

Further aspects include a non-transitory server-readable storage medium storing configured processor-executable instructions, wherein the processor-executable instructions cause the computing device to perform a steady state operation of the second processor Determining the amount of work required to perform the steady state workload determined on the second processor, computing a performance guarantee value for the second processor, computing a performance guarantee value for the second processor from the idle state to the busy state Performing dynamic clock and voltage scaling operations to scale the frequency of the second processor based on the actual workload of the second processor, updating the performance guarantee value based on the scaled frequency, During a period in which the second processor is equal to or greater than the sum of the determined amount of work and the performance guarantee value And increasing the frequency of the second processor when it is determined that the second processor has stayed in the busy state for a period equal to or greater than the sum of the determined amount of work and the performance guarantee value To perform some operations.

In one aspect, the stored processor-executable software instructions cause the processor to increase the frequency of the second processor when it is determined that the second processor has stayed in the busy state for a period of time equal to or greater than the sum of the determined amount of work and the performance- May include increasing the frequency of the second processor to the maximum processor frequency.

In a further aspect, the stored processor-executable software instructions cause the second processor to, when it is determined that the second processor has stayed in the busy state for a period of time equal to or greater than the sum of the determined amount of work and the performance- Increasing the frequency may include increasing the frequency of the second processor in steps and updating the performance guarantee value based on the scaled frequency and updating the performance guarantee value during a period of time equal to or greater than the sum of the determined amount of work and the performance guarantee value Determining whether the second processor has stayed in busy state and repeatedly performing operations to increase the frequency of the second processor when it is determined that the second processor has stayed in busy state for a period of time equal to or greater than the sum of the determined work and performance guarantee values To perform actions that may also include .

In a further aspect, the stored processor-executable software instructions may be configured to cause the processor to perform operations that may include computing a performance guarantee value for the second processor may include computing a deadline value have. In a further aspect, the stored processor-executable software instructions may be configured to cause the processor to perform operations that may include computing a performance value for the second processor may include computing the value of the budget . In a further aspect, the stored processor-executable software instructions cause the processor to determine that determining a steady state workload of the second processor may include determining requirements of tasks scheduled to run on the second processor To perform operations. In a further aspect, the stored processor-executable software instructions may be configured to cause the processor to perform operations, including generating pulse trains by sampling transitions between busy and idle states.

In a further aspect, stored processor-executable software instructions cause the processor to: determine a steady state workload of a second processor; determine an amount of work required to perform a steady state workload on a second processor; Operations that compute the performance assurance value for the second processor may be configured to perform operations to be performed by a single thread. In a further aspect, the stored processor-executable software instructions may be configured to cause the processor to perform operations that cause a single thread to execute on the processor. In a further aspect, the stored processor-executable software instructions may be configured to cause the processor to perform operations that cause a single thread to execute on the second processor.

Various aspects may be implemented in laptops and other mobile devices that provide a number of benefits and are performance, power consumption, and / or responsiveness. Various aspects may be implemented in servers and personal computers to reduce energy and cooling costs for low load machines. Reducing the heat output causes the system cooling fans to be lowered or turned off, thereby lowering noise levels and further reducing power consumption. Various aspects may also be used to degrade heat in poorly cooled systems when the temperature reaches a certain threshold.

While various aspects are described above for exemplary purposes in terms of processing cores, the methods, systems, and executable instructions of the embodiments may be implemented in any system in which methods enable the recognition and control of frequency or voltage have. In addition, operations to scale the frequency or voltage may be performed on any single or multiprocessor system.

Various aspects may be implemented in a variety of portable or mobile computing devices, an example of which is illustrated in Fig. The portable computing device 1400 may include a memory 1402 and a processing core 1401 coupled to the transceiver 1405. The transceiver 1405 may be coupled to an antenna 1404 for transmitting and receiving electromagnetic radiation. The portable computing device 1400 may also include a display 1403 (e.g., a touch screen display), and menu selection buttons or rocker switches 1406 for accepting user inputs . In some portable computing devices, multiple processors 1401 may be provided, such as one processor dedicated to running other applications and one processor dedicated to wireless communication functions.

Various aspects may also be implemented on any of a variety of commercially available server devices, such as the server 1500 illustrated in FIG. Such a server 1500 typically includes a processing core 1501 and may include multiple processor systems 1511, 1521, and 1531, one or more of which may be multi-core processors or may include multi-core processors. The processing core 1501 may be coupled to volatile memory 1502 and a mass non-volatile memory, such as a disk drive 1503. The server 1500 may also include a floppy disc drive, a compact disc (CD) or a DVD disc drive 1506 coupled to the processing core 1501. The server 1500 also includes network access ports 1504 coupled to the processing core 1501 to establish data connections with the network 1505, such as a local area network coupled to other broadcast system computers and servers. .

The aspects described above may also be implemented within a variety of personal computer devices, such as the laptop computer 1600 illustrated in FIG. The laptop computer 1600 may include a processing core 1601 coupled to a volatile memory 1602 and a mass storage nonvolatile memory such as a disk drive 1604 of flash memory. The computer 1600 may also include a floppy disc drive 1606 and a compact disc (CD) drive 1608 coupled to the processing core 1601. The computer device 1600 may also be connected to external memory devices such as USB, FireWire®, or Lightning® connector sockets, or other network connection circuitry for coupling the processing core 1601 to a network or computer And may include a plurality of connector ports coupled to the processing core 1601 to accommodate the processing cores. In a notebook configuration, the computer housing includes a touch pad 1616, a keyboard 1618, and a display 1620 all coupled to the processing core 1601. Other configurations of computing devices may include a computer mouse or trackball coupled to the processor as is well known (e.g., via a USB input).

The processing cores 1401, 1501, and 1601 may be implemented as any programmable processor, processor, and / or code that may be configured by software instructions (applications) to perform various functions, including the functions and operations of the various aspects described herein. A microprocessor, a microprocessor, a multi-core processor, or a multi-processor chip. Typically, software applications may be stored in internal memory 1402, 1502, 1602 before they are accessed and loaded into processing cores 1401, 1501, 1601. Each processing core 1401, 1501, 1601 may include sufficient internal memory to store application software instructions. In some computing devices, additional memory chips (e.g., Secure Data (SD) cards) may be plugged into the computing device and coupled to the processing cores 1401, 1501, 1601 . Internal memories 1402, 1502 and 1602 may be volatile or non-volatile memories such as flash memory, or a mixture of both. For purposes of this description, a general reference to memory includes processing cores 1401, 1501, 1601, including internal memory 1402, detachable memory plugged into a mobile device, and memory in processing core 1401. [ ≪ / RTI >

The processing cores 1501, 1601, and 1710 may include sufficient internal memory to store application software instructions. In many devices, the internal memory may be a volatile or nonvolatile memory such as a flash memory, or a mixture of both. For purposes of this description, a generic reference to a memory may include a processor 1501, 1601, 1710, or 1710, including memory within the processing core 1501, 1601, 1710 itself, and a removable memory plugged into the internal memory, Quot;). ≪ / RTI >

The above method descriptions and process flow diagrams are provided by way of illustrative examples only, and are not intended to imply or imply that the steps of the various aspects should be performed in the order presented. As will be appreciated by those skilled in the art, the order of the steps in the above aspects may be performed in any order. The words "after "," next ", "next" and the like are not intended to limit the order of the steps; These words are simply used to guide the reader through a description of methods. In addition, any reference to a claim element, for example, that uses the articles "a", "an", or "the" is not to be construed as limiting the element in a singular manner.

The various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the aspects disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. In order to clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

The hardware utilized to implement the various illustrative logic, logical blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC) Field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a multiprocessor, but, in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a DSP and a multiprocessor, a plurality of multiprocessors, one or more multiprocessors in conjunction with a DSP core, or any other such combination of configurations. Alternatively, some of the steps or methods may be performed by circuitry specific to a given function.

In one or more of the exemplary aspects, the functions described may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, the functions may be stored as one or more processor-executable instructions or code on a non-temporary computer-readable storage medium. The steps of a method or algorithm disclosed herein may be embodied in a processor-executable software module that may reside on a tangible or non-temporary computer-readable storage medium. Non-temporary computer-readable storage media may be any available storage media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can be embodied as computer readable code in the form of RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage, or other magnetic storage devices, And may include any other medium that may be used to carry or store the program code and which may be accessed by a computer. As used herein, discs and discs may be referred to as compact discs (CD), laser discs, optical discs, digital versatile discs (DVDs) Includes a floppy disk and a blu-ray disc, where disks typically reproduce data magnetically, while discs optically reproduce data with lasers do. Combinations of the above may also be included within the scope of non-temporary computer-readable media. Additionally, the operations of a method or algorithm may be embodied in one or any combination of codes and / or instructions on a non-transitory machine-readable medium and / or non-transitory computer-readable medium, May also reside as a set.

The preceding description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects without departing from the spirit or scope of the invention. Accordingly, the invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles of the following claims and the principles and novel features disclosed herein.

Claims (40)

CLAIMS 1. A method for improving performance on a computing device having a processor,
Determining a steady state workload of the processor;
Determining an amount of work required to perform the steady state workload determined on the processor;
Computing a performance guarantee value for the processor;
Transitioning the processor from an idle state to a busy state;
Performing dynamic clock and voltage scaling operations to scale the frequency of the processor based on an actual workload of the processor;
Updating the performance guarantee value based on the scaled frequency;
Determining whether the processor has stayed in the busy state for a period of time equal to or greater than the sum of the amount of the determined work and the performance guarantee value; And
Increasing the frequency of the processor when it is determined that the processor has stayed in the busy state for a period of time equal to or greater than the amount of the determined work and the performance guarantee value . The method according to claim 1,
Increasing the frequency of the processor when it is determined that the processor has stayed in the busy state for a period of time equal to or greater than the determined amount of the task and the performance guarantee value,
And increasing the frequency of the processor to a maximum processor frequency. The method according to claim 1,
Increasing the frequency of the processor when it is determined that the processor has stayed in the busy state for a period of time equal to or greater than the sum of the determined performance and the workload, ≪ / RTI >
The method comprises:
Updating the performance guarantee value based on the scaled frequency;
Determining whether the processor has stayed in the busy state for a period equal to or greater than the sum of the amount of the determined work and the performance guarantee value; And
Increasing the frequency of the processor when it is determined that the processor has stayed in the busy state for a period of time equal to or greater than the sum of the amount of the determined work and the performance guarantee value
≪ / RTI > further comprising the step of repeatedly performing operations of the computing device. The method according to claim 1,
Wherein computing the performance guarantee value for the processor comprises computing a deadline value. The method according to claim 1,
Wherein computing the performance guarantee value for the processor comprises computing a budget value. The method according to claim 1,
Wherein determining a steady state workload of the processor comprises determining requirements of tasks scheduled to run on the processor. The method according to claim 1,
And generating pulse trains by sampling transitions between the busy and idle states. ≪ Desc / Clms Page number 22 > The method according to claim 1,
Determining a steady state workload of the processor, determining an amount of work required to perform a steady state workload on the processor, and computing the performance guarantee value for the processor are performed by a single thread ≪ / RTI > A method for improving performance on a computing device. 9. The method of claim 8,
Wherein the single thread is executing on the processor. 9. The method of claim 8,
Wherein the single thread is executing on a second processor of the computing device. As a computing device,
A processor;
Means for determining a steady state workload of the processor;
Means for determining an amount of work required to perform the steady state workload determined on the processor;
Means for computing a performance guarantee value for the processor;
Means for transitioning the processor from an idle state to a busy state;
Means for performing dynamic clock and voltage scaling operations to scale the frequency of the processor based on an actual workload of the processor;
Means for updating the performance guarantee value based on the scaled frequency;
Means for determining whether the processor has stayed in the busy state for a period of time equal to or greater than a sum of the amount of the determined work and the performance guarantee value; And
And means for increasing the frequency of the processor when it is determined that the processor has stayed in the busy state for a period of time equal to or greater than the sum of the amount of the determined work and the performance guarantee value. 12. The method of claim 11,
The means for increasing the frequency of the processor when it is determined that the processor has stayed in the busy state for a period of time equal to or greater than the sum of the amount of the determined work and the performance guarantee value,
And means for increasing said frequency of said processor to a maximum processor frequency. 12. The method of claim 11,
Wherein the means for increasing the frequency of the processor when it is determined that the processor has stayed in the busy state for a period of time equal to or greater than the sum of the determined performance and the performance assurance value comprises incrementing the frequency of the processor by steps And means for,
The computing device includes:
Updating the performance guarantee value based on the scaled frequency;
Determining whether the processor has stayed in the busy state for a period equal to or greater than the sum of the amount of the determined work and the performance guarantee value; And
Increasing the frequency of the processor when it is determined that the processor has stayed in the busy state for a period of time equal to or greater than the sum of the amount of the determined work and the performance guarantee value
Further comprising means for iteratively performing operations of the computing device. 12. The method of claim 11,
Wherein the means for computing a performance guarantee value for the processor comprises means for computing a deadline value. 12. The method of claim 11,
Wherein the means for computing a performance guarantee value for the processor comprises means for computing a budget value. 12. The method of claim 11,
Wherein the means for determining a steady state workload of the processor comprises means for determining requirements of tasks scheduled to run on the processor. 12. The method of claim 11,
And means for generating pulse trains by sampling transitions between said busy and idle states. 12. The method of claim 11,
Determining a steady state workload of the processor, determining an amount of work required to perform a steady state workload on the processor, and computing the performance guarantee value for the processor over a single thread Further comprising means for establishing a connection to the computing device. 19. The method of claim 18,
And means for executing the single thread on the processor. 19. The method of claim 18,
Further comprising means for executing the single thread on a second processor of the computing device. As a computing device,
A first processor,
Wherein the first processor comprises:
Determining a steady state workload of the second processor;
Determining an amount of work required to perform the steady state workload determined on the second processor;
Computing a performance guarantee value for the second processor;
Transitioning the second processor from an idle state to a busy state;
Performing dynamic clock and voltage scaling operations to scale the frequency of the second processor based on an actual workload of the second processor;
Updating the performance guarantee value based on the scaled frequency;
Determining whether the second processor has stayed in the busy state for a period of time equal to or greater than the sum of the amount of the determined work and the performance guarantee value; And
Increasing the frequency of the second processor when it is determined that the second processor has stayed in the busy state for a period of time equal to or greater than the amount of the determined work and the performance guarantee value
Comprising processor-executable instructions for performing the operations comprising. 22. The method of claim 21,
Increasing the frequency of the second processor when it is determined that the second processor has stayed in the busy state for a period of time equal to or greater than the sum of the amount of the determined work and the performance guarantee value,
And increasing the frequency of the second processor to a maximum processor frequency. 22. The method of claim 21,
Wherein the first processor is configured to increase the frequency of the second processor when it is determined that the second processor has stayed in the busy state for a period equal to or greater than the sum of the determined performance and the performance guarantee value, Comprising increasing the frequency of the two processors to steps, wherein the processor-executable instructions comprise:
The first processor may further include:
Updating the performance guarantee value based on the scaled frequency;
Determining whether the second processor has stayed in the busy state for a period of time equal to or greater than the sum of the amount of the determined work and the performance guarantee value; And
Increasing the frequency of the second processor when it is determined that the second processor has stayed in the busy state for a period of time equal to or greater than the amount of the determined work and the performance guarantee value
And processor-executable instructions for iteratively performing operations of the computing device. 22. The method of claim 21,
Wherein the first processor is configured with processor-executable instructions to compute a performance guarantee value for the second processor includes computing a deadline value. 22. The method of claim 21,
Wherein the first processor is configured with processor-executable instructions to include computing a performance value for the second processor to compute a budget value. 22. The method of claim 21,
Wherein the first processor is configured with processor-executable instructions to include determining requirements of tasks scheduled to run on the second processor to determine a steady state workload of the second processor. 22. The method of claim 21,
Wherein the first processor comprises:
And generating pulse trains by sampling transitions between said busy and idle states. ≪ Desc / Clms Page number 19 > 22. The method of claim 21,
Wherein the first processor is further configured to: determine a steady state workload of the second processor; determine an amount of work required to perform a steady state workload on the second processor; Wherein the operations of computing the guaranteed value are performed by a single thread. 29. The method of claim 28,
Wherein the first processor is configured with processor-executable instructions that cause the single thread to execute on the first processor. 29. The method of claim 28,
Wherein the first processor is further configured to: determine a steady state workload of the second processor; determine an amount of work required to perform a steady state workload on the second processor; Wherein computing the guaranteed value comprises executing the single thread on the second processor. 18. A non-transient computer readable storage medium having stored thereon processor-executable software instructions,
The processor-executable software instructions cause the processor to:
Determining a steady state workload of the second processor;
Determining an amount of work required to perform the steady state workload determined on the second processor;
Computing a performance guarantee value for the second processor;
Transitioning the second processor from an idle state to a busy state;
Performing dynamic clock and voltage scaling operations to scale the frequency of the second processor based on an actual workload of the second processor;
Updating the performance guarantee value based on the scaled frequency;
Determining whether the second processor has stayed in the busy state for a period of time equal to or greater than the sum of the amount of the determined work and the performance guarantee value; And
And to increase the frequency of the second processor when it is determined that the second processor has stayed in the busy state for a period of time equal to or greater than the amount of the determined work and the performance guarantee value , Non-transitory computer readable storage medium. 32. The method of claim 31,
Wherein the stored processor-executable software instructions cause the processor to: when it is determined that the second processor has stayed in the busy state for a period of time equal to or greater than the determined amount of the job and the performance guarantee value, Increasing the frequency,
And increasing the frequency of the second processor to a maximum processor frequency. ≪ RTI ID = 0.0 > A < / RTI > 32. The method of claim 31,
Wherein the stored processor-executable software instructions cause the processor to: when it is determined that the second processor has stayed in the busy state for a period of time equal to or greater than the determined amount of the job and the performance guarantee value, Increasing the frequency,
Increasing the frequency of the second processor to steps, and
As repeatedly performing the operations,
Updating the performance guarantee value based on the scaled frequency;
Determining whether the second processor has stayed in the busy state for a period of time equal to or greater than the sum of the amount of the determined work and the performance guarantee value; And
Increasing the frequency of the second processor when it is determined that the second processor has stayed in the busy state for a period of time equal to or greater than the amount of the determined work and the performance guarantee value
And performing the operations of step < RTI ID = 0.0 > of: < / RTI > 32. The method of claim 31,
The stored processor-executable software instructions are instructions for causing a processor to perform operations that include computing a deadline value by computing a performance guarantee value for the second processor, Storage medium. 32. The method of claim 31,
Wherein the stored processor-executable software instructions are configured to cause the processor to perform operations to include computing a performance value for the second processor to compute a budget value. media. 32. The method of claim 31,
Wherein the stored processor-executable software instructions cause the processor to: determine the steady-state workload of the second processor to perform operations that include determining requirements of tasks scheduled to run on the second processor Lt; RTI ID = 0.0 > computer-readable < / RTI > 32. The method of claim 31,
The stored processor-executable software instructions cause the processor to:
And generating pulses by sampling transitions between the busy and idle states. ≪ Desc / Clms Page number 24 > 32. The method of claim 31,
Wherein the stored processor-executable software instructions cause the processor to: determine a steady state workload of the second processor; determine an amount of work required to perform a steady state workload on the second processor; And computing the performance guarantee value for the second processor to be performed by a single thread. ≪ Desc / Clms Page number 19 > 39. The method of claim 38,
Wherein the stored processor-executable software instructions are configured to cause the processor to perform operations that cause the single thread to execute on the processor. 39. The method of claim 38,
Wherein the stored processor-executable software instructions are configured to cause the processor to perform operations that cause the single thread to execute on the second processor.

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