CN104756043B

CN104756043B - For controlling the system and method for central processing unit power with the guaranteed transient state deadline date

Info

Publication number: CN104756043B
Application number: CN201380057181.5A
Authority: CN
Inventors: S·S·汤姆森; B·雷赫利克; A·伊兰里; S·苏尔; N·S·加尔加什
Original assignee: Qualcomm Inc
Current assignee: Qualcomm Inc
Priority date: 2012-11-05
Filing date: 2013-09-25
Publication date: 2016-06-08
Anticipated expiration: 2033-09-25
Also published as: EP2915020A1; JP2016505913A; JP5930504B2; KR101578336B1; CN104756043A; WO2014070338A1; KR20150083883A

Abstract

One includes dynamic clock and the method for voltage-regulation (DCVS) solution, system and equipment, it is configured to calculate and enforce performance guarantee, to guarantee that processor will not at busy state (such as, due to transient working load) keep time more than predetermined time quantum, between at this moment, in section, this predetermined time amount is the time that this processor completes required for its precalculated steady state operation load. This DCVS can adjust frequency and/or the voltage of processor based on variable delay, and to guarantee operating frequency or the voltage of no matter processor, this process kernel only falls behind the maximum predefined maximal workload of its steady state operation load.

Description

For controlling the system and method for central processing unit power with the guaranteed transient state deadline date

Related application

Present patent application was submitted on November 11st, 2010, name is called the U.S. Patent application No.12/944 of " SystemandMethodforControllingCentralProcessingUnitPowerw ithGuaranteedTransientDeadlines ", the further part of 467, this application requires within 6th, to submit in December in 2009, name is called the U.S. Provisional Application No.61/286 of " SystemandMethodofDynamicallyControllingPowerinaCentralPr ocessingUnit ", the benefit of priority of 991, the two application is all incorporated hereby the application.

Cross-referenced applications

The application about and merge Rychlik et al. name submitted to way of reference and be called the U.S. Patent application No.12/944,140 of " SystemAndMethodForControllingCentralProcessingUnitPowerB asedOnInferredWorkloadParallelism "; The name that Richlik et al. submits to is called the U.S. Patent application No.12/944,202 of " SystemandMethodforControllingCentralProcessingUnitPoweri naVirtualizedSystem "; The name that Richlik et al. submits to is called the U.S. Patent application No.12/944,321 of " SystemandMethodforAsynchronouslyandIndependentlyControll ingCoreClocksinaMulticoreCentralProcessingUnit "; The name that Thomson et al. submits to is called the U.S. Patent application No.12/944,378 of " SystemandMethodforControllingCentralProcessingUnitPowerw ithReducedFrequencyOscillations "; The name that Thomson et al. submits to is called the U.S. Patent application No.12/944,561 of " SystemandMethodforControllingCentralProcessingUnitPowerW ithGuaranteedSteadyStateDeadlines "; And the name submitted to of Sur et al. is called the U.S. Patent application No.12/944,564 of " SystemandMethodforDynamicallyControllingaPluralityofCore sinaMulticoreCentralProcessingUnitbasedonTemperature ".

Background technology

Portable computing device (PCD) is found everywhere. These equipment can include cellular phone, portable digital-assistant (PDA), portable game console, palmtop computer and other portable electric appts. Except the major function of these equipment, many equipment include peripheral function. For example, cellular phone can include the major function carrying out honeycomb telephone call and the peripheral function of still camera, video camera, global positioning system (GPS) navigation, network browsing, transmission and reception Email, transmission and reception text message, PoC ability etc. Along with the functional increase of this kind equipment, support that this type of functional required calculating or disposal ability also increase. Additionally, along with computing capability increases, with greater need for effectively managing the processor or multiple processor that provide computing capability.

It is therefore desirable to the method for the improvement of power in control multi-core CPU.

Accompanying drawing explanation

It is merged into herein and constitutes the accompanying drawing of a part of this specification, it is shown that the illustrative aspects of the present invention, and be used for explaining inventive feature together with general introduction given above and detailed description given below.

Fig. 1 is in the front plan view of the first aspect of the portable computing device (PCD) of make position;

Fig. 2 is in the front plan view of the first aspect of the PCD of open position;

Fig. 3 is the block diagram of the second aspect of PCD;

Fig. 4 is the block diagram of process system;

Fig. 5 is the flow chart illustrating dynamically to control the first aspect of the method for the power in CPU;

Fig. 6 is the flow chart illustrating dynamically to control the Part I of the second aspect of the method for the power in CPU;

Fig. 7 is the flow chart illustrating dynamically to control the Part II of the second aspect of the method for the power of multi-core CPU;

Fig. 8 is the example chart illustrating the cpu frequency controlled by dynamic clock and voltage-regulation (DCVS) drawn over time; And

Fig. 9 is the example chart of the effective transient response time illustrating various performance level.

Figure 10 is the block diagram that logical block and the flow of information realizing enforcing in the computing equipment of dynamic clock frequency/voltage adjustment (DCVS) solution of performance guarantee according to various aspects is described.

Figure 11 A-B illustrates the process flow graph for the generation one side method that can guarantee that.

Figure 12-13 illustrates to enforce performance guarantee, the process flow graph of various aspects method of time more than predetermined time amount will not be kept at busy state guaranteeing to process kernel, wherein at this moment between in section this predetermined time amount be that this process kernel completes that it is precalculated, estimates and/or time required for the steady state operation load of reality.

Figure 14 is the process flow graph that another aspect method for enforcing performance guarantee is described.

Figure 15 applies to the component block diagram of the mobile equipment used in an aspect.

Figure 16 applies to the component block diagram of the server apparatus used in an aspect.

Figure 17 applies to the component block diagram of the laptop computer device used in an aspect.

Detailed description of the invention

With reference to the accompanying drawings to describe various aspects in detail. Whenever possible, identical reference numerals will be used for referring to same or analogous part in running through accompanying drawing. It is for explanatory purposes for quoting of carrying out of particular example and implementation, and is not intended to limit the present invention or scope of the claims.

Word " exemplary " is used herein to mean that " as an example, example or explanation ". Any aspect being described herein as " exemplary " is not necessarily to be construed as more preferred or favourable than other side.

In the description herein, term " application " can also include the file with executable content, for instance: object identification code, script, syllabified code, making language document and patch. It addition, involved herein " application " can also include substantially not executable file, for instance other data file that the document being likely to need to be opened or needs are accessed.

Term " content " can also include the file with executable content, for instance: object identification code, script, syllabified code, making language document and patch. It addition, involved herein " content " can also include substantially not executable file, for instance other data file that the document being likely to need to be opened or needs are accessed.

Being used in so describing, term " assembly ", " data base ", " module ", " system " etc. are intended to mean the entity that computer is relevant, hardware, firmware, the combination of hardware and software, software or executory software. For example, assembly can be that (but not limited to) runs process on a processor, processor, object, executable file, the thread of execution, program and/or computer. By way of illustration, run application on the computing device and computing equipment can both be assembly. One or more assemblies may reside in the thread of process and/or execution, and assembly may be located on a computer and/or is distributed between two or more computers. It addition, the various computer-readable mediums that these assemblies can store various data structure from it perform. Assembly such as can communicate (such as, from the data of the assembly interacting with local system, distributed system and/or another assembly in crossing over the network of such as the Internet, being interacted by the mode of signal and other system) by locally and/or remotely process according to having one or more packet.

Referring initially to Fig. 1 and Fig. 2, it illustrates illustrative portable computing equipment (PCD) and is generally designated as 100. As it can be seen, PCD100 can include shell 102. Shell 102 can include top housing section 104 and lower housing section 106. Fig. 1 illustrates that top housing section 104 can include display 108. In particular aspects, display 108 can be touch-screen display. Top housing section 104 can also include tracking ball input equipment 110. Additionally, as shown in fig. 1, top housing section 104 can include power supply opening button 112 and cut-off button 114. As shown in fig. 1, the top housing section 104 of PCD100 can include multiple indicator lamp 116 and speaker 118. Each indicator lamp 116 can be light emitting diode (LED).

In particular aspects, as depicted in fig. 2, top housing section 104 is moveable relative to lower housing section 106. Specifically, top housing section 104 can be relative to lower housing section 106 slidably. As shown in Figure 2, lower housing section 106 can include many button keyboards 120. In particular aspects, many button keyboards 120 can be standard QWERTY key. When top housing section 104 moves relative to lower housing section 106, it is possible to represent many button keyboards 120.Fig. 2 further illustrates the PCD100 reset button 122 that can include on lower housing section 106.

Referring to Fig. 3, it illustrates the exemplary nonrestrictive aspect of portable computing device (PCD) and be generally designated as 320. As it can be seen, PCD320 includes SOC(system on a chip) 322, this SOC(system on a chip) 322 includes multi-core CPU 324. Multi-core CPU 324 can include the 0th kernel the 325, first kernel 326 and N kernel 327.

As shown in Figure 3, display controller 328 and touch screen controller 330 are coupled to multi-core CPU 324. Display/touch screen 332 outside SOC(system on a chip) 322 is in turn coupled to display controller 328 and touch screen controller 330.

Fig. 3 indicates video encoder 334 (such as further, line-by-line inversion (PAL) encoder, Sequential Couleur and storage (SECAM) encoder, or National Television System committee (NTSC) encoder) it is coupled to multi-core CPU 324. Additionally, video amplifier 336 is coupled to video encoder 334 and display/touch screen 332. And, video port 338 is coupled to video amplifier 336. As depicted in figure 3, USB (universal serial bus) (USB) controller 340 is coupled to multi-core CPU 324. And, USB port 342 is coupled to USB controller 340. Memorizer 344 and subscriber identity module (SIM) block 346 and can also be coupled to multi-core CPU 324. Additionally, as shown in Figure 3, digital camera 348 is alternatively coupled to multi-core CPU 324. In illustrative aspects, digital camera 348 is charge (CCD) photographing unit or complementary metal oxide semiconductors (CMOS) (CMOS) photographing unit.

Illustrating further in Fig. 3, stereo audio CODEC350 is alternatively coupled to multi-core CPU 324. It addition, audio frequency amplifier 352 is alternatively coupled to stereo audio CODEC350. In illustrative aspects, the first boombox 354 and the second boombox 356 are coupled to audio frequency amplifier 352. Fig. 3 illustrates that amplifier of microphone 358 can also be coupled to stereo audio CODEC350. It addition, mike 360 is alternatively coupled to amplifier of microphone 358. In particular aspects, frequency modulation (FM) radio tuner 362 is alternatively coupled to stereo audio CODEC350. And, FM antenna 364 is coupled to FM radio tuner 362. Additionally, stereo headset 366 is alternatively coupled to stereo audio CODEC350.

Fig. 3 indicates radio frequency (RF) transceiver 368 to be alternatively coupled to multi-core CPU 324 further. RF switch 370 is alternatively coupled to RF transceiver 368 and RF antenna 372. As shown in Figure 3, keypad 374 is alternatively coupled to multi-core CPU 324. And, the mono headset 376 with mike is alternatively coupled to multi-core CPU 324. Additionally, vibrator equipment 378 is alternatively coupled to multi-core CPU 324. Fig. 3 also illustrates that power supply 380 is alternatively coupled to SOC(system on a chip) 322. In particular aspects, power supply 380 is direct current (DC) power supply of the various assemblies supplying power to PCD320, needing power. Additionally, in particular aspects, power supply is rechargeable DC battery or D/C power, wherein this D/C power obtains from the exchange (AC) being connected to AC power supplies to DC transformator.

Fig. 3 indicates PCD320 can also include network interface card 388 further, and this network interface card 388 can be used for accessing data network, for instance LAN, individual territory net or other network any. Network interface card 388 can be bluetooth network interface card, WiFi network interface card, individual territory net (PAN) card, individual territory net ultra low power technology (PeANUT) network interface card, or other network interface card any well known in the art.Additionally, network interface card 388 can be incorporated in chip, namely network interface card 388 can be the whole solution on chip, and can not be independent network interface card 388.

As depicted in figure 3, display/touch screen 332, video port 338, USB port 342, photographing unit the 348, first boombox the 354, second boombox 356, mike 360, FM antenna 364, stereo headset 366, RF switch 370, RF antenna 372, keypad 374, mono headset 376, vibrator 378 and power supply 380 are in the outside of SOC(system on a chip) 322.

In particular aspects, one or more in method step described herein can be stored in memorizer 344 as computer program instructions. These instructions can be performed by multi-core CPU 324, in order to performs method described herein. Additionally, multi-core CPU 324, memorizer 344 or its combination may serve as the one or more method steps performed in method step described herein, in order to dynamically control the unit of the power of each CPU in multi-core CPU 324 or kernel.

Referring to Fig. 4, it is shown that process system and be generally designated as 500. In particular aspects, process system 500 can be incorporated into above in association with in the PCD320 described by Fig. 3. As it can be seen, processor system 500 can include multinuclear CPU (CPU) 402 and be connected to the memorizer 404 of multi-core CPU 402. Multi-core CPU 402 can include the 0th kernel the 410, first kernel 412 and N kernel 414. 0th kernel 410 can include the zero dy namics clock and voltage-regulation (DCVS) algorithm 416 that perform thereon. First kernel 412 can include the DCVS algorithm 417 performed thereon. Additionally, N kernel 414 can include the NDCVS algorithm 418 performed thereon. In particular aspects, each DCVS algorithm 416,417,418 can perform independently on corresponding kernel 412,414,416.

It addition, as described, memorizer 404 can include the operating system 420 being stored thereon. Operating system 420 can include scheduler 422, and scheduler 422 can include first operation queue the 424, second operation queue 426 and N operation queue 428. Memorizer 404 can also include the first application the 430, second application 432 and the N application 434 being stored thereon.

In particular aspects, one or more tasks 436 can be sent to operating system 420 by application 430,432,434, process with kernel 410,412,414 place in multi-core CPU 402. Task 436 can be processed or perform as individual task, thread or its combination. Additionally, scheduler 422 can scheduler task, thread or its combination for multi-core CPU 402 in execution. It addition, task, thread or its combination can be positioned in operation queue 424,426,428 by scheduler 422. Kernel 410,412,414 can such as (e.g.) being ordered by operating system 420, task, thread or its combination is fetched, for the process to those tasks and thread at kernel 410,412,414 place or execution from operation queue 424,426,428.

Fig. 4 also show the degree of parallelism watch-dog 440 that memorizer 404 can include being stored thereon. Degree of parallelism watch-dog 440 may be coupled to operating system 420 and multi-core CPU 402. Specifically, degree of parallelism watch-dog 440 may be coupled to the scheduler 422 in operating system 420.

Referring to Fig. 5, it illustrates the first aspect of the method for the power dynamically controlling CPU, and be generally designated as 500. Method 500 can start with Do statement (doloop) at square frame 502, wherein when equipment is energized, it is possible to performs following steps.

At square frame 504 place, power controller (such as, dynamic clock and voltage-regulation (DCVS) algorithm) can monitor one or more CPU. At decision-making 506 place, power controller may determine that whether the mapping deadline date for CPU expires. If not expired, then method 500 can terminate. Otherwise, if the mapping deadline date expires, then method 500 may be advanced to square frame 508, and CPU can be moved to higher performance level by power controller, i.e. next higher operation frequency. In an aspect, CPU can be moved to maximum performance level, i.e. maximum cpu frequency by controller. But, in another aspect, CPU can not jump to maximum performance level. CPU can jump to medium level, and again jumps to maximum horizontal or another higher performance level subsequently. Time quantum between quantity and the jump of medium jump is determined for the frequency values jumped.

At square frame 510 place, CPU can enter idle condition. Additionally, at square frame 512 place, the mapping deadline date can be reset. At square frame 514 place, CPU can exit from idle status. Moving to decision-making 516, power controller may determine that whether imminent cpu frequency is in maximum cpu frequency. If it is, method 500 can terminate. Otherwise, if cpu frequency is not at maximum cpu frequency, then method may be advanced to square frame 518, and can reschedule intervalometer. Subsequently, method 500 can terminate.

Referring to Fig. 6, it is shown that dynamically control the second aspect of the method for the power of CPU, and be generally designated as 600. Starting from square frame 602, CPU (CPU) can enter idle condition. At square frame 604 place, power controller (such as, dynamic clock and voltage-regulation (DCVS) algorithm) can be set equal to current time (CurrentTime) by starting free time (StartIdleTime). Additionally, at square frame 606 place, power controller can pass through to deduct beginning free time (StartIdleTime) from end free time (EndIdleTime) and determine the rush hour (BusyTime).

At square frame 608 place, CPU can enter (SWFI) the to be interrupted states such as software. At square frame 610 place, CPU can exit SWFI state. Moving to square frame 612, power controller can be set equal to current time (CurrentTime) by terminating free time (EndIdleTime). Additionally, at square frame 614 place, power controller can pass through to deduct beginning free time (StartIdleTime) from end free time (EndIdleTime) and determine free time (IdleTime). At square frame 616 place, power controller can determine imminent cpu frequency (CPUFreq) according to the steady statue wave filter (UpdateSteadyStateFilter) being updated over, the rush hour (BusyTime) and free time (IdleTime). Thereafter, method 600 can continue to the square frame 702 of Fig. 7.

At square frame 702 place, power controller can use below equation to determine effective transient state budget (EffectiveTransientBudget):

EffectiveTransientBudget=(TransientResponseDeadline^NextCPUFreq)/(NextCPUFreq-CPUFreq)

Wherein,

The TransientResponseDeadline=transient response deadline date, i.e. lax budget,

Next cpu frequency of a NextCPUFreq=frequency step higher than imminent cpu frequency, and

The imminent cpu frequency of CPUFreq=(CPUFreq).

In particular aspects, it is also possible to add clock-time scheduling expense (ClockSchedulingOverhead) and clock handover overhead (ClockSwitchOverhead) to EffectiveTransientBudget. Furthermore, it is possible to voltage is changed expense (VoltageChangeOverhead) add EffectiveTransientBudget to. Moving to square frame 704, power controller can terminate free time (EndIdleTime) plus effective transient state budget (EffectiveTransientBudget) by the deadline date jumping to upper frequency (SetJumpToFrequency) is set equal to. In another aspect, the deadline date to jump can be that current time adds transient state budget. Thereafter, method 600 can terminate.

In particular aspects, may be used for calculating CPU before exhausting the transient state deadline date in conjunction with the method 600 described by Fig. 6 and Fig. 7 and may remain in the time quantum of the frequency determined by DCVS, and be dispatched to the jump of higher cpu frequency in the future with described time quantum. If reentering the free time before jumping to upper frequency, then can cancel scheduled jump. The time quantum that hop delay to upper frequency can be determined by method 600 by EffectiveTransientBudget.

It should be understood that method step described herein need not certain perform with described order. Additionally, such as " thereafter ", " subsequently ", the word such as " next " be not intended to the order of conditioning step. These words are only for guiding the description of readers ' reading method step. It addition, method described herein is described as above to perform at portable computing device (PCD). PCD can be mobile telephone equipment, portable digital-assistant's equipment, smartbook computing equipment, net book computing equipment, lap-top computing devices, desktop computing equipment or its combination.

In particular aspects, DCVS algorithm is a kind of mechanism, and it is measured cpu load/free time, and dynamically adjusts cpu clock frequency to make great efforts to follow the tracks of workload, thus reducing power consumption, still provides gratifying systematic function simultaneously. Along with workload changes, the change of CPU handling capacity can follow the tracks of the change of (but also must retardation) workload. Regrettably, when workload have service quality (QoS) require, this is likely to introducing problem, because DCVS algorithm is likely to not follow the tracks of fast enough workload. It is likely to unsuccessfully additionally, follow the tracks of.

Many DCVS technology relate to the steady statue performance requirement measuring CPU, and are set as cpu frequency and voltage meeting the steady statue CPU floor level used. This completes usually by the following manner: measure the cpu busy percentage (busy percentage ratio) in a period of time; And be the performance level that average CPU utilization falls between high threshold and Low threshold wherein by cpu performance level set. Average period is optimized so that the frequency changing clock frequency minimizes, maintains rational responsiveness simultaneously. Beginning in response to transient working load and/or new workload, it is already possible to utilize emergent (panic) input to heighten cpu frequency rapidly.

In order to avoid DCVS retardation workload the problem causing mission failure, system and method disclosed herein provides mapping and ensures. Can ensure to be defined to by mapping, compared with running with under higher level of performance, it is possible to postpone continuously the maximum amount of busy pulse. This can be accomplished by: arrived higher performance level before the mapping deadline date expires; And just will reset the deadline date whenever becoming the free time, because if CPU is idle, then according to definition, it is not at overbooking state.As shown in this article, whenever system leave free time and system CPU not with peak frequency to run time, it is possible to reschedule intervalometer to retain QoS guarantee.

In order to make the power impact that mapping ensures minimize, system and method makes the pulse of input be likely to need frequency to increase to meet the minimizing possibility of deadline date. This can be accomplished by: postpones frequency (namely, performance level) change, until having exhausted effective transient state budget, and jump directly to higher performance level subsequently and rest on there, until pulse completes, as shown in Figure 8.

In particular aspects, effective transient state budget is calculated as the transient response deadline date being adjusted to current performance level. For example, if CPU runs the maximum clock speed of 75%, and the transient response deadline date is 16ms, then effectively transient state budget is 64ms, i.e. 16ms/ (1-0.75). Effective transient state budget represents how long CPU can run under current performance level before exhausting budget. If CPU is idle, then effectively transient state budget can be identical with the transient response deadline date. If being in maximum performance level, then effectively transient state is pre-unlimited at last, as shown in Figure 9.

Use method described herein, the maximum amount that task can be run by system under certain level except maximum horizontal provides strict boundary, and therefore to need QoS guarantee task complete computable boundary is impliedly provided, still allow for simultaneously dynamic cpu clock regulate. Can be currently running based on which task, global system characteristic, DCVS algorithm design or other characteristic sets described boundary, if and system not do not running any task with qos requirement or if CPU just runs under maximum clock, then can disable described boundary completely.

In particular aspects, this method can be extended in the following manner: replaces jumping to peak frequency when the deadline date has expired, set shorter inside effective deadline date and jump to one or more intermediate frequency, still ensuring that CPU is in peak frequency before exhausting maximum QoS delay simultaneously. Additionally, this method can guarantee the transient state QoS maintaining good restriction fully, and reduce total cpu power simultaneously.

System and method described herein can be improved the occasion sampling (opportunisticsampling). In other words, described system and method can check timer expiration on a periodic basis. In other side, described system and method can not utilize sampling by chance.

As discussed above, various aspects provide the strict and computable boundary (such as, performance guarantee) that task is completed. in all fields, such performance guarantee can realize as a part for dynamic clock and voltage/frequency adjustment (DCVS) solution, to improve processor performance on portable computing device (PCD) and/or to reduce power overhead, this PCD includes the mobile equipment of such as the following: cell phone, smart mobile phone, individual or mobile multimedia player, personal digital assistant (PDA's), laptop computer, tablet PC, smartbook, super, palmtop computer, push mail receiver, there is the cell phone of multimedia internet function, wireless game controller and similar personal electronic equipments, like such, personal electronic equipments includes memorizer, programmable processor or kernel (referred to herein, generally, as " process kernel "), and work under battery supply, so that power saving method is helpful.In addition, when various aspects have the used time particularly with portable and movement the computing equipment run on battery power, these aspects are generally including any computing equipment of processor (such as, general purpose computer, desktop computer, server etc.) in be all useful, and the power consumption reduced to its benefit.

In general, the dynamic power (power switched) of chip waste is C*V²* f, wherein, C is the electric capacity of exchange of each clock cycle, and V is voltage, and f is switching frequency. Therefore, along with frequency changes, dynamic power is by linear change therewith. What processor chips to be consumed by dynamic power is responsible for close to 2/3rds of general power. Voltage-regulation can regulate in conjunction with frequency and complete together, because the frequency that chip runs can about its running voltage. The efficiency of some electricity parts (such as manostat) raises such as temperature and reduces, thus power consumption increases along with temperature. Power owing to increasing uses and is likely to raise temperature, and therefore the increase of voltage or frequency is likely to even more increase system power requirement. Therefore, it can to reduce, by or light hours idle at it, the frequency being applied to its processor and/or voltage increases the battery life of computing equipment. The reduction of such frequency and/or voltage can in real time or regulate (DCVS) solution via dynamic clock and voltage/frequency and come " online " and complete.

In general, DCVS solution monitoring processor is in the time scale (being in the busy time compared to it) of free time, and is in idle and/or busy time scale based on processor and determines the frequency/voltage of processor should be adjusted how many. Monitoring processor is in the time scale of free time and can include calculating and/or measure for indicating this processor execution idle process or thread (such as, system idle process etc.) the value (such as, quantity of time quantum, cpu cycle etc.) of persistent period.

Operating system can determine processor does not have other thread be ready to be scheduled time, perform idle software application, process or thread (being referred to as " thread " in the application) on the processor. This idle thread can perform various task (such as, wait interrupt task, dormancy task etc.), and each task can include the operation of multiple processor. When processor performs idle thread, this processor can be referred to as " free time " that be in " idle condition " and/or be in " idle condition ".

In a multi-processor system, operating system (or scheduler, controller etc.) can be that each processor keeps one or more idle threads. Idle thread maintaineds ready for performing, thus each processor always has the thread being ready to perform. By this way, no matter when thread concedes processor (such as, owing to this thread completes task or the workload of its scheduling), this operating system have be ready on the processor perform thread (such as, availability via idle thread), even if when other threads all complete, waiting resource or otherwise currently without when being ready to perform.

As discussed above, DCVS solution can adjust (it can include steady state operation load) frequency and/or the voltage of processor based on the workload of processor. Steady state operation load can upon execution between before determine, namely process kernel enter busy or active state with performs promotion workload operation before. This steady state operation load can be determined in advance by the time quantum calculating, estimating or the prediction quantity in cpu clock cycle, the quantity of operation, the quantity of instruction and/or the required by task that completes to be scheduled on this process kernel are wanted.Each processor can have more than one workload (such as, steady state operation load and transient working load), and each processor can be required to be maintained at busy, run or active state (being referred to as " busy state " in the application) is until all tasks in its all working load complete.

In some scene, DCVS solution can reduce frequency and/or the voltage (that is, the speed of processor) of processor, saves with the power realized when not affecting the performance of processor. Such as, when the workload of processor include the execution time accounted for leading task by memory access time time, will not there be significant impact the execution time of processor performance or this task by the reduction of frequency. But, more conventional, DCVS solution must between the performance (time required for such as, completing Given task set etc.) of processor and power consumption (such as, completing the battery electric quantity that Given task set consumes) characteristic equilibrium compromise. Generally, task completes more fast, and the power that processor consumes when completing those tasks is more many.

DCVS solution can be configured to the steady state operation load based on processor and steady statue performance requirement, is balanced between performance and power consumption. This steady statue performance requirement can be determined: calculate or measure for indicating processor to be in the value of busy and/or idle persistent period (such as by following operation, time quantum, quantity of cpu cycle etc.), computed/the result of value measured is averaged, and determined required for the steady state operation load of this processor time/amount of process. Calculate based on these, DCVS solution can calculating upper limit frequency threshold and lower frequency limit threshold value, may be operative to meet calculated steady statue requirement at such scope inner treater, simultaneously realize reduce power and acceptable responsiveness level (such as, mobile device user is made to will not notice that difference, etc.).

Generally, processor is required to process/perform transient working load, that a priori do not notified and that do not account in steady statue or frequency threshold calculate " work burst " including DCVS solution. Transient working load can be the prior ignorant any task of system or working cell, including any working cell on the unexpected peak (spike) in workload that is dynamic, interim or that cause processor. For example, transient working load can include in response to user's input, system event, the environmental aspect detected, remote procedure call etc., processor any or all task performed. For another example, transient working load can be generate when user touches the touch screen of portable computing device (PCD) to initiate user action, PCD must respond thereto (such as, update with interface, pass through the new picture of display, start new element etc.) immediately.

As mentioned above, transient working load is not (such as, as the part determining upper limit threshold and lower threshold) continuous print steady state operation load that DCVS solution can shift to an earlier date with due regard to. Therefore, transient working load is likely to so that processor keeps longer than expected at busy state, and/or otherwise causes processor to perform the uncertainty of time. Such uncertainty is likely to so that computing equipment inefficiently or inadequately allocation process and system resource, and is likely to the overall performance on computing equipment and/or responsiveness has appreciable impact, when including multiple process kernel particularly in computing equipment.

Modern computing devices is usually multicomputer system, and it includes SOC(system on a chip) (SoC) and/or multiprocessing kernel (such as, processor, kernel etc.). In a multi-processor system, single-threaded by the first process kernel processes, then by the second process kernel processes, it is very common for then being processed kernel processes by first again. It is also very common that first result processing a thread in kernel triggers in the second operation processed in another thread performed in kernel. Such as, one or more process kernels may rely on the result that the processor of current active generates, and is likely to be required to be maintained at free time or waiting state, until current active processor completes its workload and/or completes to process one or more task. In such cases, each process kernel can when it waits from the result of current active processor, alternatively enter free time/waiting state. When these process the result that kernel waits the generation of current active processor, the DCVS solution of each of which can reduce their operating rate (that is, via the reduction of frequency/voltage) so that computing equipment seems slow without response or speed. That is, the DCVS solution realized on multiprocessor computing equipment is likely to infer improperly: processing some the process kernels in kernel should be operated with relatively low frequency or voltage (it is lower than the frequency optimized for the thread running current active or voltage), and makes computing equipment seem slow without response or speed.

Various aspects overcome above-mentioned limitation by calculating and enforce performance guarantee, it ensures that processor cores will not at busy state (such as, owing to transient working load causes) maintenance time more longer than predetermined time amount, this predetermined time amount is to process kernel to complete its precalculated steady state operation load required time amount. Such performance guarantee can by operating system, resource, DCVS solution and/or other process kernel for estimating better, scheduling and/or plan operation in the future, such as Resources allocation and the thread being used for performing is scheduling. In this way, this performance guarantee can make computing equipment meet its responsiveness requirement, and thus improves Consumer's Experience.

Performance guarantee allows DCVS solution to adjust frequency and/or the voltage of processor based on variable delay, it guarantees the operating frequency/voltage currently or previously regardless of processor, processes kernel and only falls behind the maximal workload of definition at most than its steady state operation load.

Figure 10 depicts the logical block in an aspect computing equipment 1000 and flow of information, and this computing equipment realizes enforcing the dynamic clock frequency/voltage of performance guarantee and regulates (DCVS) solution. This computing equipment 1000 can include hardware cell 1002, kernel spacing software unit 1004 and user's space software unit 1006. In one aspect, kernel spacing software unit 1004 and user's space software unit 1006 can be included in the kernel of operating system or computing equipment 1000. Such as, computing equipment can include being organized in user's space (non-authorized code here runs) and kernel spacing (authorized code here runs). Such separation is even more important in Android and other general public license (GPL) environment, wherein in described GPL environment, code as a part for kernel spacing must be GPL license, and runs code in the user space and need not be GPL license.

Hardware cell 1002 can include multiple process kernel (such as, CPU0, CPU1,2D-GPU0,2D-GPU1,3D-GPU0 etc.) and resource module 1020, this resource module 1020 includes processing various hardware resources that kernel shares (such as, clock, power management integrated circuits or " PMIC ", scratchpad or " SPM " etc.).

Kernel spacing software unit 1004 can include the processor module (CPU_0 idle condition, CPU_1 idle condition, 2D-GPU_0 driving, 2D-GPU_1 driving, 3D-GPU_0 driving etc.) corresponding at least one the process kernel processed in kernel in hardware cell 1002, and each module in these modules can communicate with one or more idle condition EM equipment modules 1008. This kernel spacing software unit 1004 can also include timer drive module 1014, incoming event module 1010 and CPU request block of state 1012. In one aspect, timer driver module 1014 can drive the intervalometer of (or maintenance) each process kernel.

User's space software unit 1006 can include DCVS and control module 416, it is configured to receive input from idle condition EM equipment module 1008, incoming event module 1010, timer driver module 1014 and CPU request block of state 1012, and/or sends output to cpu frequency hot plug module 1018. This cpu frequency hot plug module 1018 can be configured to send signal of communication to resource module 1020. This cpu frequency hot plug module 1018 can be additionally configured to individually (such as, one next, continuously etc.) or simultaneously (such as, at almost identical time point) to each kernel applied voltage/frequency change.

DCVS controls module 1016 and can include being suitable for processing, at any or all, the thread that kernel (such as, CPU0, CPU1,2D-GPU0,2D-GPU1,3D-GPU0 etc.) is upper that perform and/or is suitable for realizing DCVS solution on computing equipment 1000. In one aspect, DCVS controls the thread that module 1016 can include port or socket are monitored, its monitoring makes DCVS control module 1016 from one or more process kernel gather information and in the generation processing the event (such as, data buffer fill up, timer expiration, State Transferring etc.) performing DCVS operation kernel. In one aspect, DCVS controls module 1016 can include single-threaded DCVS solution, and it is monitored two or more and processes kernel. In one aspect, DCVS control module 1016 can include the DCVS solution thread for each process kernel.

In one aspect, DCVS control module 1016 can be configurable to generate pulse train. DCVS controls module 1016 and the busy and/or idle condition (or the conversion between state) passed through processing kernel can be monitored or sample, and generates this pulse train. DCVS controls module 1016 and is also based on being monitored acquired information to the degree of depth of one or more processor operation queues, generates pulse train. But operation queue can include active thread and can process operation on kernel also not have enough time to run the set of one or more threads of (such as, due to current at another active threads run etc.). Each process kernel can have the operation queue of its own, or single operation queue can be shared by multiple process kernels. When thread request enters resting state, is made available by wait resource or terminates, it is possible to it is removed from operation queue. Therefore, number of threads in this operation queue is (namely, the operation queue degree of depth) may identify which (operation) thread including being presently processing active threads (such as, that wait, what run) and etc. the quantity of thread to be treated.

In one aspect, DCVS controls module 1016 and can be configured to calculate based on the pulse train generated steady state operation load, steady statue requirement and/or upper limiting frequency/voltage threshold and lower frequency limit/voltage threshold. Upper limiting frequency/voltage threshold and lower frequency limit/voltage threshold can define frequency/voltage scope, within the scope of this, process kernel may be operative to meet its steady statue performance requirement, and realize the power overhead reduced the responsiveness requirement meeting computing equipment 1000 simultaneously. Meeting responsiveness to require can include performing all tasks in workload, the user of such computing equipment 1000 will not notice that the performance of this computing equipment or the reduction of speed.

DCVS controls module 1016 and can be configured to monitoring overall calculation equipment 1000 performance and/or guarantee the one or more process kernels processing in kernel operation between upper limiting frequency threshold value and the lower frequency limit threshold value established. This DCVS controls module 1016 can adjust the process resource and/or operating frequency that process kernel, thus they are suitable with threshold value.

As discussed above, DCVS controls module 1016 can generate pulse train. In one aspect, can synchronize in time for processing caryogenic pulse train in the two or more process in kernel, and crosscorrelation is to generate correlation model, it includes being adapted to determine that the information whether process kernel performs collaborative and/or complementary operation. In one aspect, DCVS controls module 1016 and this correlation model can be used to determine that upper limiting frequency threshold value and lower frequency limit threshold value, initial operating frequency, steady statue require and processor workload, thus these value considerations process the interdependency between kernel.

In one aspect, DCVS controls module 1016 and can be configured to calculating and/or compulsory execution performance guarantee. As described above, process kernel can be required to process/perform the transient working load that DCVS solution cannot suitably consider in advance. Therefore, transient working load can make DCVS control module 1016 with suboptimization frequency level or in suboptimization frequency range operation process the one or more process kernels in kernel. Such as, these transient working loads cannot be considered in advance owing to DCVS controls module 1016, therefore it is likely to infer improperly: processes kernel and may operate in relatively low frequency level, this relatively low frequency level is within the time period that the responsiveness being applicable to meet computing equipment 1000 requires, completes the frequency level that both steady state operation load and transient working load are required.

Performance guarantee provides strict and computable boundary to computing equipment 1000, this guarantee can by DCVS control module 1016 for guarantee to process kernel will not busy state keep with the scheduled time/workload compared with want many time/workload (such as, due to transient working load), between at this moment in section this scheduled time/workload be process kernel complete required for its steady state operation burden requirement time/workload. Performance guarantee allows DCVS control module 1016 to guarantee, and process kernel simultaneously completes its steady state operation load and its transient working load within the time period that the responsiveness being applicable to meet this computing equipment 1000 requires.

In all fields, performance guarantee can calculate by any measurement unit, defines and/or include any measurement unit, this measurement unit is applicable to measurement processor performance or persistent period, such as time quantum, workload, task quantity, instruction number, cpu cycle quantity etc.In all fields, performance guarantee can join and/or can be the function of frequency with frequency dependence.

In one aspect, performance guarantee can include one or more performance guarantee value. In all fields, this performance guarantee value (such as, deadline date value, estimated value, jump to maximum (jump-to-maxvalue) etc.) can represent by any measurement unit suitable in measurement processor performance or persistent period (such as time quantum, workload, task quantity, instruction number, cpu cycle quantity etc.).

In all fields, this performance guarantee value can include estimated value (such as, lax budget, transient state budget etc.), deadline date value (such as, transient state deadline date, transient response deadline date, performance deadline date etc.) and/or jump to maximum.

This deadline date value could be for instruction processor cores and completes the value of the value of relative time before its workload processes and/or relative time for indicating the frequency processing kernel to be behind increased.

This estimated value could be for instruction and processes the time quantum that remaining and/or processor cores behind the frequency before kernel to complete the process of its workload to be increased.

Jump to maximum to could be for instruction processor cores and to complete before its workload processes and/or the frequency of processor cores behind to be added to the value of relative time of peak frequency.

This performance guarantee value can relevant to frequency or voltage, be associated and/or be its function. Such as, budget, deadline date and/or to jump to each of maximum can be the time value calculated according to the corresponding operating frequency processing kernel. Therefore, when processing kernel and working with the frequency of 100MHz, each in these values can be 10 milliseconds, with the frequency of 200MHz work time for 20 milliseconds, with the frequency of 400MHz work time for 40 milliseconds etc. By this way, this performance guarantee value can by DCVS solution for realizing the variable delay that increase processes the frequency of kernel.

As described above and depicted in figure 9, DCVS solution can realize variable delay. Such variable delay guarantees the actual operating frequency no matter processing kernel, and this process kernel only falls behind the maximal workload that its steady state operation load defines at most. In one aspect, the maximal workload (that is, process kernel and can lag behind the amount of its steady state operation load) of definition can be equal to deadline date value and be multiplied by the peak frequency/voltage of this process kernel by DCVS solution. In this way, performance guarantee do not required based on steady statue by DCVS solution dynamically or " online " adjust the impact of frequency/voltage of this process kernel.

In one aspect, this DCVS control module 1016 can be configured to every time corresponding process kernel from the free time be transformed into busy, enter busy state (such as, processing workload etc.) and/or exit from idle status (such as, process kernel etc. is conceded when idle thread) time, will be worth the deadline date and be equal to this estimated value.

In one aspect, DCVS control module 1016 can be configured to every time the corresponding kernel that processes and be transformed into free time, entrance idle condition (such as from busy, performing idle thread etc.) and/or exit busy state (such as, complete all task dispatchings in workload) time, arrange or reset existing deadline date value.

Figure 11 A-B depicts for generating/an aspect DCVS solution method 1100 ensureing of calculated performance, it guarantees to process kernel will not at busy state (such as, due to transient working load etc.) keep the time more than predetermined time amount, between at this moment, in section, this predetermined time amount is the time that process kernel completes required for the steady state operation load of its precalculated, prediction and/or reality. In all fields, the work of DCVS solution can be performed by the thread performed on this process kernel or another process kernel. In one aspect, one or more operations of DCVS solution can be performed by processing the idle thread performed on kernel.

In square frame 1102, DCVS solution can make process kernel be transformed into busy state from idle condition. In square frame 1104, the value terminating idle time parameters (EndIdleTime) can be equal to current time value (CurrentTime) by DCVS solution. Therefore, this terminates idle time parameters (EndIdleTime) and can store the time for indicating this process kernel last time to exit from idle status.

In all fields, the operation of square frame 1102 and 1104 can order, perform parallel and/or in any order. Such as, in one aspect, this DCVS solution can process kernel be transformed into from the free time busy before arrange terminate idle time parameters (EndIdleTime) value. In yet another aspect, DCVS solution can process kernel be transformed into from the free time busy after arrange end idle time parameters (EndIdleTime) value.

In square frame 1106, DCVS solution can monitor the operating frequency or voltage that process kernel, and adjusts as required. In square frame 1108, this DCVS solution can so that processing kernel to be transformed into idle condition from busy state. In one aspect, DCVS solution can be passed through to start to perform idle thread on process kernel, and this process kernel is transformed into idle condition. In one aspect, process kernel can be transformed into idle condition by DCVS solution after processing kernel and completing all tasks that its all working load is associated.

In optional square frame 1110, DCVS solution can arrange or reset existing deadline date value. As discussed above, deadline date value can be included in performance guarantee or performance guarantee value associated therewith. Will provide information about setting further below, reset and/or calculate the extra details of the operation of this deadline date value.

In square frame 1112, the value starting idle time parameters (StartIdleTime) can be equal to current time value (CurrentTime) by DCVS solution. Difference in square frame 1114, between time when the value of rush hour parameter (BusyTime) can be equal to process the time (can be represented by terminating idle time parameters " EndIdleTime ") when the exiting previous idle condition kernel last time and process kernel entrance current availability by DCVS solution (can by idle time parameters " StartIdleTime "). Therefore, rush hour parameter (BusyTime) can store for indicating the value processing the persistent period that interior kernel nearest is maintained at busy state.

In square frame 1116, DCVS solution can make process kernel perform various idle state operation, and such as the operation of sleep operation, deep-sleep or software wait interrupt operation.Therefore, in square frame 1116, DCVS solution (such as, via idle thread, operating system etc.) can make process kernel enter resting state, deep sleep state, wait interrupt status etc.

In square frame 1118, DCVS solution and/or idle thread can receive interrupt requests and/or otherwise determine that this process kernel to be transformed into busy state from its current state. This can pass through DCVS solution and receive and realize about the notice (such as, from operating system scheduler, controller etc.) of herein below: task has been scheduled in this process kernel to perform and/or the task of being scheduled is already prepared to perform.

In square frame 1120, DCVS solution can be equal to current time value (CurrentTime) by terminating idle time parameters (EndIdleTime). In square frame 1122, idle time parameters (IdleTime) can be equal to the difference of the value of StartIdleTime parameter and the value of EndIdleTime parameter by DCVS solution. Therefore, this idle time parameters (IdleTime) can store for indicating this process kernel finally to keep the value of persistent period of idle condition.

In square frame 1124, DCVS solution can computing kernel operating frequency, frequency range and/or the frequency threshold to operate in. In one aspect, DCVS solution can be maintained at persistent period of busy state (such as based on processing the kernel last time, and/or process the kernel last time and be maintained at persistent period of idle condition (such as BusyTime), IdleTime), this frequency or frequency range are calculated. In one aspect, this DCVS solution can based on historical information, such as processor is previously held in busy and/or idle condition (such as, in predetermined time period or time window) the meansigma methods (or meansigma methods of movement) of persistent period, calculate this operating frequency, frequency range and/or frequency threshold. In one aspect, DCVS solution can come evaluation work frequency, frequency range and/or frequency threshold based on pulse train. As discussed above, pulse train can generate based on the degree of depth etc. of the conversion between busy and/or the sampling of idle condition, state, operation queue.

In square frame 1126, DCVS solution can calculate or select deadline date value. This deadline date value could be for the value indicating the frequency processing kernel to be behind set to increase to the relative time of next higher frequency step-length or peak frequency. In all fields, it is possible to arrange based on configuration, driver input, the quantity of task of scheduling and/or type, the steady state operation load of prediction and/or computing equipment responsiveness requirement, calculate this deadline date value. This deadline date value can be based on static state and/or dynamic value and determine. Such as, this deadline date value based on static Configuration Values, or can be determined based on the type (such as, streaming 1080p video convection type 720p video etc.) being scheduled as performing on this process kernel of task.

In one aspect, this deadline date value can require be inversely proportional to (that is, responsiveness requires more high, and the deadline date is more short) with the responsiveness of computing equipment. In one aspect, this deadline date value can be time value, this time value be the present operating frequency processing kernel function (such as, at 10 milliseconds of 100MHz frequency place, 20 milliseconds of 200MHz frequency place, 40 milliseconds of 400MHz frequency place etc.).

In square frame 1128, DCVS solution can calculate or select estimated value. This estimated value could be for the value of instruction time quantum, process in this time quantum kernel may remain in activity or busy state and less than deadline date value be confirmed as this process kernel and complete the time sum required for its steady state operation burden requirement. In one aspect, this estimated value can be time value, this time value be the present operating frequency processing kernel function (such as, at 10 milliseconds of 100MHz frequency place, 20 milliseconds of 200MHz frequency place, 40 milliseconds of 400MHz frequency place etc.).

In all fields, this estimated value can be worth based on the deadline date, multiple frequency level or step-length, maximum processor frequency, steady statue processor frequencies etc. calculate. In one aspect, this estimated value can effective transient state budget and/or calculate via any formula discussed above.

In optional square frame 1130, DCVS solution can calculate and jump to maximum. This jumps to maximum and could be for indicating the value of relative time that the frequency processing kernel behind to be set to maximum process frequency. In one aspect, this jumps to maximum and can calculate by the value of EndIdleTime parameter and estimated value are sued for peace.

In square frame 1132, DCVS solution can be transformed into busy state by processing kernel from idle condition. In one aspect, as a part for square frame 1132, the deadline date can be worth and is equal to estimated value by DCVS solution. In all fields, DCVS solution can be configured to every time process kernel from the free time be converted to busy, entrance is movable or busy state (such as, beginning reason workload etc.) and/or exit from idle status (such as, when idle thread concedes process kernel), will be worth the deadline date and be equal to estimated value.

Figure 12 describes to enforce performance guarantee, and to guarantee to process, kernel will not DCVS solution method 1200 be (such as in busy state keeps one of time more than predetermined time amount, existence due to transient working load, etc.), between at this moment, in section, this predetermined time amount is the time that this process kernel completes required for the steady state operation load of its precalculated, expectation and/or reality. In square frame 1202, DCVS solution can calculate the steady state operation load of prediction based on being scheduled of task. In square frame 1204, DCVS solution can the computing kernel various performance requirements (such as frequency threshold) for meeting the power consumption of this computing equipment and/or responsiveness requires. This performance requirement (such as, frequency threshold etc.) can be determined based on steady state operation load, historical information (time quantum etc. such as, previously spent in busy state), processor characteristic, responsiveness requirement etc.

In square frame 1206, DCVS solution can calculate and arrange initial operating frequency and/or various performance guarantee value (such as, deadline date value, estimated value, jump to maximum etc.). In square frame 1208, DCVS solution can complete all tasks in steady state operation load and meet the time required for each performance requirement or workload (such as, cpu cycle, instruction etc.) simultaneously by computing kernel.

In square frame 1210, DCVS solution can be transformed into busy state by processing kernel from idle condition, runs thus processing kernel with the initial operating frequency/voltage (or in the threshold value calculated) calculated and/or meets various equipment or system requirements.In square frame 1212, DCVS solution can monitor the real work load and/or operating frequency that process kernel, and is adjusted as required by frequency/voltage (such as, according to default clock and voltage adjustment algorithms). In optional square frame 1214, DCVS solution can update performance guarantee value based on the present operating frequency/voltage processing kernel.

In determination block 1216, DCVS solution may determine that process kernel whether maintained in busy state than calculate time/work long time (that is, be confirmed as process kernel complete prediction steady state operation load in all required by task want time/workload). When DCVS solution determine process kernel do not keep in busy state than calculate time/work long time (namely, determination step 1216="No") time, in square frame 1212, DCVS solution can continue workload/frequency that monitoring is actual, and adjusts when necessary.

When DCVS solution determine process kernel busy state maintain than calculate time/work long persistent period (namely, determination step 1216="Yes") time, in determination block 1218, DCVS solution may determine whether to exhaust budget. This DCVS solution may determine that: when estimated value is equal to zero and/or when process kernel busy state maintain add more than or equal to deadline date value calculate time/persistent period (with time or the work measurement) of work time, budget exhausts.

When DCVS solution determines that budget is but without exhausting (namely it is decided that step 1218="No"), in square frame 1212, DCVS solution can continue workload/frequency that monitoring is actual, and adjusts as required. When determining this budget when DCVS solution and exhaust (namely it is decided that step 1218="Yes"), in square frame 1220, DCVS solution can increase the operating frequency/voltage processing kernel. In one aspect, the operating frequency/voltage processing kernel can be increased to maximum processor frequency by this DCVS solution in square frame 1220. In one aspect, DCVS solution can increase operating frequency/voltage threshold in square frame 1220. In one aspect, in square frame 1220, DCVS solution can increase the operating frequency/voltage processing kernel step by step.

Figure 13 depicts another the aspect DCVS solution method 1300 for enforcing performance guarantee. In square frame 1302-1314, DCVS solution can perform and the same or analogous operation of operation such as discussed above for the square frame 1202-1214 of Figure 12. In determination block 1316, DCVS solution may determine whether that significantly high probability appearance processes kernel and will complete its current work load in the time (that is, be confirmed as this process kernel and complete the time quantum that all required by task in the steady state operation load of prediction are wanted) calculated before plus deadline date value (calculate time+deadline date).

Its current work load was completed (namely before DCVS solution is determined and had significantly high probability appearance process kernel by deadline date value in the time machine calculated, determination step 1316="Yes") time, in square frame 1312, DCVS solution can continue monitoring real work load/frequency, and as required operating frequency/voltage is adjusted.

When DCVS solution determine do not have significantly high probability to occur this process kernel will in the time calculated plus complete its current work load (namely before deadline date value, determination step 1316="No") time, in square frame 1318, DCVS solution can increase the operating frequency/voltage processing kernel.Operating frequency/the voltage of this process kernel can be added to maximum processor frequency or be increased step by step.

The method that various aspects include improving the performance on the computing equipment with processor, the method can include determining that the steady state operation load of processor, determine the workload required for the steady state operation load performing to determine on this processor, calculate the performance guarantee value of this processor, this processor is transformed into busy state from idle condition, real work load based on processor performs dynamic clock and voltage adjustment operations to regulate the frequency of this processor, this performance guarantee value is updated based on the frequency regulated, determine whether this processor maintains a period of time more than or equal to the workload determined and performance guarantee value sum at busy state, and when determining that this processor maintains a period of time more than or equal to the workload determined and performance guarantee value sum at busy state, increase the frequency of processor.

In one aspect, when determining that processor maintains a period of time more than or equal to the workload determined and performance guarantee value sum at busy state, the frequency increasing processor can include processor frequencies is increased to maximum processor frequency. In other side, when determining that processor maintains a period of time more than or equal to the workload determined and performance guarantee value sum at busy state, the frequency of increase processor can include the frequency increasing processor step by step. In other side, the method can also include being repeatedly carried out following operation: updates performance guarantee value based on the frequency regulated, determine whether processor maintains a period of time more than or equal to the workload determined and performance guarantee value sum at busy state, and when determining that processor maintains a period of time more than or equal to the workload determined and performance guarantee value sum at busy state, increase the frequency of processor.

In other side, the performance guarantee value of computation processor can include calculating deadline date value. In other side, the performance guarantee value of computation processor can include computation budget value. In other side, it is determined that the steady state operation load of processor can include determining that the requirement of performing on the processor of the task of scheduling. In other side, the method can include generating pulse train by the conversion between described busy and idle condition of sampling. In other side, it is determined that the steady state operation load of processor, determine the workload performed on a processor required for steady state operation load, and the operation of the performance guarantee value of computation processor can be performed by single-threaded. In other side, described single-threaded perform on a processor. In other side, described single-threaded execution on the second processor of computing equipment.

Other side includes a kind of computing equipment, it has the unit of the steady state operation load for determining processor, for determining the unit of the workload required for the steady state operation load performing to determine on processor, unit for the performance guarantee value of computation processor, for processor to be transformed into the unit of busy state from idle condition, for performing dynamic clock and voltage adjustment operations to regulate the unit of the frequency of processor based on the real work load of processor, for updating the unit of performance guarantee value based on the frequency regulated, for determining whether described processor maintains the unit more than or equal to the workload determined and a period of time of performance guarantee value sum at busy state, and for when determining that processor maintains a period of time more than or equal to the workload determined and performance guarantee value sum at busy state, increase the unit of the frequency of described processor.

In one aspect, for when determining that described processor maintains a period of time more than or equal to the workload determined and performance guarantee value sum at busy state, the unit of the frequency increasing processor may include that the unit for the frequency of described processor increases to maximum processor frequency.

In other side, for when determining that processor maintains a period of time more than or equal to the workload determined and performance guarantee value sum at busy state, the unit increasing the frequency of processor may include that the unit of the frequency for increasing processor step by step. In other side, described computing equipment also includes the unit for being repeatedly carried out following operation: update performance guarantee value based on the frequency regulated, determine whether processor maintains a period of time more than or equal to the workload determined and performance guarantee value sum at busy state, and when determining that processor maintains a period of time more than or equal to the workload determined and performance guarantee value sum at busy state, increase the frequency of processor.

An other side, the unit for the performance guarantee value of computation processor includes the unit for calculating deadline date value. An other side, the unit for the performance guarantee value of computation processor includes the unit for computation budget value. An other side, the unit for determining the steady state operation load of processor can include the unit for determining the requirement being scheduled as performing on a processor of task. An other side, computing equipment can include the unit for being generated pulse train by the conversion between described busy and idle condition of sampling.

An other side, computing equipment can include for via the single-threaded steady state operation load completing to determine processor, determine the workload performed on a processor required for steady state operation load and the unit of the operation of the performance guarantee value of computation processor. An other side, computing equipment can include for performing single-threaded unit on a processor. An other side, computing equipment can include for performing single-threaded unit on the second processor of computing equipment.

Other side includes a kind of computing equipment, it can include the processor being configured with processor executable to perform operation, it can include first processor, it is configured with processor executable to perform to include the operation of the following: determine the steady state operation load of the second processor, determine the workload required for the steady state operation load performing to determine on the second processor, calculate the performance guarantee value of the second processor, second processor is transformed into busy state from idle condition, real work load based on the second processor performs dynamic clock and voltage adjustment operations, to regulate the frequency of the second processor, performance guarantee value is updated based on the frequency regulated, determine whether the second processor maintains a period of time more than or equal to the workload determined and performance guarantee value sum at busy state, and when determining that the second processor maintains a period of time more than or equal to the workload determined and performance guarantee value sum at busy state, increase the frequency of the second processor.

In one aspect, first processor can be configured with processor executable, so that when determining that the second processor maintains a period of time more than or equal to the workload determined and performance guarantee value sum at busy state, increase the frequency of the second processor and may include that the second processor frequencies is increased to maximum processor frequency.

An other side, first processor can be configured with processor executable, so that when determining that the second processor maintains a period of time more than or equal to the workload determined and performance guarantee value sum at busy state, the frequency increasing by the second processor may include that the frequency being incrementally increased the second processor.

An other side, first processor can be configured with processor executable, to be repeatedly carried out following operation: update performance guarantee value based on the frequency regulated, determine whether the second processor maintains a period of time more than or equal to the workload determined and performance guarantee value sum at busy state, and when determining that the second processor busy state maintains a period of time more than or equal to the workload determined and performance guarantee value sum, increase the frequency of the second processor.An other side, first processor can be configured with processor executable, so that the performance guarantee value calculating the second processor can include calculating deadline date value.

An other side, first processor can be configured with processor executable, so that the performance guarantee value calculating the second processor can include computation budget value. An other side, first processor can be configured with processor executable configuration, so that determining that the steady state operation load of the second processor includes determining the requirement of the task of being scheduled as on the second processor to perform. An other side, first processor can be configured with processor executable configuration, to perform also to include the operation of following item: by sampling, the conversion between described busy and idle condition generates pulse train.

An other side, first processor can be configured with processor executable, so that following operation is performed by single-threaded: determine the steady state operation load of the second processor, determine the workload performed on the second processor required for steady state operation load, and calculate the performance guarantee value of the second processor. An other side, first processor can be configured with processor executable, can perform so that single-threaded on first processor. An other side, first processor can be configured with processor executable configuration, so that the operation completing the following can include performing on the second processor single-threaded: determine the steady state operation load of the second processor, determine the workload performed on the second processor required for steady state operation load, and calculate the performance guarantee value of the second processor.

Other side includes a kind of non-transitory server readable storage medium storing program for executing, on it, storage has processor can perform software instruction, described can being configured with is configured such that processor performs operation, described operation can include determining that the steady state operation load of the second processor, determine the workload required for the steady state operation load performing to determine on the second processor, calculate the performance guarantee value of the second processor, second processor is transformed into busy state from idle condition, real work load based on the second processor performs dynamic clock and voltage adjustment operations, to regulate the frequency of the second processor, performance guarantee value is updated based on the frequency regulated, determine whether the second processor maintains a period of time more than or equal to the workload determined and performance guarantee value sum at busy state, and when determining that the second processor maintains a period of time more than or equal to the workload determined and performance guarantee value sum at busy state, increase the frequency of the second processor.

In one aspect, the processor of storage can perform software instruction and be configured such that processor performs operation, so that when determining that the second processor maintains a period of time more than or equal to the workload determined and performance guarantee value sum at busy state, increase the frequency of the second processor and may include that the second processor frequencies is increased to maximum processor frequency.

An other side, the processor of storage can perform software instruction and be configured such that the second processor performs operation, so that when determining that described second processor maintains a period of time more than or equal to the workload determined and performance guarantee value sum at busy state, the frequency increasing by the second processor can include being incrementally increased the frequency of the second processor, and it is repeatedly carried out following operation: update performance guarantee value based on the frequency regulated, determine whether the second processor maintains a period of time more than or equal to the workload determined and performance guarantee value sum at busy state, and when determining that the second processor maintains a period of time more than or equal to the workload determined and performance guarantee value sum at busy state, increase the frequency of the second processor.

An other side, the processor of storage can perform software instruction and be configured such that processor performs operation, so that the performance guarantee value calculating the second processor can include calculating deadline date value.An other side, the processor of storage can perform software instruction and be configured such that processor performs operation, so that the performance guarantee value calculating the second processor can include computation budget value. An other side, the processor of storage can perform software instruction and is configured such that processor performs operation, so that determining that the steady state operation load of the second processor can include determining that to be scheduled as on the second processor the requirement of the task of execution. An other side, the processor of storage can perform software instruction and be configured such that processor performs operation, and described operation includes generating pulse train by the conversion between described busy and idle condition of sampling.

An other side, the processor of storage can perform software instruction and be configured such that processor performs operation, so that following operation is performed by single-threaded: determine the steady state operation load of the second processor, determine the workload performed on the second processor required for steady state operation load, and calculate the performance guarantee value of the second processor. An other side, the processor of storage can perform software instruction and be configured such that processor performs operation, performs on a processor so that single-threaded. An other side, the processor of storage can perform software instruction and be configured such that processor performs operation, performs on the second processor so that single-threaded.

Various aspects provide a lot of benefit, and can be implemented in notebook laptop computer and other moves in equipment, and performance, power consumption and/or responsiveness are critically important in such devices. Various aspects can be implemented in server and personal computer, to reduce energy and the cooling expense of underload machine. Reduce heat output permission system cooling fan lower speed or close, reduce noise level, and reduce power consumption further. Various aspects can be also used for when temperature reaches certain threshold value, reduces the temperature in the system of cooling not.

Although illustratively describing various aspects round process kernel above, but each side method, system and executable instruction can be implemented in any system that these methods were capable of identify that and controlled frequency or voltage wherein. Additionally, the operation of regulating frequency or voltage can perform on any uniprocessor or multicomputer system.

Various aspects can be implemented in different portable or mobile formula computing equipments, depicts an example in Figure 14. This portable computing device 1400 can include the process kernel 1401 being coupled to memorizer 1402 and transceiver 1405. Transceiver 1405 is alternatively coupled to the antenna 1404 for sending and receive electromagnetic radiation. This portable computing device 1400 could be included for receiving the display 1403 (such as, touch-screen display) of user's input and menu selection buttons or rocker switch 1406. In some portable computing devices, it is provided that multiple processors 1401, such as a processor is exclusively used in radio communication function, and a processor is exclusively used in other application of operation.

Various aspects can also realize in any one of different commercial use server apparatus, the server 1500 described in such as Figure 15. Such server 1500 generally includes process kernel 1501, and can include multiple processor system 1511,1521,1531, and one or more of which can be or include polycaryon processor.Process kernel 1501 and be alternatively coupled to volatile memory 1502 and Large Copacity nonvolatile memory, such as hard drive 1503. This server 1500 can also include being coupled to the process disk drive of kernel 1501, compact disk (CD) or DVD and drive 1506. This server 1500 can also include being coupled to the network access port 1504 processing kernel 1501, for setting up data cube computation with network 1505, is such as coupled to the LAN of other broadcast system computer and server.

Aspects described above can also realize in different personal computing devices, the laptop computer 1600 described in such as Figure 16. Laptop computer 1600 can include the process kernel 1601 being coupled to volatile memory 1602 and Large Copacity nonvolatile memory (disk drive 1604 of such as flash memory). Computer 1600 can also include being coupled to the disk drive 1606 processing kernel 1601 and compact disk (CD) drives 1608. This computer equipment 1600 can also include being coupled to the multiple connector ports processing kernel 1601, is used for setting up data cube computation or receiving External memory equipment, such as USB,OrAdapter socket or other network connection circuit, for being coupled to network or computer by process kernel 1601. In notebook computer configures, counter body includes being all coupled to process the touch pad 1616 of kernel 1601, keyboard 1618 and display 1620. Other configuration of computing equipment can include the well-known computer mouse being coupled to processor (such as, inputting) via USB or trace ball.

Processing kernel 1401,1501,1601 can be any programmable processor, microprocessor, microcomputer, polycaryon processor or processor chip, it can be configured to perform several functions by software instruction (application), including function and the operation of various aspects described herein. Generally, software application can be stored in internal storage 1402,1502,1602 before being accessed and be loaded in process kernel 1401,1501,1601. Each process kernel 1401,1501,1601 can include the internal storage enough storing application software instructions. In some computing equipments, other memory chip (such as, secure data (SD) card) can be inserted into computing equipment and be coupled to process kernel 1401,1501,1601. This internal storage 1402,1502,1602 can be volatibility or nonvolatile memory, such as flash memory or the mixing of the two. For the purpose this specification, generally quoting of memorizer is referred to the process addressable all memorizeies of kernel 1401,1501,1601, including the memorizer in internal storage 1402, the removable memorizer being inserted in mobile equipment and process kernel 1401.

Process the internal storage that kernel 1501,1601,1710 can include enough storing application software instructions. In a lot of equipment, this internal storage can be volatibility or nonvolatile memory, the mixing of such as flash memory or both of which. For the purpose this specification, generally quoting of memorizer is referred to the memorizer that can be accessed by processor 1501,1601,1710, including the internal storage processed in kernel 1501,1601,1710 itself or be inserted into the removable memorizer in equipment and memorizer.

Said method describes and process chart merely exemplary property example provides, and is not intended as requiring or imply that the step of various aspects must be executed in the order shown. Skilled person will appreciate that, the order of the step in above-mentioned aspect can perform in any order. The order of step such as it is not intended to limit as the word such as " afterwards ", " then ", " next "; These words are used only for the description running through method to guide reader. Additionally, any quoting claim element in the singular, for instance use article " (a) ", " (an) " or " described (the) " and be not construed as this unit is limited to odd number.

Electronic hardware, computer software or its combination can be implemented as in conjunction with the various illustrative box described by aspect disclosed herein, module, circuit and algorithm steps. In order to be clearly shown that the interchangeability between hardware and software, above various illustrative assemblies, square frame, module, circuit and step are carried out total volume description around its function. It is implemented as hardware as this function and is also implemented as software, depend on specific application and the design constraint that whole system is applied. Those skilled in the art for each application-specific, can realize described function in the way of flexible, but, this realize decision-making and be not necessarily to be construed as and deviate from protection scope of the present invention.

It is designed to perform the general processor of function described herein, digital signal processor (DSP), special IC (ASIC), field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components or its combination in any, it is possible to achieve or perform for realizing the hardware in conjunction with the various illustrative logical block of aspect disclosed herein description, box, module and circuit. General processor can be multiprocessor, or, this processor can also be the processor of any routine, controller, microcontroller or state machine. Processor is also implemented as the combination of computing equipment, for instance, the combination of the combination of DSP and multiprocessor, multiple multiprocessor, one or more multiprocessor and DSP core, or other this kind of structure any. It addition, some steps or method can be performed by the circuit being exclusively used in given function.

In one or more illustrative aspects, described function can use hardware, software, firmware, or its combination in any realizes. If realized in software, then described function can be stored in non-transitory computer-readable storage media as one or multiple processor executable or code. The step of the methods disclosed herein or algorithm can be embodied in processor and can perform in software module, and it may reside within tangible or non-transitory computer-readable storage media. Non-transitory computer-readable storage media can be the accessible any usable storage medium of computer. Give an example, but it is not intended as restriction, this computer-readable medium can include RAM, ROM, EEPROM, CD-ROM or other optical disc storage, disk storage or other magnetic storage apparatus, or may be used for carrying with the form of instruction or data structure or store desired program code can by other medium any of computer access. As used herein, disk and CD include compact disk (CD), laser-optical disk, CD, digital versatile disc (DVD), floppy disk and Blu-ray Disc, wherein disk generally magnetically replicates data, and CD then generally utilizes laser to replicate data optically. Combinations of the above should also be as including in the scope of non-transitory computer-readable medium. It addition, the operation of method or algorithm can as of the code in non-transitory machine readable media and/or non-transitory computer-readable medium and/or instruction or any combination or set, it can be incorporated in computer program.

Description to open aspect before offer, so that any person skilled in the art can make or use the present invention. The various amendments of these aspects be will be apparent from for a person skilled in the art, and rule defined herein can be applied to other side without departing from the spirit or scope of the present invention. Therefore, the present invention is not intended to limit aspect shown herein, and is to fit to the widest scope consistent with appended claim and principle disclosed herein and novel features.

Claims

1. the method for improving the performance on the computing equipment with processor, described method includes:

Determine the steady state operation load of described processor;

Determine the workload performed on the processor required for determined steady state operation load;

Calculate the performance guarantee value of described processor;

Described processor is transformed into busy state from idle condition;

Based on the real work load of described processor, perform dynamic clock and voltage adjustment operations to regulate the frequency of described processor;

Described performance guarantee value is updated based on the frequency regulated;

Determine whether described processor maintains a period of time more than or equal to determined workload and described performance guarantee value sum at described busy state; And

When determining that described processor maintains a period of time more than or equal to determined workload and described performance guarantee value sum at described busy state, increase the described frequency of described processor.

2., the method for claim 1, wherein when determining that described processor maintains a period of time more than or equal to determined workload and described performance guarantee value sum at described busy state, the described frequency increasing described processor includes:

The described frequency of described processor is increased to maximum processor frequency.

3. the method for claim 1, wherein, when determining that described processor maintains a period of time more than or equal to determined workload and described performance guarantee value sum at described busy state, the described frequency increasing described processor includes being incrementally increased the described frequency of described processor, and described method also includes being repeatedly carried out following operation:

4. the performance guarantee value the method for claim 1, wherein calculating described processor includes calculating deadline date value.

5. the performance guarantee value the method for claim 1, wherein calculating described processor includes computation budget value.

6. the method for claim 1, wherein determine that the steady state operation load of described processor comprises determining that the requirement of performing on the processor of the task that is scheduled.

7. the method for claim 1, also includes:

By the conversion between described busy state and described idle condition is sampled, generate pulse train.

8. the method for claim 1, wherein, hereinafter operate and performed by single-threaded: determine the steady state operation load of described processor, it is determined that perform the workload required for steady state operation load on the processor, and calculate the performance guarantee value of described processor.

9. method as claimed in claim 8, wherein, described single-threaded performs on the processor.

10. method as claimed in claim 8, wherein, described single-threaded execution on the second processor of described computing equipment.

11. a computing equipment, including:

For determining the unit of the steady state operation load of processor;

For determining the unit performing the workload required for determined steady state operation load on the processor;

For calculating the unit of the performance guarantee value of described processor;

For described processor to be transformed into the unit of busy state from idle condition;

For the real work load based on described processor, perform dynamic clock and voltage adjustment operations to regulate the unit of the frequency of described processor;

For updating the unit of described performance guarantee value based on the frequency regulated;

For determining whether described processor maintains the unit more than or equal to determined workload and a period of time of described performance guarantee value sum at described busy state; And

For when determining that described processor maintains a period of time more than or equal to determined workload and described performance guarantee value sum at described busy state, increasing the unit of the described frequency of described processor.

12. computing equipment as claimed in claim 11, wherein, for when determining that described processor maintains a period of time more than or equal to determined workload and described performance guarantee value sum at described busy state, the unit of the described frequency increasing described processor includes:

For the described frequency of described processor being increased to the unit of maximum processor frequency.

13. computing equipment as claimed in claim 11, wherein, for when determining that described processor maintains a period of time more than or equal to determined workload and described performance guarantee value sum at described busy state, the unit increasing the described frequency of described processor includes the unit of the described frequency for being incrementally increased described processor, and described computing equipment also includes the unit for being repeatedly carried out following operation:

14. computing equipment as claimed in claim 11, wherein, the unit of the performance guarantee value for calculating described processor includes the unit for calculating deadline date value.

15. computing equipment as claimed in claim 11, wherein, the unit of the performance guarantee value for calculating described processor includes the unit for computation budget value.

16. computing equipment as claimed in claim 11, wherein, the unit for determining the steady state operation load of described processor includes: for determining the unit of the requirement of performing on the processor of the task that is scheduled.

17. computing equipment as claimed in claim 11, also include:

For by the conversion between described busy state and described idle condition is sampled, generating the unit of pulse train.

18. computing equipment as claimed in claim 11, also include for via the single-threaded unit completing following operation:

Determine the steady state operation load of described processor,

Determine the workload performed on the processor required for steady state operation load, and

Calculate the performance guarantee value of described processor.

19. computing equipment as claimed in claim 18, wherein, also include for performing described single-threaded unit on the processor.

20. computing equipment as claimed in claim 18, wherein, also include for performing described single-threaded unit on the second processor of described computing equipment.

21. a computing equipment, including;

First processor, its configuration is to perform to include the operation of the following:

Determine the steady state operation load of the second processor;

Determine the workload performed on described second processor required for determined steady state operation load;

Calculate the performance guarantee value of described second processor;

Described second processor is transformed into busy state from idle condition;

Based on the real work load of described second processor, perform dynamic clock and voltage adjustment operations to regulate the frequency of described second processor;

Determine whether described second processor maintains a period of time more than or equal to determined workload and described performance guarantee value sum at described busy state; And

When determining that described second processor maintains a period of time more than or equal to determined workload and described performance guarantee value sum at described busy state, increase the described frequency of described second processor.

22. computing equipment as claimed in claim 21, wherein, described first processor is configured such that the described frequency increasing described second processor includes when determining that described second processor maintains a period of time more than or equal to determined workload and described performance guarantee value sum at described busy state:

The described frequency of described second processor is increased to maximum processor frequency.

23. computing equipment as claimed in claim 21,

Wherein, described first processor is configured such that when determining that described second processor maintains a period of time more than or equal to determined workload and described performance guarantee value sum at described busy state, the described frequency increasing described second processor includes being incrementally increased the described frequency of described second processor, and

Wherein, described first processor is also configured to be repeatedly carried out following operation:

24. computing equipment as claimed in claim 21, wherein, described first processor is configured such that the performance guarantee value calculating described second processor includes calculating deadline date value.

25. computing equipment as claimed in claim 21, wherein, described first processor is configured such that the performance guarantee value calculating described second processor includes computation budget value.

26. computing equipment as claimed in claim 21, wherein, described first processor is configured such that the requirement determining that the steady state operation load of described second processor comprises determining that the task of being scheduled on described second processor to perform.

27. computing equipment as claimed in claim 21, wherein, described first processor is configured to perform the operation also including the following:

28. computing equipment as claimed in claim 21, wherein, described first processor is configured such that following operation is performed by single-threaded: determine the steady state operation load of described second processor, determine the workload performed on described second processor required for steady state operation load, and calculate the performance guarantee value of described second processor.

29. computing equipment as claimed in claim 28, wherein, described first processor is configured such that described single-threaded execution on described first processor.

30. computing equipment as claimed in claim 28, wherein, described first processor has been configured such that following operation includes performing on described second processor described single-threaded: determine the steady state operation load of described second processor, determine the workload performed on described second processor required for steady state operation load, and calculate the performance guarantee value of described second processor.