KR20150083763A - Dual-mode switching dc-dc converter and method of controlling the same - Google Patents

Abstract

Disclosed is a DC-DC converter having a dual mode. The switching DC-DC converter includes a power conversion part and a switch driving part. The power conversion part generates a DC output voltage based on a switch driving signal and a DC input voltage. The switch driving part generates a first feedback voltage by performing frequency compensation for the DC output voltage, and the first feedback voltage, produces a pulse width modification signal comparing the first feedback voltage with a comparison input signal, generates a comparison output signal comparing the DC output voltage with the a first reference voltage, generates the switch driving signal based on the pulse width modification signal during normal operation, and generates the switch driving signal based on the comparison output signal during abnormal operation. Therefore, the switching DC-DC converter can generate a stable DC output voltage even load is changed.

Description

TECHNICAL FIELD [0001] The present invention relates to a dual-mode switching DC-DC converter and a control method thereof.

The present invention relates to a power converter, and more particularly, to a dual mode switching DC-DC converter and a control method thereof.

Recently, energy saving is highly demanded for environmental reasons. BACKGROUND ART [0002] In a portable information processing apparatus using a battery such as a cellular phone, a portable personal information terminal, and the like, saving of power consumption is becoming a very important problem. Switch mode power supplies such as step-down converters, boost converters, and buck-boost converters are used in a variety of electronic devices.

It is an object of the present invention to provide a switching DC-DC converter capable of generating a stable DC output voltage even when the load changes.

It is another object of the present invention to provide a control method of a switching DC-DC converter capable of generating a stable DC output voltage even when a load is changed.

In order to achieve the above object, a switching DC-DC converter according to an embodiment of the present invention may include a power conversion unit and a switch driving unit.

The power conversion unit generates a DC output voltage based on the switch driving signal and the DC input voltage. The switch driving unit generates a first feedback voltage by performing frequency compensation on the DC output voltage, compares the first feedback voltage with a comparison input signal to generate a pulse width modulation signal, Generates a comparator output signal in comparison with the voltage, generates the switch driving signal based on the pulse width modulated signal in normal operation, and generates the switch driving signal based on the comparison output signal in an abnormal operation.

According to one embodiment of the present invention, the comparison input signal may be a ramp signal.

According to one embodiment of the present invention, the abnormal operation may include a momentary change in the voltage level of the DC output voltage due to a change in the load current.

According to one embodiment of the present invention, the switching DC-DC converter may be a buck converter.

According to one embodiment of the present invention, the power conversion unit may include a first power switch, a second power switch, an inductor, and a capacitor.

The first power switch is connected between the first node and the second node to which the DC input voltage is applied, and operates in response to the first switch driving signal. A second power switch is connected between the second node and ground, and operates in response to the second switch drive signal. An inductor is coupled between the second node and the output node, and a capacitor is coupled between the output node and the ground.

According to one embodiment of the present invention, the switch driver may include a voltage divider circuit, a signal generator, a frequency compensation circuit, a first comparator, a transient response feedback circuit, a selection circuit, and a gate driver.

A voltage divider circuit divides the DC output voltage to generate a first voltage signal. The signal generator generates a duty signal having a duty ratio that varies according to the magnitude of the ramp signal, the clock signal, and the DC input voltage based on the DC input voltage and the first reference voltage. A frequency compensation circuit performs frequency compensation on the first voltage signal to generate the first feedback voltage. A first comparator compares the first feedback voltage to the ramp signal to generate the pulse width modulated signal. A transient response feedback circuit generates the comparison output signal by comparing the DC output voltage to the first reference voltage and provides a transient response control based on the clock signal, the duty signal, the pulse width modulated signal, Signal. The selection circuit selects one of the pulse width modulation signal and the comparison output signal in response to the transient response control signal and outputs the selected signal as a gate control signal. The gate driver generates the switch driving signal based on the gate control signal.

According to one embodiment of the present invention, the signal generator may include a first comparator, a second comparator, a flip flop and a third comparator.

A first comparator compares the ramp signal to a lower limit to generate a first comparison output, and a second comparator compares the ramp signal to an upper limit to generate a second comparison output. The flip-flop generates the clock signal based on the first comparison output and the second comparison output. The third comparator compares the ramp signal with a first voltage signal whose duty ratio varies according to the magnitude of the DC input voltage to generate the duty signal.

According to one embodiment of the present invention, the transient response feedback circuit may include a second comparator and a duty-based transient response control circuit.

The second comparator compares the DC output voltage with the first reference voltage to generate the comparison output signal. A duty-based transient response control circuit generates the transient response control signal based on the clock signal, the duty signal, the pulse width modulated signal, and the comparison output signal.

According to one embodiment of the present invention, the transient response feedback circuit can detect the comparison output signal using the clock signal and detect the pulse width modulated signal using the duty signal.

According to one embodiment of the present invention, the transient response feedback circuit may enable the transient response control signal when a pulse of the comparison output signal is not generated during one period of the clock signal.

According to one embodiment of the present invention, when the transient response control signal is enabled, the comparison output signal is outputted as the gate control signal, and when the transient response control signal is disabled, Can be output as a signal.

According to one embodiment of the present invention, if the transient response control signal is enabled, the switching DC-DC converter can have a fast transient response characteristic.

According to one embodiment of the present invention, the switching DC-DC converter operates in a fast transient response mode of operation, samples the pulse width modulated signal at the rising edge of the duty signal, and samples the logic of the pulse width modulated signal The transient response feedback circuit may disable the transient response control signal when the state transitions from the first state to the second state.

According to one embodiment of the present invention, when the transient response control signal is disabled, the switching DC-DC converter can operate in a normal operation mode.

According to an embodiment of the present invention, the duty ratio of the second clock signal can be adjusted.

According to one embodiment of the present invention, the duty ratio of the duty signal may be determined based on the DC input voltage and the first reference voltage.

According to one embodiment of the present invention, the transient response feedback circuit may include a pre-amplifier, a second comparator and a duty-based transient response control circuit.

The preamplifier amplifies the difference between the DC output voltage and the first reference voltage to generate a differential output signal pair. A second comparator compares the differential output signal pairs with each other to generate the comparison output signal. The duty-based transient response control circuit generates the transient response control signal based on the clock signal, the duty signal, the pulse width modulated signal, and the comparison output signal.

A method of controlling a switching DC-DC converter according to an embodiment of the present invention includes: generating a first feedback voltage by performing frequency compensation on a DC output voltage; Comparing the first feedback voltage to a comparison input signal to generate a pulse width modulated signal; Comparing the DC output voltage with a first reference voltage to generate a comparison output signal; Generating a switch driving signal based on the pulse width modulation signal in normal operation and generating the switch driving signal based on the comparison output signal in an abnormal operation; And generating the DC output voltage based on the switch driving signal and the DC input voltage.

According to an embodiment of the present invention, the step of generating the switch driving signal includes detecting a rising edge of the comparison output signal during one period of the clock signal; Determining whether a rising edge of the comparison output signal is present; Disabling the transient response control signal and controlling a duty cycle of the switch driving signal based on the pulse width modulated signal when a rising edge of the comparison output signal is present; Enabling the transient response control signal and controlling the duty cycle of the switch drive signal based on the comparison output signal if the rising edge of the comparison output signal is not present; Determining whether the value of the comparison output signal is "0 "; Determining whether the value of the pulse width modulation signal is "0" at the rising edge of the duty signal if the value of the comparison output signal is not "0 "; Wherein when the value of the pulse width modulation signal is "0" at the rising edge of the duty signal, the transient response control signal is disabled, and the duty cycle of the switch driving signal is controlled based on the pulse width modulation signal ; And the duty cycle of the switch driving signal is controlled based on the comparison output signal if the value of the pulse width modulation signal is not "0" at the rising edge of the duty signal step; Determining whether a value of the pulse width modulation signal is "1" at a rising edge of the duty signal when the value of the comparison output signal is "0 "; The duty cycle of the switch driving signal is controlled based on the pulse width modulation signal, if the value of the pulse width modulation signal is "1 " at the rising edge of the duty signal, ; And controlling the duty cycle of the switch driving signal based on the comparison output signal if the value of the pulse width modulation signal at the rising edge of the duty signal is not "1 " Step < / RTI >

The switching DC-DC converter according to the embodiment of the present invention operates in a fast transient response mode during an abnormal operation such as a momentary change in the voltage level of the DC output voltage, so that a stable DC output voltage can be generated even when the load changes . In particular, the switching DC-DC converter according to the embodiment of the present invention can be applied to various switching DC-DC converters by changing the duty ratio of the clock signal. Therefore, the switching DC-DC converter according to the embodiment of the present invention has high stability of operation and fast response speed.

1 is a circuit diagram illustrating a dual-mode buck converter according to one embodiment of the present invention.
2 is a circuit diagram showing one example of a signal generator included in the buck converter of FIG.
3 is a circuit diagram illustrating an example of a transient response feedback circuit included in the buck converter of FIG.
4 is a circuit diagram showing another example of the transient response feedback circuit included in the buck converter of FIG.
5 is a circuit diagram showing another example of the transient response feedback circuit included in the buck converter of FIG.
FIGS. 6 to 9 are timing charts for explaining the operation of the buck converter shown in FIG.
10 is a circuit diagram showing a dual mode buck converter according to another embodiment of the present invention.
11 is a circuit diagram illustrating a dual-mode buck converter according to another embodiment of the present invention.
12 is a circuit diagram showing a dual mode buck converter according to another embodiment of the present invention.
13 is a circuit diagram showing a dual mode boost converter according to one embodiment of the present invention.
FIG. 14 is a timing chart for explaining the operation of the boost converter shown in FIG. 13; FIG.
15 is a circuit diagram showing a dual-mode boost converter according to another embodiment of the present invention.
16 is a flowchart illustrating a method of controlling a dual-mode switching DC-DC converter according to an embodiment of the present invention.
17 is a flowchart showing a step of generating a switch driving signal in the control method of the dual mode switching DC-DC converter of FIG.
18 and 19 are simulation diagrams showing transient response characteristics of a switching DC-DC converter according to an embodiment of the present invention.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, And should not be construed as limited to the embodiments described in the foregoing description.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

The terms first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprising ", or" having ", and the like, are intended to specify the presence of stated features, integers, But do not preclude the presence or addition of steps, operations, elements, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

On the other hand, if an embodiment is otherwise feasible, the functions or operations specified in a particular block may occur differently from the order specified in the flowchart. For example, two consecutive blocks may actually be performed at substantially the same time, and depending on the associated function or operation, the blocks may be performed backwards.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

Figure 1 is a circuit diagram illustrating a dual-mode buck converter 100 according to one embodiment of the present invention.

Referring to FIG. 1, the buck converter 100 may include a switch driver and a power converter.

The power conversion section generates the DC output voltage VOUT based on the switch driving signals PDRV, NDRV and the DC input voltage VIN. The switch driving unit generates a first feedback voltage VEA by performing frequency compensation on the DC output voltage VOUT and compares the first feedback voltage VEA with a ramp signal VRAMP, Generates a comparison output signal VCOMP by comparing the DC output voltage VOUT with the first reference voltage VREF1 and generates a comparison output signal VCOMP based on the pulse width modulation signal VPWM in normal operation, (PDRV, NDRV) and generates the switch driving signals PDRV, NDRV based on the comparison output signal VCOMP in the abnormal operation.

The abnormal operation may include a momentary change in the voltage level of the DC output voltage VOUT due to a change in the load current.

The power conversion section may include a PMOS transistor MP1, an NMOS transistor MN1, an inductor L1 and a capacitor CO.

The PMOS transistor MP1 is connected between the first node N1 and the second node N2 to which the DC input voltage VIN is applied and operates in response to the first switch driving signal PDRV. The NMOS transistor MN1 is connected between the second node N2 and the ground, and operates in response to the second switch driving signal NDRV. The inductor L1 is connected between the second node N2 and the output node N3 and the capacitor CO is connected between the output node N3 and the ground.

The switch driver may include a voltage divider circuit, a frequency compensation circuit, a first comparator 130, a transient response feedback circuit 150, a signal generator 160, a selection circuit 120 and a gate driver 110.

The voltage divider circuit is composed of feedback resistors RF1 and RF2 and generates a first voltage signal by dividing the DC output voltage VOUT. The signal generator 160 generates a duty ratio that varies depending on the magnitude of the ramp signal VRAMP, the clock signal CLK, and the DC input voltage VIN based on the DC input voltage VIN and the first reference voltage VREF1. Lt; RTI ID = 0.0 > VDUTY < / RTI > The frequency compensation circuit performs frequency compensation on the first voltage signal to generate a first feedback voltage VEA. The first comparator 130 compares the first feedback voltage VEA with the ramp signal VRAMP to generate a pulse width modulated signal VPWM. The transient response feedback circuit 150 generates a comparison output signal VCOMP by comparing the DC output voltage VOUT with the first reference voltage and generates a comparison output signal VCOMP based on the pulse width modulation signal VPWM and the comparison output signal VCOMP And generates a transient response control signal VFAST. The selection circuit 120 selects one of the pulse width modulation signal VPWM and the comparison output signal VCOMP in response to the transient response control signal VFAST and outputs it as the gate control signal VG. The gate driver 110 generates the switch driving signals PDRV and NDRV based on the gate control signal VG.

The frequency compensation circuit may include an error amplifier 140, a first capacitor CZ1, a first resistor RZ1, and a second capacitor CP.

The error amplifier 140 has a first input terminal to which the first voltage signal is applied, a second input terminal to which a first reference voltage VREF1 is applied, and a second input terminal to which the first voltage signal and the first reference voltage VREF1 And amplifies the difference to generate the first feedback voltage VEA. The first capacitor CZ1 and the first resistor RZ1 are connected in series between the first input terminal of the error amplifier 140 and the output terminal of the error amplifier 140. [ The second capacitor CP is connected between the first input terminal of the error amplifier 140 and the output terminal of the error amplifier 140.

A load RL may be connected between the output node N3 of the buck converter 100 and ground. The buck converter 100 may further include a ramp signal generator 160 for generating a ramp signal VRAMP.

The operation of the buck converter 100 of FIG. 1 is as follows.

First, when the first switch driving signal PDRV is activated and the second switch driving signal NDRV is inactivated, the PMOS transistor MP1 is turned on and the NMOS transistor MN1 is turned off. The inductor L1 converts the electric energy into a form of a magnetic energy corresponding to the current and stores the same in the inductor L1. The longer the activation period is, the more the magnetic energy stored in the inductor L1 gradually increases.

Next, when the first switch driving signal PDRV is inactivated and the second switch driving signal NDRV is activated, the PMOS transistor MP1 is turned off and the NMOS transistor MN1 is turned on. Therefore, the current of the inductor L1 flows through the feedback circuit composed of the NMOS transistor MN1, the inductor L1 and the feedback resistors RF1 and RF2. In addition, the inductor current IL charges the capacitor CO.

2 is a circuit diagram showing one example of the signal generator 160 included in the buck converter of FIG.

2, the signal generator 160 includes PMOS transistors MP11, MP12, MP13 and MP14, a current source IB1, slave current sources IS1 and IS2, capacitors CP, C1, C2 and C3, An NMOS transistor MN11, resistors R1 to R7, comparators 161, 162 and 163, and an R / S flip-flop 164.

The source terminals of the PMOS transistors MP11, MP12, MP13 and MP14 are connected to the DC input voltage VIN. The PMOS transistors MP11, MP12, MP13 and MP14 are connected to each other in the form of a current mirror . The source terminal and the drain terminal of the PMOS transistor MP11 are connected to each other and connected to the first terminal of the current source IB1. And the second terminal of the current source IB1 is connected to the ground. The capacitor CP is connected between the drain terminal of the PMOS transistor MP12 and ground, and outputs the ramp signal VRAMP. The NMOS transistor MN11 has a gate terminal to which the output signal of the R / S flip-flop 164, i.e., the clock signal CLK, is applied, a drain terminal connected to the drain terminal of the PMOS transistors MP12, . The capacitor CP is charged by the PMOS transistor MP12 and discharged by the NMOS transistor MN11.

In FIG. 2, the resistors R1, R2, R3, and R4 function to determine the voltage level of the comparison input signal of the comparators 161, 162, and 163. The resistors R1 and R2 are connected to each other in series and connected between the drain terminal of the PMOS transistor MP13 and the ground. The resistors R3 and R4 are connected to each other in series and connected between the drain terminal of the PMOS transistor MP14 and the ground. The resistors R5, R6 and R7 and the capacitors C1, C2 and C3 serve to reduce the noise of the signal generator 160. [

The resistor R4 is connected to the inverted input terminal of the comparator 163 and determines the lower limit VL of the ramp signal VRAMP and the resistors R3 and R4 are connected to the inverting input terminal of the comparator 163, Inverted input terminal of the inverter 162 and determines the upper limit VH of the ramp signal VRAMP. The non-inverting input terminal of the comparator 163 and the inverting input terminal of the comparator 162 receive the ramp signal VRAMP. The comparator 163 compares the ramp signal VRAMP with the lower limit value VL to generate a first comparison output and the comparator 162 compares the ramp signal VRAMP with the upper limit value VH, . The R / S flip-flop 164 generates the clock signal (CLK) based on the first comparison output and the second comparison output.

In FIG. 2, the slave current sources IS1 and IS2, the resistors R1 and R2, and the comparator 161 are used to generate the duty signal VDUTY. The slave current sources IS1 and IS2 may be connected in series to each other and connected between the DC input voltage VIN and ground and the connection point of the slave current sources IS1 and IS2 may be connected to the drain terminal of the PMOS transistor MP13 . The slave current source IS1 generates a current that changes in response to the reference voltage VREF1 and the slave current source IS2 can generate a current that changes in response to a signal proportional to the DC input voltage VIN. For example, the slave current source IS2 may generate a varying current in response to half of the DC input voltage VIN (VIN / 2). The comparator 161 compares the ramp signal VRAMP with the first voltage signal VM to generate the duty signal VDUTY. The magnitude of the first voltage signal VM can be determined by the magnitude of the current flowing through the resistors R1 and R2 and the slave current sources IS1 and IS2. The magnitude of the first voltage signal VM may have a voltage level between the lower limit value VL and the upper limit value VH. Therefore, the resistor R4 may have a resistance value such as the resistor R2, and the resistor R3 may have a resistance value larger than the resistor R1. For example, the resistor R3 may have a resistance value twice that of the resistor R1. Also, the magnitude of the first voltage signal VM used as the comparison input signal of the comparator 161 is changed according to the magnitude of the current flowing through the slave current sources IS1 and IS2. For example, when the DC input voltage VIN increases and the magnitude of the current flowing through the current source IS2 increases, the magnitude of the first voltage signal VM decreases. In addition, when the magnitude of the reference voltage VREF1 increases and the magnitude of the current flowing through the dependent current source IS1 increases, the magnitude of the first voltage signal VM increases.

Therefore, the duty ratio of the duty signal VDUTY can be changed in response to the DC input voltage VIN and the reference voltage VREF1. Thus, the duty signal VDUTY may have the target duty ratio information of the buck converter 100 of FIG.

FIG. 3 is a circuit diagram illustrating one example of a transient response feedback circuit included in the buck converter 100 of FIG.

Referring to FIG. 3, the transient response feedback circuit 150a may include a second comparator 153 and a duty-based transient response control circuit 151.

The second comparator 153 compares the DC output voltage VOUT with the first reference voltage VREF1 to generate the comparison output signal VCOMP. Based on the clock signal CLK, the duty signal VDUTY, the pulse width modulation signal VPWM and the comparison output signal VCOMP, the duty-based transient response control circuit 151 generates a transient response control signal VFAST ).

According to the embodiment, the transient response feedback circuit 150a can detect the comparison output signal VCOMP using the clock signal CLK and detect the pulse width modulated signal VPWM using the duty signal VDUTY have.

According to the embodiment, the transient response feedback circuit 150a can enable the transient response control signal VFAST when a pulse of the comparison output signal VCOMP does not occur during one period of the clock signal CLK. When the transient response control signal VFAST is enabled, the comparison output signal VCOMP is output as the gate control signal VG, and when the transient response control signal VFAST is disabled, (VG).

According to the embodiment, the duty ratio of the duty signal VDUTY can be adjusted. Further, the duty ratio of the duty signal VDUTY may be determined based on the DC input voltage VIN and the first reference voltage VREF1.

4 is a circuit diagram showing another example of the transient response feedback circuit included in the buck converter 100 of FIG.

4, the transient response feedback circuit 150b may include a pre-amplifier 154, a second comparator 153 and a duty-based transient response control circuit 151. The pre-

The preamplifier 154 amplifies the difference between the DC output voltage VOUT and the first reference voltage VREF1 to generate a pair of differential output signals. The second comparator 153 compares the differential output signal pairs with each other to generate a comparison output signal VCOMP. Based on the clock signal CLK, the duty signal VDUTY, the pulse width modulation signal VPWM and the comparison output signal VCOMP, the duty-based transient response control circuit 151 generates a transient response control signal VFAST ). The transient response feedback circuit 150b of FIG. 4 may further include a preamplifier 154 to reduce the DC offset of the second comparator 153.

5 is a circuit diagram showing another example of the transient response feedback circuit included in the buck converter 100 of FIG.

5, the transient response feedback circuit 150c includes a first resistor RLPF, a first capacitor CLPF, a second resistor RF3, a third resistor RF4, a pre-amplifier 154, a second comparator 153 and a duty-based transient response control circuit 151.

The first resistor RLPF has a first terminal to which the direct current output voltage VOUT is applied and a second terminal connected to the first input terminal of the preamplifier 154. The first capacitor CLPF is connected between the second terminal of the first resistor RLPF and ground. The second resistor RF3 has a first terminal to which a first reference voltage VREF1 is applied and a second terminal connected to a second input terminal of the preamplifier 154. [ The third resistor RF4 is connected between the first reference voltage VREF1 and ground. The preamplifier 154 amplifies the difference between the DC output voltage VOUT and the first reference voltage VREF1 to generate a pair of differential output signals. The second comparator 153 compares the differential output signal pairs with each other to generate a comparison output signal VCOMP. Based on the clock signal CLK, the duty signal VDUTY, the pulse width modulation signal VPWM and the comparison output signal VCOMP, the duty-based transient response control circuit 151 generates a transient response control signal VFAST ).

FIGS. 6 to 9 are timing charts for explaining the operation of the buck converter 100 shown in FIG.

Referring to FIG. 6, each of the clock signal CLK and the duty signal VDUTY has a constant period, and the duty signal VDUTY has a duty ratio that is greater than the clock signal CLK. The ramp signal VRAMP oscillates in synchronization with the clock signal CLK and can have a waveform of a triangle wave.

Referring to FIG. 7, the transient response feedback circuit 150 detects the comparison output signal VCOMP using the clock signal CLK and outputs a pulse of the comparison output signal VCOMP during one period of the clock signal CLK If it does not occur, the transient response control signal VFAST can be enabled. For example, when a pulse of the comparison output signal VCOMP does not occur during one period of the clock signal CLK, the transient response feedback circuit 150 changes the transient response control signal VFAST to logic "1 ". When the pulse of the comparison output signal VCOMP is not generated during one cycle of the clock signal CLK, the voltage of the output node N3, that is, the voltage level of the DC output voltage VOUT, . ≪ / RTI >

When the transient response control signal VFAST is enabled, the comparison output signal VCOMP is output as the gate control signal VG, and when the transient response control signal VFAST is disabled, (VG). When the transient response control signal VFAST is enabled, the switching DC-DC converter 100 may have a fast transient response characteristic.

Referring to FIG. 8, the transient response feedback circuit 150 can detect the pulse width modulation signal VPWM using the clock signal CLK.

The buck converter 100 operates in a fast transient response mode of operation and samples the pulse width modulated signal VPWM at the rising edge of the duty signal VDUTY and the logic state of the sampled pulse width modulated signal VPWM is in the first state The transient response feedback circuit 150 may disable the transient response control signal VFAST. When the transient response control signal VFAST is disabled, the switching DC-DC converter 100 can operate in the normal operation mode.

9, if the DC output voltage VOUT of the buck converter 100 increases and an abnormal operation is detected and the comparison output signal VCOMP continues to have a logic "1" state, the transient response control signal VFAST Is enabled, and the buck converter 100 can operate in a fast transient response mode of operation. Thereafter, when the pulse width modulation signal VPWM is sampled at the rising edge of the duty signal VDUTY and the logic state of the sampling result pulse width modulation signal VPWM changes from the first state to the second state, the transient response feedback circuit 150 May disable the transient response control signal VFAST. In the example of FIG. 9, it can be seen that the logic state of the pulse width modulation signal VPWM changes from logic "1" to logic "0 ", and the transient response control signal VFAST is disabled. Thus, the switching DC-DC converter 100 can operate in the normal operation mode.

10 is a circuit diagram showing a dual mode buck converter 200 according to another embodiment of the present invention.

The dual mode buck converter 200 of FIG. 10 has a structure in which a resistor RZ2 and a capacitor CZ2 are connected in series to both ends of a resistor RF1 constituting a feedback circuit in the dual mode buck converter 100 of FIG. 1 . The dual mode buck converter 200 having the structure of FIG. 8 can reduce the noise of the DC output voltage VOUT.

11 is a circuit diagram illustrating a dual mode buck converter 300 according to another embodiment of the present invention.

In the dual mode buck converter 100 of FIG. 1, the first comparator 130 compares the first feedback voltage VEA with the ramp signal VRAMP to generate the pulse width modulated signal VPWM, The comparator 130a of the dual mode buck converter 300 compares the first feedback voltage VEA with the second reference voltage VREF2 to generate a pulse width modulated signal VPWM. The remaining circuit configuration of FIG. 9 except for the comparator 130a is the same as the circuit configuration of FIG.

12 is a circuit diagram showing a dual mode buck converter 400 according to another embodiment of the present invention. The dual-mode buck converter 400 of FIG. 12 differs from the circuit of FIG. 1 in the configuration of the power conversion section. The power conversion unit of FIG. 12 may include a PMOS transistor MP1, a diode D1, an inductor L1 and a capacitor CO.

The PMOS transistor MP1 is connected between the first node N1 and the second node N2 to which the DC input voltage VIN is applied and operates in response to the first switch driving signal PDRV. Diode D1 is connected between the second node N2 and ground. The inductor L1 is connected between the second node N2 and the output node N3 and the capacitor CO is connected between the output node N3 and the ground.

13 is a circuit diagram showing a dual mode boost converter 500 according to one embodiment of the present invention.

Referring to FIG. 13, the dual-mode boost converter 500 may include a switch driver and a power converter.

The power conversion section generates the DC output voltage VOUT based on the switch driving signals PDRV, NDRV and the DC input voltage VIN. The switch driving unit generates the first feedback voltage VEA by performing frequency compensation on the DC output voltage VOUT and compares the first feedback voltage VEA with the reference voltage VREF2 to generate the pulse width modulation signal VPWM, Generates the comparison output signal VCOMP by comparing the DC output voltage VOUT with the reference voltage VREF1 and generates the switch driving signals PDRV and NDRV based on the pulse width modulation signal VPWM in normal operation, And generates switch driving signals PDRV and NDRV based on the comparison output signal VCOMP in the abnormal operation.

The abnormal operation may include a momentary change in the voltage level of the DC output voltage VOUT due to a change in the load current.

The power conversion unit includes an inductor L2 connected between the first node N11 and the second node N12 to which the DC input voltage VIN is applied, a second node N12 connected between the second node N12 and the output node N13, A PMOS transistor MP2 that operates in response to the first switch driving signal PDRV, an NMOS transistor MN2 that is connected between the second node N12 and ground and operates in response to the second switch driving signal NDRV, And a capacitor CO connected between the output node N13 and ground.

The switch driver may include a voltage divider circuit, a frequency compensation circuit, a first comparator 530, a transient response feedback circuit 550, a signal generator 160 selection circuit 520 and a gate driver 510.

The voltage divider circuit is composed of feedback resistors RF1 and RF2 and generates a first voltage signal by dividing the DC output voltage VOUT. The signal generator 560 generates a duty signal VDUTY having a duty ratio that varies according to the magnitude of the DC input voltage VIN and the clock signal CLK based on the DC input voltage VIN and the first reference voltage VREF1, ). ≪ / RTI > The frequency compensation circuit performs frequency compensation on the first voltage signal to generate a first feedback voltage VEA. The first comparator 530 compares the first feedback voltage VEA with the reference voltage VREF2 to generate the pulse width modulated signal VPWM. The transient response feedback circuit 550 generates the comparison output signal VCOMP by comparing the DC output voltage VOUT with the reference voltage VREF1 and generates the comparison output signal VCOMP based on the pulse width modulation signal VPWM and the comparison output signal VCOMP And generates a transient response control signal VFAST. The selection circuit 520 selects one of the pulse width modulation signal VPWM and the comparison output signal VCOMP in response to the transient response control signal VFAST and outputs it as the gate control signal VG. The gate driver 510 generates the switch driving signals PDRV and NDRV based on the gate control signal VG.

The frequency compensation circuit may include an error amplifier 540, a first capacitor CZ1, a first resistor RZ1, and a second capacitor CP.

The error amplifier 540 has a first input terminal to which the first voltage signal is applied and a second input terminal to which the first reference voltage VREF1 is applied and a difference between the first voltage signal and the reference voltage VREF1 And generates a first feedback voltage VEA. The first capacitor CZ1 and the first resistor RZ1 are connected in series between the first input terminal of the error amplifier 140 and the output terminal of the error amplifier 540. [ The second capacitor CP is connected between the first input terminal of the error amplifier 540 and the output terminal of the error amplifier 540.

A load RL may be connected between the output node N13 of the boost converter 500 and ground.

The operation of the boost converter 500 of FIG. 13 is as follows.

First, when the second switch driving signal NDRV is activated and the first switch driving signal PDRV is inactivated, the NMOS transistor MN2 is turned on and the PMOS transistor MP2 is turned off. Therefore, the inductor current IL flows through the inductor L2 and the NMOS transistor MN2. At this time, the inductor L2 converts the electric energy into a form of magnetic energy corresponding to the current and stores it. Accordingly, as the activation period of the second switch driving signal NDRV becomes longer, the magnetic energy stored in the inductor L2 gradually increases.

Next, when the second switch driving signal NDRV is inactivated and the first switch driving signal PDRV is activated, the NMOS transistor MN2 is turned off and the PMOS transistor MP2 is turned on. Therefore, the current of the inductor L2 flows through the feedback circuit composed of the PMOS transistor MP2 and the feedback resistors RF1 and RF2. In addition, the inductor current charges the capacitor CO. Here, the magnetic energy stored in the inductor L2 decreases at the same rate as it increases.

The boost converter 500 increases the direct current output voltage VOUT by increasing the electromotive force of the inductor L2 when the duty ratio of the second switch driving signal NDRV becomes high and the duty ratio of the second switch driving signal NDRV is low The electromotive force of the ground inductor L2 is reduced to reduce the DC output voltage VOUT.

The duty ratio of the first switch driving signal PDRV and the second switch driving signal NDRV is changed according to the magnitude of the feedback voltage obtained by dividing the DC output voltage VOUT, as shown in FIG.

FIG. 14 is a timing chart for explaining the operation of the boost converter 500 shown in FIG.

14, if the DC output voltage VOUT of the boost converter 500 decreases and an abnormal operation is detected and the comparison output signal VCOMP continues to have a logic "0" state, the transient response control signal VFAST Is enabled, and the boost converter 500 can operate in a fast transient response mode of operation. Thereafter, when the pulse width modulation signal VPWM is sampled at the rising edge of the duty signal VDUTY and the logic state of the sampling result pulse width modulation signal VPWM changes from the first state to the second state, the transient response feedback circuit 150 May disable the transient response control signal VFAST. In the example of Fig. 14, it can be seen that the logic state of the pulse width modulation signal VPWM changes from a logic "0" to a logic "1 ", and the transient response control signal VFAST is disabled. Thus, the boost converter 500 can operate in a normal operating mode.

15 is a circuit diagram showing a dual-mode boost converter 600 according to another embodiment of the present invention. The dual-mode boost converter 600 of FIG. 15 differs from the circuit of FIG. 13 in the configuration of the power conversion section. The power conversion unit of Fig. 15 may include an inductor L2, an NMOS transistor MN2, a diode D2, and a capacitor CO.

The NMOS transistor MN2 is connected between the second node N12 and ground, and operates in response to the second switch driving signal NDRV. The diode D2 is connected between the second node N12 and the thrust node N13. The inductor L2 is connected between the first node N11 and the second node N12 to which the DC input voltage VIN is applied and the capacitor CO is connected between the output node N13 and the ground.

16 is a flowchart illustrating a method of controlling a dual-mode switching DC-DC converter according to an embodiment of the present invention.

Referring to FIG. 16, a method of controlling a switching DC-DC converter according to an embodiment of the present invention may include the following operations.

1) Frequency compensation is performed on the DC output voltage to generate a first feedback voltage (S1).

2) The first feedback voltage is compared with a comparison input signal to generate a pulse width modulated signal (S2).

3) The DC output voltage is compared with the first reference voltage to generate a comparison output signal (S3).

4) generates a switch driving signal based on the pulse width modulation signal in normal operation, and generates the switch driving signal based on the comparison output signal in an abnormal operation (S4).

5) The DC output voltage is generated based on the switch driving signal and the DC input voltage (S5).

17 is a flowchart showing a step of generating a switch driving signal in the control method of the dual mode switching DC-DC converter of FIG.

Referring to FIG. 17, a method of generating a switch driving signal according to an embodiment of the present invention may include the following operations.

1) detects a rising edge of the comparison output signal during one period of the clock signal (S41).

2) Whether a rising edge of the comparison output signal exists (S42).

3) If there is a rising edge of the comparison output signal, the transient response control signal is disabled, and the duty cycle of the switch driving signal is controlled based on the pulse width modulation signal (S43).

4) If there is no rising edge of the comparison output signal, the transient response control signal is enabled, and the duty cycle of the switch driving signal is controlled based on the comparison output signal (S47).

5) It is determined whether the value of the comparison output signal is "0" (S44).

6) If the value of the comparison output signal is not "0 ", it is determined whether the value of the pulse width modulation signal is" 0 "at the rising edge of the duty signal (S45).

7) If the value of the pulse width modulation signal at the rising edge of the duty signal is "0 ", S47 is performed. If the value of the pulse width modulation signal at the rising edge of the duty signal is not & S43.

8) If the value of the comparison output signal is "0 ", it is determined whether the value of the pulse width modulation signal is" 1 "at the rising edge of the duty signal (S46).

9) If the value of the pulse width modulation signal at the rising edge of the duty signal is "1 ", S47 is performed, and if the value of the pulse width modulation signal at the rising edge of the duty signal is not & S43.

18 and 19 are simulation diagrams showing transient response characteristics of a switching DC-DC converter according to an embodiment of the present invention. FIG. 18 shows the relationship between the DC output voltage VOUT (VOUT) when the load current of the buck converter increases from 500 mA to 1 mA and then decreases to 500 mV when the DC input voltage (VIN) is 3.3 V and the DC output voltage ). ≪ / RTI > 19 is a graph showing the relationship between the DC output voltage VOUT (VOUT) when the load current of the buck converter increases from 500 mA to 1 mA and then decreases to 500 mV when the DC input voltage VIN is 3.3 V and the DC output voltage VOUT is 2.1 V ). ≪ / RTI >

Referring to FIGS. 18 and 19, the DC output voltage VOUT of the switching DC-DC converter according to embodiments includes a duty-based transient response control circuit 151, Mode, it can be seen that the fluctuation of the DC output voltage is reduced and the recovery time is reduced as compared with the conventional switching DC-DC converter.

The present invention can be applied to a power converter, and particularly applicable to a switching DC-DC converter.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims It can be understood that

100, 200, 300, 400: Buck converter
110, 510: gate driver
120, 520: selection circuit
130, 530: comparator
140, 540: error amplifier
150, 550: Transient response feedback circuit
160, 560: Signal generator
500, 600: Boost converter

Claims (10)

A power converter for generating a DC output voltage based on a switch driving signal and a DC input voltage; And
Generating a first feedback voltage by performing frequency compensation on the DC output voltage, comparing the first feedback voltage with a comparison input signal to generate a pulse width modulation signal, comparing the DC output voltage with a first reference voltage And a switch driver for generating the switch driving signal based on the pulse width modulation signal in normal operation and generating the switch driving signal based on the comparison output signal in abnormal operation, DC to DC converters. The method according to claim 1,
Wherein the abnormal operation includes a momentary change in the voltage level of the DC output voltage due to a change in the load current. The apparatus of claim 1, wherein the switch driver
A voltage divider circuit for dividing the DC output voltage to generate a first voltage signal;
A signal generator for generating a duty signal having a duty ratio that varies according to the magnitude of the ramp signal, the clock signal, and the DC input voltage based on the DC input voltage and the first reference voltage;
A frequency compensation circuit for performing frequency compensation on the first voltage signal to generate the first feedback voltage;
A first comparator for comparing the first feedback voltage to the ramp signal to generate the pulse width modulated signal;
Generating a comparison output signal by comparing the DC output voltage with the first reference voltage and generating a transient response control signal based on the clock signal, the duty signal, the pulse width modulated signal, and the comparison output signal; Response feedback circuit;
A selection circuit for selecting one of the pulse width modulation signal and the comparison output signal in response to the transient response control signal and outputting the selected signal as a gate control signal; And
And a gate driver for generating the switch driving signal based on the gate control signal. 4. The apparatus of claim 3, wherein the signal generator
A first comparator for comparing the ramp signal with a lower limit to generate a first comparison output;
A second comparator for comparing the ramp signal with an upper limit to generate a second comparison output;
A flip-flop for generating the clock signal based on the first comparison output and the second comparison output; And
And a third comparator for comparing the ramp signal with a first voltage signal having a duty ratio that varies according to a magnitude of the DC input voltage to generate the duty signal. 4. The apparatus of claim 3, wherein the transient response feedback circuit
A second comparator for comparing the DC output voltage with the first reference voltage to generate the comparison output signal; And
And a duty-based transient response control circuit for generating the transient response control signal based on the clock signal, the duty signal, the pulse width modulated signal, and the comparison output signal. DC converter. 4. The apparatus of claim 3, wherein the transient response feedback circuit
And the transient response control signal is enabled when a pulse of the comparison output signal is not generated during one period of the clock signal. The method of claim 3,
Wherein the comparison output signal is output as the gate control signal when the transient response control signal is enabled and the pulse width modulated signal is output as the gate control signal when the transient response control signal is disabled. - DC converters. The method of claim 3,
And the switching DC-DC converter has a fast transient response characteristic when the transient response control signal is enabled. The method of claim 3,
Wherein the switching DC-DC converter is operating in a fast transient response mode of operation, sampling the pulse width modulated signal at a rising edge of the duty signal, and sampling the logic state of the pulse width modulated signal from a first state to a second state The transient response feedback circuit disables the transient response control signal. Performing frequency compensation on the DC output voltage to generate a first feedback voltage;
Comparing the first feedback voltage to a comparison input signal to generate a pulse width modulated signal;
Comparing the DC output voltage with a first reference voltage to generate a comparison output signal;
Generating a switch driving signal based on the pulse width modulation signal in normal operation and generating the switch driving signal based on the comparison output signal in an abnormal operation; And
And generating the direct current output voltage based on the switch driving signal and the direct current input voltage.

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