KR20150078165A - Semiconductor memory device, memory system including the same and operating method thereof - Google Patents

Abstract

The present invention relates to a semiconductor memory device, a memory system including the same, and an operating method thereof. The memory system comprises: a semiconductor memory device which has a cam data block for storing cam data; and a controller which controls the operation of the semiconductor memory device when a cam data program command is received from a host, wherein the semiconductor memory device is configured to program the cam data after performing pre-programming and erasing operations when the cam data program command is received.

Description

TECHNICAL FIELD [0001] The present invention relates to a semiconductor memory device, a memory system including the memory device, and a method of operating the same. BACKGROUND OF THE INVENTION [0002]

The present invention relates to a semiconductor memory device, a memory system including the same, and a method of operating the same.

A semiconductor memory device is a memory device implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP) to be. Semiconductor memory devices are classified into a volatile memory device and a nonvolatile memory device.

The volatile memory device is a memory device in which data stored in the volatile memory device is lost when power supply is interrupted. Volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). A nonvolatile memory device is a memory device that retains data that has been stored even when power is turned off. A nonvolatile memory device includes a ROM (Read Only Memory), a PROM (Programmable ROM), an EPROM (Electrically Programmable ROM), an EEPROM (Electrically Erasable and Programmable ROM), a flash memory, a PRAM , RRAM (Resistive RAM), and FRAM (Ferroelectric RAM). Flash memory is divided into NOR type and NOR type.

The flash memory device can be divided into a two-dimensional semiconductor device in which a string is formed horizontally on a semiconductor substrate and a three-dimensional semiconductor device in which the string is formed perpendicularly to the semiconductor substrate.

A three-dimensional semiconductor device is a memory device designed to overcome the limit of integration of a two-dimensional semiconductor device, and includes a plurality of strings formed vertically on a semiconductor substrate. The strings include a drain select transistor, memory cells, and a source select transistor connected in series between the bit line and the source line.

The above-described three-dimensional semiconductor device can be constituted by a charge trap memory cell. A three-dimensional semiconductor device composed of charge trap memory cells is formed of a charge storage cell type memory cell for storing a CAM (Contents Addressable Memory) data. When such a charge trap memory cell is used as a cam cell, when the cam data is programmed in the erased cam cell before the packaging process of the memory chip, the cam data is transferred by the subsequent high temperature packaging process to the trap Electrons move within the charge storage layer or recombine with the holes, thereby changing the threshold voltage of the charge trap memory cell. This may cause errors in the cam data programmed in the charge trap memory cell.

The present invention provides a semiconductor memory device capable of being programmed to stabilize cam data programmed in a cam cell, a memory system including the same and an operation method thereof.

A memory system according to the present invention includes a semiconductor memory device including a cam data block for storing cam data and a controller for controlling operation of the semiconductor memory device when a cam data program command is received from the host, The memory device programs the cam data after preceding the pre-program operation and the erase operation when the cam data program instruction is received.

A semiconductor memory device according to the present invention includes a memory cell array including a cam data block and a peripheral circuit and a cam data program command for performing a pre-program operation, an erase operation, and a cam data program operation of the cam data block And control logic for controlling the peripheral circuit to perform the cam data program operation after performing the pre-program operation and the erase operation before the cam data program operation.

A method of operating a semiconductor memory device according to the present invention includes the steps of providing a semiconductor memory device including a cam data block, inputting a cam data program command, and performing a pre-program operation and an erase operation on the cam data block And programming the cam data in the cam data block.

According to the present invention, the characteristics of the charge trap memory cell are improved by preceding the pre-program operation and the erase operation before the cam cell data is programmed in the charge trap memory cell, thereby improving the error of the cam data programmed into the charge trap memory cell The phenomenon is improved.

1 is a block diagram showing a memory system including a semiconductor memory device.
2 is a block diagram showing the semiconductor memory device of FIG. 1 in more detail.
3 is a perspective view showing a memory cell array according to an embodiment of the present invention.
4 is a cross-sectional view illustrating the penetrating structure by enlarging the area A shown in FIG.
5A to 5D are block diagrams of elements for explaining the operation of the charge trap memory cell.
6 is a flowchart for explaining cam data program operation according to the present invention.
7A to 7E are block diagrams of elements for explaining the cam data programming operation of the charge trap memory cell according to the present invention.
8 is a block diagram showing a memory system including the semiconductor memory device of FIG.
9 is a block diagram showing an application example of the memory system of FIG.
10 is a block diagram illustrating a computing system including the memory system described with reference to FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish it, will be described with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. The embodiments are provided so that those skilled in the art can easily carry out the technical idea of the present invention to those skilled in the art.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "indirectly connected" . Throughout the specification, when an element is referred to as "comprising ", it means that it can include other elements as well, without excluding other elements unless specifically stated otherwise.

1 is a block diagram showing a memory system including a semiconductor memory device.

Referring to FIG. 1, a memory system 10 includes a semiconductor memory device 100 and a controller 200. The semiconductor memory device 100 includes a memory cell array 110 and a read and write circuit 130 connected to the memory cell array 110.

The memory cell array 110 includes a plurality of memory cells. Each of the plurality of memory cells may be defined as a multi level memory cell storing two or more data bits.

The semiconductor memory device 100 operates in response to the control of the controller 200. Semiconductor memory device 100 is configured to perform a cam data program operation on memory cells (selected memory cells) indicated by the address received with the instruction when a cam data program instruction from controller 200 is received. At this time, the semiconductor memory device 100 repeats the pre-program operation and the erase operation in the cam data program operation a predetermined number of times, and then performs the cam data program operation.

As an example, the semiconductor memory device 100 may be a flash memory device. However, it will be understood that the technical spirit of the present invention is not limited to flash memory devices.

The controller 200 is connected between the semiconductor memory device 100 and the host. The controller 200 is configured to interface the semiconductor memory device 100 with a host. For example, at the time of the cam data program operation in response to a request from the host, the controller 200 sets the logical block address (physical block address) received from the host as the physical block address And provides the converted physical block address to the semiconductor memory device 100 together with the command.

As an example, the controller 200 includes an error correction block 210. The error correction block 210 is configured to detect and correct errors in data received from the semiconductor memory device 100. The error correction function performed by the error correction block 210 is limited by the number of error bits in the data received from the semiconductor memory device 100. [ When the number of error bits in the data received from the semiconductor memory device 100 is smaller than a certain value, the error correction block 210 performs an error detection and correction function. When the number of error bits in the data received from semiconductor memory device 100 is larger than a certain value, error detection and correction can not be performed. When error detection and correction can not be performed, the controller 200 controls the semiconductor memory device 100 to adjust the read voltage applied to the selected word line.

2 is a block diagram showing the semiconductor memory device of FIG. 1 in more detail.

2, the semiconductor memory device 100 includes a memory cell array 110, an address decoder 120, a read and write circuit 130, a control logic 140, and a voltage generator 150 .

The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. At least one of the plurality of memory blocks BLK1 to BLKz is defined as a cam block to which the cam data is programmed. For example, in the embodiment of the present invention, the last memory block BLKz among the plurality of memory blocks BLK1 to BLKz is defined as a cam block. The plurality of memory blocks BLK1 to BLKz are connected to the address decoder 120 via the word lines WL. The plurality of memory blocks BLK1 to BLKz are connected to the read and write circuit 130 via bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. In an embodiment, the plurality of memory cells are charge trap memory cells having a three-dimensional structure. A plurality of memory cells are defined as one page of memory cells connected to the same word line. That is, the memory cell array 110 is composed of a plurality of pages.

In the embodiment of the present invention, a plurality of memory cells are defined as charge trap memory cells having a three-dimensional structure, but charge trap memory cells having a SONOS or MANOS structure having a two-dimensional structure are also applicable to the embodiments of the present invention .

The address decoder 120, the read and write circuit 130, and the voltage generator 150 operate as peripheral circuits for driving the memory cell array 110.

The address decoder 120 is coupled to the memory cell array 110 via word lines WL. The address decoder 120 is configured to operate in response to control of the control logic 140. The address decoder 120 receives the address ADDR through an input / output buffer (not shown) in the semiconductor memory device 100. The address ADDR is provided from the controller 200 (see FIG. 1).

The address decoder 120 decodes the row address of the address ADDR received during the pre-program operation and the cam data program operation and supplies the selected word line to a voltage generator (not shown) in accordance with the decoded row address 150, and applies the pass voltage Vpass to the remaining unselected word lines.

The address decoder 120 is configured to decode the column address of the received address ADDR. The address decoder 120 sends the decoded column address Yi to the read and write circuit 130.

The pre-program operation and the cam data program operation of the semiconductor memory device 100 are performed page by page. In addition, since the pre-program operation is to program the same data, it is programmable in block units. The address decoder 120 selects one memory block and one word line in accordance with the block address and the row address. The column address is decoded by the address decoder 120 and provided to the read and write circuit 130.

The address decoder 120 may include a block decoder, a row decoder, a column decoder, and an address buffer.

The read and write circuit 130 includes a plurality of page buffers PB1 to PBm. The plurality of page buffers PB1 to PBm are connected to the memory cell array 110 through bit lines BL1 to BLm. Each of the plurality of page buffers PB1 to PBm receives the pre-program data (for example, 0 data) set during the pre-program operation and temporarily stores the data, and controls the potential of the corresponding bit line to the program allowable voltage. Each of the plurality of page buffers PB1 to PBm receives and temporarily stores the cam data DATA during the cam data program operation and controls the potential of the corresponding bit line to the program allowable voltage or the program inhibit voltage.

The read and write circuitry 130 operates in response to control of the control logic 140.

As an example embodiment, the read and write circuitry 130 may include page buffers (or page registers), column select circuitry, and the like.

The control logic 140 is coupled to the address decoder 120, the read and write circuit 130, and the voltage generator 150. The control logic 140 receives the command CMD and the control signal CTRL through an input / output buffer (not shown) of the semiconductor memory device 100. [ The command CMD and the control signal CTRL are provided from the controller 200 (see FIG. 1). The control logic 140 is configured to control all operations of the semiconductor memory device 100 in response to the command CMD and the control signal CTRL. The control logic 140 also controls the address decoder 120, the read and write circuit 130 and the voltage generator 150 to generate a command signal CMD The pre-program operation and the erase operation are performed for the memory block BLKz a predetermined number of times, and then the cam data program operation is performed.

The voltage generator 150 generates the program voltage Vpgm and the pass voltage Vpass during the pre-program operation and the cam data program operation. The voltage generator 150 generates a plurality of program voltages Vpgm sequentially increasing according to the control of the control logic 140 during an incremental step pulse program (ISPP) program operation.

3 is a perspective view showing a memory cell array according to an embodiment of the present invention.

In FIG. 3, the illustration of the insulating film is omitted for convenience of explanation.

3, a semiconductor memory device according to the present invention includes a substrate 11, a pipe gate PG, a plurality of conductive patterns 13, at least one drain select line (DSL) A source selection line (SSL), and a U-shaped penetrating structure 12 through a plurality of conductive patterns 13 and a pipe gate (PG).

Here, the plurality of conductive patterns 13, the drain select line DSL, and the source select line SSL are stacked while surrounding the through-hole structure 12. The U-shaped penetrating structure 12 is connected to the bit lines BL and the source line SL.

 According to such a structure, a source selection transistor is formed at a position where the source side channel layer S_CH and the through structure 12 intersect, and a source selection transistor is formed at a position where the plurality of conductive patterns 13 cross the through structure 12 A memory cell is formed and a pipe transistor is formed at a position where the pipe gate PG and the penetrating structure 12 intersect and a drain select transistor is formed at a position where the penetrating structure 12 and the drain select line DSL intersect with each other do.

Thus, the drain select transistor, the plurality of memory cells, the pipe transistor, the plurality of memory cells and the source select transistor connected in series constitute one string, and the strings are arranged in U-shape.

Although a structure in which strings are arranged in a U-shape has been described in the embodiment of the present invention, a structure in which a common source line is formed on a semiconductor substrate 11, bit lines are formed on a common source line, By forming a string, a semiconductor memory device having a string of a straight structure can be formed.

Region A represents a partial region including a through structure to be described later.

4 is a cross-sectional view illustrating the penetrating structure by enlarging the area A shown in FIG.

4, the penetrating structure 12 includes a channel film 12a passing through the insulating patterns 14 alternately stacked with the conductive patterns 13, a tunnel insulating film (not shown) surrounding the side walls of the channel film 12a 12b, and a charge storage film 12c surrounding the tunnel insulating film 12b. The channel film 12a may be formed of a polysilicon film. The tunnel insulating film 12b may be formed of at least one of a thermal oxide film, a radical oxide film, a dry oxide film, and a wet oxide film. The charge storage film 12c may be formed of a nitride film. Also, the center region of the penetrating structure 12 may be filled with the insulating film 12d. Further, a blocking insulating film 15 and a barrier film 16 may be further formed between the conductive patterns 13 and the penetrating structure 12. [

5A to 5D are diagrams for explaining the program operation in the charge trap memory cell.

5A to 5D, a general program operation of the charge trap memory cell will be described below.

Referring to FIG. 5A, the charge trap memory cell performs an erase operation by injecting holes into the charge storage layer 12c. Therefore, the charge storage layer 12c of the charge trap memory cell in the erased state is filled with holes.

5B, when the program operation is performed on the charge trap memory cell in the erase state to inject electrons e into the charge storage layer 12c, the injected electrons e are injected into the charge storage layer 12c The threshold voltage of the charge trap memory cell is increased. At this time, an electric field (E-field) may be formed by electrons () and holes () existing in the upper and lower parts of the charge storage layer 12c.

Referring to FIG. 5C, when an external factor, for example, a temperature of the charge trap memory cell by the chip packaging process rises, electrons e and holes in the charge storage layer 12c receive energy and move The positions of the electrons e and holes are redistributed and the electrons e and holes are recombined as shown in Fig. 5d, so that even if new holes are not injected from the outside, The voltage is lowered. This may cause errors in stored data.

Since CAM (Contents Addressable Memory) data is the main information of a semiconductor memory device, reliability is more important than anything. However, when the cam data is stored in the charge trap memory cell, it is important to improve the reliability of the data stored in the charge trap memory cell because the reliability of the data is deteriorated by the heat generated in the subsequent chip packaging process.

6 is a flowchart for explaining cam data program operation according to the present invention.

7A to 7E are cross-sectional views of elements for explaining a program operation of the charge trap memory cell according to the present invention.

The operation of the semiconductor memory device according to the present invention will now be described with reference to FIGS. 1 to 4, 6, and 7A to 7E.

First, when a cam data program command is input from the host (S610), the controller 200 transmits a command (layer and cam data corresponding to the cam data program command to the semiconductor memory device 100) For example, BLKz.

The control logic 140 controls the address decoder 120, the read and write circuit 130 and the voltage generator 150 to perform a pre-program operation on the cam cell block BLKz of the semiconductor memory device 100 (S620). At this time, the cam cell block BLKz may be in an erase state. The pre-program operation programs the threshold voltage of all the memory cells in the cam cell block BLKz to a certain value (e.g., higher than 0 V). Referring to FIG. 7A, the charge storage layer 12c of the charge trap memory cell in the cam cell block BLKz is injected with electrons e due to the pre-program operation.

At this time, the pre-program operation may be performed on all the charge trap memory cells in the cam cell block BLKz or on some charge trap memory cells to be selected in the subsequent cam data program operation.

When the pre-program operation is performed for only some of the charge trap memory cells to be selected, the charge storage layer 12c of the non-selected charge trap memory cells is filled with only holes, The immunity to lead disturb is increased.

When the pre-program operation is completed, the control logic 140 controls the address decoder 120, the read and write circuit 130, and the voltage generator 150 to perform the erase operation of the cam cell block BLKz S630). Referring to FIG. 7B, in the charge storage layer 12c of the charge trap memory cell in the cam cell block BLKz, due to the erase operation, the lower electrons e are trapped or holes are injected.

The control logic 140 controls the pre-program operation S620 and the erase operation S630 of the cam cell block BLKz until the number of times of execution of the erase operation S630 is larger than the set number of times (N (N is 0 or a positive integer) The address decoder 120, the read and write circuit 130, and the voltage generator 150 so as to repeatedly perform the operation S620 and the erase operation S630.

If the pre-program operation S620 and the erase operation S630 are repeatedly performed, the charge storage layer 12c of the charge trap memory cell in the cam cell block BLKz increases in number of electrons e as shown in FIG. 7A do.

The number of times of the pre-program operation S620 and the number of times of the erase operation S630 performed as a result of comparing the number of times of the pre-program operation S620 of the cam cell block BLKz and the number of times of the erase operation S630 and the set number N The control logic 140 controls the address decoder 120, the read and write circuit 130 and the voltage generator 150 to output the cam data (DATA) to the cam cell block BLKz, (S650).

When the cam data program operation (S650) is performed within a short time after the erase operation (S630) of the cam cell block (BLKz) is completed, the charge storage layer (S650) of the charge trap memory cell in the cam cell block (BLKz) 12c are filled with electrons e, so that no electric field is generated in the charge storage layer 12c. In addition, since there is no hole, no threshold voltage change occurs according to the external temperature.

When a relatively long time passes after the erase operation (S630) of the cam cell block BLKz is completed, redistribution of electrons e and holes in the charge storage layer 12c occurs as shown in FIG. 7D . However, when the subsequent cam data program operation S650 is performed, as shown in FIG. 7E, relatively positive holes exist only in the upper portion of the charge storage layer 12c, so that recombination and rearrangement of electrons e and holes The problem that the phenomenon is reduced and the threshold voltage is lowered is also improved.

As described above, according to the semiconductor memory device and the method of operating the same according to the present invention, when the cam data is programmed in the semiconductor memory device having the charge trap memory cell, the pre-program operation and the erase operation are repeated a predetermined number of times By performing the cam data program operation, the reliability of the cam data program operation can be improved.

8 is a block diagram showing a memory system including the semiconductor memory device of FIG.

8, a memory system 1000 includes a semiconductor memory device 100 and a controller 1100.

The semiconductor memory device 100 may be configured and operated as described with reference to Fig. Hereinafter, a duplicate description will be omitted.

The controller 1100 includes the functions of the controller 200 described with reference to FIG. The controller 1100 is connected to the host (Host) and the semiconductor memory device 100. In response to a request from the host (Host), the controller 1100 is configured to access the semiconductor memory device 100. For example, the controller 1100 is configured to control the read, write, erase, and background operations of the semiconductor memory device 100. The controller 1100 is configured to provide an interface between the semiconductor memory device 100 and the host. The controller 1100 is configured to drive firmware for controlling the semiconductor memory device 100.

The controller 1100 includes a random access memory 1110, a processing unit 1120, a host interface 1130, a memory interface 1140, and an error correction block 1150 . The RAM 1110 is connected to at least one of an operation memory of the processing unit 1120, a cache memory between the semiconductor memory device 100 and the host and a buffer memory between the semiconductor memory device 100 and the host . The processing unit 1120 controls all operations of the controller 1100. In addition, the controller 1100 may temporarily store program data provided from a host in a write operation.

The host interface 1130 includes a protocol for exchanging data between the host (Host) and the controller 1100. As an exemplary embodiment, the controller 1200 may be implemented using a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI- Various interface protocols such as protocol, Serial-ATA protocol, Parallel-ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, IDE (Integrated Drive Electronics) protocol, (Host) via at least one of the following:

The memory interface 1140 interfaces with the semiconductor memory device 100. For example, the memory interface includes a NAND interface or a NOR interface.

The error correction block 1150 performs the same function as the error correction block 210 of FIG. The error correction block 1150 is configured to detect and correct errors in data received from the semiconductor memory device 100 using an error correcting code (ECC). The processing unit 1120 will control the semiconductor memory device 100 to adjust the read voltage according to the error detection result of the error correction block 1150 and to perform the re-reading. As an illustrative example, an error correction block may be provided as a component of the controller 1100. [

The controller 1100 and the semiconductor memory device 100 may be integrated into one semiconductor device. In an exemplary embodiment, the controller 1100 and the semiconductor memory device 100 may be integrated into a single semiconductor device to form a memory card. For example, the controller 1100 and the semiconductor memory device 100 may be integrated into one semiconductor device and may be a PC card (PCMCIA), a compact flash card (CF), a smart media card (SM, SMC ), A memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), and a universal flash memory device (UFS).

The controller 1100 and the semiconductor memory device 100 may be integrated into a single semiconductor device to form a solid state drive (SSD). A semiconductor drive (SSD) includes a storage device configured to store data in a semiconductor memory. When the memory system 2000 is used as a semiconductor drive (SSD), the operation speed of a host connected to the memory system 2000 is remarkably improved.

As another example, the memory system 1000 may be a computer, a UMPC (Ultra Mobile PC), a workstation, a netbook, a PDA (Personal Digital Assistants), a portable computer, a web tablet, A mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box A digital camera, a digital camera, a 3-dimensional television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, Ha Is provided as one of various components of an electronic device, such as one of a variety of electronic devices, one of various electronic devices that make up a telematics network, an RFID device, or one of various components that make up a computing system.

As an exemplary embodiment, semiconductor memory device 100 or memory system 1000 may be implemented in various types of packages. For example, the semiconductor memory device 100 or the memory system 2000 may include a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package Level Processed Stack Package (WSP) or the like.

9 is a block diagram showing an application example of the memory system of FIG.

9, the memory system 2000 includes a semiconductor memory device 2100 and a controller 2200. [ Semiconductor memory device 2100 includes a plurality of semiconductor memory chips. A plurality of semiconductor memory chips are divided into a plurality of groups.

In Fig. 9, a plurality of groups are shown communicating with the controller 2200 through first through k-th channels CH1-CHk, respectively. Each semiconductor memory chip will be configured and operated similarly to one of the semiconductor memory devices 100 described with reference to FIG.

Each group is configured to communicate with the controller 2200 via one common channel. The controller 2200 is configured similarly to the controller 1100 described with reference to Fig. 8 and is configured to control a plurality of memory chips of the semiconductor memory device 2100 through a plurality of channels CH1 to CHk.

10 is a block diagram illustrating a computing system including the memory system described with reference to FIG.

10, a computing system 3000 includes a central processing unit 3100, a random access memory (RAM) 3200, a user interface 3300, a power source 3400, a system bus 3500, (2000).

The memory system 2000 is electrically coupled to the central processing unit 3100, the RAM 3200, the user interface 3300 and the power supply 3400 via the system bus 3500. Data provided through the user interface 3300 or processed by the central processing unit 3100 is stored in the memory system 2000.

10, the semiconductor memory device 2100 is shown connected to the system bus 3500 through a controller 2200. However, the semiconductor memory device 2100 may be configured to be connected directly to the system bus 3500. [ At this time, the functions of the controller 2200 will be performed by the central processing unit 3100 and the RAM 3200.

In Fig. 10, it is shown that the memory system 2000 described with reference to Fig. 9 is provided. However, the memory system 2000 may be replaced by the memory system 1000 described with reference to Fig. As an example embodiment, the computing system 3000 may be configured to include all of the memory systems 1000, 2000 described with reference to Figs.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present invention as well as the claims of the following.

10: memory system 100: semiconductor memory device
110: memory cell array 120: address decoder
130: read and write circuit 140: control logic
150: voltage generator 200:

Claims (16)

A semiconductor memory device including a cam data block for storing cam data; And
And a controller for controlling operation of the semiconductor memory device when a cam data program instruction is received from the host,
Wherein the semiconductor memory device programs the cam data after preceding the pre-program operation and the erase operation when the cam data program instruction is received.
The method according to claim 1,
Wherein the cam data block comprises charge trap memory cells.
The method according to claim 1,
Wherein the semiconductor memory device repeatedly performs the pre-program operation and the erase operation a predetermined number of times.
The method according to claim 1,
The semiconductor memory device
A memory cell array including the cam data block;
A peripheral circuit for performing the pre-program operation and the erase operation of the cam data block; And
And control logic for controlling the peripheral circuit to perform the pre-program operation and the erase operation under the control of the controller.
The method according to claim 1,
Wherein the pre-program operation is performed for all memory cells contained within the cam data block.
The method according to claim 1,
Wherein the pre-program operation is performed by selecting only memory cells to be selected during a subsequent one of the total memory cells included in the cam data block.
The method according to claim 1,
Wherein the cam data block comprises a plurality of charge trap memory cells having a three-dimensional structure.
A memory cell array including a cam data block;
A peripheral circuit for performing a pre-program operation, an erase operation, and a cam data program operation of the cam data block; And
And a control logic for controlling the peripheral circuit to perform the cam data program operation after performing the pre-program operation and the erase operation before the cam data program operation when a cam data program instruction is input, .
9. The method of claim 8,
Wherein the Chem data block comprises charge trap memory cells.
9. The method of claim 8,
Wherein the control logic controls the peripheral circuit so that the pre-program operation and the erase operation are repeated a predetermined number of times.
9. The method of claim 8,
Wherein the pre-program operation is performed on all memory cells contained in the cam data block.
9. The method of claim 8,
Wherein the pre-program operation is performed by selecting only the memory cells to be selected in a subsequent one of the total memory cells included in the cam data block.
Providing a semiconductor memory device comprising a cam data block;
Inputting a cam data program command;
Performing a pre-program operation and an erase operation on the cam data block; And
And programming the cam data to the cam data block.
14. The method of claim 13,
Wherein the cam data block comprises charge trap memory cells.
14. The method of claim 13,
Wherein the pre-program operation and the erase operation are repeatedly performed a predetermined number of times.
14. The method of claim 13,
Wherein the pre-program operation proceeds selectively for all memory cells included in the cam data block, or for memory cells to be selected in the step of programming the cam data.

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