KR20160004068A

KR20160004068A - Semiconductor memory device and operating method thereof

Info

Publication number: KR20160004068A
Application number: KR1020140082454A
Authority: KR
Inventors: 탁재일; 박경환
Original assignee: 에스케이하이닉스 주식회사
Priority date: 2014-07-02
Filing date: 2014-07-02
Publication date: 2016-01-12

Abstract

The present invention relates to a semiconductor memory device and a method of operating the same, including a memory cell array including a plurality of memory cells, a peripheral circuit section for performing a program operation for the plurality of memory cells, And control logic for controlling the peripheral circuitry to perform a charge distribution operation to distribute the trapped charge to a selected one of the plurality of memory cells during program operation.

Description

Technical Field [0001] The present invention relates to a semiconductor memory device and a method of operating the same,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic device, and more particularly, to a semiconductor memory device and a method of operating the same.

A semiconductor memory device is a memory device implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP) to be. Semiconductor memory devices are classified into a volatile memory device and a nonvolatile memory device.

The volatile memory device is a memory device in which data stored in the volatile memory device is lost when power supply is interrupted. Volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). A nonvolatile memory device is a memory device that retains data that has been stored even when power is turned off. A nonvolatile memory device includes a ROM (Read Only Memory), a PROM (Programmable ROM), an EPROM (Electrically Programmable ROM), an EEPROM (Electrically Erasable and Programmable ROM), a flash memory, a PRAM , RRAM (Resistive RAM), and FRAM (Ferroelectric RAM). Flash memory is divided into NOR type and NOR type.

The flash memory device can be divided into a two-dimensional semiconductor device in which a string is formed horizontally on a semiconductor substrate and a three-dimensional semiconductor device in which the string is formed perpendicularly to the semiconductor substrate.

A three-dimensional semiconductor device is a memory device designed to overcome the limit of integration of a two-dimensional semiconductor device, and includes a plurality of strings formed vertically on a semiconductor substrate. The strings include a drain select transistor, memory cells, and a source select transistor connected in series between the bit line and the source line.

The present invention provides a semiconductor memory device and a method of operating the semiconductor memory device, which can solve the problem that charge trapped in memory cells spread during program operation of a semiconductor memory device, thereby lowering the threshold voltage and deteriorating the retention characteristics of the memory cell. to provide.

A semiconductor memory device according to an embodiment of the present invention includes a memory cell array including a plurality of memory cells, a peripheral circuit unit for performing a program operation for the plurality of memory cells, And control logic for controlling the peripheral circuitry to perform a charge distribution operation for distributing the trapped charge to a neighboring region in a selected one of the plurality of memory cells.

A semiconductor memory device according to an embodiment of the present invention includes a memory cell array including a plurality of memory cells, a peripheral circuit unit for performing a program voltage application operation and a charge distribution operation for the plurality of memory cells, The program voltage application operation and the charge distribution operation are performed, and the number of times of performing the program voltage application operation is counted so that the charge distribution operation is performed when the number of counting times reaches a set number of times.

A method of operating a semiconductor memory device according to an embodiment of the present invention includes the steps of: applying a program voltage to selected memory cells of a plurality of memory cells to perform a program voltage application operation; Performing a charge distribution operation to distribute the trapped charge in the selected memory cells when the voltage of the selected memory cell is the same, and re-executing the program voltage application operation by raising the program voltage according to the verification result after performing the verify operation do.

According to an embodiment of the present invention, a high voltage is applied to an adjacent memory cell of a selected memory cell during program operation of the semiconductor memory device to diffuse the trapped charge of the selected memory cell toward the adjacent memory cell, It is possible to improve the phenomenon that the charge trapped in the memory cell after the completion of the program operation diffuses to other regions and the threshold voltage is lowered.

1 is a block diagram for explaining a semiconductor memory device according to the present invention.
2 is a perspective view for explaining a memory string included in a memory block according to the present invention.
Fig. 3 is a circuit diagram for explaining the memory string shown in Fig. 2. Fig.
4 is a flowchart illustrating an operation of the semiconductor memory device according to the present invention.
5A to 5C are diagrams for explaining the movement of charges trapped in a charge storage layer of a memory cell during a program operation of the semiconductor memory device according to the present invention.
6 is a block diagram showing a memory system including the semiconductor memory device of FIG.
7 is a block diagram illustrating an application example of the memory system of FIG.
8 is a block diagram illustrating a computing system including the memory system described with reference to FIG.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish it, will be described with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. The embodiments are provided so that those skilled in the art can easily carry out the technical idea of the present invention to those skilled in the art.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "indirectly connected" . Throughout the specification, when an element is referred to as "comprising ", it means that it can include other elements as well, without excluding other elements unless specifically stated otherwise.

1 is a block diagram for explaining a semiconductor memory device according to the present invention.

1, a semiconductor memory device 100 includes a memory cell array 110, an address decoder 120, a read and write circuit 130, a control logic 140, and a voltage generator 150 .

The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to the address decoder 120 via the word lines WL. The plurality of memory blocks BLK1 to BLKz are connected to the read and write circuit 130 via bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. In an embodiment, the plurality of memory cells are non-volatile memory cells, and more specifically, the plurality of memory cells may be non-volatile memory cells based on charge trap devices. A plurality of memory cells are defined as one page of memory cells connected to the same word line. That is, the memory cell array 110 is composed of a plurality of pages. Each of the plurality of memory blocks BLK1 to BLKz of the memory cell array 110 includes a plurality of strings. Each of the plurality of strings includes a drain select transistor connected in series between a bit line and a source line, a plurality of drain side memory cells, a pipe transistor, a plurality of source side memory cells, and a source select transistor.

The address decoder 120, the read and write circuit 130, and the voltage generator 150 operate as peripheral circuits for driving the memory cell array 110.

The address decoder 120 is coupled to the memory cell array 110 via word lines WL. The address decoder 120 is configured to operate in response to control of the control logic 140. The address decoder 120 receives the address ADDR through an input / output buffer (not shown) in the semiconductor memory device 100.

The address decoder 120 decodes the row address among the received address ADDR of the program voltage Vpgm and the path voltage generated by the voltage generator 150 during the program voltage application operation during the program operation, To the plurality of word lines (WL) of the memory cell array (110). The address decoder 120 applies the dispersion voltage Vspread generated by the voltage generator 150 to the word line adjacent to the selected word line during the charge dispersion operation during the program operation. At this time, a voltage of 0V can be applied to the selected word line.

The address decoder 120 is configured to decode the column address of the address (ADDR) received during the read operation. The address decoder 120 sends the decoded column address Yi to the read and write circuit 130.

The program operation of the semiconductor memory device 100 is performed page by page. The address ADDR received in the program operation request includes a block address, a row address, and a column address. The address decoder 120 selects one memory block and one word line in accordance with the block address and the row address. The column address is decoded by the address decoder 120 and provided to the read and write circuit 130.

The address decoder 120 may include a block decoder, a row decoder, a column decoder, and an address buffer.

The read and write circuit 130 includes a plurality of page buffers PB1 to PBm. The plurality of page buffers PB1 to PBm are connected to the memory cell array 110 through bit lines BL1 to BLm. Each of the plurality of page buffers PB1 to PBm temporarily stores input data (DATA) during a program operation and controls potentials of corresponding bit lines (BL1 to BLm) according to temporarily stored data. Further, during the program verify operation, the potential of the bit lines BL1 to BLm of the memory cell array 110 is sensed and compared with the data temporarily stored in the program operation to perform a verify operation. Each of the plurality of page buffers PB1 to PBm precharges the potential of the bit lines BL1 to BLm before sensing the potential of the bit lines BL1 to BLm in the verify operation.

The read and write circuitry 130 operates in response to control of the control logic 140.

As an example embodiment, the read and write circuitry 130 may include page buffers (or page registers), column select circuitry, and the like.

The control logic 140 is coupled to the address decoder 120, the read and write circuit 130, and the voltage generator 150. The control logic 140 receives the command CMD through an input / output buffer (not shown) of the semiconductor memory device 100. The control logic 140 is configured to control all operations of the semiconductor memory device 100 in response to the command CMD. Also, the control logic 140 counts the number of times of application of the program voltage Vpgm applied during the program voltage application operation during the program operation, and performs the charge distribution operation when the counted number of application times is equal to the preset number 150 and the address decoder 120. [ The control logic 140 performs the verify operation after the charge dispersion operation and controls the peripheral circuitry to re-execute the program voltage application operation or to terminate the program operation according to the result.

The voltage generating unit 150 generates the program voltage Vpgm and the pass voltage Vpass in the program voltage application operation under the control of the control logic 140. [ The voltage generating unit 150 generates the program voltage Vpgm so that the program voltage Vpgm gradually increases by the step voltage as the number of application times increases. The voltage generator 150 generates the set voltage Vspread during the charge dispersion operation under the control of the control logic 140. [ The voltage generator 150 generates an operating voltage of 0V to be applied to the selected word line.

2 is a perspective view for explaining a memory string included in a memory block according to the present invention. 3 is a circuit diagram for explaining a memory string.

Referring to FIGS. 2 and 3, a common source line SL is formed on a semiconductor substrate. A vertical channel layer SP is formed on the common source line SL. The upper part of the vertical channel layer SP is connected to the bit line BL. The vertical channel layer SP may be formed of polysilicon. A plurality of conductive films SGS, WL0 to WLn, and SGD are formed to surround the vertical channel layer SP at different heights of the vertical channel layer SP. A multilayer film (not shown) including a charge storage film is formed on the surface of the vertical channel layer SP and the multilayer film is also located between the vertical channel layer SP and the conductive films SGSL, WL0 to WLn and SGD. The multilayer film may be formed of an ONO structure in which an oxide film, a nitride film, and an oxide film are sequentially laminated.

The lowermost conductive film becomes a source selection line (or first selection line) SGS, and the uppermost conductive film becomes a drain selection line (or second selection line) SGD. The conductive films between the selection lines SGS and SGD become the word lines WL0 to WLn. In other words, the conductive films SGS, WL0 to WLn and SGD are formed in multiple layers on the semiconductor substrate and the vertical channel layer SP penetrating the conductive films SGS, WL0 to WLn and SGD is connected to the bit lines BL ) And the source line SL formed on the semiconductor substrate.

A drain select transistor SDT is formed at a portion where the top conductive film SGD surrounds the vertical channel layer SP and a portion at which the lowermost conductive film SGS surrounds the vertical channel layer SP A source selection transistor (or first selection transistor) SST is formed. The memory cells C0 to Cn are formed in portions where the intermediate conductive layers WL0 to WLn surround the vertical channel layer SP.

With this structure, the memory string includes a source select transistor SST, memory cells C0 to Cn, and a drain select transistor SDT, which are vertically connected to the substrate between the common source line SL and the bit line BL. . The source select transistor SST electrically connects the memory cells C0 to Cn to the common source line SL in accordance with the first select signal applied to the first select line SGS. The drain select transistor SDT electrically connects the memory cells C0 to Cn to the bit line BL in accordance with a second select signal applied to the second select line SGD.

As the program / erase cycle is repeatedly performed, trap layers are formed in the oxide films of the multilayered film used as the tunnel insulating films, and electrons are trapped in the memory cells C0 to Cn. As a result, after the program operation is completed, electrons trapped in the tunnel insulating film may move to lower the threshold voltage, thereby deteriorating the retention characteristics of the memory cell.

4 is a flowchart illustrating an operation of the semiconductor memory device according to the present invention.

5A to 5C are diagrams for explaining the movement of charges trapped in a charge storage layer of a memory cell during a program operation of the semiconductor memory device according to the present invention.

The operation of the semiconductor memory device according to the present invention will now be described with reference to FIGS. 1 to 5C.

1) Program voltage application (S410)

When the command CMD for the program operation of the semiconductor memory device is received by the control logic 140, the control logic 140 controls the read and write circuit 130 so that the program data (DATA) And the plurality of page buffers PB1 to PBm of the write circuit 130, respectively. Each of the plurality of page buffers PB1 to PBm temporarily stores input data (DATA) during a program operation and controls potentials of corresponding bit lines (BL1 to BLm) according to temporarily stored data.

The voltage generator 150 generates the program voltage Vpgm and the pass voltage Vpass under the control of the control logic 140. [ The address decoder 120 applies the program voltage Vpgm generated by the voltage generator 150 to the selected word line WL1 during the application of the program voltage, (Vpass) to the remaining word lines except for the selected word line WL1. As a result, as shown in FIG. 5A, the charges e are trapped in the memory layer ML of the memory cell to which the program voltage Vpgm is applied, from the vertical channel layer SP. This increases the threshold voltage of the selected memory cell.

2) Comparison of program voltage application times (S420)

The control logic 140 counts the number of times the program voltage is applied and determines whether it is equal to the set number N of times.

3) Setting voltage is applied to the adjacent cell (S430)

As a result of the comparison of the program voltage application times (S420), if the set number of program voltage application times N is the same, the set voltage Vspread is applied to the memory cells adjacent to the selected memory cell in the word line direction, And performs a distributed operation. At this time, the adjacent memory cell may be a memory cell in which the programming operation is performed before the selected memory cell. That is, the set voltage Vspread is applied to the memory cell connected to the word line WL adjacent to the selected word line WL1 in the direction of the source line SL among the adjacent word lines WL0 and WL2. At this time, an operating voltage of 0 V can be applied to the selected word line WL1. As a result, some of the charges (e) trapped in the memory film (ML) of the selected memory cell are moved and trapped in the memory film region (A) extending in the direction of the adjacent memory cell as shown in FIG. 5B. That is, the charges trapped in the memory film ML of the selected memory cell are dispersed and moved in the direction of the source line.

4) Verification operation (S440)

If the number of program voltage application times is smaller than or greater than the set number of times N as a result of the comparison of the program voltage application times (S420), or if the setup voltage application step S430 is performed in the adjacent cell, .

First, the read and write circuit 130 precharges the bit lines BL1 to BLm to a constant potential level. The voltage generating unit 150 generates the verify voltage and the pass voltage Vpass under the control of the control logic 140. [ The address decoder 120 outputs the verify voltage and the pass voltage Vpass generated in the voltage generator 150 during the verify operation to the selected word line WL1 of the memory cell array 110 and the remaining word lines WL1, Respectively. Thereafter, the read and write circuit 130 senses the potential level change of the precharged bit lines (BL1 to BLm) to perform the verify operation of the memory cells.

5) Program voltage rise (S450)

If the threshold voltage of some or all of the plurality of memory cells connected to the selected word line WL1 as a result of the verifying operation S440 described above is determined to be lower than the verify voltage and is judged as fail, the control logic 140 sets the program voltage Vpgm The voltage generator 150 is controlled so as to generate a new program voltage Vpgm by raising the voltage of the program voltage Vpgm by a step voltage so that the program voltage Vpgm is applied to the peripheral circuits . The control logic 140 also counts the number of times the program voltage application (S410) is performed.

When the program voltage is applied again (S410), the charges (e) are injected from the vertical channel layer (SP) into the memory film (ML) of the memory cell to which the new program voltage Vpgm is applied Trapped.

As described above, according to the present invention, when the number of times of application of the program voltage during the programming operation is a predetermined number, the charge trapped in the memory film of the selected memory cell is dispersed around and then a new program voltage application operation is performed. Therefore, even if a certain period of time has elapsed after the program operation is completed, the charges (e) are already trapped in the memory film region A located between the selected memory cell and the adjacent memory cells, so that the charges (e) trapped in the selected memory cell Do not move to the A area. As a result, the retention characteristics of the memory cell are improved.

6 is a block diagram showing a memory system including the semiconductor memory device of FIG.

Referring to FIG. 6, a memory system 1000 includes a semiconductor memory device 100 and a controller 1100.

The semiconductor memory device 100 may be constructed and operated as described with reference to Fig. Hereinafter, a duplicate description will be omitted.

The controller 1100 is connected to the host (Host) and the semiconductor memory device 100. In response to a request from the host (Host), the controller 1100 is configured to access the semiconductor memory device 100. For example, the controller 1100 is configured to control the read, write, erase, and background operations of the semiconductor memory device 100. The controller 1100 is configured to provide an interface between the semiconductor memory device 100 and the host. The controller 1100 is configured to drive firmware for controlling the semiconductor memory device 100.

The controller 1100 includes a random access memory 1110, a processing unit 1120, a host interface 1130, a memory interface 1140, and an error correction block 1150 . The RAM 1110 is connected to at least one of an operation memory of the processing unit 1120, a cache memory between the semiconductor memory device 100 and the host and a buffer memory between the semiconductor memory device 100 and the host . The processing unit 1120 controls all operations of the controller 1100. In addition, the controller 1100 may temporarily store program data provided from a host in a write operation.

The host interface 1130 includes a protocol for exchanging data between the host (Host) and the controller 1100. As an exemplary embodiment, the controller 1200 may be implemented using a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI- Various interface protocols such as protocol, Serial-ATA protocol, Parallel-ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, IDE (Integrated Drive Electronics) protocol, (Host) via at least one of the following:

The memory interface 1140 interfaces with the semiconductor memory device 100. For example, the memory interface includes a NAND interface or a NOR interface.

The error correction block 1150 is configured to detect and correct errors in data received from the semiconductor memory device 100 using an error correcting code (ECC). The processing unit 1120 will control the semiconductor memory device 100 to adjust the read voltage according to the error detection result of the error correction block 1150 and to perform the re-reading. As an illustrative example, an error correction block may be provided as a component of the controller 1100. [

The controller 1100 and the semiconductor memory device 100 may be integrated into one semiconductor device. In an exemplary embodiment, the controller 1100 and the semiconductor memory device 100 may be integrated into a single semiconductor device to form a memory card. For example, the controller 1100 and the semiconductor memory device 100 may be integrated into one semiconductor device and may be a PC card (PCMCIA), a compact flash card (CF), a smart media card (SM, SMC ), A memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), and a universal flash memory device (UFS).

The controller 1100 and the semiconductor memory device 100 may be integrated into a single semiconductor device to form a solid state drive (SSD). A semiconductor drive (SSD) includes a storage device configured to store data in a semiconductor memory. When the memory system 1000 is used as a semiconductor drive (SSD), the operation speed of the host connected to the memory system 2000 is remarkably improved.

As another example, the memory system 1000 may be a computer, a UMPC (Ultra Mobile PC), a workstation, a netbook, a PDA (Personal Digital Assistants), a portable computer, a web tablet, A mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box A digital camera, a digital camera, a 3-dimensional television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital image player a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, Ha Is provided as one of various components of an electronic device, such as one of a variety of electronic devices, one of various electronic devices that make up a telematics network, an RFID device, or one of various components that make up a computing system.

As an exemplary embodiment, semiconductor memory device 100 or memory system 1000 may be implemented in various types of packages. For example, the semiconductor memory device 100 or the memory system 1000 may be a package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carriers (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package Level Processed Stack Package (WSP) or the like.

7 is a block diagram illustrating an application example of the memory system of FIG.

7, the memory system 2000 includes a semiconductor memory device 2100 and a controller 2200. [ Semiconductor memory device 2100 includes a plurality of semiconductor memory chips. A plurality of semiconductor memory chips are divided into a plurality of groups.

In Fig. 7, a plurality of groups are shown communicating with controller 2200 through first through k-th channels CH1-CHk, respectively. Each semiconductor memory chip will be configured and operated similarly to one of the semiconductor memory devices 100 described with reference to FIG.

Each group is configured to communicate with the controller 2200 via one common channel. The controller 2200 is configured similarly to the controller 1100 described with reference to Fig. 6 and is configured to control a plurality of memory chips of the semiconductor memory device 2100 through a plurality of channels CH1 to CHk.

8 is a block diagram illustrating a computing system including the memory system described with reference to FIG.

8, a computing system 3000 includes a central processing unit 3100, a random access memory (RAM) 3200, a user interface 3300, a power source 3400, a system bus 3500, (2000).

The memory system 2000 is electrically coupled to the central processing unit 3100, the RAM 3200, the user interface 3300 and the power supply 3400 via the system bus 3500. Data provided through the user interface 3300 or processed by the central processing unit 3100 is stored in the memory system 2000.

In FIG. 8, the semiconductor memory device 2100 is shown connected to the system bus 3500 via a controller 2200. However, the semiconductor memory device 2100 may be configured to be connected directly to the system bus 3500. [ At this time, the functions of the controller 2200 will be performed by the central processing unit 3100 and the RAM 3200.

In Fig. 8, it is shown that the memory system 2000 described with reference to Fig. 7 is provided. However, the memory system 2000 may be replaced by the memory system 1000 described with reference to FIG. As an example embodiment, the computing system 3000 may be configured to include all of the memory systems 1000, 2000 described with reference to Figures 7 and 6. [

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present invention as well as the claims of the following.

100: semiconductor memory device 110: memory cell array
120: address decoder 130: read and write circuit
140: control logic 150: voltage generator

Claims

A memory cell array including a plurality of memory cells;
A peripheral circuit unit for performing a program operation on the plurality of memory cells; And
And a control logic for controlling the peripheral circuitry to control the peripheral circuitry to perform a charge distribution operation for distributing the trapped charge to selected ones of the plurality of memory cells during the program operation to an adjacent region, Device.

The method according to claim 1,
Wherein the control logic controls the peripheral circuitry portion to perform a verify operation after the charge distribution operation and to re-execute the program voltage application operation by raising the program voltage according to the result of the verify operation.

The method according to claim 1,
Wherein the plurality of memory cells are non-volatile memory cells based on a charge trap device.

The method according to claim 1,
Wherein the charge distribution operation applies a set voltage to a memory cell adjacent to the selected memory cell.

The method according to claim 1,
Wherein the charge distributing operation applies a set voltage to memory cells adjacent to the selected memory cell in the direction of the source line of the memory cells adjacent to the selected memory cell.

The method according to claim 1,
Wherein said charge distributing operation applies an operating voltage of 0V to said selected memory cell.

The method according to claim 1,
Wherein the charge distribution operation moves charge trapped in the memory film of the selected memory cell to the memory film region extending in the direction of the source line during the program voltage application operation.

The method according to claim 1,
Wherein the control logic compares the program voltage application times with a preset number of times and controls the peripheral circuitry section to perform the charge distribution operation when the program voltage application times and the set number of times are equal.

The method according to claim 1,
The peripheral circuit unit includes a voltage generator for generating a program voltage for application to the selected memory cell during the program voltage application operation and generating a setup voltage for application to the memory cell adjacent to the selected memory cell during the charge dispersion operation Lt; / RTI >

A memory cell array including a plurality of memory cells;
A peripheral circuit unit for performing a program voltage application operation and a charge distribution operation for the plurality of memory cells; And
And a control circuit for controlling the peripheral circuitry to perform the program voltage application operation and the charge distribution operation, counting the number of times of the program voltage application operation and counting the number of counting times, Memory device.

11. The method of claim 10,
Wherein the control logic controls the peripheral circuitry portion to perform a verify operation after the charge distribution operation and to re-execute the program voltage application operation by raising the program voltage according to the result of the verify operation.

11. The method of claim 10,
Wherein the plurality of memory cells are non-volatile memory cells based on a charge trap device.

11. The method of claim 10,
Wherein the charge distribution operation applies a set voltage to a memory cell adjacent to the selected memory cell.

11. The method of claim 10,
Wherein the charge distributing operation applies a set voltage to memory cells adjacent to the selected memory cell in the direction of the source line of the memory cells adjacent to the selected memory cell.

11. The method of claim 10,
Wherein said charge distributing operation applies an operating voltage of 0V to said selected memory cell.

11. The method of claim 10,
Wherein the charge distribution operation moves charge trapped in the memory film of the selected memory cell to the memory film region extending in the direction of the source line during the program voltage application operation.

11. The method of claim 10,
The peripheral circuit unit includes a voltage generator for generating a program voltage for application to the selected memory cell during the program voltage application operation and generating a setup voltage for application to the memory cell adjacent to the selected memory cell during the charge dispersion operation Lt; / RTI >

Performing a program voltage application operation by applying a program voltage to selected memory cells among a plurality of memory cells;
Performing a charge distribution operation for distributing trapped charge in the selected memory cells when the number of times of performing the program voltage application is equal to a set number of times; And
Performing a verify operation and then re-executing the program voltage application operation by raising the program voltage according to a verification result.

19. The method of claim 18,
Wherein the charge distribution operation applies a set voltage to memory cells adjacent to the selected memory cells.

19. The method of claim 18,
Wherein the charge distributing operation applies an operating voltage of 0V to the selected memory cell while applying a set voltage to memory cells adjacent to the selected memory cell in the source line direction among the memory cells adjacent to the selected memory cell.