KR20150077014A - Thin film transistor substrate and Liquid Crystal Display Device using the same - Google Patents

Abstract

The present invention comprises: gate wiring including first gate wiring, second gate wiring, third gate wiring, and fourth gate wiring sequentially arranged in a first direction on a substrate; data wiring including first data wiring, second data wiring, third data wiring, and fourth data wiring sequentially arranged in a second direction on the substrate; a semiconductor layer formed to be respectively overlapped with the gate wiring and the data wiring, and connected to the data wiring; and a pixel electrode connected to the semiconductor layer. A gap between the first data wiring and the second data wiring and a gap between the third data wiring and the fourth data wiring are narrower than a gap between the second data wiring and the third data wiring. According to the present invention, an opening rate is able to be improved in high resolution.

Description

[0001] The present invention relates to a thin film transistor substrate and a liquid crystal display using the thin film transistor substrate.

The present invention relates to a thin film transistor substrate, and more particularly, to a thin film transistor substrate having a high resolution.

BACKGROUND ART [0002] Thin film transistors are widely used as switching devices for display devices such as liquid crystal display devices (OLED) or organic light emitting display devices.

The thin film transistor includes a gate electrode, a semiconductor layer, a source electrode, and a drain electrode. Hereinafter, a conventional thin film transistor substrate will be described with reference to the drawings.

1 is a schematic plan view of a conventional thin film transistor substrate.

1, the conventional thin film transistor substrate includes a gate wiring 10, a gate electrode 12, a data wiring 20, a source electrode 22, a drain electrode 24, a semiconductor layer 30, And a pixel electrode (40).

The gate wirings 10 are arranged in the lateral direction, and the gate electrodes 12 protrude from the gate wirings 10.

The data lines 20 are arranged in the vertical direction while intersecting the gate lines 10. The gate line 10 and the data line 20 intersect to define a pixel region.

The source electrode 22 protrudes from the data line 20 and the drain electrode 24 is spaced apart from the source electrode 22 while facing the source electrode 22.

The semiconductor layer 30 is formed to overlap the gate electrode 12, the source electrode 22, and the drain electrode 24.

The pixel electrode 40 is formed in a pixel region defined by the gate line 10 and the data line 20. The pixel electrode 40 is connected to the drain electrode 24 through a predetermined contact hole.

Such a conventional thin film transistor substrate is used in a display device such as a liquid crystal display device, but is limited to a recent high resolution display device.

In the case of a high-resolution display device, the number of pixels increases and the number of thin film transistors also increases. However, when the structure of a conventional thin film transistor is applied to a high-resolution display device, the aperture ratio is reduced.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a thin film transistor substrate and a liquid crystal display device using the thin film transistor substrate, which can be applied to a display device having an improved aperture ratio and a high resolution.

In order to achieve the above object, the present invention provides a semiconductor device comprising: a gate wiring including a first gate wiring, a second gate wiring, a third gate wiring and a fourth gate wiring which are sequentially arranged in a first direction on a substrate; A data line including a first data line, a second data line, a third data line, and a fourth data line arranged in order on the substrate in the second direction; A semiconductor layer formed to overlap with the gate wiring and the data wiring, respectively, and connected to the data wiring; And a pixel electrode connected to the semiconductor layer, wherein an interval between the first data line and the second data line and an interval between the third data line and the fourth data line are different from the interval between the second data line And the third data line is smaller than the interval between the third data line and the third data line.

The present invention also relates to a thin film transistor substrate; An opposing substrate; And a liquid crystal layer formed between the both substrates, wherein the thin film transistor substrate comprises the thin film transistor substrate described above.

According to the present invention as described above, the aperture ratio is improved and can be easily applied to a high-resolution display device.

1 is a schematic plan view of a conventional thin film transistor substrate.
2 is a schematic plan view of a thin film transistor substrate according to an embodiment of the present invention.
FIG. 3 is a schematic cross-sectional view of a thin film transistor substrate according to an embodiment of the present invention, which corresponds to the cross section of line AB in FIG.
FIG. 4 is a schematic cross-sectional view of a thin film transistor substrate according to an embodiment of the present invention, which corresponds to a cross-section of the CD line of FIG.
FIG. 5 is a schematic cross-sectional view of a thin film transistor substrate according to an embodiment of the present invention, which corresponds to a cross section of line EF of FIG.
6 illustrates a liquid crystal display according to an embodiment of the present invention.

The term "on " as used herein is meant to encompass not only when a configuration is formed on the immediate surface of another configuration, but also to the extent that a third configuration is interposed between these configurations.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

2 is a schematic plan view of a thin film transistor substrate according to an embodiment of the present invention.

2, the thin film transistor substrate according to an embodiment of the present invention includes a gate wiring 400, a data wiring 500, a semiconductor layer 300, a common electrode 600, and a pixel electrode 700, .

The gate wiring 400 is arranged in a first direction, for example, in a lateral direction.

The gate wiring 400 includes a first gate wiring G1, a second gate wiring G2, a third gate wiring G3 and a fourth gate wiring G4 arranged in order.

The first gate wiring G1 and the second gate wiring G2 are electrically connected to each other. Therefore, the same gate voltage is applied to the first gate wiring G1 and the second gate wiring G2. The first gate wiring G1 and the second gate wiring G2 are connected to each other in a non-display area outside the display area where the image is displayed.

The third gate wiring G3 and the fourth gate wiring G4 are also electrically connected to each other. Therefore, the same gate voltage is applied to the third gate wiring G3 and the fourth gate wiring G4. The third gate wiring G3 and the fourth gate wiring G4 are also connected to each other in a non-display area outside the display area where an image is displayed.

As a result, one gate wiring to which a predetermined gate voltage is applied is formed by the combination of the first gate wiring G1 and the second gate wiring G2, and the third gate wiring G3 and the fourth The other gate wiring to which the predetermined gate voltage is applied is constituted by the combination of the gate wiring G4.

The data lines 500 are arranged in a second direction, for example, in the longitudinal direction so as to intersect with the gate lines 400.

The data line 500 includes a first data line D1, a second data line D2, a third data line D3, a fourth data line D4, a fifth data line D5, , And a sixth data line (D6).

The respective data lines D1, D2, D3, D4, D5, and D6 are not connected to each other, and therefore, the respective data voltages are applied to the data lines D1, D2, D3, D4, D5, and D6.

The distance between the third data line D3 and the fourth data line D4 and the distance between the fifth data line D5 and the fourth data line D4 are set to be equal to or less than the distance between the first data line D1 and the second data line D2, The interval between the sixth data lines D6 is shorter than the interval between the second data lines D2 and the third data lines D3 and the interval between the fourth data lines D4 and the fifth data lines D5 Lt; / RTI >

A region between the first data line D1 and the second data line D2 arranged at relatively small intervals, a region between the third data line D3 and the fourth data line D4, The region between the fifth data wiring D5 and the sixth data wiring D6 becomes a non-opening portion through which light is not transmitted.

The region between the second data line D2 and the third data line D3 and the region between the fourth data line D4 and the fifth data line D5 arranged at a relatively wide interval are arranged in such a manner that light is transmitted .

In the present invention, the non-opening portion and the opening portion are clearly divided into a matrix structure and the thin film transistor is located in the non-opening portion. Therefore, it is possible to have a large process margin in the non-opening portion, and the aperture ratio can be improved even at a high resolution.

The semiconductor layer 300 is formed in a region where the gate wiring 400 and the data wiring 500 cross each pixel. As shown in the figure, the semiconductor layer 300 may have a U-shaped pattern, but the present invention is not limited thereto.

The semiconductor layer 300 is formed so as to overlap with the gate wiring 400 and the data wiring 500 and is formed by a combination of the semiconductor layer 300, the gate wiring 400, and the data wiring 500, . A region of the gate line 400 overlapping with the semiconductor layer 300 functions as a gate electrode and a region of the data line 500 overlapping the semiconductor layer 300 functions as a source / do.

The semiconductor layer 300 is formed in the non-opening portion and is not formed in the opening portion. That is, the semiconductor layer 300 has a region between the first data line D1 and the second data line D2, a region between the third data line D3 and the fourth data line D4, And a fourth data line (D4) formed in a region between the fifth data line (D5) and the sixth data line (D6), the region between the second data line (D2) and the third data line ) And the fifth data line D5.

(X) in the drawing denotes a first contact hole H1 to which the semiconductor layer 300 and the data line 500 are connected. In the drawing, the mark (?) Indicates that the semiconductor layer 300 And a second contact hole H2 to which the pixel electrode 700 is connected.

As shown in the drawing, the pixel electrode 700 may be formed to overlap the semiconductor layer 300 and the data line 500 in the first contact hole H1, The electrode 700 is not connected to the semiconductor layer 300 and the data line 500 in the first contact hole H1 indicated by (X), and the first contact hole (H) H1), only the semiconductor layer 300 and the data line 500 are connected.

Each of the first semiconductor layers S1 overlapping the first gate line G1 among the plurality of semiconductor layers 300 formed for each pixel is electrically connected to the first data line D1, D3, and the fifth data line D5, and are connected to the data lines D1, D3, and D5 through the first contact holes H1.

Among the plurality of semiconductor layers 300 formed for individual pixels, each of the second semiconductor layers S2 overlapping the second gate line G2 is electrically connected to the second data line D2, D4 and the sixth data line D6 and are connected to the data lines D2, D4 and D6 through the first contact holes H1.

The third semiconductor layer S3 overlapping the third gate line G3 among the plurality of semiconductor layers 300 formed for each pixel is electrically connected to the first data line D1, D3, and the fifth data line D5, and are connected to the data lines D1, D3, and D5 through the first contact holes H1.

Among the plurality of semiconductor layers 300 formed for each pixel, each of the fourth semiconductor layers S4 overlapping the fourth gate line G4 is electrically connected to the second data line D2, D4 and the sixth data line D6 and are connected to the data lines D2, D4 and D6 through the first contact holes H1.

Therefore, the first semiconductor layer S1, the second semiconductor layer S2, the third semiconductor layer S3, and the fourth semiconductor layer S4 are arranged in a non-opening portion in a zigzag shape as shown in the figure, Accordingly, the thin film transistor formed for each individual pixel is also formed in the non-opening portion in a staggered shape.

The common electrode 600 may form an electric field together with the pixel electrode 700 to control the alignment direction of the liquid crystal layer. In particular, according to an embodiment of the present invention, a fringe field may be formed between the common electrode 600 and the pixel electrode 700 to adjust the alignment direction of the liquid crystal layer.

In order to form the fringe field, the common electrode 600 is formed in a plate structure on the entire display region where an image is displayed, and the pixel electrode 700 is formed on the common electrode 600, ) May be formed.

When the common electrode 600 is formed below the pixel electrode 700, in order to prevent a short-circuit with the pixel electrode 700 in the second contact hole H2 region, An open hole is formed in the substrate 600, which can be easily understood by referring to a cross-sectional structure described later.

However, the present invention is not limited thereto, and the pixel electrode 700 may be formed under the common electrode 600. In this case, a slit for forming a fringe field may be formed in the common electrode 600 do.

The pixel electrode 700 is formed for each individual pixel. That is, the pixel electrode 700 has a pixel region between the first gate wiring G1 and the second gate wiring G2, a pixel region between the second gate wiring G2 and the third gate wiring G3, And the pixel region between the third gate wiring G3 and the fourth gate wiring G4.

The pixel electrode 700 is connected to the semiconductor layer 300 through a second contact hole H2 marked with (O). That is, in one embodiment of the present invention, the pixel electrode 700 is directly connected to the semiconductor layer 300 without passing through another metal layer.

The pixel electrode 700 includes a slit for forming the fringe field and the common electrode 600 as described above. The pixel electrode 700 may have a fork structure as shown in FIG. Although a single slit is formed in the pixel electrode 700, a plurality of slits may be formed.

The pixel electrode 700 includes a first pixel electrode P1 connected to the first semiconductor layer S1, a second pixel electrode P2 connected to the second semiconductor layer S2, A third pixel electrode P3 connected to the fourth semiconductor layer S4 and a fourth pixel electrode P4 connected to the fourth semiconductor layer S4.

The first pixel electrode P1 is connected to the first semiconductor layer S1 through a second contact hole H2 and extends in a first direction, for example, a right direction. The second contact hole H2 exposes the right end of the first semiconductor layer S1 and the first contact hole H1 exposes the left end of the first semiconductor layer S1 .

The second pixel electrode P2 is connected to the second semiconductor layer S2 through a second contact hole H2 and extends in a second direction, for example, a left direction. The second contact hole H2 exposes the left end of the second semiconductor layer S2 and the first contact hole H1 exposes the right end of the second semiconductor layer S2 .

The third pixel electrode P3 extends in the first direction, for example, the right direction, while being connected to the third semiconductor layer S3 through the second contact hole H2. The second contact hole H2 exposes the right end of the third semiconductor layer S3 and the first contact hole H1 exposes the left end of the third semiconductor layer S3. .

The fourth pixel electrode P4 is connected to the fourth semiconductor layer S4 through the second contact hole H2 and extends in the second direction, for example, the left direction. The second contact hole H2 exposes the left end of the fourth semiconductor layer S4 and the first contact hole H1 exposes the right end of the fourth semiconductor layer S4. .

As described above, the first contact hole H1 exposes one side of the first semiconductor layer S1 and the third semiconductor layer S3, for example, the left end, and the second semiconductor layer S2 and fourth And the right end is exposed as the other example of the semiconductor layer S4. The second contact hole H2 exposes the other side of the first semiconductor layer S1 and the third semiconductor layer S3, for example, the right end, and the second semiconductor layer S2 and the fourth semiconductor layer S3, For example, the left end portion of the rear surface S4. The first pixel electrode P1 and the third pixel electrode P3 are connected to the first semiconductor layer S1 and the third semiconductor layer S3 through the second contact hole H2, The second pixel electrode P2 and the fourth pixel electrode P4 extend in the other direction such as the right direction and the second pixel electrode P2 and the fourth pixel electrode P4 are connected to the second semiconductor layer S2 and the fourth pixel electrode P4 through the second contact hole H2. For example, leftward, while being connected to the semiconductor layer S4.

FIG. 3 is a schematic cross-sectional view of a thin film transistor substrate according to an embodiment of the present invention, which corresponds to a cross section taken along line A-B of FIG. That is, Fig. 3 corresponds to a cross section of the thin film transistor region.

3, the thin film transistor substrate according to an embodiment of the present invention includes a substrate 100, a light shielding layer 200, a buffer layer 250, a semiconductor layer 300, a gate insulating layer 350, And a pixel electrode 700. The pixel electrode 700 includes a first electrode layer 400, an interlayer insulating layer 450, a data line 500, a first protective layer 550, a common electrode 600, a second protective layer 650,

The substrate 100 may be made of glass or transparent plastic.

The light blocking layer 200 is formed on the substrate 100. The light shielding layer 200 prevents the semiconductor layer 300 from being deviated due to the light introduced from the lower portion of the substrate 100. Therefore, the light shielding layer 200 is formed to overlap with the semiconductor layer 300. The light shielding layer 200 may be made of various materials known in the art that can prevent light transmission.

The buffer layer 250 is formed on the light shielding layer 200. The buffer layer 250 functions to prevent impurities contained in the substrate 100 from penetrating into the semiconductor layer 300 during a high-temperature process. The buffer layer 250 may be made of an insulating material known in the art.

The semiconductor layer 300 is formed on the buffer layer 250 and overlaps with the light shielding layer 200. The semiconductor layer 300 may be formed of a silicon-based semiconductor material or an oxide semiconductor material.

The gate insulating layer 350 is formed on the semiconductor layer 300 to insulate the semiconductor layer 300 from the gate wiring 400. The gate insulating layer 350 may be formed of an inorganic insulating material known in the art.

The gate wiring 400 is formed on the gate insulating film 350. The gate wiring 400 is formed to overlap with the semiconductor layer 300 and activates the semiconductor layer 300 when a gate voltage is applied to the gate wiring 400. The gate wiring 400 may be formed of a metal such as molybdenum (Mo), aluminum (Al), chrome (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) Alloy, and may be composed of a single layer of the metal or alloy or multiple layers of two or more layers.

The interlayer insulating layer 450 is formed on the gate line 400 to insulate the gate line 400 from the data line 500. The interlayer insulating layer 450 may be made of an inorganic insulating material known in the art.

The data line 500 is formed on the interlayer insulating layer 450. The data line 500 is directly connected to the semiconductor layer 300 through the first contact hole H1. The first contact hole H1 is formed by removing a predetermined region of the gate insulating layer 350 and the interlayer insulating layer 450 so that the first contact hole H1 is formed in a predetermined region of the semiconductor layer 300 by the first contact hole H1, Lt; / RTI > The data line 500 may be formed of one selected from the group consisting of Mo, Al, Cr, Au, Ti, Ni, Ne, Alloy, and may be composed of a single layer of the metal or alloy or multiple layers of two or more layers.

The first passivation layer 550 is formed on the data line 500. The first passivation layer 550 may be formed of an organic insulating material such as photo-acryl. The first passivation layer 550 may also perform a substrate planarization function.

The common electrode 600 is formed on the first passivation layer 550. Except that the common electrode 600 has an open hole H3 in the second contact hole H2 region for connection between the pixel electrode 700 and the semiconductor layer 300, Is formed on the entire surface. The common electrode 600 is made of a transparent conductive material such as ITO.

The second protective film 650 is formed on the common electrode 600. The second protective layer 650 may be formed of an inorganic insulating material.

The pixel electrode 700 is formed on the second passivation layer 650. The pixel electrode 700 is directly connected to the semiconductor layer 300 through the second contact hole H2. The second contact hole H2 is formed by removing a predetermined region of the gate insulating layer 350, the interlayer insulating layer 450, the first passivation layer 550, and the second passivation layer 650, H2, a predetermined region of the semiconductor layer 300 is exposed. The pixel electrode 700 is made of a transparent conductive material such as ITO.

FIG. 4 is a schematic cross-sectional view of a thin film transistor substrate according to an embodiment of the present invention, which corresponds to a cross section taken along the line C-D in FIG. That is, FIG. 4 corresponds to a cross section of a region where the semiconductor layer 300 and the data line 500 overlap.

4, the thin film transistor substrate according to an exemplary embodiment of the present invention includes a substrate 100, a light shielding layer 200, a buffer layer 250, a semiconductor layer 300, a gate insulating layer 350, And a pixel electrode 700. The pixel electrode 700 includes a first electrode layer 400, an interlayer insulating layer 450, a data line 500, a first protective layer 550, a common electrode 600, a second protective layer 650, A detailed description of the same configuration as that described above will be omitted.

The light blocking layer 200 is formed on the substrate 100. The light blocking layer 200 is formed to overlap with the semiconductor layer 300.

The buffer layer 250 is formed on the light shielding layer 200 and the semiconductor layer 300 is formed on the buffer layer 250. The semiconductor layer 300 is formed to overlap with the light shielding layer 200.

The gate insulating layer 350 is formed on the semiconductor layer 300 and the gate wiring 400 is formed on the gate insulating layer 350. The gate wiring 400 is formed to overlap with the semiconductor layer 300.

The interlayer insulating layer 450 is formed on the gate line 400 and the data line 500 is formed on the interlayer insulating layer 450. The data line 500 is connected to the semiconductor layer 300 through the first contact hole H1.

The first passivation layer 550 is formed on the data line 500 and the common electrode 600 is formed on the first passivation layer 550.

The second passivation layer 650 is formed on the common electrode 600 and the pixel electrode 700 is formed on the second passivation layer 650.

FIG. 5 is a schematic cross-sectional view of a thin film transistor substrate according to an embodiment of the present invention, which corresponds to a cross-section of line E-F in FIG. That is, Fig. 5 corresponds to the cross section of the opening region.

5, a buffer layer 250 is formed on a substrate 100, a gate insulating layer 350 is formed on the buffer layer 250, an interlayer insulating layer 450 is formed on the gate insulating layer 350, A first protective film 550 is formed on the interlayer insulating film 450 and a common electrode 600 is formed on the first protective film 550 and a second And a pixel electrode 700 is formed on the second passivation layer 650. In addition,

The present invention is not limited to the top gate structure in which the gate wiring 400 is formed on the semiconductor layer 300. The present invention is not limited to the top gate structure in which the gate wiring 400 is formed on the semiconductor layer 300, And a bottom gate structure formed under the substrate 300.

6 is a schematic cross-sectional view of a liquid crystal display device according to an embodiment of the present invention.

6, the liquid crystal display device according to the embodiment of the present invention includes a thin film transistor substrate 1, a counter substrate 2, and a liquid crystal layer 6 formed between both substrates 1 and 2 .

The thin film transistor substrate 1 uses the thin film transistor substrate according to the above embodiment.

The counter substrate 2 comprises a substrate 3, a black matrix 4, and a color filter 5.

The black matrix 4 is formed on the lower surface of the substrate 3 and is patterned to correspond to the non-opening portions of the thin film transistor substrate described above.

The color filter 5 is formed in the region between the black matrices 4 and includes a red color filter, a green color filter, and a blue color filter.

FIG. 6 is a perspective view of a liquid crystal display device according to an embodiment of the present invention. The present invention is not limited to the structure shown in FIG. 6, and may be changed into various structures known in the art. For example, a color filter 5 may be formed on the thin film transistor substrate 1.

100: substrate 200: shielding layer
250: buffer layer 300: semiconductor layer
350: gate insulating film 400: gate wiring
450: interlayer insulating film 500: data wiring
550: first protective film 600: common electrode
650: second protective film 700: pixel electrode

Claims (10)

A gate wiring including a first gate wiring, a second gate wiring, a third gate wiring, and a fourth gate wiring sequentially arranged in the first direction on the substrate;
A data line including a first data line, a second data line, a third data line and a fourth data line arranged in order on the substrate in a second direction;
A semiconductor layer formed to overlap with the gate wiring and the data wiring, respectively, and connected to the data wiring; And
And a pixel electrode connected to the semiconductor layer,
Wherein an interval between the first data line and the second data line and an interval between the third data line and the fourth data line are smaller than an interval between the second data line and the third data line. Transistor substrate. The method according to claim 1,
Wherein the first gate wiring and the second gate wiring are connected to each other, and the third gate wiring and the fourth gate wiring are connected to each other. 3. The method of claim 2,
The first gate wiring and the second gate wiring are connected to each other in a non-display area outside the display area, and the third gate wiring and the fourth gate wiring are connected to each other in a non-display area outside the display area . The method according to claim 1,
Wherein the semiconductor layer is formed in a region between the first data line and the second data line and in an area between the third data line and the fourth data line and is formed in a region between the second data line and the third data line Wherein the thin film transistor substrate is a thin film transistor substrate. The method according to claim 1,
Wherein the semiconductor layer is directly connected to the data line through the first contact hole and is directly connected to the pixel electrode through the second contact hole. The method according to claim 1,
Wherein the semiconductor layer includes a first semiconductor layer overlapping the first gate wiring and a second semiconductor layer overlapping the second gate wiring,
Wherein the first semiconductor layer is connected to the first data line and the second semiconductor layer is connected to the second data line. The method according to claim 6,
Wherein the pixel electrode includes a first pixel electrode connected to the first semiconductor layer and a second pixel electrode connected to the second semiconductor layer,
Wherein the extending direction of the first pixel electrode is different from the extending direction of the second pixel electrode. The method according to claim 1,
Wherein the pixel electrode is provided with a slit therein, and a common electrode for forming a fringe field together with the pixel electrode is further formed below the pixel electrode. The method according to claim 1,
A region between the first data line and the second data line and a region between the third data line and the fourth data line correspond to a non-opening portion through which light is not transmitted, and a region between the second data line and the third data line Region corresponds to an opening through which light is transmitted. A thin film transistor substrate;
An opposing substrate; And
And a liquid crystal layer formed between the both substrates,
Wherein the thin film transistor substrate comprises the thin film transistor substrate according to any one of claims 1 to 9.

Images