KR20150075733A - Thin film transistor and flat panel display device having the same - Google Patents

Abstract

The embodiment of the present invention relates to a thin film transistor and a flat panel display device including the same. The thin film transistor includes a source electrode and a drain electrode which are arranged on a substrate, a first gate electrode which is arranged on the substrate between the source and drain electrodes, a first insulation layer which is arranged on the source and drain electrodes and the first gate electrode, a semiconductor layer which is arranged on the first insulation layer and is connected to the source and drain electrodes, a second insulation layer which is arranged on the semiconductor layer and a second gate electrode which is arranged on the second insulation layer.

Description

[0001] The present invention relates to a thin film transistor and a flat panel display having the thin film transistor.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a flat panel display including the thin film transistor, and more particularly, to a thin film transistor having a dual structure gate electrode and a flat panel display including the thin film transistor.

The thin film transistor includes a semiconductor layer providing source and drain regions and a channel region, a gate electrode overlapping the channel region and insulated from the semiconductor layer by a gate insulating layer, and source and drain electrodes connected to the semiconductor layers of the source and drain regions .

The thin film transistor thus configured is used not only in a semiconductor integrated circuit but also in a flat panel display such as a liquid crystal display (LCD) or an organic light emitting display (AMOLED).

An object of an embodiment of the present invention is to provide a thin film transistor in which damage of a semiconductor layer can be prevented.

Another object of the present invention is to provide a thin film transistor having improved electrical characteristics and reliability.

It is another object of an embodiment of the present invention to provide a flat panel display with improved image quality.

According to an aspect of the present invention, there is provided a thin film transistor including source and drain electrodes disposed on a substrate, a first gate electrode disposed on the substrate between the source and drain electrodes, A first insulating layer disposed on the first gate electrode, a semiconductor layer disposed on the first insulating layer and connected to the source and drain electrodes, a second insulating layer disposed on the semiconductor layer, And a second gate electrode disposed on the insulating layer.

According to another aspect of the present invention, there is provided a flat panel display including a scan line and a data line, a thin film transistor connected between the scan line and the data line, and an organic electroluminescent device connected to the thin film transistor. And a second substrate disposed to face the first substrate, wherein the thin film transistor includes source and drain electrodes disposed on the first substrate, a first substrate on the first substrate between the source and drain electrodes, A first insulating layer disposed on the source and drain electrodes and on the first gate electrode, a semiconductor layer disposed on the first insulating layer and connected to the source and drain electrodes, A second insulating layer disposed on the first insulating layer, and a second gate electrode disposed on the second insulating layer.

The first gate electrode may include a material of the source and drain electrodes, and may be formed to be thinner than the source and drain electrodes.

The source and drain electrodes may be formed of first, second, and third conductive layers, and the first gate electrode may be formed of the first conductive layer.

The second conductive layer may be formed thicker than the first and third conductive layers.

Wherein the first and third conductive layers comprise at least one material selected from the group consisting of titanium (Ti), tantalum (Ta), and tungsten (W), and the second conductive layer comprises at least one selected from the group consisting of molybdenum (Mo) ) And copper (Cu).

A contact hole is formed in the first insulating layer, and the semiconductor layer is connected to the source and drain electrodes through the contact hole.

The semiconductor layer may include polysilicon or an oxide semiconductor. The oxide semiconductor may include zinc oxide (ZnO), and gallium (Ga), indium (In), stannum (Sn), zirconium (Zr) , Hafnium (Hf), and vanadium (V) may be doped.

The first gate electrode and the second gate electrode are arranged to overlap with each other.

Since the parasitic capacitance due to the overlapping of the source and drain electrodes and the gate electrode can be minimized and the source and drain electrodes can be formed of a metal having a low resistance value in the thin film transistor according to the embodiment of the present invention, Can be improved as compared with a thin film transistor. In addition, since the insulating layer is interposed between the source and drain electrodes and the semiconductor layer, the damage of the semiconductor layer due to contact with the metal can be minimized. The reliability of the semiconductor layer is improved and the electrical characteristics of the thin film transistor are improved so that the operation characteristics and the image quality can be improved when the thin film transistor is applied to the flat panel display.

1 is a cross-sectional view illustrating a thin film transistor according to an embodiment of the present invention.
2 is a cross-sectional view illustrating a thin film transistor according to another embodiment of the present invention.
3A to 3E are cross-sectional views illustrating a method of manufacturing a thin film transistor according to an embodiment of the present invention.
4A to 4E are cross-sectional views illustrating a method of manufacturing a thin film transistor according to another embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided so that those skilled in the art will be able to fully understand the present invention, and various modifications may be made thereto, and the scope of the present invention is limited to the embodiments described below It is not.

1 is a cross-sectional view illustrating a thin film transistor according to an embodiment of the present invention.

Referring to FIG. 1, a buffer layer 12 is formed on a substrate 10, and source and drain electrodes 14a and a first gate electrode 14b are disposed on a buffer layer 12. The first gate electrode 14b is disposed between the source and drain electrodes 14a.

A first insulating layer 16 is disposed on the source and drain electrodes 14a and the first gate electrode 14b and a semiconductor layer 18 is disposed on the first insulating layer 16. The semiconductor layer 18 includes a source region, a channel region, and a drain region, and the channel region overlaps with the first gate electrode 14b, and the source and drain regions are connected to the source And the drain electrode 14a.

A second insulating layer 20 is disposed on the semiconductor layer 18 and a second gate electrode 22 is disposed on the second insulating layer 20. The second gate electrode 22 is disposed above the channel region of the semiconductor layer 18, and part or all of the second gate electrode 22 may overlap with the first gate electrode 14b.

In the conventional thin film transistor having one gate electrode, a channel is formed only on one side of the semiconductor layer adjacent to the gate electrode. However, the thin film transistor according to the embodiment of the present invention includes the first gate electrode 14b and the second gate electrode Since the channel is formed on both sides of the semiconductor layer 18 adjacent to the gate electrode 22, the on-current characteristic can be improved as compared with the conventional thin film transistor. The threshold voltage can be easily adjusted to a desired level by adjusting the bias voltage applied to the first gate electrode 14b and the second gate electrode 22, respectively.

In addition, since the first and second gate electrodes 14b and 22 can be arranged so as not to overlap the source and drain electrodes 14a, the embodiment of the present invention can minimize the parasitic capacitance inside the thin film transistor, 1 and the second gate electrodes 14b and 22 are disposed on both sides of the semiconductor layer 18, the reliability of the semiconductor layer 18 due to external light and the change in electrical characteristics can be prevented.

2 is a cross-sectional view illustrating a thin film transistor according to another embodiment of the present invention.

2, a buffer layer 32 is formed on a substrate 30, and source and drain electrodes 36a and a first gate electrode 36b are disposed on a buffer layer 32. [ The first gate electrode 36b is disposed between the source and drain electrodes 36a and may be formed to be thinner than the source and drain electrodes 36a.

For example, the source and drain electrodes 36a may include a first conductive layer 34a, a second conductive layer 35 that is thicker than the first conductive layer 34a, and a third conductive layer 34 that is thinner than the second conductive layer 35. [ Layer 34b, and the first gate electrode 36b may be formed of the first conductive layer 34a.

A first insulating layer 38 is disposed on the source and drain electrodes 36a and the first gate electrode 36b and a semiconductor layer 40 is disposed on the first insulating layer 38. [ The semiconductor layer 40 includes a source region, a channel region, and a drain region, the channel region overlapping the first gate electrode 36b, and the source and drain regions overlapping the source And the drain electrode 36a.

A second insulating layer 42 is disposed on the semiconductor layer 40 and a second gate electrode 44 is disposed on the second insulating layer 42. The second gate electrode 44 is disposed above the channel region of the semiconductor layer 40, and part or all of the second gate electrode 44 may overlap with the first gate electrode 36b.

In the conventional thin film transistor having one gate electrode, a channel is formed only on one side of the semiconductor layer adjacent to the gate electrode. However, the thin film transistor according to the embodiment of the present invention includes the first gate electrode 36b and the second gate electrode Since the channel is formed on both sides of the semiconductor layer 40 adjacent to the gate electrode 44, the on-current characteristic can be improved as compared with the conventional thin film transistor. The threshold voltage can be easily adjusted to a desired level by adjusting the magnitude of the bias voltage applied to the first gate electrode 36b and the second gate electrode 44, respectively.

In addition, the embodiment of the present invention can minimize the parasitic capacitance inside the thin film transistor because the first and second gate electrodes 36b and 44 can be arranged so as not to overlap with the source and drain electrodes 36a, 1 and the second gate electrodes 36b and 44 are disposed on both sides of the semiconductor layer 40, the reliability of the semiconductor layer 40 due to external light and the change in electrical characteristics can be prevented.

The thin film transistor of Fig. 2 has a structure which is advantageous for forming the source and drain electrodes 36a into a metal having a low resistance value.

When the source and drain electrodes 14a are formed of a metal having a low resistance value, for example, aluminum (Al) or copper (Cu) in the thin film transistor of FIG. 1, It may be oxidized or contaminated and the electrical characteristics may be changed.

2, the second conductive layer 35 is formed of aluminum (Al) or copper (Cu), and the first and third conductive layers 34a and 34b are formed of titanium (Ti), tantalum The first and third conductive layers 34a and 34b may be formed of a barrier layer or a capping layer that prevents diffusion of aluminum (Al) or copper (Cu) atoms, And prevents direct contact with the semiconductor layer 40, the damage of the semiconductor layer 40 can be effectively prevented.

1 and 2, since the first insulating layers 16 and 38 are disposed between the source and drain electrodes 14a and 36a and the semiconductor layers 18 and 40, The damage of the semiconductor layers 18 and 40 due to the contact with the metal can be minimized.

Hereinafter, embodiments of the present invention will be described in detail through a manufacturing process of a thin film transistor.

3A to 3E are cross-sectional views illustrating a method of manufacturing a thin film transistor according to an embodiment of the present invention.

Referring to FIG. 3A, a buffer layer 12 and a conductive layer 14 are sequentially formed on a substrate 10.

The substrate 10 may be a semiconductor substrate such as silicon (Si), an insulating substrate such as glass or resin, or a metal substrate.

The buffer layer 12 may be formed of silicon oxide or silicon nitride, or may be formed of a lamination or compound of silicon oxide and silicon nitride.

The conductive layer 14 may be formed of at least one of tungsten (W), titanium (Ti), molybdenum (Mo), silver (Ag), tantalum (Ta), aluminum (Al), copper (Cu) And niobium (Nb), or an alloy of these metals.

Referring to FIG. 3B, the conductive layer 14 is patterned to form the source and drain electrodes 14a and the first gate electrode 14b.

The first gate electrode 14b may be disposed between the source and drain electrodes 14a and thinner than the source and drain electrodes 14a.

For example, a photoresist layer is formed on the conductive layer 14, and the photoresist layer is patterned by a photolithography process using a half-tone mask (first mask). When the conductive layer 14 is etched using the photoresist pattern as a mask, the source and drain electrodes 14a and the first gate electrode 14b having a thickness thinner than the source and drain electrodes 14a can be simultaneously formed.

Referring to FIG. 3C, a first insulating layer 16 is formed on an upper portion including the source and drain electrodes 14a and the first gate electrode 14b, and a first insulating layer 16 is formed by photolithography and etching using a second mask. The layer 16 is patterned to form the contact hole 16a so that a predetermined portion of the source and drain electrodes 14a is exposed.

The first insulating layer 16 may be formed of silicon oxide (SiOx), silicon nitride (SiN), aluminum oxide (AlOx), or a laminate or a compound thereof. The first insulating layer 16 may be formed of, for example, a lamination of silicon oxide (SiOx) and aluminum oxide (AlOx).

Referring to FIG. 3D, a semiconductor layer 18 is formed on the first insulating layer 16 so that the contact hole 16a is buried. The second insulating layer 20 is formed on the semiconductor layer 18 and then the second insulating layer 20 and the semiconductor layer 18 are patterned by photolithography and etching using a third mask.

The semiconductor layer 18 may be formed of polycrystalline silicon or an oxide semiconductor. The oxide semiconductor may include zinc oxide (ZnO), and may include at least one selected from the group consisting of Ga, In, Sn, Zr, Hf, At least one of ions of copper (Cu), germanium (Ge), gadolinium (Gd) and vanadium (V) can be doped.

The second insulating layer 20 may be formed of silicon oxide (SiOx), silicon nitride (SiN), aluminum oxide (AlOx), or a laminate or a compound thereof. The second insulating layer 20 may be formed of, for example, a lamination of aluminum oxide (AlOx) and silicon oxide (SiOx).

Referring to FIG. 3E, a second gate electrode 22 is formed on the second insulating layer 20.

For example, after the conductive layer is formed on the second insulating layer 20, the conductive layer is patterned by a photolithography and etching process using a fourth mask to form a second insulating layer 20 on the first gate electrode 14b The second gate electrode 22 can be formed. The second gate electrode 22 may partially or wholly overlap with the first gate electrode 14b.

4A to 4E are cross-sectional views illustrating a method of manufacturing a thin film transistor according to another embodiment of the present invention.

4A, a buffer layer 32 is formed on a substrate 30, and a first conductive layer 34a, a second conductive layer 35, and a third conductive layer 34b are formed on the buffer layer 32 Sequentially.

The substrate 30 may be a semiconductor substrate such as silicon (Si), an insulating substrate such as glass or resin, or a metal substrate.

The buffer layer 32 may be formed of silicon oxide or silicon nitride, or may be formed of a lamination or compound of silicon oxide and silicon nitride.

The second conductive layer 35 is formed thicker than the first conductive layer 34a and the third conductive layer 34b and is made of molybdenum (Mo), aluminum (Al), and copper (Cu) It is preferable to form at least one material selected from the group.

The first conductive layer 34a and the third conductive layer 34b may have the same thickness and include at least one material selected from the group consisting of titanium (Ti), tantalum (Ta), and tungsten (W) . The first and third conductive layers 34a and 34b may be formed of, for example, titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tungsten silicon nitride (WSiN) . The first conductive layer 34a and the third conductive layer 34b may serve as a barrier layer or a capping layer to prevent metal atoms of the second conductive layer 35 from diffusing.

4B, the source and drain electrodes 36a and the first gate electrode 36b are sequentially patterned by sequentially patterning the third conductive layer 34b, the second conductive layer 35, and the first conductive layer 34a, . The first gate electrode 36b may be disposed between the source and drain electrodes 36a and thinner than the source and drain electrodes 36a.

For example, a photosensitive film is formed on the third conductive layer 34b, and the photosensitive film is patterned by a photolithography process using a halftone mask (first mask) and a developing process. When the third conductive layer 34b, the second conductive layer 35 and the first conductive layer 34a are sequentially etched using the photoresist pattern as a mask, the first conductive layer 34a and the second conductive layer 35 The source and drain electrodes 36a formed of the first conductive layer 34a and the third conductive layer 34b and the first gate electrode 36b formed of the first conductive layer 34a can be formed at the same time.

Referring to FIG. 4C, a first insulating layer 38 is formed on an upper portion including the source and drain electrodes 36a and the first gate electrode 36b, and the first insulating layer 38 is formed by photolithography and etching using a second mask. The layer 38 is patterned to form a contact hole 38a such that a predetermined portion of the source and drain electrodes 36a are exposed.

The first insulating layer 38 may be formed of silicon oxide (SiOx), silicon nitride (SiN), aluminum oxide (AlOx), or a laminate or a compound thereof. The first insulating layer 38 may be formed of, for example, a laminate of silicon oxide (SiOx) and aluminum oxide (AlOx).

Referring to FIG. 4D, a semiconductor layer 40 is formed on the first insulating layer 38 so that the contact hole 38a is embedded. The second insulating layer 42 is formed on the semiconductor layer 40 and then the second insulating layer 42 and the semiconductor layer 40 are patterned by photolithography and etching using a third mask.

The semiconductor layer 40 may be formed of polycrystalline silicon or an oxide semiconductor. The oxide semiconductor may include zinc oxide (ZnO), and may include at least one selected from the group consisting of Ga, In, Sn, Zr, Hf, At least one of ions of copper (Cu), germanium (Ge), gadolinium (Gd) and vanadium (V) can be doped.

The second insulating layer 42 may be formed of silicon oxide (SiOx), silicon nitride (SiN), aluminum oxide (AlOx), or a laminate or a compound thereof. The second insulating layer 42 can be formed of, for example, a lamination of aluminum oxide (AlOx) and silicon oxide (SiOx).

Referring to FIG. 4E, a second gate electrode 44 is formed on the second insulating layer 42.

For example, after the conductive layer is formed on the second insulating layer 42, the conductive layer is patterned by a photolithography and etching process using a fourth mask to form a second insulating layer 42 The second gate electrode 44 can be formed. The second gate electrode 44 may partially or entirely overlap with the first gate electrode 36b.

The thin film transistor according to the embodiment of the present invention is formed by simultaneously patterning the source and drain electrodes 14a and 36a and the first gate electrodes 14b and 36b using a halftone mask and forming the semiconductor layers 18 and 40 and the second Since the insulating layers 20 and 42 can be patterned simultaneously using one mask, they can be manufactured using four masks.

The thin film transistor according to the embodiment of the present invention can be applied to a flat panel display.

FIGS. 5A and 5B are a plan view and a cross-sectional view for explaining an embodiment of a flat panel display device to which a thin film transistor is applied according to an embodiment of the present invention, and will be schematically described with reference to a display panel for displaying an image.

The display panel comprises a substrate 100 on which various devices are formed as a first substrate, a second substrate arranged so as to face the substrate 100, an encapsulation substrate 300, and a substrate 100, And a sealing material 400 interposed between the sealing substrate 300 and the sealing substrate 300.

Referring to FIG. 5A, a substrate 100 is defined as a pixel region 140 and a non-pixel region 150 around the pixel region 140. A plurality of organic light emitting devices 130 connected in a matrix manner between the scan lines 142 and the data lines 144 are formed on the substrate 100 of the pixel region 140, A scan line 142 and a data line 144 extending from the scan line 142 and the data line 144 of the pixel region 140 and a power supply line (not shown) for operating the organic electroluminescent device 130 A scan driver 160 and a data driver 170 for processing a signal supplied from the outside through the pad 152 and supplying the signal to the scan line 142 and the data line 144 are formed.

6, the organic electroluminescent device 130 includes an anode electrode 132 and a cathode electrode 138, and an organic thin film layer 136 interposed between the anode electrode 132 and the cathode electrode 138 . The organic thin film layer 136 may be formed by stacking a hole transport layer, an organic light emitting layer, and an electron transport layer, and may further include a hole injection layer and an electron injection layer. In addition, a thin film transistor connected between the scan line 142 and the data line 144 for controlling the operation of the organic electroluminescent device 130 and a capacitor for holding the signal may be further included.

The thin film transistor has the structure of FIG. 1 or FIG. 2, and can be manufactured according to the manufacturing method described with reference to FIGS. 3A to 3E or 4A to 4E.

The organic electroluminescent device 130 including the thin film transistor will now be described in more detail with reference to FIGS. 5A and 6.

The buffer layer 112 is formed on the substrate 100 and the source and drain electrodes 114a and the first gate electrode 114b are disposed on the buffer layer 112. [ The first gate electrode 114b is disposed between the source and drain electrodes 114a.

In this case, a scan line 142 connected to the first gate electrode 114b is formed in the pixel region 140, and a scan line 142 extending from the scan line 142 of the pixel region 140 is formed in the non- A pad 142 for receiving a signal from the outside and a pad 152 for receiving a signal from the outside.

A first insulating layer 116 is disposed on the source and drain electrodes 114a and the first gate electrode 114b and a semiconductor layer 118 is disposed on the first insulating layer 116. [ The semiconductor layer 118 includes a source region, a channel region, and a drain region, with the channel region overlapping the first gate electrode 114b and the source and drain regions being electrically connected to the source < RTI ID = 0.0 > And the drain electrode 114a.

A second insulating layer 120 is disposed on the semiconductor layer 118 and a second gate electrode 122 is disposed on the second insulating layer 120. The second gate electrode 122 may be disposed above the channel region of the semiconductor layer 118, and some or all of the second gate electrode 122 may overlap with the first gate electrode 114b.

In this case, a data line 144 connected to the source and drain electrodes 114a is formed in the pixel region 140 and a data line 144 extending from the data line 144 of the pixel region 140 is formed in the non- A pad 144 and a pad 152 for receiving a signal from the outside may be formed.

A planarization layer 124 is formed on the entire upper surface including the thin film transistor and the anode electrode 132 is formed on the planarization layer 124 so as to be connected to the source or drain electrode 114a. Although not shown in FIG. 6, the anode electrode 132 is connected to the source or drain electrode 114a through a via hole formed in the planarization layer 124.

A pixel defining layer 134 is formed on the planarization layer 124 and a organic thin film layer 136 is formed on the exposed anode electrode 132 so that a part of the region of the anode electrode 132 A cathode electrode 138 is formed on the pixel defining layer 134 including the organic thin film layer 136.

5B, an encapsulation substrate 300 for encapsulating the pixel region 140 is disposed on the substrate 100 on which the organic light emitting device 130 is formed, and the encapsulation substrate 300 Are bonded to the substrate 100 to complete the display panel.

The flat panel display according to the embodiment of the present invention can improve the image quality by improving the current and voltage characteristics by the thin film transistor whose electrical characteristics and reliability are improved as compared with the conventional one. Particularly, the current-driven flat panel display device can have high reliability because the luminance is not lowered by the thin film transistor in which the threshold voltage is stably maintained.

As described above, the best embodiments of the present invention have been disclosed through the detailed description and the drawings. It is to be understood that the terminology used herein is for the purpose of describing the present invention only and is not used to limit the scope of the present invention described in the claims or the claims. Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

10, 30, 100: substrate 12, 32, 112: buffer layer
14, 114: conductive layers 14a, 36a, 114a: source and drain electrodes
14b, 36b, 114b: first gate electrode 16, 38, 116: first insulating layer
16a, 38a: contact holes 18, 40, 118: semiconductor layers
20, 42, 120: second insulating layer 22, 44, 122: second gate electrode
34a and 34b: first and third conductive layers 35: second conductive layer
124: planarization layer 130: organic electroluminescent device
132: anode electrode 134: pixel defining film
136: organic thin film layer 138: cathode electrode
140: pixel region 142: scan line
144: Data line 150: Non-pixel area
152: pad 160: scan driver
170: Data driver 300: Encapsulation substrate
400: Seal material

Claims (24)

Source and drain electrodes disposed on the substrate;
A first gate electrode disposed on the substrate between the source and drain electrodes;
A first insulating layer disposed on the source and drain electrodes and the first gate electrode;
A semiconductor layer disposed on the first insulating layer and connected to the source and drain electrodes;
A second insulating layer disposed on the semiconductor layer; And
And a second gate electrode disposed on the second insulating layer.
The thin film transistor of claim 1, wherein the first gate electrode comprises a material of the source and drain electrodes.
The thin film transistor of claim 2, wherein the first gate electrode is thinner than the source and drain electrodes.
The thin film transistor according to claim 1, wherein the source and drain electrodes comprise first, second and third conductive layers, and the first gate electrode comprises the first conductive layer.
The thin film transistor according to claim 4, wherein the second conductive layer is thicker than the first and third conductive layers.
The thin film transistor of claim 4, wherein the first and third conductive layers comprise at least one material selected from the group consisting of titanium (Ti), tantalum (Ta), and tungsten (W).
The thin film transistor of claim 4, wherein the second conductive layer comprises at least one material selected from the group consisting of molybdenum (Mo), aluminum (Al), and copper (Cu).
The thin film transistor of claim 1, wherein the first insulating layer is provided with a contact hole, and the semiconductor layer is connected to the source and drain electrodes through the contact hole.
The thin film transistor according to claim 1, wherein the semiconductor layer comprises polysilicon or an oxide semiconductor.
The thin film transistor of claim 9, wherein the oxide semiconductor comprises zinc oxide (ZnO).
The method according to claim 10, wherein the oxide semiconductor is doped with at least one of ions of gallium (Ga), indium (In), stannum (Sn), zirconium (Zr), hafnium (Hf) and vanadium .
The thin film transistor of claim 1, wherein the first gate electrode and the second gate electrode overlap each other.
A first substrate including a scan line and a data line, a thin film transistor connected between the scan line and the data line, and an organic electroluminescent device connected to the thin film transistor; And
And a second substrate disposed to face the first substrate,
The thin film transistor
Source and drain electrodes disposed on the first substrate;
A first gate electrode disposed on the first substrate between the source and drain electrodes;
A first insulating layer disposed on the source and drain electrodes and the first gate electrode;
A semiconductor layer disposed on the first insulating layer and connected to the source and drain electrodes;
A second insulating layer disposed on the semiconductor layer; And
And a second gate electrode disposed on the second insulating layer.
14. The flat panel display of claim 13, wherein the first gate electrode comprises a material of the source and drain electrodes.
The flat panel display according to claim 13, wherein the first gate electrode is thinner than the source and drain electrodes.
14. The flat panel display according to claim 13, wherein the source and drain electrodes comprise first, second and third conductive layers, and the first gate electrode comprises the first conductive layer.
The flat panel display according to claim 16, wherein the second conductive layer is thicker than the first and third conductive layers.
17. The flat panel display of claim 16, wherein the first and third conductive layers comprise at least one material selected from the group consisting of titanium (Ti), tantalum (Ta), and tungsten (W).
17. The flat panel display of claim 16, wherein the second conductive layer comprises at least one material selected from the group consisting of molybdenum (Mo), aluminum (Al), and copper (Cu).
14. The flat panel display of claim 13, wherein the first insulating layer is provided with a contact hole, and the semiconductor layer is connected to the source and drain electrodes through the contact hole.
14. The flat panel display according to claim 13, wherein the semiconductor layer comprises polysilicon or an oxide semiconductor.
The flat panel display according to claim 21, wherein the oxide semiconductor comprises zinc oxide (ZnO).
The method according to claim 22, wherein the oxide semiconductor is a flat panel display in which at least one of ions of gallium (Ga), indium (In), stannum (Sn), zirconium (Zr), hafnium (Hf), and vanadium Device.
14. The flat panel display of claim 13, wherein the first gate electrode and the second gate electrode overlap each other.

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