KR20150054261A - Nitnide based field effect transistor and method of fabricating the same - Google Patents

Abstract

A manufacturing method of a nitride-based field device of the present invention comprises: a step of forming a nitride-based laminate which forms a nitride-based field device on a sapphire substrate; a step of attaching a first heat conduction substrate on the opposite side of an area in which the sapphire substrate of the nitride-based laminate is located; a step of removing the sapphire substrate; a step of forming an additional laminate on the nitride-based laminate area in which the sapphire substrate is removed; and a step of attaching a second heat conduction substrate on an exposing area of the additional laminate. According to the present invention, leakage current can be effectively prevented with low priced manufacturing costs.

Description

[0001] NITRIDE BASED FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING THE SAME [0002]

The present invention relates to a nitride-based transistor device having a high-voltage, high-current density, and more particularly to a nitride-based vertical field effect transistor (FET) having a good heat-releasing characteristic based on an epitaxial lateral overgrowth transistor (HFET) device.

A power device using a silicon semiconductor is used for a power amplifier circuit, a power supply circuit, and a motor drive circuit. However, due to the limitations of silicon semiconductors, the demand for high-voltage, low-resistance, and high-speed silicon devices has reached their limits and it has become difficult to meet market demands. Therefore, the development of a III-V device having features such as high breakdown voltage, high temperature operation, high current density, high speed switching and low on-resistance is under development.

However, the proposed III-V device has a horizontal structure in which the source, gate, and drain are arranged along the surface of the substrate, so that it is not suitable for a power device requiring a large current. Moreover, since the structure is not easy to dissipate heat, there is a problem of malfunction and device deterioration in an excessive operation. Further, there is a problem in that a so-called current collapse phenomenon occurs in which electrons are trapped between the semiconductor and the protective film in a high-voltage operation and the drain current is reduced. Furthermore, a III-V device of a horizontal structure, especially a GaN device, is used for high-speed response of 600 V or less due to insufficient pressure resistance.

CAVET (Current Aperture Vertical Electron Transistor) is a vertical type field effect transistor grown on a GaN substrate. The field effect transistor uses 2DEG and CBL (Current Blocking Layer) So that the performance can be improved. However, since CAVET is a normally-on device, there is a practical limitation.

On the other hand, when a GaN substrate is used for manufacturing a gallium nitride transistor, there is a disadvantage due to a high price. When a sapphire substrate is used, a breakdown voltage (BV) is generated due to a large amount of occurrence of threading dislocation (TD) Is low.

The present invention provides a nitride-type field-effect transistor of a vertical type which is fabricated at low cost and can effectively block a leakage current.

Alternatively, the present invention provides a nitride-based field-effect transistor having good heat-generating characteristics.

Alternatively, the present invention aims to provide a vertical type nitride-based field effect transistor having a high breakdown voltage and a high current density.

According to an aspect of the present invention, there is provided a method of manufacturing a gallium nitride-based device, including: forming a gallium nitride-based laminate constituting a gallium nitride-based device on a sapphire substrate; Attaching a first thermally conductive substrate to a surface of the gallium nitride-based laminate opposite to a surface on which the sapphire substrate is located; Removing the sapphire substrate; Forming an additional laminate on the surface of the gallium nitride based laminate from which the sapphire substrate has been removed; And attaching a second thermally conductive substrate to the exposed surface of the additional laminate.

Here, the step of attaching the first thermally conductive substrate may include: forming a protective layer made of aluminum nitride or silicon nitride on the gallium nitride-based laminate; And attaching a first thermally conductive substrate to the protective layer.

Here, the step of attaching the second thermally conductive substrate may include the steps of: forming an intermediate layer of a metal material containing nano silver, AuSn, NiSn, or gold or silver on the gallium nitride-based laminate; And attaching a second thermally conductive substrate to the protective layer.

The step of forming the gallium nitride-based laminate may include: forming a seed layer of a first conductivity type on a sapphire substrate; Performing ELO growth on the seed layer to form an intrinsic gallium nitride semiconductor layer; Forming a first switch semiconductor layer of a first conductivity type surrounding the intrinsic gallium nitride semiconductor layer by continuously performing ELO growth with gallium nitride of a first conductivity type; Forming a second switch semiconductor layer of a second conductivity type on the first switch semiconductor layer; Forming a third switch semiconductor layer of a first conductivity type on the second switch semiconductor layer; Etching a portion of the upper part of the second switch semiconductor layer and the first switch semiconductor layer, and forming a gate insulating film on the etched surface; Forming a gate electrode on the gate insulating film; And forming a source electrode on the third switch semiconductor layer between the gate electrodes.

Here, the forming of the additional laminate may include forming a drain electrode on the surface of the gallium nitride-based laminate from which the sapphire substrate is removed.

The method may further include forming a protective layer for protecting the source electrode and the gate electrode.

Here, after forming the seed layer, a step of forming a TD blocking insulating layer on the seed layer may be performed before forming the intrinsic gallium nitride semiconductor layer.

Here, before the step of forming the gate insulating layer, the step of forming the third switch semiconductor layer may further include the step of performing a net-like etching on the third switch semiconductor layer.

The step of forming the gallium nitride-based laminate may include: forming a seed layer on the sapphire substrate; Performing ELO growth on the seed layer to form an intrinsic gallium nitride semiconductor layer; Forming a first switch semiconductor layer of a first conductivity type surrounding the intrinsic gallium nitride semiconductor layer by continuously performing ELO growth with gallium nitride of a first conductivity type; Forming a second switch semiconductor layer of a second conductivity type on the first switch semiconductor layer; Forming a third switch semiconductor layer of a first conductivity type on the second switch semiconductor layer; Etching a region not overlapping the seed layer as a partial upper region of the second switch semiconductor layer and the first switch semiconductor layer and forming a gate insulating film on the etched surface; And forming a gate electrode on the gate insulating film and forming a source electrode on the third switch semiconductor layer between the gate insulating films.

The forming of the additional layered body may include forming an insulating layer on the seed layer and the intrinsic gallium nitride semiconductor layer exposed on the surface from which the sapphire substrate is removed; And forming a drain electrode on the insulating film.

Here, before the step of forming the insulating layer on the exposed seed layer and the intrinsic gallium nitride semiconductor layer, etching is performed on the gallium nitride-based laminate from which the sapphire substrate has been removed to remove damage due to the lift-off process The method comprising the steps of:

The forming of the gallium nitride-based laminate may include: forming a high-concentration gallium nitride semiconductor layer on a sapphire substrate; Forming at least two window insulating layers spaced apart from each other on the high-concentration gallium nitride semiconductor layer; Performing ELO growth from the surface of the highly concentrated gallium nitride semiconductor layer exposed between the window insulating layers to form an initial growth layer; Continuing ELO growth with gallium nitride or intrinsic gallium nitride of the first conductivity type to form a first switch semiconductor layer surrounding the initial growth layer; Forming a second switch semiconductor layer of a second conductivity type on the first switch semiconductor layer; Forming a third switch semiconductor layer of a first conductivity type on the second switch semiconductor layer; Etching a region not overlapping the seed layer as a partial upper region of the second switch semiconductor layer and the first switch semiconductor layer and forming a gate insulating film on the etched surface; And forming a gate electrode on the gate insulating film and forming a source electrode on the third switch semiconductor layer between the gate insulating films.

The step of forming the gallium nitride-based laminate may include a step of removing a portion of the gallium nitride-based stacked body to the high-concentration gallium nitride semiconductor layer after the step of forming the gate electrode and the source electrode, And forming a drain electrode on the high-concentration gallium nitride semiconductor layer.

Here, after forming the initial growth layer, a buffer layer may be formed of gallium nitride of a first conductivity type, which is a high concentration, prior to forming the first switch semiconductor layer. And forming a TD blocking insulating layer on the buffer layer in a staggered position with respect to the window insulating layer.

Here, in the forming of the first switch semiconductor layer, the first switch semiconductor layer in which a TD blocking insulating layer is inserted may be formed at a middle height between the window insulating layer and the window insulating layer.

Here, the forming of the additional laminate may include forming a drain electrode on the surface of the gallium nitride-based laminate from which the sapphire substrate is removed.

When the gallium nitride-based field-effect transistor of the present invention according to the above-described configuration is used, there is an advantage that the leakage current can be effectively blocked at a low manufacturing cost.

Alternatively, the present invention has an advantage that a nitride-based field-effect transistor having good heat-generating characteristics can be implemented.

Alternatively, the present invention has an advantage that a nitride-based field-effect transistor having high breakdown voltage, high current density, and normally off characteristics can be implemented.

FIG. 1 illustrates a structure of a nitride-based field-effect transistor according to an embodiment of the present invention.
Fig. 2 shows a nitride-based field-effect transistor of another embodiment capable of more effectively suppressing the channel's TD.
3A to 3Q illustrate a process for fabricating the nitride-based field-effect transistor of FIG.
FIG. 4 illustrates a structure of a nitride-based field-effect transistor according to another embodiment of the present invention.
FIGS. 5A to 5R show a process of manufacturing the nitride-based field-effect transistor of FIG.
FIG. 6 illustrates the structure of a nitride-based field-effect transistor according to another embodiment of the present invention.
FIG. 7 shows a nitride-based field-effect transistor of another embodiment capable of more effectively suppressing the channel's TD.
Fig. 8 shows a nitride-based field-effect transistor of another embodiment capable of more effectively suppressing the channel's TD.
Fig. 9 shows a nitride-based field-effect transistor of another embodiment capable of more effectively suppressing the channel's TD.
FIGS. 10A to 10G show a process of manufacturing the nitride-based field-effect transistor of FIG.
Figs. 11A to 11C show processes performed instead of Figs. 10A to 10C when the sapphire substrate is replaced with a silicon substrate.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. The following embodiments are provided by way of example so that those skilled in the art can sufficiently convey the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the width, length, thickness, etc. of components may be exaggerated for convenience. It is also to be understood that when an element is referred to as being "above" or "above" another element, But also includes the case where there are other components in between. Like reference numerals designate like elements throughout the specification.

In the following description of the embodiments, the expression of a gallium nitride semiconductor is not limited to GaN, but may be a three-component system such as AlGaN or InGaN, or a variety of nitride-based semiconductors such as AlInGaN.

In the description of the embodiments described below, the n-type is described as the first conductive type and the p-type is described as the second conductive type. However, the opposite case is of course possible

FIG. 1 illustrates a structure of a nitride-based field-effect transistor according to an embodiment of the present invention. The numerical values set forth in the drawings and the following description are for illustrative purposes only and are not intended to be limiting.

The illustrated nitride-based field effect transistor comprises a thermally conductive lower substrate 2; An intermediate layer (8) located on the thermally conductive lower substrate (2); A drain electrode (11) located on the intermediate layer; A high concentration n-type gallium nitride semiconductor layer 22 located on the drain electrode 11; An intrinsic gallium nitride semiconductor layer (24) located on the high-concentration n-type gallium nitride semiconductor layer; A first switch semiconductor layer (40) disposed on the intrinsic gallium nitride semiconductor layer (24) so as to surround the intrinsic gallium nitride semiconductor layer (24); A second switch semiconductor layer (50) located on the first switch semiconductor layer (40); A third switch semiconductor layer (60) located on the second switch semiconductor layer (50); A gate insulating layer 74 disposed on the trench structure in which a portion of the upper portion of the third switch semiconductor layer 60, the second switch semiconductor layer 50, and the first switch semiconductor layer 40 is recessed; A gate electrode 76 located above the gate insulating film; A source electrode 72 located on the third switch semiconductor layer 60 between the gate electrodes 76; And a thermally conductive top substrate 99.

Depending on the implementation, the space between the drain electrodes 11 may be replaced by a lower protective layer 12. For example, a lower protective layer 12 made of AlN or SiN may be formed, for example.

According to the implementation, the electrode pad 93 and the connection 91 to the gate electrode 76, the electrode pad 95 and the connection portion 94 to the source electrode 72, A layer 96 is located and a thermally conductive substrate 99 can be attached to the top of the layer 96.

Although the drain electrode 11 is formed in a downward direction to facilitate heat dissipation in the vertical type field effect transistor structure, in the case of another embodiment for reducing the thickness of the device, the high concentration n-type gallium nitride semiconductor layer or a separate And may be located on the side in the form of being connected to the conductive layer.

The drain electrode 11 may be formed of a metal material such as a material including at least one of Ti, Al, and Au so as to be advantageous to heat emission, but may be formed of a conductive semiconductor or an organic material in applications where heat emission is not important.

The intermediate layer 8 may be formed of a noble metal based material having high process affinity and high thermal / electrical conductivity. For example, nano Ag may be formed of AuSn, NiSn, Au, Ag, Al, or the like.

The lower thermally conductive substrate 2 and the upper thermally conductive substrate 99 may be formed of a material having excellent thermal conductivity and mechanical properties such as a copper substrate.

The high-concentration n-type gallium nitride semiconductor layer (22) comprises the intrinsic gallium nitride semiconductor layer (24); And the first switch semiconductor layer 40 are formed by ELO growth.

The first switch semiconductor layer 40 as the n-GaN layer, the second switch semiconductor layer 50 as the pGaN layer, and the third switch semiconductor layer 60 as the n + GaN layer are grown by c- .

The source electrode 72 is connected to a source core 71 passing through the third switch semiconductor layer 60. For example, before the source electrode 72 is formed, a net-like etching is performed on the third switch semiconductor layer 60, which is an n + GaN layer, to remove a portion of the upper portion of the second switch semiconductor layer 50, which is a p- The source electrode 71 can be formed by depositing the source electrode 71 with a metal material.

The gate electrode 76 is formed in a trench shape having a slope so that a channel corresponding to the npn junction can be formed by the first to third switch semiconductor layers 40, 50, and 60 when a turn-on voltage is applied. . The trench shape may have a shape in which the third switch semiconductor layer 60, the second switch semiconductor layer 50, and a part of the upper part of the first switch semiconductor layer 40 are removed.

The source electrode 72 and the gate electrode 76 are formed at alternate positions, and may be formed of a conductive material such as a metal or a conductive film. A protection layer 96 may be formed to cover the source electrode 72 and the gate electrode 76 or protect the source electrode 72 and the gate electrode 76, . For example, a protective layer 96 made of AlN or SiN may be formed.

The illustrated field effect transistor has a structure in which a gallium nitride field effect transistor stack is located between a thermally conductive lower substrate 2 and a thermally conductive upper substrate 99, It has an advantage that it can be released effectively and rapidly.

In addition, in the illustrated field effect transistor, a device is formed by ELO growth using a GaN seed on a comparatively inexpensive sapphire substrate or a silicon substrate, and effectively suppressing occurrence of TD (Threading dislocation) due to ELO growth on the source electrode side have. As a result, it is possible to implement a vertical type GaN-based electronic device having good pressure resistance characteristics at low cost.

Fig. 2 shows a nitride-based field-effect transistor of another embodiment capable of more effectively suppressing the channel's TD.

The illustrated field effect transistor is similar to most of the elements shown in FIG. 1 except that the TD blocking insulating layer 23 is further provided on the high-concentration n-type gallium nitride semiconductor layer 22.

The illustrated TD blocking insulating layer 23 can be formed of SiO 2 or the like on the ELO seed, thereby decreasing the TD, increasing the electron mobility, and reducing the turn-on resistance. In addition, since there is no TD starting from n + GaN in the channel between the source electrode 72 and the drain electrode 11, the leakage current can be greatly reduced.

3A to 3Q illustrate a process for fabricating the nitride-based field-effect transistor of FIG.

First, as shown in Fig. 3A, an n + type gallium nitride semiconductor layer 22-1 is formed on a sapphire substrate 1, and the n + type gallium nitride semiconductor layer 22-1 of Fig. An insulating layer 22-2 is formed on the n + -type gallium nitride semiconductor layer 22-1. The formed n + -type gallium nitride semiconductor layer 22-1 may have a thickness of less than 0.7 um. In addition, the insulating layer 22-2 may be formed in a <11-00> or <112-0> direction as a SiO2 stripe.

Next, as shown in FIG. 3B, the stacked n + type gallium nitride semiconductor layer 22-1 is etched to form the n + type gallium nitride semiconductor layers 22 shown in FIG. 1, The insulating layer on the n + -type gallium nitride semiconductor layers 22 is removed. At this time, RIE (Reactive Ion Etching) may be applied as an etching method, or general dry etching and / or wet etching may be used. A portion of the sapphire substrate 1 under the etching region may be etched in the etching process.

Next, as shown in FIG. 3D, the n-type gallium nitride semiconductor layer 22 remaining on the sapphire substrate 1 is used as a seed layer to perform the ELO growth to form the intrinsic gallium nitride semiconductor layer 24 .

Next, as shown in FIG. 3E, ELO growth is continued with n-GaN to form a first switch semiconductor layer 40 of n-GaN material surrounding the intrinsic gallium nitride semiconductor layer 24.

The ELO growth in FIGS. 3D and / or 3D can be performed by the so-called PENDEO type ELO growth in which growth proceeds from the seed layer adhered on the sapphire substrate, without a window between the insulating films.

Next, as shown in FIG. 3F, a second switch semiconductor layer 50 made of p-GaN is formed on the n-GaN first switch semiconductor layer 40, and then the second switch semiconductor layer 50 is formed. A third switch semiconductor layer 60 made of n + GaN is formed. The first switch semiconductor layer 40, the second switch semiconductor layer 50, and the third switch semiconductor layer 60 may be formed by c plane growth in a layer structure. The second switch semiconductor layer 50 made of p-GaN may be formed of GaN doped with Mg or the like.

Next, as shown in Fig. 3G, etching of the mesh shape (which may be referred to as a dot pattern in terms of the spaces to be etched) is performed on the third switch semiconductor layer 60 in order to provide a position where the source core is to be formed . It is preferable to determine the mask shape so that the trench region for the gate is also removed in the etching process for performing the net-like etching. As the etching method, RIE (Reactive Ion Etching) may be applied, or general dry etching and / or wet etching may be used.

Next, as shown in FIG. 3H, a portion of the upper portion of the second switch semiconductor layer 50 and the first switch semiconductor layer 40 is etched, as a process of forming a trench structure for a gate. As the etching method, RIE (Reactive Ion Etching) may be applied, or general dry etching and / or wet etching may be used.

Next, as shown in FIG. 3I, an insulating film layer 74-1 is formed in the upper region of the laminated structure of FIG. 3H in order to form a gate insulating film. The insulating film layer 74-1 may be deposited to a thickness of 100 to 1000 angstroms.

3J, photolithography using the photoresist 76-2 is performed in a state in which a gate insulating film 74 in which an unnecessary region is removed from the insulating film layer 74-1 is formed And a gate electrode 76 are formed. For example, a metal layer 76-1 such as Ti / Al / Au or Ni / Au may be deposited on the top of the laminated structure including the photoresist 76-2 for forming the gate electrode 76. [

Next, the photoresist 76-2 and the unnecessary metal layer 76-1 are removed, and photolithography using the photoresist 72-2 is performed as shown in FIG. 3K. Then, the source electrode 72 is removed, . For example, a metal layer 72-1 such as Ni / Au can be deposited on the laminated structure including the photoresist 72-2 for forming the source electrode 72. [ By the above-described deposition process, the metal to be deposited is also filled in the etched holes formed in the mesh as shown in FIG. 3G, thereby forming the source core 71 shown in FIG.

Next, as shown in FIG. 31, the photoresist 72-2 and the unnecessary metal layer 72-1 are removed.

Next, as shown in FIG. 3M, a passivation layer 92-1 (passivation layer) is formed on the laminated structure of FIG. For example, the protective layer 92-1 may be formed by depositing SiNx.

Next, as shown in FIG. 3N, a connecting body (not shown) for connecting the gate electrode 76 and the source electrode 72 to the electrode pad (not shown) in the protective layer 92-2 over the laminated structure of FIG. 1, 91, 94).

3O, an electrode pad 93 for the gate electrode 76, an electrode pad 95 for the source electrode 72, and a protective layer 96 for protecting the electrode pads are formed And a thermally conductive substrate 99 is attached to the upper portion. For example, the thermally conductive substrate 99 may be attached to a metal substrate such as copper (Cu) through a medium layer including AuSn or a noble metal (Au, Ag) so as to function as a kind of heat sink.

Next, as shown in Fig. 3P, in the laminated structure of Fig. 30, the sapphire substrate 1 below is removed. For example, the sapphire substrate 1 can be removed by a laser lift-off process. Depending on the implementation, dry etching may be performed to remove the damaged surface in the lift-off process.

Next, as shown in FIG. 3Q, the insulating layer 12 is formed on the surface from which the sapphire substrate 1 is removed, the region where the drain electrode 11 is to be formed is removed, And then the lower thermally conductive substrate 2 is attached. For example, a SiO2 film is deposited as the insulating layer 12, a drain electrode 11 is deposited using a metal such as Ti / Al / Au or the like, and a lower thermoelectric The conductive substrate 2 can be formed. The attachment of the lower thermally conductive substrate 2 and the drain electrode 11 can be performed by an intermediate layer 18 which is made of a noble metal material having high process affinity and high thermal / For example, nano Ag, AuSn, NiSn, Au, Ag, Al, or the like.

FIG. 4 illustrates a structure of a nitride-based field-effect transistor according to another embodiment of the present invention. The numerical values set forth in the drawings and the following description are for illustrative purposes only and are not intended to be limiting.

In the illustrated nitride-based field-effect transistor,

A thermally conductive lower substrate 2; An intermediate layer (8) located on the thermally conductive lower substrate (2); A drain electrode layer 211 located on the intermediate layer;

A TD blocking insulating layer 221 located in a source region on the drain electrode layer 211;

A seed layer 222 located on the window insulating layer 221; An initial growth layer 224 formed to surround the seed layer 222; A first switch semiconductor layer 240 stacked while covering the initial growth layer 224; A second switch semiconductor layer 250 disposed on the first switch semiconductor layer 240; A third switch semiconductor layer 260 located on the second switch semiconductor layer 250; A gate insulating layer 274 disposed on the trench structure in which a portion of the upper portion of the third switch semiconductor layer 260, the second switch semiconductor layer 250, and the first switch semiconductor layer 240 is recessed; A gate electrode 276 located above the gate insulating layer 274; A source electrode 272 located on the third switch semiconductor layer 260 between the gate electrodes 276; And a thermally conductive upper substrate 299.

According to the implementation, the electrode pad 293 and the connection portion 291 to the gate electrode 276, the electrode pad 295 and the connection portion 294 to the source electrode 272, A layer 296 is located on top of which a thermally conductive substrate 299 can be attached.

The drain electrode layer 211 is formed in a downward direction to facilitate heat dissipation in a vertical type field effect transistor structure. However, in another embodiment for reducing the thickness of the device, the high concentration n-type gallium nitride semiconductor layer or a separate And may be located on the side in the form of being connected to the conductive layer.

The drain electrode layer 211 may be formed of a metal material such as a material including at least one of Ti, Al, and Au so as to be advantageous to heat emission, but may be formed of a conductive semiconductor or an organic material in applications where heat emission is not important.

The intermediate layer 8 may be formed of a noble metal based material having high process affinity and high thermal / electrical conductivity. For example, nano Ag may be formed of AuSn, NiSn, Au, Ag, Al, or the like.

The lower thermally conductive substrate 2 and the upper thermally conductive substrate 299 may be formed of a material having excellent thermal conductivity and mechanical properties such as a copper substrate.

The seed layer 222 may be used as a seed layer when the initial growth layer 224 and the first switch semiconductor layer 40 are formed by ELO growth.

The seed layer 222 may be formed of an intrinsic gallium nitride semiconductor layer and the initial growth layer 224 may be an intrinsic gallium nitride semiconductor layer or an n-GaN semiconductor layer.

The first switch semiconductor layer 240, which is an n-GaN layer, the second switch semiconductor layer 250 which is a pGaN layer, and the third switch semiconductor layer 260 which is an n + GaN layer are grown by c- .

The source electrode 272 is connected to a source core 271 passing through the third switch semiconductor layer 260. For example, before the source electrode 272 is formed, a net-like etching is performed on the third switch semiconductor layer 260, which is an n + GaN layer, to remove a portion of the upper portion of the second switch semiconductor layer 250, which is a p- The source electrode 271 can be formed by depositing the source electrode 271 with a metal material.

The gate electrode 276 is formed in a trench shape having a slope so that a channel corresponding to the npn junction can be formed by the first to third switch semiconductor layers 240, 250, and 260 when a turn-on voltage is applied. . The trench shape may have a shape in which the third switch semiconductor layer 260, the second switch semiconductor layer 250, and a part of the upper part of the first switch semiconductor layer 240 are removed.

The source electrode 272 and the gate electrode 276 are formed at alternate positions, and may be formed of a conductive material such as a metal or a conductive film. According to the implementation, a protective layer 296 may be formed to cover the source electrode 272 and the gate electrode 276, or a protection layer 296 to support connection and insulation with lines drawn out to the outside . For example, a protective layer 296 made of AlN or SiN may be formed.

However, since the field effect transistor shown in the figure is stable in the ELO process, the TD is induced in the upper portion of the source region, and the leakage current may be a problem. In this case, between the drain electrode layer 211 and the TD- A TD blocking insulating layer 221 is provided to block the leakage current. On the other hand, the drain electrode layer 211 extends to the entire bottom surface, and even when the TD blocking insulating layer 221 is present, a path through which the channel current flows when the transistor is turned on is secured.

The illustrated field effect transistor has a structure in which a gallium nitride field effect transistor stack is located between a thermally conductive lower substrate 2 and a thermally conductive upper substrate 99, It has an advantage that it can be released effectively and rapidly.

In addition, in the field effect transistor shown, a device is formed by ELO growth using a GaN seed on a relatively inexpensive sapphire substrate or a silicon substrate, and effective suppression of occurrence of TD (Threading dislocation) due to ELO growth in the channel bottom Thus, it is possible to implement a vertical type GaN-based electronic device having good withstand voltage characteristics at low cost.

In addition, the illustrated field effect transistor can suppress the uncertainty in the ELO process and improve the reliability of the produced product.

FIGS. 5A to 5R show a process of manufacturing the nitride-based field-effect transistor of FIG.

5A, the intrinsic gallium nitride semiconductor layer 222-1 is formed on the sapphire substrate 1 and the intrinsic gallium nitride semiconductor layer 222-1 is grown to a size suitable for the seed layer 222 of FIG. An insulating layer 222-2 is formed on the layer 222-1. The formed intrinsic gallium nitride semiconductor layer 222-1 may have a thickness of less than 0.7 um. In addition, the insulating layer 222-2 may be formed in a <11-00> or <112-0> direction as a SiO2 stripe.

Next, as shown in FIG. 5B, the stacked intrinsic gallium nitride semiconductor layer 222-1 is etched to form the seed layers 222 of FIG. 1, and as shown in FIG. 5C, The insulating layer on the upper portion 22 is removed. At this time, RIE (Reactive Ion Etching) may be applied as an etching method, or general dry etching and / or wet etching may be used. A portion of the sapphire substrate 1 under the etching region may be etched in the etching process.

Next, as shown in FIG. 5D, ELO growth is performed from the seed layer 111 left on the sapphire substrate 1 to form an initial growth layer 224. FIG. The initial growth layer 224 may be formed of an intrinsic gallium nitride semiconductor layer having characteristics similar to the seed layer 111 or an n-GaN semiconductor layer having characteristics similar to those of the first switch semiconductor layer 240 to be formed in a subsequent process. have.

Next, as shown in FIG. 5E, ELO growth is continued with n-GaN to form a first switch semiconductor layer 240 of n-GaN material surrounding the intrinsic gallium nitride semiconductor layer 224.

The ELO growth in FIGS. 5D and / or 5D can be performed by so-called PENDEO-type ELO growth, in which growth proceeds from the seed layer adhered on the sapphire substrate without a window between the insulating films.

Next, as shown in FIG. 5F, a second switch semiconductor layer 250 made of p-GaN is formed on the n-GaN first switch semiconductor layer 240, and then the second switch semiconductor layer 250 is formed. A third switch semiconductor layer 260 made of n + GaN is formed. The first switch semiconductor layer 240, the second switch semiconductor layer 250, and the third switch semiconductor layer 260 may be formed by c-plane growth in a layer structure. The second switch semiconductor layer 250 made of p-GaN may be formed of GaN doped with Mg or the like.

Next, as shown in Fig. 5G, the third switch semiconductor layer 260 is etched in a net shape (which may also be referred to as a dot pattern in terms of the spaces to be etched) in order to provide a position where the source core is to be formed . It is preferable to determine the mask shape so that the trench region for the gate is also removed in the etching process for performing the net-like etching. As the etching method, RIE (Reactive Ion Etching) may be applied, or general dry etching and / or wet etching may be used.

Next, as shown in FIG. 5H, the photoresist 260-1 is covered and photolithography is performed to form a trench structure for the gate. Then, the second switch semiconductor layer 250 and the A portion of the upper portion of the first switch semiconductor layer 240 is etched. As the etching method, RIE (Reactive Ion Etching) may be applied, or general dry etching and / or wet etching may be used.

Next, as shown in Fig. 5I, an insulating film layer 274-1 is formed in the upper region of the laminated structure in Fig. 5H in order to form a gate insulating film. For example, the insulating film layer 274-1 may be deposited by a surface plasma oxidation method with a thickness of 100 to 1000 angstroms, and then a region excluding the gate insulating film may be removed by wet etching using HCl / H2O .

5G, photolithography using the photoresist 276-2 is performed, and a photoresist 276-2 is formed on the gate insulating film 274. In this state, A gate electrode 276, and a source electrode 272 are formed. For example, a metal layer 276-1 such as Ti / Al / Au or Ni / Au is deposited on the laminated structure including the photoresist 276-2 for forming the gate electrode 276 and the source electrode 272 can do.

Next, the photoresist 276-2 and the unnecessary metal layer 276-1 are removed, and a passivation layer 92-1 (passivation layer) is formed on the laminated structure as shown in FIG. 5K. For example, the protective layer 292-1 may be formed by depositing SiNx.

Next, as shown in FIG. 5L, a connecting body (not shown) for connecting the gate electrode 276 and the source electrode 272 to the electrode pad (not shown) in the protective layer 292-2 on the upper part of the laminated structure in FIG. 4, 291, 294).

Next, as shown in FIG. 5M, an electrode pad 293 for the gate electrode 276, an electrode pad 295 for the source electrode 272, and a protective layer 296 for protecting the electrode pads are formed And a thermally conductive substrate 299 is attached to the upper portion. For example, the thermally conductive substrate 299 may be attached to a metal substrate such as copper (Cu) through a medium layer including AuSn or a noble metal (Au, Ag) so as to function as a heat sink.

Next, as shown in Fig. 5N, in the laminated structure of Fig. 5M, the sapphire substrate 1 below is removed. For example, the sapphire substrate 1 can be removed by a laser lift-off process.

Next, as shown in FIG. 5O, dry etching is performed to remove the damaged surface in the lift-off process, and simultaneously or subsequently, a space where the TD blocking insulating layer 221 of FIG. 1 is to be formed is etched . The etch process may be performed in a dry or wet etched state, with the thermally conductive substrate 299 in an upside down position.

Next, as shown in FIG. 5P, an insulating layer is formed on the etched surface, and an unnecessary portion of the insulating layer is removed by photolithography to form a TD blocking insulating layer 221.

Next, as shown in FIG. 5Q, the drain electrode layer 211 is formed on the surface on which the TD blocking insulating layer 221 is formed, and then the lower thermally conductive substrate 2 is removed, as shown in FIG. . For example, the drain electrode layer 211 can be deposited using a metal material such as Ti / Al / Au. The lower thermally conductive substrate 2 can be formed of a material such as copper (Cu) so as to have a heat-sink characteristic. The attachment of the lower thermally conductive substrate 2 and the drain electrode layer 211 can be performed by the intermediate layer 18 which is made of a noble metal material having high process affinity and high thermal / For example, nano Ag, AuSn, NiSn, Au, Ag, Al, or the like.

FIG. 6 illustrates the structure of a nitride-based field-effect transistor according to another embodiment of the present invention. The numerical values set forth in the drawings and the following description are for illustrative purposes only and are not intended to be limiting.

The illustrated nitride-based field-effect transistor comprises a lower substrate 2; A drain electrode layer 411 formed on the lower substrate 2; A high-concentration gallium nitride semiconductor layer 420 formed on the drain electrode layer 411; Window insulating layers 421 located on the high-concentration gallium nitride semiconductor layer 420; An initial growth layer 423 formed between the window insulating layers 421 at a height slightly higher than the initial growth layer 423; A first switch semiconductor layer 440 laminated while surrounding the initial growth layer 423; A second switch semiconductor layer 450 disposed on the first switch semiconductor layer 440; A third switch semiconductor layer 460 located on the second switch semiconductor layer 450; A gate insulating layer 474 disposed on the trench structure in which a portion of the upper portion of the third switch semiconductor layer 460, the second switch semiconductor layer 450, and the first switch semiconductor layer 440 is recessed; A gate electrode 476 located above the gate insulating film 474; And a source electrode 472 located on the third switch semiconductor layer 460 between the gate electrodes 476.

A protective layer 496 for protecting the gate electrode 476 and the source electrode 472 is located and a thermally conductive substrate 499 may be attached thereon. For example, a protective layer 496 made of AlN or SiN may be formed.

Although the drain electrode layer 411 is formed in a downward direction to facilitate heat dissipation in the vertical type field effect transistor structure, in the case of another implementation for reducing the thickness of the device, the high concentration n-type gallium nitride semiconductor layer or a separate And may be located on the side in the form of being connected to the conductive layer.

The drain electrode layer 411 may be formed of a metal material such as a material including at least one of Ti, Al, and Au so as to be advantageous to heat emission, but may be formed of a conductive semiconductor or an organic material in applications where heat emission is not important. The drain electrode layer 411 may be attached to the lower substrate 2 via the intermediate layer 8.

The intermediate layer 8 may be formed of a noble metal based material having high process affinity and high thermal / electrical conductivity. For example, nano Ag may be formed of AuSn, NiSn, Au, Ag, Al, or the like.

The lower substrate 2 and the upper thermally conductive substrate 499 may be formed of a material having excellent thermal conductivity and mechanical characteristics such as a copper substrate.

The high-concentration gallium nitride semiconductor layer 420 may be formed of an n + GaN layer and may have a carrier concentration of more than 1 * 10 ¹⁸ / cm ³ .

The window insulating layers 421 may function as a window for ELO growth, so that intrinsic gallium nitride semiconductor is grown on the surface of the high-concentration gallium nitride semiconductor layer 420 between the window insulating layers, An initial growth layer 423 can be formed. In another embodiment, the initial growth layer 423 may be formed of an n-GaN semiconductor layer. ELO growth continues to form the first switch semiconductor layer 440 of the n-GaN layer. In another implementation, the first switch semiconductor layer 440 may be formed of an iGaN layer.

The first switch semiconductor layer 440 which is an n-GaN layer, the second switch semiconductor layer 450 which is a pGaN layer, and the third switch semiconductor layer 460 which is an n + GaN layer are grown by c- .

The gate electrode 476 is formed in a trench shape having a slope so that a channel corresponding to the npn junction can be formed by the first to third switch semiconductor layers 440, 650, and 660 when a turn-on voltage is applied thereto. . The trench shape may have a shape in which the third switch semiconductor layer 460, the second switch semiconductor layer 450, and a part of the upper part of the first switch semiconductor layer 440 are removed.

The source electrode 472 and the gate electrode 476 are formed at alternate positions, and may be formed of a conductive material such as a metal or a conductive film.

The illustrated field effect transistor can effectively suppress occurrence of TD (Threading dislocation) due to ELO growth on the source electrode side. As a result, it is possible to implement a vertical type GaN-based electronic device having good withstand voltage characteristics.

In addition, the illustrated field effect transistor has a structure in which a gallium nitride field effect transistor stack is located between a thermally conductive lower substrate 2 and a thermally conductive upper substrate 499, And has an advantage that the heat can be released quickly and effectively.

FIG. 7 shows a nitride-based field-effect transistor of another embodiment capable of more effectively suppressing the channel's TD.

In the illustrated nitride-based field-effect transistor,

A sapphire substrate 1; A high concentration gallium nitride semiconductor layer 620 formed on the sapphire substrate 1; Window insulating layers 621 located on the high-concentration gallium nitride semiconductor layer 620; An initial growth layer 623 formed between the window insulating layers 621 at a height slightly higher than the initial growth layer 623; A first switch semiconductor layer 640 laminated while surrounding the initial growth layer 623; A second switch semiconductor layer 650 disposed on the first switch semiconductor layer 640; A third switch semiconductor layer 660 located on the second switch semiconductor layer 650; A gate insulating layer 674 located on a trench structure in which a portion of the upper portion of the third switch semiconductor layer 660, the second switch semiconductor layer 650, and the first switch semiconductor layer 640 is recessed; A gate electrode 676 located above the gate insulating film 674; And a source electrode 672 located on the third switch semiconductor layer 660 between the gate electrodes 676.

The high-concentration gallium nitride semiconductor layer 620 may be formed of an n + GaN layer and may have a carrier concentration of more than 1 * 10 ¹⁸ / cm ³ .

The window insulating layers 621 may function as a window for ELO growth, so that intrinsic gallium nitride semiconductor is grown on the surface of the high-concentration gallium nitride semiconductor layer 620 between the window insulating layers, An initial growth layer 623 can be formed. In another embodiment, the initial growth layer 623 may be formed of an n-GaN semiconductor layer. The ELO growth continues and the first switch semiconductor layer 640 of the n-GaN layer can be formed. In another implementation, the first switch semiconductor layer 640 may be formed of an iGaN layer.

The first switch semiconductor layer 640, which is an n-GaN layer, the second switch semiconductor layer 650 which is a pGaN layer, and the third switch semiconductor layer 660 which is an n + GaN layer are grown by c- .

The gate electrode 676 is formed in a trench shape having a slope so that a channel corresponding to the npn junction can be formed by the first to third switch semiconductor layers 640, 650, and 660 when a turn-on voltage is applied. . The trench shape may have a shape in which the third switch semiconductor layer 660, the second switch semiconductor layer 650, and a part of the upper part of the first switch semiconductor layer 640 are removed.

The source electrode 672 and the gate electrode 676 are formed at alternate positions and may be formed of a conductive material such as a metal or a conductive film.

The illustrated field effect transistor can effectively suppress generation of TD (Threading dislocation) due to ELO growth on the side of the source electrode by forming an element by ELO growth using a GaN seed on a comparatively inexpensive sapphire substrate or a silicon substrate. As a result, it is possible to implement a vertical type GaN-based electronic device having good pressure resistance characteristics at low cost.

Fig. 8 shows a nitride-based field-effect transistor of another embodiment capable of more effectively suppressing the channel's TD.

7, a first additional TD blocking insulating layer 631 is formed in the upper region first switch semiconductor layer 640 of the initial growth layer 623, And the second portion of the first switch semiconductor layer 640 of the window insulating layer 621 is further provided with a TD blocking insulating layer 632.

The first and second additional TD blocking insulating layers 631 and 632 may be formed of SiO 2 or the like so that TD is prevented from extending from the first switch semiconductor layer 640, The mobility increases, and the turn-on resistance is reduced. On the other hand, it can be seen that the region under the gate slope through which the channel current flows is formed so as not to be blocked by the first / second part TD blocking insulating layers 631 and 632.

In addition, the first / second additional blocking insulating layers 631 and 632 may provide a function of providing a window for ELO growth of the first switch semiconductor layer 640.

Fig. 9 shows a nitride-based field-effect transistor of another embodiment capable of more effectively suppressing the channel's TD.

8, the n + GaN buffer layer 625 is further provided below the first / second additional TD blocking insulating layers 631 and 632, so that the field effect transistor shown in FIG. .

The stability of ELO growth for the first switch semiconductor layer 640 is increased by the buffer layer 625 although the process complexity is increased due to the buffer layer 625. [

FIGS. 10A to 10G show a process of manufacturing the nitride-based field-effect transistor of FIG.

10A, an n + -type gallium nitride semiconductor layer 620 is formed on a sapphire substrate 1 and a window insulating layer 621 is formed on the n + -type gallium nitride semiconductor layer 620 do. For example, the window insulating layer 621 may be formed in a <11-00> or <112-0> direction as a SiO 2 stripe material, and unnecessary portions may be etched to form the illustrated structure.

10B, the ELO growth proceeds from the surface of the n + -type gallium nitride semiconductor layer 620 between the window insulating layers 621 to nGaN to form an initial growth layer 623 ).

Next, as shown in FIG. 10C, ELO growth is continued with n-GaN to form a first switch semiconductor layer 640 of n-GaN material surrounding the initial growth layer 623, A second switch semiconductor layer 650 of a p-GaN material is formed on the GaN first switch semiconductor layer 640 and a third switch semiconductor layer of n + GaN is formed on the second switch semiconductor layer 650 660). The first switch semiconductor layer 640, the second switch semiconductor layer 650, and the third switch semiconductor layer 660 may be formed by c-plane growth in a layer structure. The second switch semiconductor layer 650 made of p-GaN may be formed of GaN doped with Mg or the like.

Next, as shown in FIG. 10D, a process of forming a trench structure for a gate includes the steps of forming the third switch semiconductor layer 660, the second switch semiconductor layer 650, and the first switch semiconductor layer 640 The upper part of the area is etched. As the etching method, ICP (Inductively Coupled Plasma) RIE (Reactive Ion Etching) may be applied, or general dry etching and / or wet etching may be used. Cl2 and / or BCl3 may be used in the etching process.

Next, in order to form the gate insulating film, an insulating film layer is formed in the upper region of the stacked structure of FIG. 10D, and unnecessary regions are removed from the insulating film layer to form a gate insulating film 674 as shown in FIG. 10E. For example, the insulating layer may be formed of SiO2 material.

Next, photolithography is performed to form a gate electrode 676 as shown in FIG. 10F. For example, a metal layer such as Ti / Al / Au or Ni / Au is deposited on the upper portion of the laminated structure including the photoresist for forming the gate electrode 676, the photoresist and the unnecessary metal layer 72-1 are removed, Electrode 676 can be formed.

Next, as shown in Fig. 10G, a source electrode 672 and a drain electrode 611 are formed. For example, the source electrode 672 and the drain electrode 611 may be formed by a metal deposition process such as Ti / Al / Au or Ni / Au and a photolithography process. On the other hand, in another embodiment, the source electrode 672 may be formed together in the step of forming the gate electrode 676.

11A to 11C show a process performed instead of FIGS. 10A to 10C when the sapphire substrate 1 is replaced with a silicon substrate 5. FIG.

As shown in the figure, the high-concentration gallium nitride semiconductor layer 620 of FIGS. 10A to 10C has the same constituents as those of FIGS. 10A to 10C, except that the buffer layer 620-1 is used for bonding the silicon substrate. . The buffer layer 620-1 for the silicon substrate bonding may be formed of AlGaN and / or GaN. It is apparent that the processes of FIGS. 10D to 10G can be performed in the same manner after FIG. 11C.

It should be noted that the above-described embodiments are intended to be illustrative, not limiting. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

1: sapphire substrate
2: thermally conductive lower substrate;
11, 211: drain electrode
22, 222: seed layer
24, 224: intrinsic gallium nitride semiconductor layer
40, 240, 440, 640: a first switch semiconductor layer
50, 250, 450, 650: second switch semiconductor layer
60, 260, 460, 660: a third switch semiconductor layer
72, 272, 472, 672: source electrode
74, 274, 474, 674: gate insulating film
76, 276, 476, 676: gate electrode
99, 299, 499: thermally conductive upper substrate

Claims (16)

Forming a gallium nitride-based laminate constituting a gallium nitride-based device on a sapphire substrate;
Attaching a first thermally conductive substrate to a surface of the gallium nitride-based laminate opposite to a surface on which the sapphire substrate is located;
Removing the sapphire substrate;
Forming an additional laminate on the surface of the gallium nitride based laminate from which the sapphire substrate has been removed; And
Attaching a second thermally conductive substrate to the exposed surface of the additional laminate
Based semiconductor layer.
The method according to claim 1,
Wherein the step of attaching the first thermally-
Forming a protective layer of aluminum nitride or silicon nitride on the gallium nitride-based laminate; And
Attaching a first thermally conductive substrate to the protective layer
Based semiconductor layer.
The method according to claim 1,
Wherein the step of attaching the second thermally-
Forming an intermediate layer of a metal material containing nano silver, AuSn, NiSn, or gold or silver on the gallium nitride based laminate; And
Attaching a second thermally conductive substrate to the protective layer
Based semiconductor layer.
The method according to claim 1,
The step of forming the gallium nitride-
Forming a seed layer of a first conductivity type on the sapphire substrate;
Performing ELO growth on the seed layer to form an intrinsic gallium nitride semiconductor layer;
Forming a first switch semiconductor layer of a first conductivity type surrounding the intrinsic gallium nitride semiconductor layer by continuously performing ELO growth with gallium nitride of a first conductivity type;
Forming a second switch semiconductor layer of a second conductivity type on the first switch semiconductor layer;
Forming a third switch semiconductor layer of a first conductivity type on the second switch semiconductor layer;
Etching a portion of the upper part of the second switch semiconductor layer and the first switch semiconductor layer, and forming a gate insulating film on the etched surface;
Forming a gate electrode on the gate insulating film;
Forming a source electrode on the third switch semiconductor layer between the gate electrodes
Based semiconductor layer.
5. The method of claim 4,
Wherein forming the additional laminate comprises:
Forming a drain electrode on a surface of the gallium nitride-based stacked body from which the sapphire substrate is removed
Based semiconductor layer.
5. The method of claim 4,
Forming a protective layer for protecting the source electrode and the gate electrode
Based on the weight of the gallium nitride-based material.
5. The method of claim 4,
After the step of forming the seed layer, before the step of forming the intrinsic gallium nitride semiconductor layer,
Forming a TD blocking insulating layer on the seed layer
Based on the weight of the gallium nitride-based material.
5. The method of claim 4,
Prior to the step of forming the gate insulating film,
Performing a net-like etching on the third switch semiconductor layer
Based on the weight of the gallium nitride-based material.
The method according to claim 1,
The step of forming the gallium nitride-
Forming a seed layer on the sapphire substrate;
Performing ELO growth on the seed layer to form an intrinsic gallium nitride semiconductor layer;
Forming a first switch semiconductor layer of a first conductivity type surrounding the intrinsic gallium nitride semiconductor layer by continuously performing ELO growth with gallium nitride of a first conductivity type;
Forming a second switch semiconductor layer of a second conductivity type on the first switch semiconductor layer;
Forming a third switch semiconductor layer of a first conductivity type on the second switch semiconductor layer;
Etching a region not overlapping the seed layer as a partial upper region of the second switch semiconductor layer and the first switch semiconductor layer and forming a gate insulating film on the etched surface; And
Forming a gate electrode on the gate insulating film, and forming a source electrode on the third switch semiconductor layer between the gate insulating films
Based semiconductor layer.
10. The method of claim 9,
Wherein forming the additional laminate comprises:
Forming an insulating film on the seed layer and the intrinsic gallium nitride semiconductor layer exposed on the surface from which the sapphire substrate is removed; And
Forming a drain electrode on the insulating film
Based semiconductor layer.
11. The method of claim 10,
Before the step of forming the insulating film on the exposed seed layer and the intrinsic gallium nitride semiconductor layer,
Performing a step of etching the gallium nitride-based laminate from which the sapphire substrate has been removed to remove damage due to the lift-off process;
Based on the weight of the gallium nitride-based material.
The method according to claim 1,
The step of forming the gallium nitride-
Forming a high-concentration gallium nitride semiconductor layer on the sapphire substrate;
Forming at least two window insulating layers spaced apart from each other on the high-concentration gallium nitride semiconductor layer;
Performing ELO growth from the surface of the highly concentrated gallium nitride semiconductor layer exposed between the window insulating layers to form an initial growth layer;
Continuing ELO growth with gallium nitride or intrinsic gallium nitride of the first conductivity type to form a first switch semiconductor layer surrounding the initial growth layer;
Forming a second switch semiconductor layer of a second conductivity type on the first switch semiconductor layer;
Forming a third switch semiconductor layer of a first conductivity type on the second switch semiconductor layer;
Etching a region not overlapping the seed layer as a partial upper region of the second switch semiconductor layer and the first switch semiconductor layer and forming a gate insulating film on the etched surface; And
Forming a gate electrode on the gate insulating film, and forming a source electrode on the third switch semiconductor layer between the gate insulating films
Based semiconductor layer.
13. The method of claim 12,
The step of forming the gallium nitride-
After forming the gate electrode and the source electrode,
Removing a portion of the gallium nitride-based stacked body to the high-concentration gallium nitride semiconductor layer, and forming a drain electrode on the high-concentration gallium nitride semiconductor layer in the removed region
Based on the weight of the gallium nitride-based material.
13. The method of claim 12,
After forming the initial growth layer, before forming the first switch semiconductor layer,
Forming a buffer layer of gallium nitride of the first conductivity type at a high concentration; And
Forming a TD blocking insulating layer on the buffer layer at positions staggered with the window insulating layer
Based on the weight of the gallium nitride-based material.
13. The method of claim 12,
In the step of forming the first switch semiconductor layer,
Wherein the first switch semiconductor layer in which a TD blocking insulating layer is inserted is formed at an intermediate height between the window insulating layer and the window insulating layer.
13. The method of claim 12,
Wherein forming the additional laminate comprises:
Forming a drain electrode on a surface of the gallium nitride-based stacked body from which the sapphire substrate is removed
Based semiconductor layer.

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