KR20150049162A - Multi-layered ceramic electronic component and mounting circuit thereof - Google Patents

Abstract

The present invention provides a multilayer ceramic electronic component. The present invention comprises: a ceramic main body on which a plurality of first dielectric layers are laminated; an active layer including a plurality of first and second inner electrodes which are formed to be alternatively exposed with the first dielectric layer inside through both cross sections of the ceramic body; upper and lower cover layers on which a plurality of second dielectric layers are laminated and which are formed on the upper and lower parts of the active layer respectively; and first and second outside electrodes which are formed on both cross sections of the ceramic main body and electrically connected to first and second inner electrodes respectively. At least one part of the second dielectric layer is formed of a material whose modulus is larger than that of the first dielectric layer.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer ceramic electronic component,

The present invention relates to a multilayer ceramic electronic component and a mounting substrate thereof.

Electronic components using ceramic materials include capacitors, inductors, piezoelectric elements, varistors and thermistors.

A multi-layered ceramic capacitor (MLCC), which is one of the ceramic electronic components, has advantages of small size, high capacity, and easy mounting.

The multilayer ceramic capacitor may be used in various electronic devices such as a video device such as a liquid crystal display (LCD) and a plasma display panel (PDP), a computer, a personal digital assistant (PDA) Is a chip-type capacitor that is mounted on a printed circuit board of a printed circuit board and plays a role of charging or discharging electricity.

The multilayer ceramic capacitor may include a plurality of stacked dielectric layers, inner electrodes of different polarities arranged to face each other between the dielectric layers, and an outer electrode electrically connected to the inner electrodes.

Since the dielectric layer has piezoelectricity and electrostrictive properties, when a direct current or an alternating voltage is applied to the multilayer ceramic capacitor, a piezoelectric phenomenon occurs between the internal electrodes and vibration may occur.

Such vibration is transmitted to the printed circuit board on which the multilayer ceramic capacitor is mounted through the external electrode of the multilayer ceramic capacitor so that the whole printed circuit board becomes an acoustic reflective surface and generates a noisy vibration noise.

The vibration sound may correspond to an audible frequency in a range of 20 to 20,000 Hz which may cause an uncomfortable feeling to a person. An unpleasant vibration sound is called an acoustic noise.

The following Patent Document 1 provides a multilayer ceramic capacitor, but does not disclose that a part of the upper and lower cover layers is formed of a material having a higher modulus than that of the dielectric layer of the active layer.

Japanese Patent Application Laid-Open No. 2009-71106

There is a need in the art for a new method that can effectively reduce the noise generated by the vibration caused by the piezoelectric phenomenon.

According to an aspect of the present invention, there is provided a ceramic body comprising: a ceramic body having a plurality of first dielectric layers stacked; An active layer including a plurality of first and second internal electrodes alternately exposed through both end faces of the ceramic body with the first dielectric layer interposed therebetween; An upper and a lower cover layer formed on upper and lower portions of the active layer, respectively, wherein a plurality of second dielectric layers are stacked; First and second external electrodes formed on both end faces of the ceramic body and electrically connected to the first and second internal electrodes, respectively; And at least a part of the second dielectric layer is made of a material having a higher modulus than that of the first dielectric layer.

In one embodiment of the present invention, when the thickness of the lower cover layer is set to T1 and the distance from the lower end of the active layer to the lower end of the lower cover layer is set to T2, 0.06? T1 / T2? have.

In one embodiment of the present invention, all of the second dielectric layer may be formed of a material having a higher modulus than the first dielectric layer.

In one embodiment of the present invention, the upper and lower cover layers may be formed by alternately stacking the first and second dielectric layers.

In one embodiment of the present invention, a gap layer may be formed in the middle of the active layer.

In an embodiment of the present invention, the gap layer may be formed by stacking a plurality of second dielectric layers.

In one embodiment of the present invention, the first dielectric layer may include a BaTiO ₃ -based or SrTiO ₃ -based powder.

In one embodiment of the invention, the second dielectric layer may include at least one of the _three systems, CaTiO ₃ and SrTiO ₃ system powder CaZrO.

In one embodiment of the present invention, the modulus of the second dielectric layer may be 1.5 to 6 times the modulus of the first dielectric layer.

Another aspect of the present invention is a printed circuit board comprising: a printed circuit board having first and second electrode pads on an upper surface thereof; The multilayer ceramic electronic component according to any one of claims 1 to 8, which is provided on the first and second electrode pads. The present invention also provides a mounting substrate for a multilayer ceramic electronic component.

According to one embodiment of the present invention, by using the material of the second dielectric layer constituting the upper and lower cover layers of the ceramic body, which is higher in modulus than the material of the first dielectric layer constituting the active layer, There is an effect that the acoustic noise generated due to the vibration transmitted to the printed circuit board can be reduced.

1 is a perspective view schematically showing a part of a multilayer ceramic capacitor according to an embodiment of the present invention.
2 is a length-thickness direction cross-sectional view of a multilayer ceramic capacitor according to an embodiment of the present invention.
3 is a length-thickness direction cross-sectional view of a multilayer ceramic capacitor according to another embodiment of the present invention.
4 is a perspective view schematically showing a state in which a part of a multilayer ceramic capacitor according to an embodiment of the present invention is cut and mounted on a printed circuit board.
Fig. 5 is a cross-sectional view of the mounting board of Fig. 4 taken along the length-thickness direction. Fig.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

However, the embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below.

Further, the embodiments of the present invention are provided to more fully explain the present invention to those skilled in the art.

The shape and size of elements in the drawings may be exaggerated for clarity.

In the drawings, like reference numerals are used to designate like elements that are functionally equivalent to the same reference numerals in the drawings.

Hereinafter, a multilayer ceramic electronic device according to an embodiment of the present invention will be described, but a multilayer ceramic capacitor will be described, but the present invention is not limited thereto.

Multilayer Ceramic Capacitors

1 is a perspective view schematically showing a part of a multilayer ceramic capacitor according to an embodiment of the present invention.

1, a multilayer ceramic capacitor 100 according to one embodiment of the present invention includes a ceramic body 110, an active layer including a plurality of first and second internal electrodes 121 and 122, Lower cover layers 112 and 113, and first and second external electrodes 131 and 132, respectively.

The ceramic body 110 is formed by laminating a plurality of first dielectric layers 111 in the thickness direction and then firing the ceramic body 110. The shape and dimensions of the ceramic body 110 and the number of laminated layers of the first dielectric layer 111 The present invention is not limited thereto.

A plurality of first dielectric layers 111 forming the ceramic body 110 are in a sintered state and the boundary between the adjacent first dielectric layers 111 is formed without using a scanning electron microscope (SEM) It can be integrated so as to be difficult to confirm.

The shape of the ceramic body 110 is not particularly limited, and may have a hexahedral shape, for example.

In the present embodiment, in order to simplify the explanation, the thickness direction facing surfaces of the ceramic body 110 are defined as two main surfaces, the longitudinal surfaces facing each other connecting the two main surfaces are intersected perpendicularly The widthwise surfaces facing each other will be defined as both sides.

In addition, when the direction of the ceramic body 110 is defined to clearly explain the present embodiment, L, W and T shown in the figure indicate the longitudinal direction, the width direction and the thickness direction, respectively.

Here, the thickness direction can be used in the same concept as the lamination direction in which the first dielectric layer 111 is laminated.

2 is a length-thickness direction cross-sectional view of a multilayer ceramic capacitor according to an embodiment of the present invention.

Referring to FIG. 2, the ceramic body 110 includes an active layer serving as a portion contributing to capacitance formation of a capacitor, and upper and lower cover layers 112 and 113 formed respectively at upper and lower portions of the active layer as upper and lower margin portions .

The upper and lower cover layers 112 and 113 may have a configuration similar to the active layer except that they do not include internal electrodes and one or more second dielectric layers may be formed on the top surface of the active layer And the first and second internal electrodes 121 and 122 may be formed by stacking the first and second internal electrodes 121 and 122 in the thickness direction.

Here, the second dielectric layer may be formed of a material having a higher modulus than the first dielectric layer 111.

The thickness of the first dielectric layer 111 and the second dielectric layer may be arbitrarily changed according to the capacity design of the multilayer ceramic capacitor 100. The thickness of one layer may preferably be 0.01 to 1.00 m after firing However, the present invention is not limited thereto.

In addition, in order to make it different from the above modulus properties, the first dielectric layer 111 may include a BaTiO ₃ type or SrTiO ₃ system, the second dielectric layer can include CaZrO ₃ based, CaTiO ₃ based or SrTiO ₃ have.

Also, the modulus of the second dielectric layer may be 1.5 to 6 times the modulus of the first dielectric layer (111).

That is, the first dielectric layer 111 has a piezo effect at a temperature lower than the Curie temperature, and a piezo phenomenon occurs according to an electric field to generate acoustic noise. At this time, the first dielectric layer 111 has a higher modulus than the first dielectric layer 111 The upper and lower cover layers 112 and 113 including the two dielectric layers prevent the first dielectric layer 111 from shaking due to the piezo phenomenon.

On the other hand, when the thickness of the lower cover layer 113, which is the mounting surface of the multilayer ceramic capacitor 100, is set to T1 and the lower end of the active layer, that is, from the lowermost first internal electrode 121 to the lower end of the lower cover layer 113 The preferable range of T1 / T2 may be 0.06? T1 / T2? 0.69.

Table 1 below shows whether acoustic noise, flexural cracks, and cracks occur after firing according to the change in T1 / T2.

# T1 / T2 Acoustic noise
(dB) Flexural cracks
(pcs) After firing
Crack occurrence
(pcs) One 0 32 11/20 0/300 2 0.02 31 7/20 0/300 3 0.04 30 3/20 0/300 4 0.06 27 0/20 0/300 5 0.1 23 0/20 0/300 6 0.2 16 0/20 0/300 7 0.5 14 0/20 0/300 8 0.6 11 0/20 0/300 9 0.66 9 0/20 0/300 10 0.69 7 0/20 0/300 11 0.72 - 3/20 38/300 12 0.76 - 6/20 64/300 13 0.8 - 15/20 145/300

Referring to Table 1, it can be seen that the acoustic noise increases as the T1 / T2 decreases. At this time, when the T1 / T2 exceeds 0.06, it can be seen that the acoustic noise exceeds 30 dB and the defective crack is generated.

Conversely, as the T1 / T2 increases, the acoustic noise decreases. However, when T1 / T2 exceeds 0.69, it can be seen that not only deflection cracks but also cracks occur after firing.

Therefore, it is understood that a preferable range in which the acoustic noise of the T1 / T2 is not large and the defective cracks and the cracks after the firing do not occur are 0.06? T1 / T2? 0.69.

The first and second internal electrodes 121 and 122 are electrodes having different polarities and are formed by printing a conductive paste containing a conductive metal to a predetermined thickness on the first dielectric layer 111.

The first and second internal electrodes 121 and 122 are alternately exposed through both end faces of the ceramic body 110 along the stacking direction of the first dielectric layer 111 with the first dielectric layer 111 interposed therebetween And may be electrically insulated from each other by the first dielectric layer 111 disposed in the middle.

 The first and second inner electrodes 121 and 122 may be electrically connected to the first and second outer electrodes 131 and 132 through the alternate exposed portions of the ceramic body 110, .

Therefore, when a voltage is applied to the first and second external electrodes 131 and 132, charges are accumulated between the first and second internal electrodes 121 and 122 opposing each other. At this time, the electrostatic charge of the multilayer ceramic capacitor 100 The capacitance is proportional to the area of the region where the first and second internal electrodes 121 and 122 overlap with each other in the active layer.

The thickness of the first and second internal electrodes 121 and 122 may be determined depending on the application, and may be determined to fall within a range of 0.2 to 1.0 占 퐉 in consideration of the size of the ceramic body 110, But is not limited thereto.

The conductive metal included in the conductive paste forming the first and second internal electrodes 121 and 122 may be any of silver (Ag), palladium (Pd), platinum (Pt), nickel (Ni), and copper One or an alloy thereof, and the present invention is not limited thereto.

The conductive paste may be printed by a screen printing method or a gravure printing method, but the present invention is not limited thereto.

The first and second external electrodes 131 and 132 are formed on both end faces of the ceramic body 110 and electrically connected to the exposed portions of the first and second internal electrodes 121 and 122, respectively.

The first and second external electrodes 131 and 132 may be formed of a conductive paste containing a conductive metal and the conductive metal may be silver (Ag), nickel (Ni), copper (Cu) And the present invention is not limited thereto.

On the other hand, first and second plating layers (not shown) may be formed on the first and second external electrodes 131 and 132, if necessary.

The first and second plating layers are for increasing the bonding strength between the multilayer ceramic capacitor 100 and the printed circuit board when soldered to the multilayer ceramic capacitor 100.

The first and second plating layers may be formed of, for example, a nickel (Ni) plating layer formed on the first and second external electrodes 131 and 132 and a tin (Sn) plating layer formed on the nickel plating layer , But the present invention is not limited thereto.

Meanwhile, referring to FIG. 3, a gap layer 114 may be formed in the middle of the active layer.

This gap layer 114 may be comprised of a ceramic layer having a different material, a different modulus, than the first dielectric layer 111 of the active layer, and may be formed of a second dielectric layer 111 of the same material as the upper and lower cover layers 112, . ≪ / RTI >

The gap layer 114 serves to reduce vibrations due to the piezoelectric phenomenon of the dielectric similarly to the upper and lower cover layers 112 and 113 of the ceramic body 110. Therefore, when the gap layer 114 is additionally formed on the ceramic body 110 together with the upper and lower cover layers 112 and 113, the vibration generated in the multilayer ceramic capacitor 100 is further reduced and transferred to the printed circuit board It is possible to further improve the effect of reducing the acoustic noise.

In the embodiment of the present invention, the upper and lower cover layers 112 and 113 are all formed using a material having a higher modulus than that of the first dielectric layer 111. However, 112 and 113 may be composed of multiple layers of various ceramic materials having the same or different modulus of the modulus as the first dielectric layer 111. [

Further, according to another embodiment of the present invention, the upper and lower cover layers 112 and 113 may be formed by alternately stacking dielectric layers having different moduli.

Here, the structure in which the first and second internal electrodes 121 and 122 and the first and second external electrodes 131 and 132 are formed is the same as the previously described embodiment, so a detailed description thereof will be omitted in order to avoid duplication .

The mounting substrate of the multilayer ceramic capacitor

FIG. 4 is a perspective view schematically showing a state in which a part of a multilayer ceramic capacitor according to an embodiment of the present invention is cut and mounted on a printed circuit board, FIG. 5 is a cross- Fig.

4 and 5, the mounting board 200 of the multilayer ceramic capacitor 100 according to the present embodiment includes a printed circuit board 210 on which the multilayer ceramic capacitor 100 is horizontally mounted, The first and second electrode pads 221 and 222 are spaced apart from each other on the upper surface of the first electrode pad 210.

In this case, the multilayer ceramic capacitor 100 is disposed such that the lower cover layer 113 is disposed on the lower side and the first and second external electrodes 131 and 132 are in contact with the first and second electrode pads 221 and 222, respectively And may be electrically connected to the printed circuit board 210 by the solder 230 in the state of FIG.

Acoustic noise may occur when a voltage is applied while the multilayer ceramic capacitor 100 is mounted on the printed circuit board 210 as described above.

The size of the first and second electrode pads 221 and 222 is equal to the size of the first and second external electrodes 131 and 132 and the first and second electrode pads 221 and 222 of the multilayer ceramic capacitor 100 The amount of the solder 230 to be connected may be an index for determining the amount of the solder 230 to be connected, and the magnitude of the acoustic noise may be adjusted according to the amount of the solder 230.

When a voltage having a different polarity is applied to the first and second external electrodes 131 and 132 formed on both end faces of the multilayer ceramic capacitor 100 in a state that the multilayer ceramic capacitor 100 is mounted on the printed circuit board 210, The ceramic body 110 expands and contracts in the thickness direction due to the inverse piezoelectric effect of the dielectric layer of the ceramic body and the ceramic body 110 having the first and second external electrodes 131 and 132 is formed, Contraction and expansion are caused by the Poisson effect, contrary to the expansion and contraction of the ceramic body 110 in the thickness direction thereof, thereby generating acoustic noise.

At this time, the magnitude of the acoustic noise is proportional to the inverse piezoelectric effect of the material of the dielectric layer constituting the ceramic body 110 and the strain under the stress.

The relationship between stress (Pa) and strain (%) can be expressed by a modulus. That is, stress = modulus x strain amount. That is, when the ceramic body is composed of a material having a high modulus, the amount of deformation under the same stress becomes small.

Therefore, if a material having a higher modulus than that of the active layer is used for the upper and lower cover layers 112 and 113 of the ceramic body 110 as in the present embodiment, the amount of deformation under the same stress is reduced, It is possible to minimize the deformation of the piezoelectric element 110 and to reduce the acoustic noise.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, and that various changes and modifications may be made therein without departing from the scope of the invention. It will be obvious to those of ordinary skill in the art.

100; A multilayer ceramic capacitor 110; Ceramic body
111; A first dielectric layer 112; The upper cover layer
113; A lower cover layer 114; Gap layer
121, 122; First and second inner electrodes 131 and 132, The first and second outer electrodes
200; A mounting substrate 210; Printed circuit board
221, 222; First and second electrode pads 230; Solder

Claims (10)

A ceramic body in which a plurality of first dielectric layers are stacked;
An active layer including a plurality of first and second internal electrodes alternately exposed through both end faces of the ceramic body with the first dielectric layer interposed therebetween;
An upper and a lower cover layer formed on upper and lower portions of the active layer, respectively, wherein a plurality of second dielectric layers are stacked; And
First and second external electrodes formed on both end faces of the ceramic body and electrically connected to the first and second internal electrodes, respectively; / RTI >
And at least a part of the second dielectric layer is formed of a material having a higher modulus than that of the first dielectric layer.
The method according to claim 1,
0.06? T1 / T2? 0.69 when the thickness of the lower cover layer is set to T1 and the distance from the lower end of the active layer to the lower end of the lower cover layer is set to T2.
The method according to claim 1,
Wherein all of the second dielectric layer is formed of a material having a higher modulus than the first dielectric layer.
The method according to claim 1,
Wherein the upper and lower cover layers are formed by alternately stacking the first and second dielectric layers.
The method according to claim 1,
And a gap layer is formed in the middle of the active layer.
6. The method of claim 5,
Wherein the gap layer is formed by stacking a plurality of second dielectric layers.
The method according to claim 1,
Wherein the first dielectric layer comprises a BaTiO ₃ -based or SrTiO ₃ -based powder .
The method according to claim 1,
The second dielectric layer is a multilayer ceramic electronic components characterized in that it comprises at least one of a _third type, CaTiO ₃ and SrTiO ₃ system powder CaZrO.
The method according to claim 1,
Wherein the modulus of the second dielectric layer is 1.5 to 6 times the modulus of the first dielectric layer.
A printed circuit board having first and second electrode pads on the top; And
10. The multilayer ceramic electronic component according to any one of claims 1 to 9, which is provided on the first and second electrode pads. And a mounting board on which the multilayer ceramic electronic component is mounted.

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