KR20150040806A - Memory transistor with multiple charge storing layers - Google Patents

Abstract

Semiconductor devices including non-volatile memories and methods of manufacturing them for improving their performance are provided. Generally, the device includes a memory transistor, which includes a polysilicon channel region for electrically connecting a source region and a drain region formed in the substrate, an oxide-nitride-nitride-oxide (ONNO) stack disposed over the channel region, And a high work function gate electrode formed on the surface of the ONNO stack. In one embodiment, the ONNO stack includes a multilayer charge-trapping region comprising an oxygen-rich first nitride layer and an oxygen-deficient second nitride layer disposed over the first nitride layer. Other embodiments are also disclosed.

Description

[0001] MEMORY TRANSISTOR WITH MULTIPLE CHARGE STORING LAYERS [0002]

[0001] This application is a continuation-in-part of co-pending U.S. Serial No. 13 / 288,919 filed on November 3, 2011, which is a continuation-in-part of U.S. Serial No. 12 / 152,518 filed May 13, 2008 Filed on May 22, 2007, which is hereby incorporated by reference in its entirety for all purposes. This application is incorporated herein by reference in its entirety for all purposes. 119 (e), each of which is hereby incorporated by reference in its entirety.

FIELD OF THE INVENTION [0002] The present invention relates generally to semiconductor devices, and more particularly to integrated circuits including non-volatile semiconductor memories and methods of fabricating them.

[0003] Non-volatile semiconductor memories are devices that can be electrically erased and reprogrammed. One type of non-volatile memory that is widely used for general data storage and delivery between computers and other electronic devices and in them is flash memory, such as split gate flash memory. The split gate flash memory transistor has an architecture similar to a conventional logic transistor, e.g., a metal-oxide-semiconductor field effect transistor (MOSFET), in that it also includes a control gate formed over the channel connecting the source and drain in the substrate . However, the memory transistor further comprises a memory or charge trapping layer between the control gate and the channel and insulated from both by an insulating layer or a dielectric layer. The programming voltage applied to the control gate traps the charge on the charge trapping layer and partially eliminates or screens the electric field from the control gate, thereby changing the threshold voltage (V _T ) of the transistor and programming the memory cell. During a read-out, this shift in V _T is sensed by the presence or absence of a current passing through the channel with the application of a predetermined read voltage. To erase the memory transistor, an erase voltage is applied to the control gate to reverse or reverse the shift at V _T.

[0004] An important measure of the advantage for flash memories is data retention time, which is the time at which a memory transistor can remain programmed or hold charge without power applied. The stored or trapped charge in the charge trapping layer is reduced over time due to current leakage through the insulating layers, thereby limiting the data retention of the memory transistor. The erased threshold voltage (VTE) and the programmed threshold voltage (VTP) is reduced.

초 미만의 EOL(end of life)(106)로 매우 급격하게 쇠퇴한다(collapse). [0005] One problem with conventional memory transistors and methods of forming them is that the charge trapping layer typically has poor or reduced data retention over time, limiting transistor useful life. 1A, if the charge trapping layer is silicon (Si) rich, there is a large initial window or difference between VTP (represented by graph or by line 102) and VTE (represented by line 104) , The window is displayed in the holding mode

Lt; RTI ID = 0.0 > (106). ≪ / RTI >

[0006] Referring to Figure IB, on the other hand, if the charge-trapping layer is a high-quality nitride layer with a low stoichiometric concentration of Si, the rate of decay of the window or Vt slope in retention mode is reduced, The erase window is also reduced. In addition, in the hold mode, the slope of Vt is still noticeably steep and the leakage path is not sufficiently minimized to significantly improve data retention, thereby causing the EOL 106 to improve only moderately.

 [0007] Another problem is that semiconductor memories are increasingly being used by logic circuits, such as MOSFETs, for integrated circuits (ICs) that are fabricated on a common substrate for embedded memory or system-on-chip (SOC) Memory transistors. Many current processes for forming the performance of memory transistors are incompatible with those used to fabricate logic transistors.

Thus, there is a need for memory transistors and methods of forming them that provide improved data retention and increased transistor lifetime. In addition, methods of forming memory devices are required to be compatible with methods of forming logic elements in the same IC formed on a common substrate.

 [0009] The present invention provides solutions to these and other problems and provides additional advantages over conventional memory cells or devices and methods of fabricating them.

In general, the device includes a memory transistor, which includes a polysilicon channel region for electrically connecting a source region and a drain region formed in the substrate, an oxide-nitride-nitride- oxide stack, and a high work function gate electrode formed on the surface of the ONNO stack. In one embodiment, the ONNO stack comprises a multilayer charge-trapping region comprising an oxygen-rich first nitride layer and an oxygen-lean second nitride layer disposed over the first nitride layer . In another embodiment, the multilayer charge-trapping region further comprises an oxide anti-tunneling layer separating the first nitride layer from the second nitride layer.

[0011] These and various other features of the present invention will become apparent upon reading the following detailed description along with the appended claims and the accompanying drawings provided below.
[0012] FIG. 1A is a graph showing data retention for a memory transistor using a charge storage layer formed according to a conventional method and having a large initial difference between a programming voltage and an erase voltage (but the charge is rapidly lost);
[0013] FIG. 1B is a graph showing data retention for a memory transistor using a charge storage layer formed according to a conventional method and having a smaller initial difference between programming and erasing voltages;
[0014] Figures 2A-2D are partial side cross-sectional views of a semiconductor device illustrating a process flow for forming a semiconductor device including a logic transistor and a non-volatile memory transistor, in accordance with an embodiment of the present invention;
[0015] FIG. 3 is a partial side cross-sectional view of a semiconductor device including a non-volatile memory transistor and logic transistor including high work function gate electrodes, in accordance with an embodiment of the present invention;
[0016] Figures 4A and 4B illustrate cross-sectional views of a non-volatile memory device including an ONONO stack;
[0017] FIG. 5 illustrates a flow diagram illustrating a series of operations in a method for fabricating a non-volatile charge trap memory device including an ONONO stack, in accordance with an embodiment of the present invention.
[0018] FIG. 6A illustrates a non-planar multigate device including a multilayer charge-trapping region;
[0019] FIG. 6B illustrates a cross-sectional view of the non-planar multi-gate device of FIG. 6A;
[0020] Figures 7a and 7b illustrate a non-planar multigate device comprising a multilayer charge-trapping region and a horizontal nanowire channel;
[0021] FIG. 7C illustrates a cross-sectional view of a vertical string of the non-planar multi-gate devices of FIG. 7A;
[0022] Figures 8a and 8b illustrate a non-planar multigate device comprising a multilayer charge-trapping region and a vertical nanowire channel;
[0023] Figures 9a-9f illustrate a gate first scheme for fabricating the non-planar multigate device of Figure 8a; And
[0024] Figures 10A-10F illustrate a gate last scheme for fabricating the non-planar multigate device of Figure 8A.

[0025] The present invention generally relates to non-volatile memory transistors comprising a multilayer charge storage layer and a high work function gate electrode for increasing data retention and / or improving programming time and efficiency. Structures and methods are particularly useful in embedded memory or system-on-chip (SOC) applications that include both non-volatile memory transistors and logic transistors comprising high work function gate electrodes formed on a common substrate Do.

[0026] For purposes of explanation, in the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known structures and techniques are not shown in detail, or are shown in block diagram form in order not to obscure the understanding of this description unnecessarily.

[0027] Reference in the description to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention . The appearances of the phrase "in one embodiment" in various parts of the specification are not necessarily all referring to the same embodiment. As used herein, the term " coupled to "may include both indirectly connected through one or more intermediate components and directly connected.

[0028] Briefly, a non-volatile memory transistor according to the present invention includes a high work function gate electrode formed on an oxide-nitride-oxide (ONO) dielectric stack. A high work function gate electrode means that the minimum energy required to remove electrons from the gate electrode is increased.

[0029] In certain preferred embodiments, the high work function gate electrode comprises a doped polycrystalline silicon or polysilicon layer, the fabrication of which includes standard complementary metal-oxide-semiconductor (CMOS) process flows, For example, metal-oxide-semiconductor (MOS) logic transistors, to enable fabrication of semiconductor memories or devices including both memory transistors and logic transistors. More preferably, the same doped polysilicon layer can also be patterned to form a high work function gate electrode for the MOS logic transistor, thereby improving the performance of the logic transistor and increasing the efficiency of the fabrication process. Optionally, the ONO dielectric stack includes a multilayer charge storage or charge trapping layer to further improve the performance of the memory transistor, particularly the data retention.

[0030] A semiconductor device including a non-volatile memory transistor including a high work function gate electrode and methods of forming the same will now be described in detail with reference to FIGS. 2A through 2D, Sectional side views of intermediate structures illustrating a process flow for forming a semiconductor device including both transistors. For the sake of clarity, numerous details of semiconductor fabrication that are not relevant to the present invention and are well known are omitted from the following description.

[0031] Referring to FIG. 2, the fabrication of a semiconductor device begins with the formation of the ONO dielectric stack 202 on the surface 204 of the wafer or substrate 206. In general, the ONO dielectric stack 202 includes a thin lower oxide (not shown) that isolates or electrically insulates the charge trapping or storage layer 210 from the channel region (not shown) of the memory transistor of the substrate 206 Layer or tunneling oxide layer 208, and a top or blocking oxide layer 212. 2a-2d, the charge storage layer 210 includes at least an upper charge trapping oxynitride layer 210A and a substantially free oxynitride free lower trap layer 210B ). ≪ / RTI >

[0032] Generally, the substrate 206 may comprise any known silicon-based semiconductor material including silicon, silicon-germanium, silicon-on-insulator, or silicon-on-sapphire substrates have. Alternatively, the substrate 206 may comprise a silicon layer formed on a non-silicon based semiconductor material, such as gallium-arsenide, germanium, gallium-nitride, or aluminum-phosphide. Preferably, the substrate 206 is a doped or undoped silicon substrate.

The lower oxide layer or tunneling oxide layer 208 of the ONO dielectric stack 202 is generally comprised of a relatively thin silicon dioxide (SiO 2) layer having a thickness of from about 15 Angstroms (A) to about 22 Angstroms, more preferably about 18 Angstroms ₂ ) layer. Tunneling oxide layer 208 may be formed or deposited by any suitable means, including, for example, deposited using chemical vapor deposition (CVD) or thermally grown. In a preferred embodiment, the tunnel dielectric layer is formed or grown using steam annealing. Generally, the process may include a wet-oxidizing method, in which a substrate 206 is placed in a deposition or processing chamber and heated to a temperature of about 700 ° C to about 850 ° C, is exposed to wet vapor for a predetermined period of time selected based on the desired thickness of the finished tunneling oxide layer (208). Exemplary process times are from about 5 to about 20 minutes. Oxidation can be performed at atmospheric pressure or at low pressure.

[0034] In a preferred embodiment, the oxynitride layers 210A, 210B of the multilayer charge storage layer 210 are formed or deposited in separate steps using different processes and process gases or source materials, 70 < / RTI > to about 150 ANGSTROM, and more preferably about 100 ANGSTROM. The oxynitride-free lower trap layer (210B), for example, a silicon source (e.g., silane (SiH _4), chlorosilane (SiH ₃ Cl), dichlorosilane (SiH ₂ Cl _2), tetrachlorosilane (SiCl ₄ )), nitrogen sources (for example, nitrogen (N _2), ammonia (NH _3), nitrogen tree oxide (N0 ₃₎ or nitrous oxide (N ₂ 0)), and an oxygen-containing gas (e.g., oxygen (0 ₂₎ Or N ₂ O), in a low pressure CVD process using a process gas. In one embodiment, the oxynitride-free trap layer 210B is maintained at a pressure of about 5 millitorr (mT) to about 500 mT for a period of about 2.5 minutes to about 20 minutes, Pressure CVD process using a process gas comprising dichlorosilane, NH ₃ and N ₂ O while maintaining the substrate at a temperature of about 850 ° C, more preferably at least about 780 ° C. In particular, the process gas may comprise a first gas mixture of N ₂ O and NH ₃ mixed in a ratio of about 8: 1 to about 1: 8, and a second gas mixture of DCS and NH ₃ mixed at a ratio of about 1: 7 to about 7: Of the second gas mixture and may be introduced at a flow rate of about 5 to about 200 sccm (standard cubic centimeters per minute).

[0035] The upper charge trapping oxynitride layer 210A may be deposited on the bottom oxynitride layer 210B in a CVD process using a process gas comprising BTBAS (Bis-Tertiary Butylene Minosilane). It has been found that the use of BTBAS increases the number of deep traps formed in the oxynitride by increasing the carbon level in the charge trapping oxynitride layer 210A. In addition, these deep traps reduce charge losses due to thermal emission, which further improves data retention. More preferably, a process gas, including a BTBAS and ammonia (NH ₃₎ mixed at a predetermined ratio to provide a narrow band gap energy level of the oxynitride charge-trapping layer. In particular, the process gas is about 7: 1 to about 1: may comprise the BTBAS and NH ₃ mixed at a ratio of 7. For example, in one embodiment, the charge-trapping oxynitride layer 210A may be deposited over a period of about 2.5 minutes to about 20 minutes at a chamber pressure of about 5 mT to about 500 mT and a temperature of about 700 < 0 > C to about 850 & more preferably, it is deposited in a low pressure CVD process using the BTBAS and ammonia (NH ₃₎ at a substrate temperature of about 780 ℃ at least.

, 보다 바람직하게는 약

내지 약

의 전하 트랩 밀도를 갖는다.The oxynitride layer produced or deposited under these conditions yields an oxynitride rich trapping layer 210A that does not compromise the charge loss rate of the memory transistor and causes an initial difference between the program voltage and the erase voltage (Windows) and improves program and erase speeds, thereby prolonging the device's operating life (EOL). Preferably, the charge-trapping oxynitride layer 210A is at least about < RTI ID = 0.0 >

, More preferably about

About

Lt; / RTI >

Alternatively, the charge-trapping oxynitride layer 210A may be deposited on the bottom oxynitride layer 210B in a CVD process using a process gas that includes BTBAS and does not substantially contain ammonia (NH ₃ ). Can be deposited. In this alternative method embodiment, in the top charge trapping step of acid depositing a nitride layer (210A) is followed by nitrous oxide _{(N 2 0), NH 3} , and / or a nitrogen atmosphere containing nitrogen oxide (NO) Followed by a thermal annealing step.

[0038] Preferably, the upper charge trapping oxynitride layer 210A is sequentially deposited on the same CVD tool used to form the oxynitride-free bottom trap layer 210B without substantially breaking the vacuum on the deposition chamber do. More preferably, the charge-trapping oxynitride layer 210A is deposited substantially without changing the temperature at which the substrate 206 is heated during deposition of the oxynitride-free trap layer 210B.

Suitable thicknesses for the oxynitride free lower trap layer 210B have been found to be from about 10 A to about 80 A and the thickness ratio between the bottom layer and the top charge trapping oxynitride layer is from about 1: 6: 1, and more preferably at least about 1: 4.

[0040] The top oxide layer 212 of the ONO dielectric stack 202 includes a relatively thick SiO ₂ layer of about 20 A to about 70 A, more preferably about 45 A. The top oxide layer 212 may be formed or deposited by any suitable means, including, for example, deposited using CVD or thermally grown. In a preferred embodiment, the top oxide layer 212 is a high-temperature-oxide (HTO) deposited using a CVD process. Generally, the deposition process is performed at a pressure of from about 50 mT to about 1000 mT in a deposition chamber, for a period of from about 10 minutes to about 120 minutes, while maintaining the substrate at a temperature of from 650 [deg.] C to about 850 [ 306) to a silicon source (e.g., silane, chlorosilane, or dichlorosilane) and an oxygen-containing gas (e.g., O ₂ or N ₂ O).

[0041] Preferably, the top oxide layer 212 is deposited sequentially in the same tool used to form the oxynitride layers 210A, 210B. More preferably, the oxynitride layers 210A and 210B and the top oxide layer 212 are formed or deposited in the same tool used to grow the tunneling oxide layer 208. [ Suitable tools include, for example, the ONO AVP commercially available from AVIZA technology of Scotts Valley, California.

[0042] Referring to FIG. 2B, in these embodiments, in which the semiconductor device further comprises a logic transistor, for example a MOS logic transistor, formed on the surface of the same substrate, the ONO dielectric stack 202 has a surface Is removed from the region or region of the substrate 204, over which an oxide layer 214 is formed.

[0043] Generally, the ONO dielectric stack 202 is removed from the desired area or area of the surface 204 using standard lithography and oxide etch techniques. For example, in one embodiment, the patterned mask layer (not shown) picture that is deposited on the ONO dielectric stack (202) is formed from a resist, the exposed region C ₂ H ₂ F, referred to as common Freon ^® (RF) coupling or generating plasma comprising fluorinated hydrocarbons and / or fluorinated carbon compounds such as < RTI ID = 0.0 > _4. ≪ / RTI > In general, the process gas further comprises argon (Ar) and nitrogen (N ₂₎ to the selected flow rate to maintain a pressure of about 50 mT to about 250 mT during processing in an etch chamber.

[0044] The oxide layer 214 of the logic transistor may comprise a layer of SiO ₂ having a thickness of about 30 to 70 Å and may be deposited or thermally grown using CVD. In one embodiment, the oxide layer 214 is deposited using a steam oxidation process, for example, for a period of about 10 minutes to about 120 minutes, at a temperature of about 650 [deg.] C to about 850 [ ), So that they are thermally grown.

[0045] Next, a doped polysilicon layer is formed on the surface of the ONO dielectric stack 202, preferably on the oxide layer 214 of the logic transistor. More preferably, the substrate 206 is a silicon substrate or has a silicon surface on which an ONO dielectric stack is formed to form a SONOS gate stack of a silicon-oxide-nitride-oxide-silicon (SONOS) memory transistor.

Referring to FIG. 2C, forming a doped polysilicon layer includes depositing a conformal polysilicon layer 216 having a thickness of about 200 ANGSTROM to about 2000 ANGSTROM over the ONO dielectric stack 202 and oxide layer 214 ). ≪ / RTI > The polysilicon layer 216 may be formed or deposited by any suitable means, including, for example, deposition in a low pressure CVD process using a silicon source or precursor. In one embodiment, the polysilicon layer 216 is formed over a substantially undoped polysilicon layer at a pressure of about 5 to 500 mT for a period of about 20 minutes to about 100 minutes, Pressure CVD process using a silicon-containing process gas such as silane or dichlorosilane and N ₂ , while maintaining the substrate 206 in the chamber. The polysilicon layer 216 is formed directly as a doped polysilicon layer through the addition of gases such as phosphine, arsine, diborane, or difluoroborane (BF ₂ ) to the CVD chamber during the low pressure CVD process Or grown.

[0047] In one embodiment, the polysilicon layer 216 is doped using an ion implantation process after growth or formation in an LPCVD process. For example, the polysilicon layer 216 may be formed to a thickness of about 5 to about 10 nm to form an N-type (NMOS) SONOS memory transistor, and preferably a P-type (PMOS) at approximately 100 keV (kilo-electron volts) energy, the dose amount (dose) of about lel4 cm ^-2 to about lel6 cm ^-2 is doped by implanting boron (B ⁺⁾ or BF ₂ ions. More preferably, the polysilicon layer 216 is doped with a selected concentration or dose such that the minimum energy required to remove electrons from the gate electrode is at least about 4.8 eV (electron volts) to about 5.3 eV.

[0048] Alternatively, the polysilicon layer 216 may be doped by ion implantation after patterning or etching the polysilicon layer and the underlying dielectric layers. It will be appreciated that this embodiment includes additional masking steps to protect the exposed areas of substrate 206 surface 204 and / or dielectric layers from accepting unwanted doping. However, in general, such a masking step is included in existing process flows, regardless of whether implantation occurs before patterning or after patterning.

2D, the polysilicon layer 216 and the underlying dielectric stack 202 and oxide layer 214 are connected to the high work function gate electrodes (not shown) of the memory transistor 220 and the logic transistor 222 218, < / RTI > In one embodiment, the polysilicon layer 216 is formed by depositing a plasma comprising hydrobromic acid (HBr), chlorine (CL ₂ ) and / or oxygen (O ₂ ) at a pressure of about 25 mTorr and a power of about 450 W May be etched or patterned. The oxide layers 208, 212, 214 and the oxynitride layers 210A, 210B can be etched using standard lithography and oxide etch techniques as described. For example, in one embodiment, the patterned polysilicon layer 216 is used as a mask, and the exposed oxide layers 208, 212, 214 and oxynitride layers 210A, 210B are patterned using a low pressure RF plasma Etched or removed. Generally, the plasma comprises fluorinated hydrocarbons and / or fluorinated carbon compounds and further comprises Ar and N ₂ at selected flow rates to maintain a pressure of about 50 mT to about 250 mT in the etch chamber during processing Is formed from the processing gas.

[0050] Finally, the substrate is heated to about 1 second to drive the implanted ions into the polysilicon layer 216 and to heal damage to the crystal structure of the polysilicon layer caused by ion implantation Lt; 0 > C to about 1050 < 0 > C for a period of about 5 minutes to about 5 minutes. Alternatively, advanced annealing techniques such as flash and laser can be utilized with high temperatures such as 1350 占 폚 and low annealing times such as 1 millisecond.

[0051] A partial side cross-sectional view of a semiconductor device 300 including a non-volatile memory transistor 304 and a logic transistor 302 comprising high work function gate electrodes in accordance with an embodiment of the present invention is shown in FIG. 3, a memory transistor 304 is formed on a silicon substrate 306 and includes a high work function gate electrode 308 formed from a doped polysilicon layer overlying the dielectric stack 310. The dielectric stack 310 overlies the channel region 312 separating the heavily doped source and drain (S / D) regions 314 and controls the current through the channel region 312. Preferably, the dielectric stack 310 comprises a tunnel dielectric layer 316, multilayer charge storage layers 318A and 318B, and a top or blocking oxide layer 320. [ More preferably, the multilayer charge storage layers 318A and 318B include at least a top charge trapping oxynitride layer 318A and a substantially oxynitride-free bottom trap layer 318B. 3, the memory transistor 304 further includes one or more sidewall spacers 322 surrounding the gate stack, and the gate stack is coupled to a semiconductor device (not shown) Electrically isolated from other transistors and from contacts (not shown) for the S / D regions 320.

The logic transistor 302 includes a gate electrode 324 overlying an oxide layer 326 formed over a channel region 328 separating heavily doped source and drain regions 330, One or more sidewall spacers 332 surrounding the gate may be included to electrically isolate the gate from contacts (not shown) for the S / D regions. Preferably, as shown in FIG. 3, the gate electrode 324 of the logic transistor 302 also includes a high work function gate electrode formed from a doped polysilicon layer.

In general, the semiconductor device 300 includes a plurality of isolation structures 334, for example, a local oxidation of silicon (LOCOS) region or a plurality of isolation regions 334, for electrically isolating individual transistors formed on the substrate 306 from one another. Structure, a field oxide region or structure (FOX), or a shallow trench isolation (STI) structure.

Implementations and alternatives

[0054] In one aspect, the present disclosure is directed to semiconductor devices comprising memory transistors having a high work function gate electrode and a multilayer charge-trapping region. FIG. 4A is a block diagram illustrating a side cross-sectional view of an embodiment of this single memory transistor 400. FIG. The memory transistor 400 includes an ONNO stack 402 that includes an ONNO structure 404 formed on a surface 406 The substrate 408 includes one or more diffusion regions 410, e.g., source and drain regions, aligned with the gate stack 402 and separated by a channel region 412. Generally, the ONNO stack 402 includes a high work function gate electrode 414 formed on and in contact with the ONNO structure 404. The high work function gate electrode 414 is separated from or electrically isolated from the substrate 408 by the ONNO structure 404. The ONNO structure 404 includes a thin underlying oxide or tunnel dielectric layer 416 that separates or electrically isolates the ONNO stack 402 from the channel region 412, a top or blocking dielectric layer 420, And a trapping area 422.

[0055] The nanowire channel region 412 may comprise polysilicon or recrystallized polysilicon to form a monocrystalline channel region. Alternatively, when the channel region 412 comprises crystalline silicon, the channel region may be formed to have a <100> surface crystalline orientation with respect to the long axis of the channel region.

[0056] The high work function gate electrode 414 comprises a doped polysilicon layer formed or deposited to a thickness of about 200 Å to about 2000 Å in a low pressure CVD process. As noted above, the polysilicon layer of the high work function gate electrode 414 can be used as an additional layer of gas such as phosphine, arsine, diborane, or difluoroborane (BF ₂ ) to the CVD chamber during the low pressure CVD process. Or may be doped using an ion implantation process after growth or formation in a CVD process. In any embodiment, the polysilicon layer of the high work function gate electrode 414 is formed to have a concentration and dose selected so that the minimum energy required to remove electrons from the gate electrode is at least about 4.8 eV (electron volts) to about 5.3 eV Doped. In an exemplary embodiment, the polysilicon layer of the high work function gate electrode 414 may be formed at an energy of about 5 to about 100 keV (kilo-electron volts) to form an N- type (NMOS) It is doped by implanting boron (B ⁺⁾ or BF ₂ ions in a dose amount of lel4 cm ^-2 to about lel6 cm ^-2.

The tunnel dielectric layer 416 is formed by tunneling the charge carriers into the multilayer charge-trapping region 422 under the applied gate bias while maintaining a proper barrier to leakage when the memory transistor 400 is not biased And may be any material having any thickness suitable for allowing it to be. In one embodiment, the tunnel dielectric layer 416 is formed by a thermal oxidation process and consists of silicon dioxide or silicon oxynitride, or combinations thereof. In another embodiment, the tunnel dielectric layer 416 is formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD), including but not limited to silicon nitride, hafnium oxide, zirconium oxide, hafnium silicate, Nitride, hafnium zirconium oxide, and lanthanum oxide. In certain embodiments, the tunnel dielectric layer 416 has a thickness in the range of 1-10 nanometers. In certain embodiments, the tunnel dielectric layer 416 has a thickness of approximately 2 nanometers.

[0058] In one embodiment, the blocking dielectric layer 420 comprises high temperature oxide (HTO). Higher quality HTO oxides enable the blocking dielectric layer 420 to be scaled in thickness. In an exemplary embodiment, the thickness of the blocking dielectric layer 420 comprising HTO oxide is between 2.5 nm and 10.0 nm.

[0059] In another embodiment, the blocking dielectric layer 420 is further modified to incorporate nitrogen. In one such embodiment, nitrogen is incorporated in the form of an ONO stack over the thickness of the blocking dielectric layer 420. [ This sandwich structure instead of a conventional pure oxygen-blocking dielectric layer preferably also allows tuning of band offsets to reduce back injection of carriers, as well as channel region 412 and high work function gate &lt; RTI ID = 0.0 &gt; Thereby reducing the EOT for the entire stack 402 between the electrodes 414. The ONO stack cutoff dielectric layer 420 then includes a tunnel dielectric layer 416 and an oxygen-rich first oxide layer 422a, an oxygen-deficient second oxide layer 422b, and an anti-tunneling layer 422c May be integrated with the multilayer charge trapping layer 422.

[0060] The multilayer charge-trapping region 422 generally comprises an oxide-rich first oxide layer 422a, and a silicon-rich, nitrogen-rich and oxygen-deficient second nitride layer 422b, , At least two nitride layers having different compositions of oxygen and nitrogen. In some embodiments, as shown in FIG. 4B, the multilayer charge-trapping region may be formed by depositing oxygen from the oxygen-rich first oxide layer 422a to provide an ONONO stack 402 that includes the ONONO structure 404, - an anti-tunneling layer 422c comprising an oxide, such as silicon dioxide, that separates the insufficient second nitride layer 422b.

The oxygen-rich first oxide layer 422a reduces the charge-loss rates that appear with small voltage shifts in the hold mode after programming and after erase, while the silicon-rich, nitrogen-rich and oxygen-deficient second nitride layers 422b can increase the initial difference between program and erase voltages and improve speed without compromising the charge loss rate of memory transistors made using embodiments of silicon-oxide-oxynitride-oxide-silicon structures, . &Lt; / RTI &gt;

[0062] The anti-tunneling layer 422c substantially reduces the probability of electron charge accumulating at the boundaries of the oxygen-deficient second nitride layer 422b due to tunneling to the first nitride layer 422a during programming , Yielding a lower leakage current than for a conventional non-volatile memory transistor.

The multilayer charge-trapping region may have a total thickness of from about 50 A to about 150 A, in certain embodiments less than about 100 A, and the thickness of the anti-tunneling layer 422c may be from about 5 A to about 20 &lt; / RTI &gt; and the thicknesses of the nitride layers 404b and 404a are substantially equal.

[0064] A method of forming or fabricating a semiconductor device including a memory transistor having a high work function gate electrode and a multilayer charge-trapping region according to one embodiment will now be described with reference to the flow diagram of FIG.

[0065] Referring to FIG. 5, the method begins with forming (500) a tunnel dielectric layer, such as a first oxide layer, over the silicon-containing layer on the surface of the substrate. The tunnel dielectric layer can be formed or deposited by any suitable means including a plasma oxidation process, an In-Situ Steam Generation (ISSG) process or a radical oxidation process. In one embodiment, the radical oxidation process is performed by flowing hydrogen (H ₂ ) and oxygen (O ₂ ) gas into a processing chamber or furnace to produce growth of the tunnel dielectric layer by oxidation consumption on a portion of the substrate &Lt; / RTI &gt;

[0066] Next, an oxygen-rich first nitride layer of the multilayer charge trapping region is formed 502 on the surface of the tunnel dielectric layer. In one embodiment, the oxygen-rich first nitride layer has a silicon source (e.g., silane (SiH _4), chlorosilane (SiH ₃ Cl), dichlorosilane or DCS (SiH ₂ Cl _2), tetrachlorosilane (SiCl ₄₎ or BTBAS (Bis-TertiaryButylAmino Silane)), nitrogen sources (for example, nitrogen (N _2), ammonia (NH _3), nitrogen tree oxide (N0 ₃₎ or nitrous oxide (N ₂ 0)) and an oxygen-containing gas (e. g. , Oxygen (O ₂ ), or N ₂ O). Alternatively, gases in which hydrogen is replaced by deuterium (e.g., deuterium deuterated for NH ₃ - including replacement of ammonia (ND ₃ )) can be used. Substitution of deuterium to hydrogen preferably passivates the Si dangling bonds at the silicon-oxide interface, thereby increasing the NBTI (Negative Bias Temperature Instability) lifetime of the devices.

[0067] For example, the lower or oxygen-rich first nitride layer may be formed by maintaining the chamber at a pressure of about 5 milliTorr (mT) to about 500 mT for a period of about 2.5 minutes to about 20 minutes, to about 850 degrees Celsius, by the specific embodiments disposing a substrate in a deposition chamber, while maintaining the substrate at a temperature of at least about 760 degrees Celsius and introduced into the process gas containing N ₂ 0, NH ₃ and DCS tunnel dielectric layer &Lt; / RTI &gt; In particular, the process gas may comprise a first gas mixture of N ₂ O and NH ₃ mixed at a ratio of about 8: 1 to about 1: 8, and a second gas mixture of DCS and NH ₃ mixed at a ratio of about 1: 7 to about 7: A second gas mixture, and may be introduced at a flow rate of from about 5 to about 200 sccm (standard cubic centimeters per minute). It has been found that the oxynitride layer produced or deposited under these conditions yields a silicon-rich, oxygen-rich first nitride layer.

Next, an anti-tunneling layer is formed or deposited 504 on the surface of the first nitride layer. Like the tunnel dielectric layer, the anti-tunneling layer may be formed by a plasma oxidation process, an In-Situ Steam Generation (ISSG) And may be formed or deposited by any suitable means including a radical oxidation process. In one embodiment, the radical oxidation process is performed by flowing hydrogen (H ₂ ) and oxygen (O ₂ ) gases into a batch-processing chamber or furnace, by oxidative depletion of a portion of the first nitride layer Resulting in the growth of the anti-tunneling dielectric layer.

[0069] The top of the multilayer charge-trapping region or the oxygen-deficient second nitride layer is then formed 506 on the surface of the anti-tunneling layer. The oxygen-deficient second nitride layer may be deposited over a period of from about 2.5 minutes to about 20 minutes at a chamber pressure of from about 5 mT to about 500 mT and at a substrate temperature of from about 700 degrees Celsius to about 850 degrees Celsius, Can be deposited on the anti-tunneling layer in a CVD process using a process gas comprising N ₂ O, NH _3, and DCS at substrate temperatures of at least about 760 degrees Celsius. In particular, the process gas comprises a first gas mixture of N ₂ O and NH ₃ mixed at a ratio of about 8: 1 to about 1: 8, and a second gas mixture of DCS and NH ₃ mixed at a ratio of about 1: 7 to about 7: 2 gas mixture, and may be injected at a flow rate of from about 5 to about 20 sccm. The nitride layer produced or deposited under these conditions yields a silicon-rich, nitrogen-rich and oxygen-deficient second nitride layer, which is a memory transistor made using an embodiment of a silicon-oxide-oxynitride-oxide- To increase the initial difference between the program and erase voltages and to improve the speed without compromising the charge-loss rate of the devices, thereby extending the operating life of the device.

[0070] In some embodiments, the oxygen-deficient second nitride layer is mixed at a ratio of from about 7: 1 to about 1: 7 such that the concentration further includes carbon selected to increase the number of traps therein It may be deposited over the tunneling layer in an anti-CVD process using a process gas containing BTBAS and ammonia (NH _3). The selected carbon concentration in the second oxynitride layer may comprise a carbon concentration of about 5% to about 15%.

Next, an upper, blocking oxide layer, or blocking dielectric layer is formed (508) on the surface of the oxygen-deficient second nitride layer in the multilayer charge-trapping region. Like the tunnel dielectric layer and the anti-tunneling layer, the barrier dielectric layer may be formed or deposited by any suitable means including a plasma oxidation process, an In-Situ Steam Generation (ISSG) process or a radical oxidation process. In one embodiment, the barrier dielectric layer comprises a high-temperature-oxide (HTO) deposited using a CVD process. Generally, the deposition process is performed in a deposition chamber at a pressure of from about 50 mT to about 1000 mT for a period of from about 10 minutes to about 120 minutes while maintaining the substrate at a temperature of from about 650 [deg.] C to about 850 [ 306) to a silicon source (e.g., silane, chlorosilane, or dichlorosilane), and an oxygen-containing gas (e.g., O ₂ or N ₂ O).

[0072] Alternatively, a blocking dielectric layer is formed using an ISSG oxidation process. In one embodiment, the ISSG is operated at a pressure of about 8 to 12 Torr in a RTP chamber, such as the ISSG chamber from the Applied Materials previously described, along with oxygen-rich gas mixture hydrogen with about 0.5% to 33% 1050 &lt; 0 &gt; C.

[0073] In any embodiment, it is recognized that the thickness of the second nitride layer can be increased or adjusted because a portion of the oxygen-deficient second nitride layer will be efficiently consumed or oxidized during the process of forming the barrier dielectric layer Will be.

[0074] Finally, a high work function gate electrode is formed 510 in contact with the blocking dielectric layer. The high work function gate electrode comprises a doped polysilicon layer formed or deposited in a low pressure CVD process and having a thickness of from about 200 A to about 2000 A. As discussed above, the polysilicon layer of the high work function gate electrode is doped into the CVD chamber during the low pressure CVD process through the addition of gases such as phosphine, arsine, diborane, or difluoroborane (BF ₂ ) May be formed or grown directly as a polysilicon layer, or may be doped using an ion implantation process after growth or formation in a CVD process. In either embodiment, the polysilicon layer of the high work function gate electrode is doped with a concentration or dose selected such that the minimum energy required to remove electrons from the gate electrode is at least about 4.8 eV (electron volts) to about 5.3 eV. In an exemplary embodiment, for a high work function of the polysilicon layer, gate electrode, forming an N- type (NMOS) memory transistors, in the range of about 5 to about 100 keV (kilo-electron volts) energy, about lel4 cm ^- a dose amount of ² to about lel6 cm ^-2 is doped by implanting boron (B ⁺⁾ or BF ₂ ions.

[0075] Upon completion of the gate stack fabrication, additional processing may occur as is known in the art to complete the fabrication of SONOS-type memory devices.

[0076] In another aspect, the disclosure is also directed to a multi-gate or multi-gate structure including charge-trapping regions located on two or more sides of a channel region formed on, Gate-surface memory transistors and methods of fabricating them. Multi-gate devices include both planar devices and non-planar devices. A planar multi-gate device (not shown) typically includes a double-gate planar device wherein a plurality of first layers are deposited to form a first gate below the channel region to be formed later and a plurality of second layers thereon To form a second gate. Non-planar multi-gate devices generally include a horizontal or vertical channel region formed on or on the surface of a substrate and surrounded by three or more faces by a gate.

[0077] Figure 6a illustrates one embodiment of a non-planar multi-gate memory transistor including a high work function gate electrode. 6A, a memory transistor 600, often referred to as a finFET, is placed over a surface 604 on a substrate 606 that connects a source region 608 and a drain region 610 of a memory transistor. And a channel region 602 formed from a layer or thin film of semiconductor material. The channel region 602 is enclosed on three sides by a fin forming the gate 612 of the device. The thickness of the gate 612 (measured in the direction from the source region to the drain region) determines the effective channel region length of the device. As in the embodiments described above, the channel region 602 may comprise polysilicon or recrystallized polysilicon to form a monocrystalline channel region. Alternatively, when the channel region 602 comprises crystalline silicon, the channel region may be formed to have a <100> surface crystalline orientation with respect to the long axis of the channel region.

[0078] In accordance with the present disclosure, the non-planar multi-gate memory transistor 600 of FIG. 6A may include a high work function gate electrode and a multilayer charge-trapping region. 6B illustrates a non-planar structure of FIG. 6A including a portion of a substrate 606, a channel region 602 and a gate 612 illustrating a high work function gate electrode 614 and a multilayer charge-trapping region 616. FIG. Sectional view of a portion of a memory transistor. The gate 612 further includes a tunnel dielectric layer 618 that is elevated above the raised channel region 602 and a blocking dielectric layer 620 that overlies the blocking dielectric layer to form the control gate of the memory transistor 600 do. The channel region 602 and the gate 612 can be formed directly on the substrate 606 or on the insulating or dielectric layer 622, e.g., on the substrate or on the buried oxide layer formed on the substrate.

[0079] As with the embodiments discussed above, the high work function gate electrode 614 comprises a doped polysilicon layer formed or deposited in a low pressure CVD process and having a thickness of about 200 A to about 2000 A. The polysilicon layer of the high work function gate electrode 614 can be formed or grown directly as a doped polysilicon layer through the addition of gases such as phosphine, arsine, diborane, or BF ₂ , To a concentration or dose selected to be at least about 4.8 eV to about 5.3 eV. In an exemplary embodiment, the polysilicon layer of the high work function gate electrode 614 is doped at a concentration of about lel 4 cm ^-2 to about lel 6 cm ^-2 .

6B, the multilayer charge-trapping region 616 includes at least one lower or bottom oxygen-rich first nitride layer 616a including nitride closer to the tunnel dielectric layer 618. [0080] ) And an upper or upper oxygen-deficient second nitride layer 616b overlying the oxygen-rich first nitride layer. Typically, the oxygen-deficient second nitride layer 616b includes a plurality of charge traps that include a silicon-rich oxygen-deficient nitride layer and are distributed in the multilayer charge-trapping region, while the oxygen- (616a) comprises an oxygen-rich nitride or silicon oxynitride and is oxygen-rich relative to the oxygen-deficient second nitride layer, thereby reducing the number of charge traps therein. Oxygen-rich means that the concentration of oxygen in the oxygen-rich first nitride layer 616a is about 15 to about 40%, while the concentration of oxygen in the oxygen-deficient second nitride layer 616b is less than about 5% .

[0081] In one embodiment, the blocking dielectric 620 also includes an oxide, such as HTO, to provide the ONNO structure. The channel region 602 and the overlying ONNO structure can be directly formed on the silicon substrate 606 and the high work function gate electrode 614 can be overlaid to provide a SONNOS structure.

[0082] In some embodiments, as shown in FIG. 6B, the multilayer charge-trapping region 616 is formed by isolating the oxygen-deficient second nitride layer 616b from the oxygen-rich first nitride layer 616a Intermediate, or anti-tunneling layer 616c, including a dielectric, such as an oxide, such as an oxide. As noted above, the anti-tunneling layer 616c substantially reduces the probability of electron charge accumulating at the boundary of the oxygen-deficient second nitride layer 616b due to tunneling to the first nitride layer 616a during programming .

[0083] As with the embodiments discussed above, either or both of the oxygen-rich first nitride layer 616a and the oxygen-deficient second nitride layer 616b can comprise silicon nitride or silicon oxynitride For example, N ₂ O / NH _{3 at} flow rates and rates tailored to provide a silicon-rich and oxygen-rich oxynitride layer, And a DCS / NH ₃ gas mixture. A second nitride layer of the multilayer charge storage structure is then formed on the intermediate oxide layer. The oxygen-deficient second nitride layer 616b has a stoichiometric composition of oxygen, nitrogen and / or silicon that is different from that of the oxygen-rich first nitride layer 616a and also includes a silicon-rich, oxygen-deficient top nitride layer Can be formed or deposited by a CVD process using a process gas comprising DCS / NH ₃ and N ₂ O / NH ₃ gas mixtures at rates and rates set to provide.

[0084] In those embodiments that include an intermediate or anti-tunneling layer 616c comprising an oxide, the anti-tunneling layer may be formed by oxidation of the bottom oxide layer to a selected depth using radical oxidation . Radical oxidation can be performed, for example, at temperatures of 1000-1100 degrees Celsius using a single wafer tool, or at 800-900 degrees Celsius using a batch reactor tool. At a pressure of 300-500 Torr for a batch process, at 10-15 Torr using a single steam tool, for 1-2 minutes using a single wafer tool, or for 30 minutes to 1 hour using a batch process H ₂ And a mixture of O ₂ gases may be used.

[0085] Finally, in these embodiments, which include a blocking dielectric 620 comprising an oxide, the oxide may be formed or deposited by any suitable means. In one embodiment, the oxide of the blocking dielectric 620 is a high temperature oxide deposited in an HTO CVD process. Alternatively, the blocking dielectric 620 or blocking oxide layer may be thermally grown, but in this embodiment, the top nitride thickness is such that a portion of the top nitride is effectively consumed during the process of thermally growing the blocking oxide layer It can be increased or adjusted because it will be oxidized. The third option is to oxidize the second nitride layer to a selected depth using radical oxidation.

[0086] A suitable thickness for the oxygen-rich first nitride layer 616a may be from about 30 A to about 160 A (some variations are permissible, for example, +/- 10 A), of which about 5-20 A May be consumed by radical oxidation to form anti-tunneling layer 616c. An appropriate thickness for the oxygen-deficient second nitride layer 616b may be at least 30 angstroms. In certain embodiments, the oxygen-deficient second nitride layer 616b may be formed to a thickness of 130 ANGSTROM, of which 30-70 ANGSTROM may be consumed by the lacquer oxidation to form the blocking dielectric 620 have. Although other ratios are also possible, in some embodiments the thickness ratio between the oxygen-rich first nitride layer 616a and the oxygen-deficient second nitride layer 616b is approximately 1: 1.

[0087] In other embodiments, either or both of the oxygen-deficient second nitride layer 616b and the blocking dielectric 620 may comprise a high-K dielectric. Suitable high-K dielectrics are, including the hafnium-based material (e.g., HfSiON, HfSiO or HfO), zirconium-based material (e.g., ZrSiON, ZrSiO or ZrO) and yttrium-based material (for example, Y ₂ O _3).

[0088] In another embodiment shown in Figures 7a and 7b, a memory transistor may comprise a nanowire channel region formed from a thin film of semiconductor material overlying a surface on a substrate, connecting a source region and a drain region of the memory transistor have. The nanowire channel region means a conductive channel region formed in a thin strip of crystalline silicon material having a maximum cross-sectional dimension of less than about 10 nanometers (nanometers), more preferably less than about 6 nm.

7A, a memory transistor 700 is formed from a layer or thin film of semiconductor material on or over a surface on a substrate 706 and includes a source region 708 and a drain region 710 of a memory transistor, And a horizontal nanowire channel region 702 connecting the nanowires. In the illustrated embodiment, the device has a gate-all-around (GAA) structure in which the nanowire channel region 702 is enclosed on all sides by the gate 712 of the device. The thickness of the gate 712 (measured in the direction from the source region to the drain region) determines the effective channel region length of the device. As in the embodiments described above, the nanowire channel region 702 may comprise polysilicon or recrystallized polysilicon to form a monocrystalline channel region. Alternatively, when the channel region 702 comprises crystalline silicon, the channel region may be formed to have a <100> surface crystalline orientation with respect to the long axis of the channel region.

[0090] In accordance with the present disclosure, the non-planar multi-gate memory transistor 700 of FIG. 7A may comprise a high work function gate electrode and a multilayer charge-trapping region. 7B shows a portion of a substrate 706 including a gate 712 illustrating a nanowire channel region 702 and a high work function gate electrode 714 and multilayer charge-trapping regions 716a-716c. 7A is a cross-sectional view of a portion of a non-planar memory transistor. 7B, the gate 712 further includes a tunnel dielectric layer 718 and a blocking dielectric layer 720 overlying the nanowire channel region 702.

[0091] As with the embodiments described above, the high work function gate electrode 714 comprises a doped polysilicon layer formed or deposited in a low pressure CVD process and having a thickness of from about 200 A to about 2000 A. The polysilicon layer of the high work function gate electrode 714 can be formed or grown directly as a doped polysilicon layer through the addition of gases such as phosphine, arsine, diborane, or BF ₂ , To a concentration or dose selected to be at least about 4.8 eV to about 5.3 eV. In an exemplary embodiment, the polysilicon layer of the high work function gate electrode 714 is doped to a concentration of about lel 4 cm ^-2 to about lel 6 cm ^-2 .

[0092] The multilayer charge-trapping regions 716a-716c include at least one inner oxygen-rich first nitride layer 716a that includes a nitride very near the tunnel dielectric layer 718, and an oxygen- And an external oxygen-deficient second nitride layer 716b overlying the layer. Generally, the outer oxygen-deficient second nitride layer 716b includes a plurality of charge traps that include a silicon-rich, oxygen-deficient nitride layer and are distributed in the multilayer charge-trapping region, while the oxygen- 1 nitride layer 716a comprises an oxygen-rich nitride or silicon oxynitride and is oxygen-rich relative to the outer oxygen-deficient second nitride layer, thereby reducing the number of charge traps therein.

[0093] In some embodiments, as shown, the multilayer charge-trapping region 716 includes an oxide that separates the outer oxygen-deficient second nitride layer 716b from the oxygen-rich first nitride layer 716a, At least one thin, intermediate or anti-tunneling layer 716c, including the same dielectric. The anti-tunneling layer 716c substantially reduces the probability of electron charge accumulating at the boundaries of the external oxygen-deficient second nitride layer 716b due to tunneling to the oxygen-rich first nitride layer 716a during programming To produce a lower leakage current.

[0094] As described above, either or both of the oxygen-rich first nitride layer 716a and the external oxygen-deficient second nitride layer 716b may comprise silicon nitride or silicon oxynitride For example, N ₂ O / NH _{3 at} rates and at flow rates adapted to provide a silicon-rich and oxygen-rich oxynitride layer And a DCS / NH ₃ gas mixture. A second nitride layer of the multilayer charge storage structure is then formed on the intermediate oxide layer. The outer oxygen-deficient second nitride layer 716b has a stoichiometric composition of oxygen, nitrogen, and / or silicon that is different from that of the oxygen-rich first nitride layer 716a and also has a silicon-rich, oxygen- a may be formed or deposited by a CVD process using a process gas including a tuned ratio and a flow rate of DCS / NH ₃ and N ₂ O / NH ₃ gas mixture to provide.

In those embodiments that include an intermediate or anti-tunneling layer 716c comprising an oxide, the anti-tunneling layer may be formed by depositing an oxygen-rich first nitride layer 716a ). &Lt; / RTI &gt; The radical oxidation can be performed, for example, at a temperature of 1000-1100 degrees Celsius using a single wafer tool, or at a temperature of 800-900 degrees Celsius using a batch reactor tool. At a pressure of 300-500 Torr for a batch process, at 10-15 Torr using a single steam tool, for 1-2 minutes using a single wafer tool, or for 30 minutes to 1 hour using a batch process H ₂ And a mixture of O ₂ gases may be used.

[0096] Finally, in these embodiments where the blocking dielectric 720 comprises an oxide, the oxide may be formed or deposited by any suitable means. In one embodiment, the oxide of the blocking dielectric layer 720 is a high temperature oxide deposited in an HTO CVD process. Alternatively, the blocking dielectric layer 720 or the blocking oxide layer may be thermally grown, but in this embodiment, the thickness of the outer oxygen-deficient second nitride layer 716b is such that a portion of the top nitride, Will be consumed or oxidized efficiently during the thermal growth process.

[0097] A suitable thickness for the oxygen-rich first nitride layer 716a may be from about 30 A to about 80 A (some variations are allowed, for example, +/- 10 A), with about 5-20 A being anti- May be consumed by radical oxidation to form the tunneling layer 716c. An appropriate thickness for the outer oxygen-deficient second nitride layer 716b may be at least 30 angstroms. In certain embodiments, the external oxygen-deficient second nitride layer 716b may be formed to a thickness of 70 ANGSTROM, of which 30-70 ANGSTROM may be consumed by the lacquer oxidation to form the barrier dielectric layer 720 . Although other ratios are also possible, in some embodiments the thickness ratio between the oxygen-rich first nitride layer 716a and the outer oxygen-deficient second nitride layer 716b is approximately 1: 1.

[0098] In other embodiments, either or both of the outer oxygen-deficient second nitride layer 716b and the blocking dielectric layer 720 may comprise a high-K dielectric. Suitable high-K dielectrics are, including the hafnium-based material (e.g., HfSiON, HfSiO or HfO), zirconium-based material (e.g., ZrSiON, ZrSiO or ZrO) and yttrium-based material (for example, Y ₂ O _3).

[0099] FIG. 7C illustrates a cross-sectional view of a vertical string of non-planar multigate devices 700 of FIG. 7A, arranged in BiCS (Bit Cost Scalable) or BiCS architecture 726. Architecture 726 is comprised of a vertical string or stack of non-planar multi-gate devices 700, wherein each device or cell rests on a substrate 706 and has a source region and a drain region of the memory transistor And a channel region 702 having a gate-all-around (GAA) structure connecting the nanowire channel region 702 to all sides by a gate 712. The BiCS architecture reduces the number of critical lithography steps compared to simple stacking of layers, resulting in reduced cost per memory bit.

[00100] In another embodiment, the memory transistor is a non-planar device comprising a vertical nanowire channel region formed in or formed from a semiconductor material that protrudes above or from a plurality of conductive, semiconductive layers on a substrate Or the like. In one version of this embodiment shown partially cutaway in FIG. 8A, the memory transistor 800 includes a source region 804 of the device and a drain region 806, And a vertical nanowire channel region 802 formed. Channel region 802 is surrounded by a tunnel dielectric layer 808, a multilayer charge-trapping region 810, a blocking dielectric layer 812 and a high work function gate electrode 814 overlying the blocking dielectric layer, 800 are formed. The channel region 802 may comprise an annular region in the outer layer of a substantially solid cylinder of semiconductor material or may comprise an annular layer formed over the cylinder of dielectric filler material. As with the horizontal nanowires described above, the channel region 802 may comprise polysilicon or recrystallized polysilicon to form a monocrystalline channel region. Alternatively, when the channel region 802 comprises crystalline silicon, the channel region may be formed to have a <100> surface crystalline orientation with respect to the major axis of the channel region.

[00101] As with the embodiments described above, the high work function gate electrode 814 comprises a doped polysilicon layer formed or deposited in a low pressure CVD process and having a thickness of about 200 Å to 2000 Å. The polysilicon layer of the high work function gate electrode 814 can be formed or grown directly as a doped polysilicon layer through the addition of gases such as phosphine, arsine, diborane, or BF ₂ , To a concentration or dose selected to be at least about 4.8 eV to about 5.3 eV. In an exemplary embodiment, the polysilicon layer of the high work function gate electrode 814 is doped to a concentration of about lel 4 cm ^-2 to about lel 6 cm ^-2 .

8B, the multilayer charge-trapping region 810 includes at least an inner or oxygen-rich first nitride layer 810a closest to the tunnel dielectric layer 808, And an outer or oxygen-deficient second nitride layer 810b. Alternatively, as shown in the illustrated embodiment, the oxygen-rich first nitride layer 810a and the oxygen-deficient second nitride layer 810b are separated by an intermediate oxide or anti-tunneling layer 810c comprising an oxide.

[00103] Either or both of the oxygen-rich first nitride layer 810a and the oxygen-deficient second nitride layer 810b may comprise silicon nitride or silicon oxynitride, for example, silicon-rich and / Can be formed by a CVD process using a process gas comprising N ₂ O / NH ₃ and DCS / NH ₃ gas mixtures in proportions and at rates that are tailored to provide an oxygen-rich oxynitride layer.

[00 104] Finally, the oxygen-shortage second nitride layer (810b), and blocking dielectric layer 812 is a high K one or both of the dielectric (e.g., HfSiON, HfSiO, HfO, ZrSiON, ZrSiO, ZrO, or Y ₂ 0 ₃ ).

[00105] A suitable thickness for the oxygen-rich first nitride layer 810a may be from about 30 A to about 80 A (some variations are permissible, for example, +/- 10 A), of which about 5-20 A May be consumed by radical oxidation to form anti-tunneling layer 820. [ A suitable thickness for the oxygen-deficient second nitride layer 810b may be at least 30 angstroms, and a suitable thickness for the blocking dielectric layer 812 may be about 30-70 angstroms.

[0106] The memory transistor 800 of FIG. 8A may be made using a gate first or gate last scheme. Figures 9A-F illustrate the gate first approach for fabricating the non-planar multigate device of Figure 8A. Figures 20A-F illustrate a gate-last approach for fabricating the non-planar multigate device of Figure 8A.

9A, in a gate-first approach, a first or bottom dielectric layer 902, such as an oxide, is deposited over a first doped diffusion region 904, such as a source region or a drain region, . The high work function gate electrode 908 is on the first dielectric layer 902 to form the control gate of the device, on which a second or top dielectric layer 910 is formed. A dopant concentration of from about lel 4 cm ^-2 to about lel 6 cm ^{-2 and} a dopant concentration of from about 200 Å to about 2000 Å ² , such that the minimum energy required to remove electrons from the gate electrode is at least about 4.8 eV to about 5.3 eV, A high work function gate electrode 908 can be formed by depositing and / or doping a polysilicon layer having a thickness of about &lt; RTI ID = 0.0 &gt; The polysilicon layer may be deposited in a low pressure CVD process as a doped polysilicon layer through the addition of gases such as phosphine, arsine, diborane, or BF ₂ , or may be doped using an ion implantation process after deposition .

[00108] The first and second dielectric layers 902 and 910 may be deposited by CVD, radical oxidation, or may be formed by oxidation of a underlying layer or a portion of the substrate. In general, the thickness of the high work function gate electrode 908 is about 40-50 ANGSTROM, and the thickness of the first and second dielectric layers 902 and 910 is about 20-80 ANGSTROM.

9B, an overlying high work function gate electrode 908 and a first opening (not shown) are formed in the diffusion region 904 in the substrate 906 through the first and second dielectric layers 902 and 910, 912 are etched. Next, layers of tunneling oxide 914, charge-trapping region 916, and blocking dielectric 918 are sequentially deposited on the surface and opening of the top dielectric layer 910 planarized to yield the intermediate structure shown in Figure 9c Lt; / RTI &gt;

Although not shown, the charge-trapping region 916 includes at least one lower or oxygen-rich first nitride layer very close to the tunnel dielectric layer 914, and an oxygen- Layered charge trapping region comprising an upper or an oxygen-deficient second nitride layer overlying the first nitride layer. Typically, the oxygen-deficient second nitride layer comprises a silicon-rich, oxygen-deficient nitride layer and comprises a plurality of charge traps distributed in the multilayer charge-trapping region, while the oxygen-rich first nitride layer comprises oxygen - enriched nitride or silicon oxynitride and oxygen-rich compared to the oxygen-deficient second nitride layer, thereby reducing the number of charge traps therein. In some embodiments, the multilayer charge-trapping region 916 includes at least one thin, middle, or anti-doping layer comprising a dielectric such as an oxide separating the oxygen-deficient second nitride layer from the oxygen-rich first nitride layer. - further comprises a tunneling layer.

Next, a second or channel region opening 920 is etched anisotropically through the tunneling oxide 914, the charge-trapping region 916, and the blocking dielectric 918 (FIG. 9D). Referring to FIG. 9E, a semiconductor material 922 is deposited in the channel region openings to form vertical channel regions 924 therein. The vertical channel region 924 may include an annular region in the outer layer of a substantially solid cylindrical cylinder of semiconductor material or may include an individual semiconductor material (e.g., silicon dioxide) surrounding the cylinder of dielectric filler material 926 922) layer.

9F, the surface of the top dielectric layer 910 is planarized to form a semiconductor material 928 (FIG. 9A) including a second doped diffusion region 930, such as a source region or a drain region, formed therein. [00112] Is deposited over the top dielectric layer to form the device shown.

10a, a dielectric layer 1002, such as an oxide, is formed over a sacrificial layer 1004 on a surface on a substrate 1006 and a vertical channel region 1008 formed therein, And the openings are etched through the dielectric layer and the sacrificial layer. As with the embodiments described above, the vertical channel region 1008 can include an annular region in the outer layer of a substantially hollow cylinder of a semiconductor material 1010, such as polycrystalline or monocrystalline silicon, And a separate semiconductor material layer surrounding the cylinder of material (not shown). The dielectric layer 1002 may comprise any suitable dielectric material, such as silicon oxide, that can electrically isolate the subsequently formed high work function gate electrode from the overlying electrically active layer or other memory transistor .

[00114] Referring to FIG. 10B, the second opening 1012 is etched through the dielectric layer 1002 and the sacrificial layer 1004 to the substrate 1006, and the sacrificial layer 1004 is at least partially etched or removed. The sacrificial layer 1004 may comprise any suitable material that can be etched or removed with a high selectivity relative to the material of the dielectric layer 1002, the substrate 1006, and the vertical channel region 1008. In one embodiment, the sacrificial layer 1004 may comprise an oxide that can be removed by BOE etching (Buffered Oxide Etch).

10C and 10D, a tunnel dielectric layer 1014, a multilayer charge-trapping region 1016a-c, and a blocking dielectric layer 1018 sequentially form the intermediate structure shown in FIG. 10C The surface of the dielectric layer 1002 planarized to form a planarized surface, and an opening. As with the previously described embodiments, the multilayered charge trapping layer 1016a-c includes at least an inner oxygen-rich first nitride layer 1016a closest to the tunnel dielectric layer 1014 and an outer oxygen- Lt; RTI ID = 0.0 &gt; 1016b. &Lt; / RTI &gt; Alternatively, the first charge trap layer and the second charge trap layer may be separated by an intermediate oxide layer or anti-tunneling layer 1016c.

[00116] Next, a high work function gate electrode 1022 is deposited on the surface of the top dielectric layer 1002 and the second opening 1012 planarized to yield the intermediate structure illustrated in FIG. 10E. Like the embodiment described above, high work function gate electrode 1022, the minimum energy needed to remove an electron from the gate electrode so that at least about 4.8 eV to about 5.3 eV, about lel4 cm ^-2 to about lel6 cm ^{- 2} &lt; / RTI &gt; dopant concentration. The polysilicon layer 1022 of the high work function gate electrode is grown directly as a doped polysilicon layer through the addition of gases such as phosphine, arsine, diborane or BF ₂ to the CVD process. Finally, the openings 1024 are etched through the gate layer 1022 to form the control gates of the individual memory devices 1026A and 1026B.

[00117] The foregoing description of specific embodiments and examples has been presented for purposes of illustration and description, and is not to be construed as limiting, though the invention has been described and illustrated by specific prior examples. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and many modifications, improvements and variations within the scope of the invention are possible in connection with the above teachings. The scope of the invention is intended to cover the general scope as claimed herein and by the claims appended hereto and their equivalents. The scope of the present invention is defined by the claims, which include known equivalents and unpredictable equivalents of the present application.

Claims (20)

1. A semiconductor device comprising:
A memory transistor,
Wherein the memory transistor comprises:
A channel region for electrically connecting a source region and a drain region formed in the substrate, the channel region including polysilicon;
An oxide-nitride-nitride-oxide (ONNO) stack disposed over the channel region, the ONNO stack comprising an oxygen-rich first nitride layer and an oxygen- lt; RTI ID = 0.0 &gt; a &lt; / RTI &gt; second nitride layer; And
The high work function gate electrode formed on the surface of the ONNO stack
&Lt; / RTI &gt; The method according to claim 1,
Wherein the channel comprises a silicon nanowire. The method according to claim 1,
Wherein the channel region comprises recrystallized polysilicon. The method of claim 3,
Wherein the high work function gate electrode comprises a P + doped polysilicon layer. 5. The method of claim 4,
Wherein the ONNO stack further comprises a blocking dielectric layer disposed over the multilayer charge-trapping region, the blocking dielectric layer comprising a dielectric comprising a high K HTO (High Temperature Oxide). The method according to claim 1,
Further comprising a metal oxide semiconductor (MOS) logic transistor on the substrate, wherein the MOS logic transistor comprises a gate oxide and a high work function gate electrode. The method according to claim 6,
Both the high work function gate electrode of the memory transistor and the high work function gate electrode of the MOS logic transistor have a P-type (PMOS) silicon-oxide-nitride-oxide-silicon (SONOS) And an N + doped polysilicon layer to form a logic transistor. The method according to claim 6,
Both the high work function gate electrode of the memory transistor and the high work function gate electrode of the MOS logic transistor are made of N-type (PMOS) silicon-oxide-nitride-oxide-silicon (SONOS) memory transistors and P- And a P + doped polysilicon layer to form a logic transistor. The method according to claim 6,
Wherein both the high work function gate electrode of the memory transistor and the high work function gate electrode of the MOS logic transistor are a single patterned and doped polysilicon layer. The method according to claim 1,
Wherein the multilayer charge-trapping region further comprises an anti-tunneling layer comprising an oxide separating the first nitride layer from the second nitride layer. 1. A semiconductor device comprising:
A memory transistor,
Wherein the memory transistor comprises:
A channel region for electrically connecting a source region and a drain region formed in the substrate, the channel region including polysilicon;
An oxide-nitride-oxide-nitride-oxide (ONONO) stack disposed over the channel region; And
A high work function gate electrode &lt; RTI ID = 0.0 &gt;
/ RTI &gt;
In the ONONO stack,
A tunnel dielectric layer disposed over the channel region;
An oxygen-rich first nitride layer disposed over the tunnel dielectric layer, an oxygen-deficient second nitride layer disposed over the first nitride layer, and an oxide separating the first nitride layer from the second nitride layer A multilayer charge-trapping region, including an anti-tunneling layer; And
A blocking dielectric layer disposed over the multilayer charge-
&Lt; / RTI &gt; 12. The method of claim 11,
Wherein the channel region comprises recrystallized polysilicon. 13. The method of claim 12,
Wherein the high work function gate electrode comprises a P + doped polysilicon layer. 14. The method of claim 13,
Wherein the blocking dielectric layer comprises a dielectric comprising a high temperature oxide (HTO). 12. The method of claim 11,
Wherein the channel comprises silicon nanowires. 12. The method of claim 11,
Wherein the high work function gate electrode comprises a P + doped polysilicon layer. 12. The method of claim 11,
Further comprising a metal oxide semiconductor (MOS) logic transistor on the substrate, wherein the MOS logic transistor comprises a gate oxide and a high work function gate electrode. 1. A semiconductor device comprising:
A memory transistor,
Wherein the memory transistor comprises:
A vertical channel comprising polysilicon extending from a first diffusion region formed on a surface on the substrate to a second diffusion region formed on a surface of the substrate, the vertical channel being electrically connected to the first diffusion region - connected;
An oxide-nitride-nitride-oxide (ONNO) stack disposed in the vicinity of the vertical channel,
An abutting tunnel dielectric layer adjacent to the vertical channel;
A first nitride layer comprising an oxygen-rich nitride adjacent the tunnel dielectric layer, and a second nitride layer comprising a silicon-rich oxygen-deficient nitride overlying the first nitride layer, the multilayer charge- ; And
The blocking dielectric layer overlying the multilayer charge-
&Lt; / RTI &gt; And
Disposed adjacent the ONNO stack, wherein the blocking dielectric layer is disposed adjacent the high work function gate electrode
&Lt; / RTI &gt; 19. The method of claim 18,
Further comprising a metal oxide semiconductor (MOS) logic transistor on the substrate, wherein the MOS logic transistor comprises a gate oxide and a high work function gate electrode. 19. The method of claim 18,
Wherein the multilayer charge-trapping region further comprises an anti-tunneling layer comprising an oxide separating the first nitride layer from the second nitride layer.

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